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ths4061, ths4062 180-mhz high-speed amplifiers slos234d december 1998 revised february 2000 1 post office box 655303 ? dallas, texas 75265 high speed 180 mhz bandwidth (g = 1, 3 db) 400 v/ m s slew rate 40-ns settling time (0.1%) high output drive, i o = 115 ma (typ) excellent video performance 75 mhz 0.1 db bandwidth (g = 1) 0.02% differential gain 0.02 differential phase very low distortion thd = 72 dbc at f = 1 mhz wide range of power supplies v cc = 5 v to 15 v available in standard soic, msop powerpad ? , jg, or fk package evaluation module available description the ths4061 and ths4062 are general- purpose, single/dual, high-speed voltage feed- back amplifiers ideal for a wide range of applications including video, communication, and imaging. the devices offer very good ac performance with 180-mhz bandwidth, 400-v/ m s slew rate, and 40-ns settling time (0.1% ). the ths4061/2 are stable at all gains for both inverting and noninverting configurations. these amplifiers have a high output drive capability of 115 ma and draw only 7.8 ma supply current per channel. excellent professional video results can be obtained with the low differential gain/phase errors of 0.02%/0.02 and wide 0.1 db flatness to 75 mhz. for applications requiring low distortion, the ths4061/2 is ideally suited with total harmonic distortion of 72 dbc at f = 1 mhz. powerpad is a trademark of texas insruments incorporated. copyright ? 2000, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ths4062 d and dgn package (top view) 1 2 3 4 8 7 6 5 1out 1in 1in + v cc v cc+ 2out 2in 2in+ 1 2 3 4 8 7 6 5 null in in + v cc null v cc+ out nc ths4061 jg, d and dgn package (top view) nc no internal connection _ + ths4061 2 k w v i 2 k w 75 w 75 w v o 75 w line driver (g = 2) cross-section view showing powerpad option (dgn) 19 20 1 32 17 18 16 15 14 13 12 11 9 10 5 4 6 7 8 nc v cc+ nc out nc nc in nc in+ nc nc null nc null nc v nc nc nc nc ths4061 fk package (top view) cc on products compliant to mil-prf-38535, all parameters are tested unless otherwise noted. on all other products, production processing does not necessarily include testing of all parameters. caution: the ths4061 and ths4062 provide esd protection circuitry. however, permanent damage can still occur if this device is subjected to high-energy electrostatic discharges. proper esd precautions are recommended to avoid any performance degradation or loss of functionality
ths4061, ths4062 180-mhz high-speed amplifiers slos234d december 1998 revised february 2000 2 post office box 655303 ? dallas, texas 75265 related devices device description ths4011/2 ths4031/2 ths4061/2 290-mhz low distortion high-speed amplifiers 100-mhz low noise high speed-amplifiers 180-mhz high-speed amplifiers available options packaged devices t a number of channels plastic small outline 2 (d) plastic msop 2 (dgn) ceramic dip (jg) chip carrier (fk) msop symbol evaluation modules 0 c to 1 ths4061cd ths4061cdgn e e tiabs ths4061evm 70 c 2 ths4062cd ths4062cdgn e e tiabm ths4062evm 40 c to 1 ths4061id THS4061IDGN e e tiabt e 85 c 2 ths4062id ths4062idgn e e tiabn e 55 c to 125 c 1 e e ths4061mjg ths4061mfk e e 2 the d and dgn packages are available taped and reeled. add an r suffix to the device type (i.e., ths4061cdgnr). functional block diagram out 8 6 1 in in+ 2 3 null + figure 1. ths4061 single channel 1out 1in 1in+ v cc 2out 2in 2in+ v cc 8 6 1 2 3 5 7 4 + + figure 2. ths4062 dual channel
ths4061, ths4062 180-mhz high-speed amplifiers slos234d december 1998 revised february 2000 3 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted) 2 supply voltage, v cc + to v cc 33 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage, v i v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output current, i o 150 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . differential input voltage, v io 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous total power dissipation see dissipation rating table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . maximum junction temperature, t j 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature, t a : c-suffix 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i-suffix 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . m-suffix 55 c to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from case for 10 seconds, d and dgn package 300 c . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from case for 60 seconds, jg package 300 c . . . . . . . . . . . . . . . . . . . . case temperature for 60 seconds, fk package 260 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. dissipation rating table package t a 25 c derating factor t a = 70 c t a = 85 c t a = 125 c package a power rating above t a = 25 c a power rating a power rating a power rating d 740 mw 6 mw/ c 475 mw 385 mw e dgn 3 2.14 w 17.1 mw/ c 1.37 w 1.11 w e jg 1057 mw 8.4 mw/ c 627 mw 546 mw 210 mw fk 1375 mw 11 mw/ c 880 mw 715 mw 275 mw 3 the dgn package incorporates a powerpad on the underside of the device. this acts as a heatsink and must be connected to a ther mal dissipation plane for proper power dissipation. failure to do so can result in exceeding the maximum specified junction temperature, which could permanently damage the device. recommended operating conditions min nom max unit su pp ly voltage v cc + and v cc dual supply 4.5 16 v s u ppl y v oltage , v cc + and v cc single supply 9 32 v c-suffix 0 70 operating free-air temperature, t a i-suffix 40 85 c m-suffix 55 125
ths4061, ths4062 180-mhz high-speed amplifiers slos234d december 1998 revised february 2000 4 post office box 655303 ? dallas, texas 75265 electrical characteristics at t a = 25 c, v cc = 15 v, r l = 150 w (unless otherwise noted) dynamic performance parameter test conditions 2 ths4061c/i, ths4062c/i unit min typ max dif llil v cc = 5 v gain = 1 180 mhz dynamic performance small-signal bandwidth ( 3 db) v cc = 15 v gain = 1 50 mhz bw bandwidth ( 3 db) v cc = 5 v gain = 1 50 mh z bandwidth for 0 1 db flatness v cc = 15 v gain = 1 75 mhz band w idth for 0 . 1 db flatness v cc = 5 v gain = 1 20 mh z sr slew rate v cc = 15 v gain = 1 400 v/ m s sr sle w rate v cc = 5 v gain = 1 350 v/ m s settling time to 0 1% v cc = 15 v, 5-v step (0 v to 5 v) gain = 1 40 ns t settling time to 0 . 1% v cc = 5 v, v o = 2.5 v to 2.5 v, gain = 1 40 ns t s settling time to 0 01% v cc = 15 v, 5-v step (0 v to 5 v) gain = 1 140 ns settling time to 0 . 01% v cc = 5 v, v o = 2.5 v to 2.5 v, gain = 1 150 ns 2 full range = 0 c to 70 c for c suffix and 40 c to 85 c for i suffix noise/distortion performance parameter test conditions 2 ths4061c/i, ths4062c/i unit min typ max thd total harmonic distortion f = 1 mhz 72 dbc v n input voltage noise f = 10 khz, v cc = 5 v or 15 v 14.5 nv/ hz i n input current noise f = 10 khz, v cc = 5 v or 15 v 1.6 pa/ hz differential gain error gain = 2 ntsc 40 ire modulation v cc = 15 v 0.02 % differential gain error gain = 2 , ntsc , 40 ire mod u lation v cc = 5 v 0.02 % differential p hase error gain = 2 ntsc 40 ire modulation v cc = 15 v 0.02 differential phase error gain = 2 , ntsc , 40 ire mod u lation v cc = 5 v 0.06 channel-to-channel crosstalk (ths4062 only) v cc = 5 v or 15 v, f = 1 mhz 65 db 2 full range = 0 c to 70 c for c suffix and 40 c to 85 c for i suffix dc performance parameter test conditions 2 ths4061c/i, ths4062c/i unit min typ max v cc = 15 v v o = 10 v r l =1k w t a = 25 c 5 15 v/mv o p en loo p gain v cc = 15 v , v o = 10 v , r l = 1 k w t a = full range 4 v/mv open loop gain v cc = 5v v o = 25v r l =1k w t a = 25 c 2.5 8 v/mv v cc = 5 v , v o = 2 . 5 v , r l = 1 k w t a = full range 2 v/mv v os input offset voltage v cc = 5 v or 15 v t a = full range 2.5 8 mv v os offset drift v cc = 5 v or 15 v t a = f u ll range 15 m v/ c i ib input bias current v cc = 5 v or 15 v t a = full range 3 6 m a i os input offset current v cc = 5 v or 15 v t a = full range 75 250 na offset current drift t a = full range 0.3 na/ c 2 full range = 0 c to 70 c for c suffix and 40 c to 85 c for i suffix
ths4061, ths4062 180-mhz high-speed amplifiers slos234d december 1998 revised february 2000 5 post office box 655303 ? dallas, texas 75265 electrical characteristics at t a = 25 c, v cc = 15 v, r l = 150 w (unless otherwise noted) (continued) input characteristics parameter test conditions 2 ths4061c/i, ths4062c/i unit min typ max v icr common mode in p ut voltage range v cc = 15 v 13.8 14.1 v v icr common - mode inp u t v oltage range v cc = 5 v 3.8 4.3 v cmrr common mode rejection ratio v cc = 15 v, v icr = 12 v t a = full range 70 110 db cmrr common mode rejection ratio v cc = 5 v, v icr = 2.5 v t a = f u ll range 70 95 db r i input resistance 1 m w c i input capacitance 2 pf 2 full range = 0 c to 70 c for c suffix and 40 c to 85 c for i suffix output characteristics parameter test conditions 2 ths4061c/i, ths4062c/i unit min typ max v cc = 15 v r l = 250 w 11.5 12.5 v v o out p ut voltage swing v cc = 5 v r l = 150 w 3.2 3.5 v v o o u tp u t v oltage s w ing v cc = 15 v r l =1k w 13 13.5 v v cc = 5 v r l = 1 k w 3.5 3.7 v i o out p ut current v cc = 15 v r l =20 w 80 115 ma i o o u tp u t c u rrent v cc = 5 v r l = 20 w 50 75 ma i sc short-circuit current v cc = 15 v 150 ma r o output resistance open loop 12 w 2 full range = 0 c to 70 c for c suffix and 40 c to 85 c for i suffix power supply parameter test conditions 2 ths4061c/i, ths4062c/i unit min typ max v cc su pp ly voltage o p erating range dual supply 4.5 16.5 v v cc s u ppl y v oltage operating range single supply 9 33 v i cc quiescent current ( p er am p lifier) v cc = 15 v t a = full range 7.8 10.5 ma i cc q u iescent c u rrent (per amplifier) v cc = 5 v t a = f u ll range 7.3 10 ma psrr power su pp ly rejection ratio v cc = 5vor 15 v t a = 25 c 70 78 db psrr po w er s u ppl y rejection ratio v cc = 5 v or 15 v t a = full range 68 db 2 full range = 0 c to 70 c for c suffix and 40 c to 85 c for i suffix
ths4061, ths4062 180-mhz high-speed amplifiers slos234d december 1998 revised february 2000 6 post office box 655303 ? dallas, texas 75265 electrical characteristics at t a = 25 c, v cc = 15 v, r l = 150 w (unless otherwise noted) dynamic performance parameter test conditions 2 ths4061m unit parameter test conditions 2 min typ max unit unity-gain bandwidth closed loop, r l = 1 k w v cc = 15 v *140 180 mhz v cc = 15 v gain = 1 180 mhz dynamic performance small-signal v cc = 5 v gain = 1 180 mh z bw yg bandwidth (3 db) v cc = 15 v gain = 1 50 mhz v cc = 5 v gain = 1 50 mh z bandwidth for 0 1 db flatness v cc = 15 v gain = 1 75 mhz band w idth for 0 . 1 db flatness v cc = 5 v gain = 1 20 mh z sr slew rate v cc = 15 v r l = 1 k w *400 500 v/ m s settling time to 0 1% v cc = 15 v, 5-v step (0 v to 5 v) gain = 1 40 ns t settling time to 0 . 1% v cc = 5 v, v o = 2.5 v to 2.5 v, gain = 1 40 ns t s settling time to 0 01% v cc = 15 v, 5-v step (0 v to 5 v) gain = 1 140 ns settling time to 0 . 01% v cc = 5 v, v o = 2.5 v to 2.5 v, gain = 1 150 ns 2 full range = 55 c to 125 c for m suffix *this parameter is not tested. noise/distortion performance parameter test conditions 2 ths4061m unit parameter test conditions 2 min typ max unit thd total harmonic distortion f = 1 mhz 72 dbc v n input voltage noise f = 10 khz, v cc = 5 v or 15 v 14.5 nv/ hz i n input current noise f = 10 khz, v cc = 5 v or 15 v 1.6 pa/ hz differential gain error gain = 2 ntsc 40 ire modulation v cc = 15 v 0.02 % differential gain error gain = 2 , ntsc , 40 ire mod u lation v cc = 5 v 0.02 % differential p hase error gain = 2 ntsc 40 ire modulation v cc = 15 v 0.02 differential phase error gain = 2 , ntsc , 40 ire mod u lation v cc = 5 v 0.06 2 full range = 55 c to 125 c for m suffix dc performance parameter test conditions 2 ths4061m unit parameter test conditions 2 min typ max unit o p en loo p gain v cc = 15 v, v o = 10 v, r l = 1 k w t a = full range 5 9 v/mv open loop gain v cc = 5 v, v o = 2.5 v, r l = 1 k w t a = f u ll range 2.5 6 v/mv in p ut offset voltage v cc = 5vor 15 v r l =1k w t a = 25 c 2.5 8 mv v io inp u t offset v oltage v cc = 5 v or 15 vr l = 1 k w t a = full range 9 mv offset drift v cc = 5 v or 15 v r l = 1 k w t a = full range 15 m v/ c i ib input bias current v cc = 5 v or 15 v r l = 1 k w t a = full range 3 6 m a i io input offset current v cc = 5 v or 15 v r l = 1 k w t a = full range 75 250 na offset current drift v cc = 5 v or 15 v r l = 1 k w t a = full range 0.3 na/ c 2 full range = 55 c to 125 c for m suffix
ths4061, ths4062 180-mhz high-speed amplifiers slos234d december 1998 revised february 2000 7 post office box 655303 ? dallas, texas 75265 electrical characteristics at t a = full range, v cc = 15 v, r l = 1 k w (unless otherwise noted) (continued) input characteristics parameter test conditions 2 ths4061m unit parameter test conditions 2 min typ max unit v icr common mode in p ut voltage range v cc = 15 v 13.8 14.1 v v icr common - mode inp u t v oltage range v cc = 5 v 3.8 4.3 v cmrr common mode rejection ratio v cc = 15 v, v icr = 12 v 70 86 db cmrr common mode rejection ratio v cc = 5 v, v icr = 2.5 v 80 90 db r i input resistance 1 m w c i input capacitance 2 pf 2 full range = 55 c to 125 c for m suffix output characteristics parameter test conditions 2 ths4061m unit parameter test conditions 2 min typ max unit v cc = 15 v r l = 250 w 12 13.1 v v o out p ut voltage swing v cc = 5 v r l = 150 w 3.2 3.5 v v o o u tp u t v oltage s w ing v cc = 15 v r l =1k w 13 13.5 v v cc = 5 v r l = 1 k w 3.5 3.7 v i o out p ut current v cc = 15 v r l =20 w 70 115 ma i o o u tp u t c u rrent v cc = 5 v r l = 20 w 50 75 ma i sc short-circuit current v cc = 15 v t a = 25 c 150 ma r o output resistance open loop 12 w 2 full range = 55 c to 125 c for m suffix power supply parameter test conditions 2 ths4061m unit parameter test conditions 2 min typ max unit v cc su pp ly voltage o p erating range dual supply 4.5 16.5 v v cc s u ppl y v oltage operating range single supply 9 33 v v cc = 15 v t a =25 c 7.8 9 i cc quiescent current v cc = 5 v t a = 25 c 7.3 8.5 ma i cc q u iescent c u rrent v cc = 15 v t a = full range 11 ma v cc = 5 v t a = f u ll range 10.5 psrr power su pp ly rejection ratio v cc = 5vor 15 v t a = 25 c 76 80 db psrr po w er s u ppl y rejection ratio v cc = 5 v or 15 v t a = full range 74 78 db 2 full range = 55 c to 125 c for m suffix
ths4061, ths4062 180-mhz high-speed amplifiers slos234d december 1998 revised february 2000 8 post office box 655303 ? dallas, texas 75265 typical characteristics figure i ib input bias current vs free-air temperature 3 v io input offset voltage vs free-air temperature 4 open-loop gain vs frequency 5 phase vs frequency 5 differential gain vs number of loads 6, 8 differential phase vs number of loads 7, 9 closed-loop gain vs frequency 10, 11 output amplitude vs frequency 12, 13 cmrr common-mode rejection ratio vs frequency 14 psrr power su pp ly rejection ratio vs frequency 15 psrr po w er - s u ppl y rejection ratio vs free-air temperature 16 v o(pp) output voltage swing vs supply voltage 17 i cc supply current vs free-air temperature 18 e nv noise spectral density vs frequency 19 thd total harmonic distortion vs frequency 20, 21
ths4061, ths4062 180-mhz high-speed amplifiers slos234d december 1998 revised february 2000 9 post office box 655303 ? dallas, texas 75265 typical characteristics figure 3 input bias current vs free-air temperature 40 20 0 20 80 t a free-air temperature c 60 40 4 3 2 3.5 2.5 100 i ib input bias current a m vcc = 15 v, 5 v figure 4 t a free-air temperature c input offset voltage vs free-air temperature 40 20 0 80 40 20 1.5 0.5 2.5 v io input offset voltage mv 60 0 1 2 3.5 100 vcc = 5 v vcc = 15 v 3 open-loop gain and phase vs frequency 40 20 0 10k 1m f frequency hz 50 30 10 100k 10m 100m 60 80 1k open-loop gain db 70 90 135 180 90 phase 45 0 1g vcc = 5 v vcc = 15 v phase figure 5
ths4061, ths4062 180-mhz high-speed amplifiers slos234d december 1998 revised february 2000 10 post office box 655303 ? dallas, texas 75265 typical characteristics figure 6 1 0.12% 0.08% 0.04% 23 number of 150 w loads 0.14% differential gain 0.1% 0.06% 0.02% 4 differential gain vs number of loads gain = 2 rf = 680 w 40 ire ntsc worst case 100 ire ramp 0% v cc = 5 gain v cc = 15 gain figure 7 1 0.6 0.4 0.2 23 number of 150 w loads 0.7 0.5 0.3 0.1 4 differential phase differential phase vs number of loads gain = 2 rf = 680 w 40 ire ntsc worst case 100 ire ramp 0 v cc = 15 phase v cc = 5 phase figure 8 1 0.18% 0.14% 0.1% 0.06% 23 number of 150 w loads differential gain 0.16% 0.12% 0.08% 4 differential gain vs number of loads 0.04% 0% 0.2% gain = 2 r f = 680 w 40 ire pal worst case 100 ire ramp 0.02% v cc = 5 gain v cc = 15 gain figure 9 1 0.9 0.7 0.5 0.3 23 number of 150 w loads 0.8 0.6 0.4 4 differential phase differential phase vs number of loads 0.2 0 1 gain = 2 r f = 680 w 40 ire pal worst case 100 ire ramp 0.1 v cc = 15 phase v cc = 5 phase
ths4061, ths4062 180-mhz high-speed amplifiers slos234d december 1998 revised february 2000 11 post office box 655303 ? dallas, texas 75265 typical characteristics figure 10 closed-loop gain vs frequency 8 12 14 1m 100m f frequency hz 6 10 10m 1g 4 0 100k closed-loop gain db 2 2 gain = 1 r f = 270 w r l = 150 w v cc = 15 v v cc = 5 v figure 11 closed-loop gain vs frequency 15 20 1m 100m f frequency hz 10 10m 1g 5 5 100k closed-loop gain db 0 v cc = 15 v, 5 v gain = 1 r f = 510 w r l = 150 w figure 12 output amplitude vs frequency 100k 1m 10m 100m 1g f frequency hz 4 8 6 output amplitude db 4 0 2 2 gain = 1 r l = 150 w r f = 1 k w r f = 200 w r f = 270 w figure 13 output amplitude vs frequency 100k 1m 10m 100m 1g f frequency hz 6 10 8 output amplitude db 2 2 0 4 gain = 1 r l = 150 w r f = 3 k w r f = 510 w
ths4061, ths4062 180-mhz high-speed amplifiers slos234d december 1998 revised february 2000 12 post office box 655303 ? dallas, texas 75265 typical characteristics figure 14 cmrr common-mode rejection ratio db common-mode rejection ratio vs frequency 10k 10m 100m f frequency hz 1m 100k 100 60 20 0 80 40 120 v cc = 15 v, 5 v figure 15 f frequency hz psrr power supply rejection ratio db power supply rejection ratio vs frequency 1k 10k 10m 100m 1m 100k 40 20 0 30 10 80 60 70 50 v cc = 15 v, 5 v figure 16 t a free-air temperature c psrr power supply rejection ratio db power supply rejection ratio vs free-air temperature 40 20 0 80 40 20 88 84 80 72 86 82 90 60 100 78 74 76 v cc = 15 v v cc = 15 v figure 17 output voltage swing vs supply voltage 4 6 8 10 16 v cc supply voltage v 14 12 30 20 10 0 25 15 5 v o(pp) output voltage swing v r l = 1 k w r l = 150 w
ths4061, ths4062 180-mhz high-speed amplifiers slos234d december 1998 revised february 2000 13 post office box 655303 ? dallas, texas 75265 typical characteristics figure 18 supply current vs free-air temperature 40 20 0 20 80 t a free-air temperature c 60 40 7 5 4 8 6 9 10 i cc supply current ma 100 v cc = 15 v v cc = 5 v figure 19 noise spectral density vs frequency 10 100 1k 10k f frequency hz 100k 140 0 180 100 60 e nv noise spectral density nv/ hz 160 120 80 20 40 t a = 25 c figure 20 total harmonic distortion vs frequency 1m f frequency mhz thd total harmonic distortion db 10m 100k 50 70 90 110 40 60 80 100 2nd harmonic gain = 2 v cc = 15 v r l = 150 w 3rd harmonic total harmonic distortion vs frequency 1m f frequency mhz thd total harmonic distortion db 10m 100k 50 70 90 110 40 60 80 100 2nd harmonic gain = 2 v cc = 5 v r l = 150 w 3rd harmonic figure 21
ths4061, ths4062 180-mhz high-speed amplifiers slos234d december 1998 revised february 2000 14 post office box 655303 ? dallas, texas 75265 application information theory of operation the ths406x is a high speed, operational amplifier configured in a voltage feedback architecture. it is built using a 30-v, dielectrically isolated, complementary bipolar process with npn and pnp transistors possessing f t s of several ghz. this results in an exceptionally high performance amplifier that has a wide bandwidth, high slew rate, fast settling time, and low distortion. a simplified schematic is shown in figure 22. in (2) in + (3) null (1) null (8) (6) out (4) v cc (7) v cc + figure 22. ths4061 simplified schematic
ths4061, ths4062 180-mhz high-speed amplifiers slos234d december 1998 revised february 2000 15 post office box 655303 ? dallas, texas 75265 application information offset nulling the ths4061 has very low input offset voltage for a high-speed amplifier. however, if additional correction is required, an offset nulling function has been provided. by placing a potentiometer between terminals 1 and 8 and tying the wiper to the negative supply, the input offset can be adjusted. this is shown in figure 23. _ + ths4061 v cc v cc + 0.1 m f 0.1 m f 10 k w figure 23. offset nulling schematic optimizing unity gain response internal frequency compensation of the ths406x was selected to provide very wideband performance yet still maintain stability when operated in a noninverting unity gain configuration. when amplifiers are compensated in this manner there is usually peaking in the closed loop response and some ringing in the step response for very fast input edges, depending upon the application. this is because a minimum phase margin is maintained for the g=+1 configuration. for optimum settling time and minimum ringing, a feedback resistor of 270 w should be used as shown in figure 24. additional capacitance can also be used in parallel with the feedback resistance if even finer optimization is required. _ + ths406x 270 w input output figure 24. noninverting, unity gain schematic
ths4061, ths4062 180-mhz high-speed amplifiers slos234d december 1998 revised february 2000 16 post office box 655303 ? dallas, texas 75265 application information driving a capacitive load driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are taken. the first is to realize that the ths406x has been internally compensated to maximize its bandwidth and slew rate performance. when the amplifier is compensated in this manner, capacitive loading directly on the output will decrease the device's phase margin leading to high frequency ringing or oscillations. therefore, for capacitive loads of greater than 10 pf, it is recommended that a resistor be placed in series with the output of the amplifier, as shown in figure 25. a minimum value of 20 w should work well for most applications. for example, in 75- w transmission systems, setting the series resistor value to 75 w both isolates any capacitance loading and provides the proper line impedance matching at the source end. + _ ths406x c load 510 w input output 510 w 20 w figure 25. driving a capacitive load circuit layout considerations in order to achieve the levels of high frequency performance of the ths406x, it is essential that proper printed-circuit board high frequency design techniques be followed. a general set of guidelines is given below. in addition, a ths406x evaluation board is available to use as a guide for layout or for evaluating the device performance. ground planes it is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. however, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. proper power supply decoupling use a 6.8- m f tantalum capacitor in parallel with a 0.1- m f ceramic capacitor on each supply terminal. it may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1- m f ceramic capacitor should always be used on the supply terminal of every amplifier. in addition, the 0.1- m f capacitor should be placed as close as possible to the supply terminal. as this distances increases, the inductance in the connecting trace makes the capacitor less effective. the designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. sockets sockets are not recommended for high-speed operational amplifiers. the additional lead inductance in the socket pins will often lead to stability problems. surface-mount packages soldered directly to the printed-circuit board is the best implementation. short trace runs/compact part placements optimum high frequency performance is achieved when stray series inductance has been minimized. to realize this, the circuit layout should be made as compact as possible thereby minimizing the length of all trace runs. particular attention should be paid to the inverting input of the amplifier. its length should be kept as short as possible. this will help to minimize stray capacitance at the input of the amplifier.
ths4061, ths4062 180-mhz high-speed amplifiers slos234d december 1998 revised february 2000 17 post office box 655303 ? dallas, texas 75265 application information circuit layout considerations (continued) surface-mount passive components using surface-mount passive components is recommended for high-frequency amplifier circuits for several reasons. first, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. second, the small size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray inductance and capacitance. if leaded components are used, it is recommended that the lead lengths be kept as short as possible. evaluation board an evaluation board is available for the ths4061 (literature number slop226) and ths4062 (literaure number slop235). this board has been configured for very low parasitic capacitance in order to realize the full performance of the amplifier. a schematic of the evaluation board is shown in figure 26. the circuitry has been designed so that the amplifier may be used in either an inverting or noninverting configuration. to order the evaluation board contact your local ti sales office or distributor. for more detailed information, refer to the ths4061 evm user's manual (literature number slou038) or the ths4062 evm user's manual (literature number slou040) _ + ths4061 v cc v cc + c1 6.8 m f c4 0.1 m f c2 6.8 m f c3 0.1 m f r4 1 k w r2 1 k w r3 49.9 w r5 49.9 w r1 49.9 w in in + null out null + + figure 26. ths4061 evaluation board schematic
ths4061, ths4062 180-mhz high-speed amplifiers slos234d december 1998 revised february 2000 18 post office box 655303 ? dallas, texas 75265 mechanical information d (r-pdso-g**) plastic small-outline package 14 pin shown 4040047 / d 10/96 0.228 (5,80) 0.244 (6,20) 0.069 (1,75) max 0.010 (0,25) 0.004 (0,10) 1 14 0.014 (0,35) 0.020 (0,51) a 0.157 (4,00) 0.150 (3,81) 7 8 0.044 (1,12) 0.016 (0,40) seating plane 0.010 (0,25) pins ** 0.008 (0,20) nom a min a max dim gage plane 0.189 (4,80) (5,00) 0.197 8 (8,55) (8,75) 0.337 14 0.344 (9,80) 16 0.394 (10,00) 0.386 0.004 (0,10) m 0.010 (0,25) 0.050 (1,27) 0 8 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). d. falls within jedec ms-012
ths4061, ths4062 180-mhz high-speed amplifiers slos234d december 1998 revised february 2000 19 post office box 655303 ? dallas, texas 75265 mechanical information dgn (s-pdso-g8) powerpad ? plastic small-outline package 0,69 0,41 0,25 thermal pad (see note d) 0,15 nom gage plane 4073271/a 01/98 4,98 0,25 5 3,05 4,78 2,95 8 4 3,05 2,95 1 0,38 0,15 0,05 1,07 max seating plane 0,10 0,65 m 0,25 0 6 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions include mold flash or protrusions. d. the package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. this pad is electrical ly and thermally connected to the backside of the die and possibly selected leads. e. falls within jedec mo-187 powerpad is a trademark of texas instruments incorporated.
ths4061, ths4062 180-mhz high-speed amplifiers slos234d december 1998 revised february 2000 20 post office box 655303 ? dallas, texas 75265 mechanical information fk (s-cqcc-n**) leadless ceramic chip carrier 4040140 / d 10/96 28 terminal shown b 0.358 (9,09) max (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) a no. of min max 0.358 0.660 0.761 0.458 0.342 (8,69) min (11,23) (16,26) 0.640 0.739 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32) (18,78) ** 20 28 52 44 68 84 0.020 (0,51) terminals 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 12 13 14 15 16 18 17 11 10 8 9 7 5 4 3 2 0.020 (0,51) 0.010 (0,25) 6 1 28 26 27 19 21 b sq a sq 22 23 24 25 20 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package can be hermetically sealed with a metal lid. d. the terminals are gold plated. e. falls within jedec ms-004
ths4061, ths4062 180-mhz high-speed amplifiers slos234d december 1998 revised february 2000 21 post office box 655303 ? dallas, texas 75265 mechanical information jg (r-gdip-t8) ceramic dual-in-line package 0.310 (7,87) 0.290 (7,37) 0.014 (0,36) 0.008 (0,20) seating plane 4040107/c 08/96 5 4 0.065 (1,65) 0.045 (1,14) 8 1 0.020 (0,51) min 0.400 (10,20) 0.355 (9,00) 0.015 (0,38) 0.023 (0,58) 0.063 (1,60) 0.015 (0,38) 0.200 (5,08) max 0.130 (3,30) min 0.245 (6,22) 0.280 (7,11) 0.100 (2,54) 0 15 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package can be hermetically sealed with a ceramic lid using glass frit. d. index point is provided on cap for terminal identification only on press ceramic glass frit seal only. e. falls within mil-std-1835 gdip1-t8
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated

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