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regarding the change of names mentioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitachi, ltd., hitachi semiconductors, and other hitachi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: http://www.renesas.com renesas technology corp. customer support dept. april 1, 2003 to all our customers
cautions keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or an y other rights, belonging to renesas technology corporation or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained i n these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, an d algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lice nse from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein.
application notes hitachi single-chip microcomputer technical questions and answers h8/500 series

preface the h8/500 series is a series of highly integrated single-chip microcontrollers. their cpu core has an internal 16-bit architecture, and each chip includes diverse high-performance peripheral hardware. these technical questions and answers relate to the h8/510, h8/520, h8/532, h8/534, and h8/536. h8/500 family item h8/510 h8/520 h8/532 h8/534 h8/536 cpu h8/500 h8/500 h8/500 h8/500 h8/500 memory rom masked rom 16 kbytes 32 kbytes 32 kbytes 62 kbytes ztat * 2 mmmm ram 512 bytes 1 kbyte 2 kbytes 2 kbytes address space (bytes) 16 m 1 m 1 m 1 m 1 m external data bus width (bits) 8/16 8888 timers 16-bit free-running timer 2 ch 2 ch 3 ch 3 ch 3 ch 8-bit timer 1 ch 1 ch 1 ch 1 ch 1 ch watchdog timer 1 ch 1 ch 1 ch 1 ch 1 ch pwm timer 3 ch 3 ch 3 ch serial communication interface 2 ch 2 ch 1 ch 2 ch 2 ch (async/sync) a/d external 10 bits, 10 bits, 4 or 10 bits, 10 bits, 10 bits, converter trigger input 4 channels, 8 * channels, 8 channels, 8 channels, 8 channels, trigger trigger no trigger no trigger no trigger interrupts external interrupts 59377 internal interrupts 18 18 19 23 23 i/o ports 60 50/54 * 1 65 65 65 packages qfp-112 dilc-64s lcc-84 lcc-84 lcc-84 (windowed) (windowed) (windowed) (windowed) dilp-64s plcc-84 plcc-84 plcc-84 plcc-68 * 1 qfp-80 qfp-80 qfp-80 qfp-64 notes: 1. plcc-68 package 2. ztat is a registered trademark of hitachi, ltd.
how to use these technical questions and answers technical questions and answers has been created by arranging technical questions actually asked by users of hitachi microcomputers in a question-and-answer format. it should be read for technical reference in conjunction with the users manual. technical questions and answers can be read before beginning a microcomputer application design project to gain a more thorough understanding of the microcomputer, or during the design process to check up on difficult points. (for questions and answers about the h8/500 cpu, see h8/500 cpu microcomputer technical questions and answers .) 4
contents q&a no. page on-chip rom (1) address bus, data bus, and control line states during access qa500 - 001b 1 to on-chip address space (2) programming the h8/536 ztat qa500 - 046a 2 clock (1) extal and system clock output line qa500 - 002b 3 (2) external clock specifications qa500 - 047a 4 (3) external clock input qa500 - 003b 5 (4) external clock input (2) qa500 - 048a 6 timers (1) external clock input to 16-bit frt qa500 - 006b 7 (2) input capture signal for 16-bit frt qa500 - 007b 8 (3) access timing to frc in 16-bit frt qa500 - 009b ?1 9 qa500 - 009b ?2 10 (4) tcnt of 8-bit timer qa500 - 011b 11 (5) wdt when system clock stops qa500 - 012b 12 (6) nmi requested by wdt qa500 - 013b 13 serial communication interface (sci) (1) input/output designation of sci clock pin qa500 - 018b 14 (2) serial i/o line status qa500 - 019b 15 (3) rdrf bit set timing qa500 - 021b ?1 16 qa500 - 021b ?2 17 (4) tdre bit set timing qa500 - 022b ?1 18 qa500 - 022b ?2 19 (5) rdr and dtr utilization when sci is not used qa500 - 023b 20 (6) rdrf bit in sci qa500 - 049a 21 (7) sci receive error 1 qa500 - 050a 22 (8) sci receive error 2 (clocked synchronous mode) qa500 - 051a 23 (9) sci rxd input example (asynchronous mode) qa500 - 052a 24 (10) sci transmit start (asynchronous mode) qa500 - 053a 25 (11) simultaneous transmit/receive in clocked synchronous mode qa500 - 054a 26 (12) clearing the scis tdre bit qa500 - 055a 27 5
q&a no. page a/d converter (1) start of a/d conversion qa500 - 024b 28 (2) non-use of a/d converter reference voltage lines (av cc , av ss ) qa500 - 025b 29 (3) changing a/d conversion mode or channels during conversion qa500 - 027b 30 (4) resistor ladder in a/d converter qa500 - 028b 31 (5) rise time of power supplies (av cc , v cc ) qa500 - 029b 32 (6) allowable impedance of a/d signal sources qa500 - 056a 33 pwm timer (1) dtr of pwm timer qa500 - 031b 34 (2) pwm pin assignments qa500 - 057a 35 data transfer controller (dtc) (1) interrupts during dtc operation qa500 - 032b 36 (2) dtc usage qa500 - 033b 37 i/o ports (1) analog input part data register during a/d conversion qa500 - 035b 38 (2) port output after reset qa500 - 037b 39 (3) as and rd signal timing qa500 - 039b 40 (4) unused i/o lines qa500 - 040b 41 power-down modes (1) power dissipation in hardware and software standby modes qa500 - 041b 42 bus controller (1) state of d 0 to d 7 with 8-bit data bus qa500 - 058a 43 bus interface (1) state of d 0 to d 7 during byte access in 16-bit data bus mode qa500 - 059a 44 miscellaneous (1) ram standby voltage qa500 - 060a 45 6
1 technical question and answer product h8/500 q&a no. qa500 - 001b topic address bus, data bus, and control line states during access to on-chip address space question additional information answer classification?8/500 software m on-chip rom m on-chip ram clock timers serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. what values are output on the following lines when on- chip memory or the on-chip register field is accessed? (1) address bus (2) data bus (3) bus control signals (1) the address bus carries the address data, regardless of whether the access is to an on-chip or off-chip address. (2) the data bus is in the high-impedance state for both read and write access by the cpu to an on-chip address. (3) the r/w signal is low for write access and high for read access. the other control signals (as, ds, rd, wr) are high.
2 technical question and answer product h8/536 q&a no. qa500 - 046a topic programming the h8/536 ztat question additional information answer classification?8/536 software m on-chip rom on-chip ram clock timers serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. we are having trouble programming the ztat version of the h8/536. are there any precautions we may be missing? 1. when programming the h8/536, you must set your prom writer to memory type hn27c101 and either write h'ff data in addresses h'f680 to h'1ffff or set h'f67f as the end address. be sure to use byte programming mode. the h8/536 does not support page programming. some prom writers do not support byte programming for the hn27c101.
3 technical question and answer product h8/500 q&a no. qa500 - 002b topic extal and system clock output line question additional information answer classification?8/500 software on-chip rom on-chip ram m clock timers serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. during external clock input, what is the phase relationship between extal and the system clock output line (?output)? 1. during external clock input, the phase relationship between extal and the system clock output line is as shown below. extal ?output approx. 40 ns internal delay the internal delay value is not guaranteed.
4 technical question and answer product h8/500 q&a no. qa500 - 047a topic external clock specifications question additional information answer classification?8/500 software on-chip rom on-chip ram m clock timers serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. when an external clock is supplied to the extal pin, what are the rise-time and fall-time requirements? 1. for a 20-mhz clock, the rise time (t cr ) and fall time (t cf ) should both be approximately 5 ns. t cf t cr external clock (extal)
5 technical question and answer product h8/520, 532, 534, 536 q&a no. qa500 - 003b topic external clock input question additional information answer classification?8/532 software on-chip rom on-chip ram m clock timers serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. for external clock input, the hardware manual shows an example of a circuit using a 74hc04 (see below). why is the 74hc04 necessary? extal xtal 74hc04 external clock input 1. if the xtal pin open is left open, operation may become unstable. the 74hc04 is necessary to assure stable operation at high clock rates. note: the xtal pin can be left open if the external clock rate is 16 mhz or less. for masked- rom versions and the h8/510, the xtal pin can be left open for external clock rates up to 20 mhz.
6 technical question and answer product h8/520, 532, 534, 536 q&a no. qa500 - 048a topic external clock input (2) question additional information answer classification?8/532 software on-chip rom on-chip ram m clock timers serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. the h8/500 series users manuals (except h8/510) show a circuit using a 74hc04 for external clock input. (see diagram on previous page.) can an als-ttl, for example, be used instead? 1. an als-ttl device can be used if its propagation delay time and drivability are equivalent to the 74hc04.
7 technical question and answer product h8/500 q&a no. qa500 - 006b topic external clock input to 16-bit frt question additional information answer classification?8/500 software on-chip rom on-chip ram clock m timers serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. when the external clock source is selected for the 16-bit free-running timer, what is the minimum pulse width of the external clock (ftci)? 1. the minimum pulse width of the external clock is 1.5 system clock cycles. ftci input 1.5 system clocks
8 technical question and answer product h8/500 q&a no. qa500 - 007b topic input capture signal for 16-bit frt question additional information answer classification?8/500 software on-chip rom on-chip ram clock m timers serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. if an frt input capture line (fti) is multiplexed with a general-purpose input/output port that is used for output, will the rise and fall of the output data update the input capture register? 1. yes. the input capture register will be updated by output on the input/output line, on the edge selected by the input edge select bit (iedg) in the timer control/status register (tcsr).
9 technical question and answer product h8/500 q&a no. qa500 - 009b ?1 topic access timing to frc in 16-bit frt question additional information answer classification?8/500 software on-chip rom on-chip ram clock m timers serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. what is the read and write timing of the free-running counter (frc) in the 16-bit free-running timer (frt)? 1. the access timing of the 16-bit timers frc is shown on the next page. word access (or two successive byte accesses) should be used. the upper byte has to be accessed first.
10 technical question and answer product h8/500 q&a no. qa500 - 009b ?2 topic access timing to frc in 16-bit frt answer operation when register is read when the upper byte is read, the upper byte value is passed to the cpu and the lower byte value is transferred to temp. next, when the lower byte is read, the lower byte value in temp is passed to the cpu. operation when register is written when the upper byte is written, the upper byte value is stored in temp. next, when the lower byte is written, it is combined with the upper byte value in temp and all 16 data bits are written in the register. internal address bus internal data bus frc frc access timing (read) one bus cycle one bus cycle t h8/500 cpu read h8/500 cpu read 1 t 2 t 3 t 1 t 2 t 3 frch temp n n + 1 (frcl temp) ? internal read signal frc access timing (write) one bus cycle one bus cycle t 1 t 2 t 3 t 1 t 2 t 3 h8/500 cpu write h8/500 cpu write (high data temp) ? high data low data (low data frcl, temp frch) ?? n write data ? internal address bus internal data bus frc internal write signal
11 technical question and answer product h8/500 q&a no. qa500 - 011b topic tcnt of 8-bit timer question additional information answer classification?8/500 software on-chip rom on-chip ram clock m timers serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. when a compare-match signal clears the timer counter (tcnt) to h'00, does tcnt remain at h'00, or does it start counting up from h'00? 1. tcnt starts counting up from h'00.
12 technical question and answer product h8/500 q&a no. qa500 - 012b topic wdt when system clock stops question additional information answer classification?8/500 software on-chip rom on-chip ram clock m timers serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. if the system clock stops, will the watchdog timer (wdt) detect anything wrong? 1. if the system clock for the whole chip stops, the wdt count also stops, so the wdt cannot detect the failure.
13 technical question and answer product h8/532 q&a no. qa500 - 013b topic nmi requested by wdt question additional information answer classification?8/532 software on-chip rom on-chip ram clock m timers serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. how can you distinguish between an nmi interrupt requested from the nmi pin and an nmi interrupt requested by the watchdog timer (wdt)? 1. when the wdt requests an nmi interrupt, it sets the overflow bit (ovf) in the wdt timer status/control register (tcsr) to 1. you can detect this by software. ovf bit in tcsr nmi requested by input signal from pin 0 nmi requested by wdt 1 when the wdt is used in interval timer mode, irq 0 interrupts can be discriminated in the same way. (h8/520, h8/532)
14 technical question and answer product h8/500 q&a no. qa500 - 018b topic input/output designation of sci clock pin question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers m serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. when the sci is used, is the serial clock pin designated for input or output by writing a 0 or 1 in the data direction register (ddr) of the corresponding port? 1. when you use the sci, the input or output setting of the clock line depends on the communication mode bit (c/a.) in the serial mode register (smr) and the clock enable 1 and 0 bits (cke1 and cke0) in the serial control register (scr). you dont have to set the ddr.
15 technical question and answer product h8/500 q&a no. qa500 - 019b topic serial i/o line status question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers m serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. after input/output ports multiplexed with txd, rxd, and sck lines have been used for serial communication, suppose they are redesignated as i/o ports by settings made in the serial control register (scr) or serial mode register (smr). what values will the corresponding data direction register (ddr) contain? 1. sci operations do not affect the contents of the ddr bits of input/output ports. given the conditions you describe, the ddr bits will retain the values they had before the pins were used for serial communication.
16 technical question and answer product h8/500 q&a no. qa500 - 021b ?1 topic rdrf bit set timing question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers m serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. when data reception is completed, the receive data register full bit (rdrf) in the serial status register (ssr) is set to 1. at what timing does this occur in asynchronous mode? 2. at what timing does this occur in clocked synchronous mode? see the next page.
17 technical question and answer product h8/500 q&a no. qa500 - 021b ?2 topic rdrf bit set timing answer 1. the rdrf bit is set to 1 after the fall of the next data sampling clock after the msb of the data is received. (see the diagram below.) 2. the rdrf bit is set to 1 after the rising edge of the serial clock cycle in which the msb of the data is received. (see the diagram below.) basic clock receive data data sampling rdrf 8-bit data, 1 stop bit, internal clock d7 stop 0.5 to 1.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 serial clock receive data rdrf 0.5 to 1.5 bit 6 bit 7 8-bit data
18 technical question and answer product h8/500 q&a no. qa500 - 022b ?1 topic tdre bit set timing question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers m serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. when eight data bits have been transmitted, the transmit data register empty bit (tdre) in the serial status register (ssr) is set to 1. at what timing does this occur in asynchronous mode? 2. at what timing does this occur in clocked synchronous mode? the tdre bit is set to 1 at different times depending on whether the transmit shift register (tsr) contains transmit data or not. 1. asynchronous mode 1.1 transmit data present in tsr (see diagram below) the timing of the start of transmission after the transmit enable bit (te) is set is similar. basic clock receive data 0.5 to 1.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 tdre start bit stop bit continued on next page.
19 technical question and answer product h8/500 q&a no. qa500 - 022b ?2 topic tdre bit set timing answer 1.2 no transmit data in tsr (see diagram below) 2. clocked synchronous mode 2.1 transmit data present in tsr (see diagram below) 2.2 no transmit data in tsr (see diagram below) internal write signal basic clock tdre 0.5 1.5 tdre is set in interval from 8 basic clocks + 0.5?to 24 basic clocks + 1.5 t 1 t 2 t 3 89101112131415161234567891011121314151612345678910111213141516 serial clock transmit data tdre bit 6 bit 7 0.5 to 1.5 internal write signal tdre tdre is set in interval from 2?to 0.5 basic clock + 1.5 t 1 t 2 t 3
20 technical question and answer product h8/500 q&a no. qa500 - 023b topic rdr and dtr utilization when sci is not used question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers m serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. when the serial communication interface is not used, can the following be utilized as data registers? (1) rdr (receive data register) (2) tdr (transmit data register) 1. the answer is as follows: (1) rdr is a read-only register, so it cannot be used as a data register. (2) tdr can be used as a data register.
21 technical question and answer product h8/500 q&a no. qa500 - 049a topic rdrf bit in sci question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers m serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. to receive serial data, the receive data register full bit (rdrf) in the serial status register (ssr) must be cleared to 0. what happens if 0 is written in the bit directly, without first reading 1? 1. the rdrf bit retains its 1 value and is not cleared to 0. an overrun error occurs at completion of receiving the next data. similar considerations apply to the transmit data register empty bit (tdre).
22 technical question and answer product h8/500 q&a no. qa500 - 050a topic sci receive error 1 question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers m serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. if the receive-error interrupt handler returns to the main program without clearing the overrun flag (orer), framing error flag (fer), or parity error flag (per) in the serial status register (ssr) to 0, will a receive error occur again? 1. after one more instruction is executed in the main program the receive error will occur again, because the error flag itself is the interrupt source. this holds for all on-chip supporting modules, excluding only the external interrupts.
23 technical question and answer product h8/500 q&a no. qa500 - 051a topic sci receive error 2 (clocked synchronous mode) question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers m serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. when the sci is used in clocked synchronous mode, at what time is an overrun error detected? 1. the overrun error bit (orer) is set to 1 after the rise of the serial clock when the most significant data bit (bit 7) is received. serial clock receive data orer 0.5 to 1.5 reception of 8-bit data bit 6 bit 7
24 technical question and answer product h8/500 q&a no. qa500 - 052a topic sci rxd input example (asynchronous mode) question additional information answer classification?8/532 software on-chip rom on-chip ram clock timers m serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. suppose the rxd pin is being used as an input port and is now low. do any precautions have to be taken in order to switch this pin over to its rxd function and receive serial data correctly? 2. do any precautions have to be taken in order to receive data correctly after detecting the break condition? 1. change the rxd input to high before setting the scis receive enable bit (re) to 1. 2. before reception of the first data, supply high input to the rxd line for at least one frame.
25 technical question and answer product h8/500 q&a no. qa500 - 053a topic sci transmit start (asynchronous mode) question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers m serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. in the sci transmitting sequence, following the transfer of data from tdr to tsr, the transmit data register empty bit (tdre) in the serial status register (ssr) is set to 1, then the sci starts transmitting data. how much delay is there from the time when the tdre bit is set to 1 until output of the start bit? 1. the delay time is eight basic clock cycles (0.5?to 1.5?. see the diagram below. basic clock transmit data tdre start bit 8 basic clock cycles (0.5?to 1.5? 0.5 to 1.5 stop bit 10 11 9 1213141516 10111213141516 23 145678 9 23 145678 the same timing applies when transmission starts from the setting of the transmit enable bit (te).
26 technical question and answer product h8/500 q&a no. qa500 - 054a topic simultaneous transmit/receive in clocked synchronous mode question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers m serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. during simultaneous transmitting and receiving in clocked synchronous mode, can data be transferred in the state when an overrun error has occurred? 1. data cannot be transferred. in simultaneous transmitting and receiving in clocked synchronous mode, transmitting or receiving cannot proceed independently before the orer and tdre bits are both cleared to 0.
27 technical question and answer product h8/500 q&a no. qa500 - 055a topic clearing the scis tdre bit question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers m serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. when transmitting data, will there be any data transfer problem if we wait until after writing transmit data in the transmit data register (tdr) to read the 1 value of the tdre bit, then clear this bit to 0? 1. no problem will occur. if you write in tdr while the tdre bit is 0, however, you will destroy the previous tdr data.
28 technical question and answer product h8/500 q&a no. qa500 - 024b topic start of a/d conversion question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers serial i/o m a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. software can select the start of a/d conversion by setting the a/d start bit (adst) in the a/d control/status register (adcsr) to 1. what happens if 1 is written in the adst bit again while a/d conversion is in progress? 2. what happens if a/d conversion starts by detection of the falling edge of the external trigger signal (adtrg), then adtrg goes high while a/d conversion is in progress? (h8/510, h8/520, h8/534, h8/536) 1. if the adst bit is set to 1 again during a/d conversion, it will be ignored and a/d conversion will continue. 2. operation will be normal if the adtrg signal is low for at least 1.5 cycles. after that, if the adtrg signal goes high again during a/d conversion, it will be ignored and a/d conversion will continue.
29 technical question and answer product h8/500 q&a no. qa500 - 025b topic non-use of a/d converter reference voltage lines (av cc , av ss ) question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers serial i/o m a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. when the a/d converter is not used, what should be done with the av cc and av ss pins? 1. even when the a/d converter is not used, av cc should be connected to v cc and av ss to v ss . (1) if av cc is left open, voltage potentials in the interface to the digital circuits in the a/d converter will be unstable. (2) av ss and v ss are shorted inside the chip. any potential difference between them will cause excessive current drain. (reference) av cc av ss 10 bit d/a av cc av ss v ss comparator
30 technical question and answer product h8/500 q&a no. qa500 - 027b topic changing a/d conversion mode or channels during conversion question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers serial i/o m a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: during a/d conversion, what happens if you: 1. change the a/d conversion mode? 2. change the channel selection? 1. avoid changing the a/d conversion mode during a/d conversion. conversion accuracy will be degraded. 2. avoid changing the channel selection during a/d conversion. the same problem will occur as in 1. note: check the a/d end flag (adf) in the a/d control/status register (adcsr), then: 1. change the a/d conversion mode. 2. select the channel(s).
31 technical question and answer product h8/500 q&a no. qa500 - 028b topic resistor ladder in a/d converter question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers serial i/o m a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. are the analog power supplies of the a/d converter connected only to the resistor ladder? 1. the analog power supplies are connected not only to the resistor ladder but also to analog circuits in the comparator etc. they also power the interface to digital circuits in the a/d converter.
32 technical question and answer product h8/500 q&a no. qa500 - 029b topic rise time of power supplies (av cc , v cc ) question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers serial i/o m a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. will any problems occur if there is a difference in rise times between the analog power supply (av cc ) and digital power supply (v cc )? 1. there is no restriction on the order in which av cc and v cc are powered up. during the interval marked a in the diagram below, voltage potentials in the interface to digital circuits in the a/d converter are unstable, which may cause fluctuations in current drain. v cc av cc a
33 technical question and answer product h8/500 q&a no. qa500 - 056a topic allowable impedance of a/d signal sources question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers serial i/o m a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. does the allowable signal source impedance remain 10 k even if the a/d conversion time is changed? 1. the low-speed conversion mode should operate even at 20 k , but this is not guaranteed.
34 technical question and answer product h8/532, h8/534, h8/536 q&a no. qa500 - 031b topic dtr of pwm timer question additional information answer classification?8/532 software on-chip rom on-chip ram clock timers serial i/o a/d m pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. the duty register (dtr) of the pwm timer is set to h'00 for pulses with 0% duty cycle, h'7d for pulses with 50% duty cycle, and h'fa for pulses with 100% duty cycle, but what if a value from h'fb to h'ff is written in dtr? 1. if a value from h'fb to h'ff is written in dtr, pulses are output with a 100% duty cycle.
35 technical question and answer product h8/534, h8/536 q&a no. qa500 - 057a topic pwm pin assignments question additional information answer classification?8/534 software on-chip rom on-chip ram clock timers serial i/o a/d m pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. the pwm timer outputs (pw 1 to pw 3 ) are can be assigned to p6 1 to p6 3 (multiplexed with irq 3 to irq 5 ) or p9 2 to p9 4 (multiplexed with sck 2 , rxd 2 , and txd 2 ). can all six pins be used for pwm output? 1. yes, they can. p6 1 to p6 3 can be used for both pwm output and irq input. p9 2 to p9 4 can be used for either pwm output or sci functions, but not both.
36 technical question and answer product h8/500 q&a no. qa500 - 032b topic interrupts during dtc operation question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers serial i/o a/d pwm m dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. during operation of the data transfer controller (dtc), what happens if an interrupt is requested with a priority higher than the interrupt the dtc is serving? 1. while the dtc is operating the cpu halts, so no other interrupts can be accepted. the dtc therefore completes its interrupt service, after which one instruction is executed; then the pending interrupt-handling sequence begins. if the instruction executed after the conclusion of dtc operations is ldc or another instruction that inhibits interrupts, the interrupt-handling sequence will not start until the next instruction after that has been executed (and if that next instruction also inhibits interrupts, another instruction will be executed).
37 technical question and answer product h8/500 q&a no. qa500 - 033b topic dtc usage question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers serial i/o a/d pwm m dtc i/o ports power-down modes elec. characteristics exception handling external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. can dtc register information be located on rom? 2. after a dtc data transfer, the data transfer count register (dtcr) is decremented by 1, and if the result is 0, the dtc will no longer be activated. if dtc register information is stored on rom with the dtcr value set to 1, will an interrupt occur after the dtc data transfer? 1. dtc register information can be located on rom. 2. an interrupt will be generated. the decision as to whether dtcr = 0 is made when the dtcr value is decremented.
38 technical question and answer product h8/500 q&a no. qa500 - 035b topic analog input port data register during a/d conversion question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers serial i/o a/d pwm dtc m i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. during a/d conversion, what happens to the values in the data register (dr) of the input port that is also used for analog input? 1. pins used for analog input return the value 1 if read during a/d conversion, regardless of the actual input voltage.
39 technical question and answer product h8/500 q&a no. qa500 - 037b topic port output after reset question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers serial i/o a/d pwm dtc m i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. to use an input/output port line to output data after a reset, which should be set first: the ports data register (dr) or its data direction register (ddr)? 1. set these registers in the following order. (1) set the output data in the output ports data register. (2) set the ddr bit of the output line to 1. note: a reset initializes the port data registers to 0.
40 technical question and answer product h8/500 q&a no. qa500 - 039b topic as and rd signal timing question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers serial i/o a/d pwm dtc m i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. are the as and rd signals synchronized with the falling edge of the system clock (?, or with output on the address lines? 1. the as and rd signals are synchronized with the falling edge of the system clock in the t 1 state. the as and rd signals never go low before the falling edge in the t 1 state. case a in the diagram below cannot occur. a to a 0 as, rd 15 t ad t dsd1 t as1 t 1 t 2 t 3 case a
41 technical question and answer product h8/500 q&a no. qa500 - 040b topic unused i/o lines question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers serial i/o a/d pwm dtc m i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. what should be done with unused i/o port lines? 1. (1) pull unused input/output port lines up or down through an approximately 10-k resistor. (2) do the same for input-only port lines. connect a separate pull-up or pull-down resistor to each line.
42 technical question and answer product h8/520, 532, 534, 536 q&a no. qa500 - 041b topic power dissipation in hardware and software standby modes question additional information answer classification?8/532 software on-chip rom on-chip ram clock timers serial i/o a/d pwm dtc i/o ports m power-down modes elec. characteristics exception handling bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. is there any difference in current dissipation between hardware standby and software standby? 1. current dissipation satisfies the relationship: hardware standby software standby. in hardware standby mode, all lines are placed in the high- impedance state, which reduces current dissipation. in software standby mode i/o ports hold their previous states, so current dissipation varies depending on the state of the port.
43 technical question and answer product h8/510 q&a no. qa500 - 058a topic state of d 0 to d 7 with 8-bit data bus question additional information answer classification?8/510 software on-chip rom on-chip ram clock timers serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface development tools m bus controller miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. in 16-bit data bus mode (mode 2 or 4), during access to the area accessed via an eight-bit bus, what are the states of the unused data bus lines (d 0 to d 7 ) and control signals? 1. d 0 to d 7 are in the high-impedance state, and lwr is always 1.
44 technical question and answer product h8/510 q&a no. qa500 - 059a topic state of d 0 to d 7 during byte access in 16-bit data bus mode question additional information answer classification?8/500 software on-chip rom on-chip ram clock timers serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling m bus interface external expansion development tools miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. what are the pin states during access to byte data in 16-bit data bus mode (mode 2 or 4)? 1. (1) in write access, the upper data bus (d 15 to d 8 ) and lower data bus (d 7 to d 0 ) both output the same data. control signal states are as follows: access to even address access to odd address lwr = 1 lwr = 0 hwr = 0 hwr = 1 (2) in read access, the states differ depending on the external circuit configuration. control signal states are as follows: rd = 0 1. the minimum ram standby voltage (vram) is specified at 2.0 v. what voltage should be supplied to av cc ?
45 technical question and answer product h8/520, 532, 534, 536 q&a no. qa500 - 060a topic ram standby voltage question additional information answer classification?8/532 software on-chip rom on-chip ram clock timers serial i/o a/d pwm dtc i/o ports power-down modes elec. characteristics exception handling bus interface external expansion development tools m miscellaneous related manuals manual title: other technical documentation document name: related microcomputer technical q&a title: 1. av cc should be the same as the ram standby voltage: 2 v. setting av cc to 5 v or vss will cause excessive current drain.

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