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etachips co., ltd. etachips co., ltd. 4-bit single chip microcomputers adam24pxx user`s manual ? ADAM24P08 ? adam24p15 ? adam24p16 ? adam24p20 ? adam24p20s ? adam24p20t ver 0.5 www.datasheet.co.kr datasheet pdf - http://www..net/
page 1 of 36 program memory (mtp) 4,096 bytes (4,096 x 8bit) [ multi-programmable by 1k-byte, 2k-byte or 4k-byte) data memory (ram) 32 nibble (32 x 4bit) 3 levels of subroutine nesting 8-bit table read instruction oscillator type (operating frequency) internal rc oscillator (typically 3.64mhz 2%) instruction cycle f osc /48 stop mode released stop mode by key input built in power-on reset circuit built in transistor for i.r led drive i ol =250ma at v dd =3v and v o =0.3v built in low voltage reset circuit built in a watch dog timer (wdt) low operating voltage 1.8 ~ 3.6v 8/16/20-sop, 20-tssop package. 1.1. features 1. overview the adam24pxx is remote control transmitter which uses cmos technology. the adam24pxx is suitable for remote c ontrol of tv, vcr, fans, air-conditioners, audio equipments, toys, games etc. the adam24pxx is mtp version. table 1.1 adam24pxx series members 1. overview adam24pxx series adam24p20 adam24p20s adam24p20t 4,096 x 8 4,096 x 8 32 x 4 6 2 10 20tssop (4.4mm) 32 x 4 6 2 10 20sop(209mil) adam24p16 adam24p15 ADAM24P08 4,096 x 8 4,096 x 8 32 x 4 2 i/o ports 2 2 1 3 8sop(150mil) 32 x 4 4 8 16sop(150mil) 4,096 x 8 32 x 4 6 10 20sop(300mil) program memory data memory input ports output ports package www.datasheet.co.kr datasheet pdf - http://www..net/
page 2 of 36 1.2. block diagram adam24pxx 1. overview remout r vdd gnd k0 ~ k3 adam27 core ram (32 nibble) watchdog timer carry generator key scan & input clock gen. & system control k port rom (4k bytes x 1) (2k bytes x 2) (1k bytes x 4) d0 ~ d8 d port r port r0 ~ r1 k r2 ~ r3 internal rc oscillator (3.64mhz 2%) www.datasheet.co.kr datasheet pdf - http://www..net/
page 3 of 36 adam24pxx 1. overview 1.3. pin assignments ( top view ) adam24p20t (20 tssop) d6 [sck]/k0 [vpp]/k3 d5/[sda] d4 3 4 5 6 7 8 9 10 2 1 14 13 12 11 15 16 r2 r1 remout r3 d0 d1 k1 d3 d2 r0 vdd 18 17 19 20 gnd d8 d7 k2 adam24p20 (20 sop 300mil) d6 [sck]/k0 [vpp]/k3 d5/[sda] d4 3 4 5 6 7 8 9 10 2 1 14 13 12 11 15 16 r2 r1 remout r3 d0 d1 k1 d3 d2 r0 vdd 18 17 19 20 gnd d8 d7 k2 adam24p16 (16 sop) d5/[sda] [sck]/k0 [vpp]/k3 d3 d2 3 4 5 6 7 8 2 1 10 9 11 12 remout r3 k1 d1 d0 r2 vdd 14 13 15 16 gnd d8 d7 k2 ADAM24P08 (8 sop) d5/[sda] r2 d2 3 4 2 1 remout vdd 6 5 7 8 gnd [sck]/k0 [vpp]/k3 adam24p15 (16 sop) d6 [sck]/k0 [vpp]/k3 d5/[sda] d2 3 4 5 6 7 8 2 1 10 9 11 12 remout r3 k1 d1 d0 r2 vdd 14 13 15 16 gnd d8 d7 k2 adam24p20s (20 sop 209mil) d6 [sck]/k0 [vpp]/k3 d5/[sda] d4 3 4 5 6 7 8 9 10 2 1 14 13 12 11 15 16 r2 r1 remout r3 d0 d1 k1 d3 d2 r0 vdd 18 17 19 20 gnd d8 d7 k2 1.4. package dimension 20 sop(300mil) pin dimension (dimensions in inch) 0.512max 0.4961min 0.020max 0.013min 0.050bsc 1 2 34 56 78910 20 19 1 8 17 16 15 14 13 12 11 outline (unit : inch) 0.419max 0.398min 0.299max 0.291min 0.104max 0.093min 0.018max 0.004min 0-8 ? www.datasheet.co.kr datasheet pdf - http://www..net/
page 4 of 36 adam24pxx 1. overview 20 tssop(4.4mm) pin dimension (dimensions in millimeters) 20 sop(209mil) pin dimension (dimensions in inch) 0.008max 0.005min 0.028max 0.012min outline (unit : inch) 0.323max 0.291min 0.221max 0.197min 0-8 ? 1 2 34 56 78910 20 19 1 8 17 16 15 14 13 12 11 0.510max 0.492min 0.022max 0.014min 0.050bsc 0.002min 0.089max www.datasheet.co.kr datasheet pdf - http://www..net/
page 5 of 36 1. overview adam24pxx 16 sop(150mil) pin dimension (dimensions in millimeters) outline (unit : mm) 3.90 0.1 0-8 ? 12345678 16 15 14 13 12 11 10 9 9.90 0.1 1.27 0.43 0.076 0.18 0.076 6.00 0.18 1.64 0.1 0.22 0.025 0.65 0.23 8 sop (150mil) pin dimension (dimensions in millimeters) www.datasheet.co.kr datasheet pdf - http://www..net/
page 6 of 36 adam24pxx 1. overview 1.5. pin function pin name input output function @reset @stop input (with pull-up) input (with pull-up) r2 ~ r3 i/o -. 2-bit input only port. (input mode is set only when each of them output `h`) -. each pin has stop mode release function. -. output mode is set when each of them output `l`. -. when used as `output`, each pin can be set and reset independently. input (with pull-up) input (with pull-up) d0 ~ d3 low output -. n-ch open drain output. -. each pin can be set and reset independently. low gnd power -. ground - - d4 ~ d8 keep status before stop remout output -. high current puls e output. `hi-z` output `hi-z` output vdd power -. positive power supply. - - -. 4-bit input only port. -. cmos input with pull-up resistor. -. each pin has stop mode release function. (it is released by `l` input at stop mode.) input k0 ~ k3 r0 ~ r1 www.datasheet.co.kr datasheet pdf - http://www..net/
page 7 of 36 1. overview adam24pxx 1.6. pin circuit pin name i/o i/o circuit note k r0~r1 i - built in mos tr. for pull-up. vdd pull up resistor pad d0 ~ d8 o - open drain output. - `l` output at reset. - d0~d3 ports are `l` output at stop mode. - d4~d8 ports keep the status before stop at stop mode. gnd pad remout o - open drain output - output tr. disable at reset and stop mode. remout pad gnd r2~r3 i/o - cmods output. - `h` output at reset. - built in mos tr. for pull-up. vdd pull up resistor pad www.datasheet.co.kr datasheet pdf - http://www..net/
page 8 of 36 adam24pxx 1. overview 1.7. electrical characteristics * thermal derating above 25 : 6mw per degree rise in temperature. 1.7.1. absolute maximum ratings (ta = 25 ) parameter symbol max. rating unit supply voltage v dd -0.3 ~ 5.0 700 * input voltage v in -0.3 ~ v dd +0.3 v output voltage v out -0.3 ~ v dd +0.3 v storage temperature t stg -65 ~ 150 v power dissipation p d ? 1.7.2. recommended operating condition parameter symbol condition min. typ. max. -3.6 3.713 (+2%) 70 3.640 - v dd 1.8 v oscillation frequency f osc vdd=1.8 ~ 3.6v temp. = -20 ~ 70 3.567 (-2%) mhz -20 f osc = 3.64mhz - unit supply voltage operating temperature t opr 1.7.3. dc characteristics (ta = 25 , v dd =3v) limits parameter symbol min. typ. max. input l voltage v il1 --0.9v - d output l voltage v ol1 - 0.15 0.4 v i ol =3 ? remout output l current i ol - 250 - ? v ol =0.3v remout leakage current i olk1 --1 ? v out =v dd , output off d output leakage current i olk2 --1 ? v out =v dd , output off current on stop mode i stp --1 ? at stop mode operating supply current i dd -0.51.0 ? f osc = 3.64mhz unit --1 ? ? 120 v - 300 - 70 input h voltage v ih1 2.1 - condition input h current i ih v i =v dd input pull-up resistance r pu v i =gnd www.datasheet.co.kr datasheet pdf - http://www..net/
page 9 of 36 1. overview adam24pxx internal rc oscillator characteristics graphs (for reference only) operating voltage vs. frequency (temp=25) -2% -1% 0% +1% +2% 3.531 3.567 3.604 3.640 3.676 3.713 3.749 3.6 3.3 3 2.7 2.4 2.1 1.8 operating voltage: vdd (v) frequency: fosc (mhz) operating temperature vs. frequency (vdd=3.0v) -1% 0% +1% +2% -2% 3.531 3.567 3.604 3.640 3.676 3.713 3.749 -20 0 25 50 70 operating temperature: t() frequency: fosc (mhz ) www.datasheet.co.kr datasheet pdf - http://www..net/
page 10 of 36 adam24pxx 2. architecture 2. architecture the adam24pxx can incorporate maximum 4,096 words (4 block 16 pages 64 words 8bits) for program memory. program counter pc (a0~a5) , page address register pa(a6~a9) and block address register ba(a10~a11) are used to address the whole area of program memory having an instruction (8bits) to be next executed. the program memory consists of 64 words on each page, and thus each page can hold up to 64 steps of instructions. the program memory is composed as shown below. 2.1. program memory fig 2-1 configuration of program memory program counter (pc) page address register (pa) 10 2 (level `1`) (level `2`) (level `3`) stack register (sr) a0~a9 00 01 a10~a11 10 page buffer (pb) 4 block address register (ba) block buffer (bb) 2 block3 block2 block1 block0 (16pages x 64words x 8bit) 10 11 y-register (y) 2 y0~y1 www.datasheet.co.kr datasheet pdf - http://www..net/
page 11 of 36 adam24pxx 2. architecture the following registers are used to address the rom. ? block address register (ba) : holds rom's block number (0~3h) to be addressed. ? block buffer register (bb) : value of bb is loaded by an lbby command when newly addressing a block. then it is shifted into the ba when rightly executing a branch instruction (br) and a subroutine call (cal). ? page address register (pa) : holds rom's page number (0~fh) to be addressed. ? page buffer register (pb) : value of pb is loaded by an lpbi command when newly addressing a page. then it is shifted into the pa when rightly executing a branch instruction (br) and a subroutine call (cal). ? program counter (pc) : available for addressing word on each page. ? stack register (sr) : stores returned-word address in the subroutine call mode. 2.2. address register 2.2.1. block address register and block buffer register : address one of block #0 to #3 in the rom by the 2-bit register. unlike the program counter, the block address register is not changed automatically. to change the block address, take two steps such as (1) writing in the block buffer what block to jump (execution of lbby) and (2) execution of br or cal, because instruct ion code is of eight bits so that block can not be specified at the same time. in case a return instruction (rtn) is executed within the subroutine that has been called in the other block, the block address will be changed at the same time. www.datasheet.co.kr datasheet pdf - http://www..net/
page 12 of 36 adam24pxx 2.2.2. page address register and page buffer register : address one of pages #0 to #15 in the rom by the 4-bit binary counter. unlike the program counter, the page address register is usually unchanged so that the program will repeat on the same page unless a page changing command is issued. to change the page address, take two steps such as (1) writing in the page buffer what page to jump (execution of lpbi) and (2) execution of br or cal, because instruction code is of eight bits so that page and word can not be specified at the same time. in case a return instruction (rtn) is executed within the subroutine that has been called in the other page, the page address will be changed at the same time. 2.2.3. program counter : this 6-bit binary counter increments for each fetch to address a word in the currently addressed page having an instruction to be next executed. for easier programming, at turning on the power, the program counter is reset to the zero location. the pa is also set to `0`. then the program counter specifies the next address in random sequence. when br, cal or rtn instructions are decoded, the switches on each step are turned off not to update the address. then, for br or cal, address data are taken in from the instruction operands (a 0 to a 5 ), or for rtn, and address is fetched from stack register no. 1. 2.2.4. stack register : this stack register provides three stages each for the program counter (6bits), the page address register (4bits) and block address (2bits) so that subroutine nesting can be made on three levels. 2. architecture www.datasheet.co.kr datasheet pdf - http://www..net/
page 13 of 36 adam24pxx 2. architecture up to 32 nibbles (16 words 2pages 4bits) is incorporated for storing data. the whole data memory area is indirectly specified by a data pointer (x,y). page number is specified by zero bit of x register, and words in the page by 4 bits in y-register. data memory is composed in 16 nibbles/page. figure 2-2 shows the configuration. y-register has 4 bits. it operates as a data pointer or a general-purpose register. y-register specifies an address ( a 0 ~ a 3 ) in a page of data memory, as well as it is used to specify an output port. further it is used to specify a mode of carrier signal outputted from the remout port. it can also be treated as a general- purpose register on a program. 2.5. y-register (y) fig 2-2 composition of data memory x-register is consist of 2bit, x0 is a data pointer of page in the ram, x1 is only used for selecting of d8 ~ d9 with value of y-register 2.4. x-register (x) table2-1 mapping table between x and y register 2.3. data memory (ram) 0 1 2 3 15 output port y-register (y) x-register (x) d0~d9 remout page 0 page 1 01 4 [x0] data memory page (0~1) x1 = 0 x1 = 1 y = 0 d0 d8 y = 1 d9 d1 [x1] a0~a3 r2~r3 www.datasheet.co.kr datasheet pdf - http://www..net/
page 14 of 36 adam24pxx 2. architecture 2.6. accumulator (a cc ) the 4-bit register for holding data and calculation results. 2.7. arithmetic and logic unit (alu) in this unit, 4bits of adder/comparator are connected in parallel as it's main components and they are combined with status latch and status logic (flag.) 2.7.1. operation circuit (alu) : the adder/comparator serves fundamentally for full addition and data comparison. it executes subtraction by making a complement by processing an inversed output of a cc (a cc +1) 2.7.2. status logic : this is to bring an st, or flag to control the flow of a program. it occurs when a specified instruction is executed in three cases such as overflow or underflow in operation and two inputs unequal. www.datasheet.co.kr datasheet pdf - http://www..net/
page 15 of 36 adam24pxx 2. architecture 2.8. clock generator the adam24pxx has an internal rc oscillator which has 3.64mhz frequency only. the oscillator circuit is designed to operat e without an external ceramic resonator. the internal oscillator is calibrate in factor y. in stop mode, internal oscillator is stopped. 2.9. pulse generator the following frequency and duty ratio are selected for carrier signal outputted from the remout port depending on a pmr (pulse mode register) value set in a program. * default value is `0` table 2-2 pmr selection table t t1 pmr remout signal 0t = 1 / f pul = [ 96/f osc ], t1/t = 1/2 1t = 1 / f pul = [ 96/f osc ], t1/t = 1/3 2t = 1 / f pul = [ 64/f osc ], t1/t = 1/2 3t = 1 / f pul = [ 64/f osc ], t1/t = 1/4 4t = 1 / f pul = [ 88/f osc ], t1/t = 4/11 5 no pulse (same to d0~d9) 6t = 1 / f pul = [ 96/f osc ], t1/t = 1/4 7t = 1 / f pul = [ 92/f osc ], t1/t = 1/2 www.datasheet.co.kr datasheet pdf - http://www..net/
page 16 of 36 adam24pxx 2. architecture 2.10. reset operation adam24pxx has three reset sources. one is a built-in low vdd detection circuit, another is the overflow of watch dog timer (wdt), the other is the overflow of stack. all reset operations are internal in the adam24pxx. 2.11. built-in low vdd reset circuit adam24pxx has a low vdd detection circuit. if vdd becomes reset voltage of low vdd detection circuit in a active status, system reset occur and wdt is cleared. when vdd is increased over reset voltage again, wdt is re-counted until wdt overflow, system reset is released. fig 2-3 low voltage detection timing chart. vdd reset voltage about 108msec at f osc = 3.64mhz internal resetb www.datasheet.co.kr datasheet pdf - http://www..net/
page 17 of 36 adam24pxx 2. architecture 2.12. watch dog timer (wdt) watch dog timer is organized binary of 14 steps. the signal of f osc /48 cycle comes in the first step of wdt after wdt reset. if this counter was overflowed, reset signal automatically comes out so that internal circuit is initialized. the overflow time is 8 6 2 13 /f osc (108.026ms at f osc = 3.64mhz) normally, the binary counter must be reset before the overflow by using reset instruction (wdtr), power-on reset pulse or low vdd detection pulse. * it is constantly reset in stop mode. when stop is released, counting is restarted. ( refer to 2.14. stop operation) fig 2-4 block diagram of watch-dog timer binary counter(14 steps) reset by instruction (wdtr) f osc /48 power-on reset stop mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 cpu reset 1 reset ( edge-trigger ) www.datasheet.co.kr datasheet pdf - http://www..net/
page 18 of 36 adam24pxx 2. architecture 2.13. stop operation stop mode can be achieved by stop instructions. in stop mode : 1. oscillator is stopped, the operating current is low. 2. watch dog timer is reset and remout output is `high-z` . 3. part other than wdt and remout output have a value before come into stop mode. 4. d0~d3 output are `low` at stop mode. 5. d4~d9 output keep the status before stop at stop mode. stop mode is released when one of k or r input is going to `low`. when stop mode released : 1. state of d0~d3 output and remout output is return to state of before stop mode is achieved. 2. after 8 6 2 10 /f osc time for stable oscillating, first instruction start to operate. 3. in return to normal operation, wdt is counted from zero. when executing stop instruction, if any one of k,r input is `low` state, stop instruction is same to nop instruction. 2.14. port operation so : d(9) 1 (high-z) ro : d(9) 0 so : d(8) 1 (high-z) ro : d(8) 0 so : d0 ~ d9 1 (high-z) ro : d0 ~ d9 0 remout port repeats `h` and `l` in pulse frequency. (when pmr=5, it is fixed at `h` or `l`) so : remout(pmr) 0 ro : remout(pmr) 1 (high-z) so : d(y) 1 (high-z) ro : d(y) 0 operation 9 0 2 or 3 1 8 0 ~ 7 0 or 1 value of y - reg value of x - reg so : r2(y = c), r3(y = d) 1 ro : r2(y = c), r3(y = d) 0 c~d so : d0 ~ d9 1 (high-z), r2~r3 1 ro : d0 ~ d9 0, r2~r3 0 f so : r2 ~ r3 1 ro : r2 ~ r3 0 e www.datasheet.co.kr datasheet pdf - http://www..net/
page 19 of 36 adam24pxx 3.1. instruction format all of the 43 instruction in adam24pxx is format in two fields of op code and operand which consist of eight bits. the following formats are available with different types of operands. *format all eight bits are for op code without operand. *format two bits are for operand and six bits for op code. two bits of operand are used for specifying bits of ram and x-register (bit 1 and bit 7 are fixed at 0 ) *format four bits are for operand and the others are op code. four bits of operand are used for specifying a constant loaded in ram or y- register, a comparison value of compare command, or page addressing in rom. *format six bits are for operand and the others are op code. six bits of operand are used for word addressing in the rom. 3. instruction 3. instruction www.datasheet.co.kr datasheet pdf - http://www..net/
page 20 of 36 adam24pxx 3. instruction 3.2. instruction table the adam24pxx provides the following 43 basic instructions. category 1 2 3 register to register lay lya laz mnemonic a y function y a a 0 s s s st *1 4 5 6 ram to register lma lmaiy lym m(x,y) a m(x,y) a, y y+1 y m(x,y) s s s 7 8 lam xma a m(x,y) a ? m(x,y) s s 9 10 11 immediate lyi i lmiiy i lxi n y i m(x,y) i, y y+1 x n s s s 12 13 14 ram bit manipulation sem n rem n tm n m(n) 1 m(n) 0 test m(n) = 1 s s e 15 16 17 rom address br a cal a rtn if st = 1 then branch if st = 1 then subroutine call return from subroutine s s s 18 lpbi i pb is 21 22 23 arithmetic am sm im a m(x,y) + a a m(x,y) - a a m(x,y) + 1 c b c 24 25 dm ia a m(x,y) - 1 a a + 1 b s 26 27 iy da y y + 1 a a - 1 c b 19 lbby bb ys 20 ldway ay [@xay] s www.datasheet.co.kr datasheet pdf - http://www..net/
page 21 of 36 adam24pxx 3. instruction note) i = 0~f, n = 0~3, a = 6bit pc address *1 column st indicates conditions for changing status. symbols have the following meanings s : on executing an instruction, status is unconditionally set. c : status is only set when carry or borrow has occurred in operation. b : status is only set when borrow has not occurred in operation. e : status is only set when equality is found in comparison. n : status is only set when equality is not found in comparison. z : status is only set when the result is zero. *2 refer to 2.14. port operation. category 28 29 30 arithmetic dy eorm nega mnemonic y y - 1 function b s z st *1 a a + m (x,y) a a + 1 31 32 comparison alem alei i test a m(x,y) test a i e e 33 34 mnez ynea test m(x,y) 0 test y a n n 35 ynei i test y i n 36 37 input / output lak lar a k a r s s 38 39 so ro output(y) 1 *2 output(y) 0 *2 s s 40 41 control wdtr stop watch dog timer reset stop operation s s 42 43 lpy nop pmr y no operation s s www.datasheet.co.kr datasheet pdf - http://www..net/
page 22 of 36 adam24pxx 3. instruction 3.3. details of instruction system all 43 basic instructions of the adam24pxx are one by one described in detail below. description form each instruction is headlined with its mnemonic symbol according to the instructions table given earlier. then, for quick reference, it is described with basic items as shown below. after that, detailed comment follows. ?items : - naming : full spelling of mnemonic symbol - status : check of status function - format : categorized into to - operand : omitted for format - function www.datasheet.co.kr datasheet pdf - http://www..net/
page 23 of 36 adam24pxx 3. instruction (1) lay naming : load accumulator from y-register status : set format : i function : a y data of four bits in the y-register is unconditionally transferred to the accumulator. data in the y-register is left unchanged. (2) lya naming : load y-register from accumulator status : set format : i function : y a load y-register from accumulator (3) laz naming : clear accumulator status : set format : i function : a 0 data in the accumulator is unconditionally reset to zero. (4) lma naming : load memory from accumulator status : set format : i function : m(x,y) a data of four bits from the accumulator is stored in the ram location addressed by the x-register and y-register. such data is left unchanged. (5) lmaiy naming : load memory from accumulator and increment y-register status : set format : i function : m(x,y) a, y y+1 data of four bits from the accumulator is stored in the ram location addressed by the x-register and y-register. such data is left unchanged. www.datasheet.co.kr datasheet pdf - http://www..net/
page 24 of 36 adam24pxx 3. instruction (6) lym naming : load y-register form memory status : set format : i function : y m(x,y) data from the ram location addressed by the x-register and y-register is loaded into the y-register. data in the memory is left unchanged. (7) lam naming : load accumulator from memory status : set format : i function : a m(x,y) data from the ram location addressed by the x-register and y-register is loaded into the y-register. data in the memory is left unchanged. (8) xma naming : exchanged memory and accumulator status : set format : i function : m(x,y) ? a data from the memory addressed by x-register and y-register is exchanged with data from the accumulator. for example, this instruction is useful to fetch a memory word into the accumulator for operation and store current data from the accumulator into the ram. the accumulator can be restored by another xma instruction. (9) lyi i naming : load y-register from immediate status : set format : operand : constant 0 i 15 function : y i to load a constant in y-register. it is typically used to specify y-register in a particular ram word address, to specify the address of a selected output line, to set y-register for specifying a carrier signal outputted from out port, and to initialize y-register for loop control. the accumulator can be restored by another xma instruction. data of four bits from operand of instruction is transferred to the y-register. www.datasheet.co.kr datasheet pdf - http://www..net/
page 25 of 36 adam24pxx 3. instruction (10) lmiiy i naming : load memory from immediate and increment y-register status : set format : operand : constant 0 i 15 function : m(x,y) i, y y + 1 data of four bits from operand of instruction is stored into the ram location addressed by the x-register and y-register. then data in the y-register is incremented by one. (11) lxi n naming : load x-register from immediate status : set format : operand : x file address 0 n 3 function : x n a constant is loaded in x-register. it is used to set x-register in an index of desired ram page. operand of 1 bit of command is loaded in x-register. (12) sem n naming : set memory bit status : set format : operand : bit address 0 n 3 function : m(x,y,n) 1 depending on the selection in operand of operand, one of four bits is set as logic 1 in the ram memory addressed in accordance with the data of the x-register and y-register. (13) rem n naming : reset memory bit status : set format : operand : bit address 0 n 3 function : m(x,y,n) 0 depending on the selection in operand of operand, one of four bits is set as logic 0 in the ram memory addressed in accordance with the data of the x-register and y-register. www.datasheet.co.kr datasheet pdf - http://www..net/
page 26 of 36 adam24pxx 3. instruction (14) tm n naming : test memory bit status : comparison results to status format : operand : bit address 0 n 3 function : m(x,y,n) 1? st 1 when m(x,y,n)=1, st 0 when m(x,y,n)=0 a test is made to find if the selected memory bit is logic. 1 status is set depending on the result. (15) br a naming : branch on status 1 status : conditional depending on the status format : operand : branch address a (addr) function : when st =1 : ba bb, pa pb, pc a (addr) when st = 0 : pc pc + 1, st 1 note : pc indicates the next address in a fixed sequence that is actually pseudo-random count. for some programs, normal sequential program execution can be change. a branch is conditionally implemented depending on the status of results obtained by executing the previous instruction. branch instruction is always conditional depending on the status. a. if the status is reset (logic 0), a branch instruction is not rightly executed but the next instruction of the sequence is executed. b. if the status is set (logic 1), a branch instruction is executed as follows. branch is available in two types - short and long. the former is for addressing in the current page and the latter for addressing in other block/page. which type of branch to execute is decided according to the bb and pb register. to execute a long branch, data of the bb or pb register should in advance be modified to a desired block/page address through the lbby or lpbi instruction. www.datasheet.co.kr datasheet pdf - http://www..net/
page 27 of 36 adam24pxx 3. instruction (16) cal a naming : subroutine call on status 1 status : conditional depending on the status format : operand : subroutine code address a (addr) function : when st =1 : pc a (addr) pa pb ba bb sr1 pc + 1 psr1 pa bsr1 ba sr2 sr1 psr2 psr1 bsr2 bsr1 sr3 sr2 psr3 psr2 bsr3 bsr2 when st = 0 : pc pc + 1 pa pa ba ba st 1 note : pc actually has pseudo-random count against the next instruction. in a program, control is allowed to be transferred to a mutual subroutine. since a call instruction preserves the return address, it is possible to call the subroutine from different locations in a program, and the subroutine can return control accurately to the address that is preserved by the use of the call return instruction (rtn). such calling is always conditional depending on the status. a. if the status is reset, call is not executed. b. if the status is set, call is rightly executed. the subroutine stack (sr) of three levels enables a subroutine to be manipulated on three levels. besides, a long call (to call another page) can be executed on any level. for a long call, lbby or lpbi instruction should be executed before the cal. when lbby or lpbi is omitted (and when ba=bb and pa=pb), a short call (calling in the same page) is executed. (17) rtn naming : return from subroutine status : set format : function : pc sr1 pa, pb psr1 ba, bb bsr1 sr1 sr2 psr1 psr2 bsr1 bsr2 sr2 sr3 psr2 psr3 bsr2 bsr3 sr3 sr3 psr3 psr3 bsr3 bsr3 st 1 control is returned from the called subroutine to the calling program. control is returned to its home routine by transferring to the pc the data of the return address that has been saved in the stack register (sr1). at the same time, data of the page stack register (psr1) is transferred to the pa and pb, and data of the block stack register(bsr1) is transferred to the ba and bb. www.datasheet.co.kr datasheet pdf - http://www..net/
page 28 of 36 adam24pxx 3. instruction (18) lpbi i naming : load page buffer register from immediate status : set format : operand : rom page address 0 i 15 function : pb i a new rom page address is loaded into the page buffer register (pb). this loading is necessary for a long branch or call instruction. the pb register is loaded together with three bits from 4 bit operand. (19) lbby naming : load block buffer register from y-register. status : set format : i function : bb y a new rom page address is loaded into the block buffer register (bb). this loading is necessary for a long branch or call instruction. the bb register is loaded two bits(y[1:0]) in the y-register. data in the y-register is left unchanged. (20) ldway naming : load word from rom addressed by xay-register. status : set format : i function : sr1 pc + 1 psr1 pa bsr1 ba sr2 sr1 psr2 psr1 bsr2 bsr1 sr3 sr2 psr3 psr2 bsr3 bsr2 pa,pc xay(addr) ay [@xay] a msb 4-bit of [@xay] y lsb 4-bit of [@xay] pc sr1 pa, pb psr1 ba bsr1 sr1 sr2 psr1 psr2 bsr1 bsr2 sr2 sr3 psr2 psr3 bsr2 bsr3 sr3 sr3 psr3 psr3 bsr3 bsr3 data transfer from rom to ay-register. the a register is loaded higher four bits in the rom, and the y register is loaded lower four bits in the rom. www.datasheet.co.kr datasheet pdf - http://www..net/
page 29 of 36 adam24pxx 3. instruction (21) am naming : add accumulator to memory and status 1 on carry status : carry to status format : function : a m(x,y) + a st 1(when total>15), st 0 (when total 15) data in the memory location addressed by the x and y-register is added to data of the accumulator. results are stored in the accumulator. carry data as results is transferred to status. when the total is more than 15, a carry is caused to put 1 in the status. data in the memory is not changed. (22) sm naming : subtract accumulator to memory and status 1 not borrow status : carry to status format : function : a m(x,y) - a st 1(when a m(x,y)) st 0(when a > m(x,y)) data of the accumulator is, through a 2`s complement addition, subtracted from the memory word addressed by the y-register. results are stored in the accumulator. if data of the accumulator is less than or equal to the memory word, the status is set to indicate that a borrow is not caused. if more than the memory word, a borrow occurs to reset the status to 0 . (23) im naming : increment memory and status 1 on carry status : carry to status format : function : a m(x,y) + 1 st 1(when m(x,y) 15) st 0(when m(x,y) < 15) data of the memory addressed by the x and y-register is fetched. adding 1 to this word, results are stored in the accumulator. carry data as results is transferred to the status. when the total is more than 15, the status is set. the memory is left unchanged. (24) dm naming : decrement memory and status 1 on not borrow status : carry to status format : function : a m(x,y) - 1 st 1(when m(x,y) 1) st 0 (when m(x,y) = 0) data of the memory addressed by the x and y-register is fetched, and one is subtracted from this word (addition of fh). results are stored in the accumulator. carry data as results is transferred to the status. if the data is more than or equal to one, the status is set to indicate that no borrow is caused. the memory is left unchanged. www.datasheet.co.kr datasheet pdf - http://www..net/
page 30 of 36 adam24pxx 3. instruction (25) ia naming : increment accumulator status : set format : function : a a+1 data of the accumulator is incremented by one. results are returned to the accumulator. a carry is not allowed to have effect upon the status. (26) iy naming : increment y-register and status 1 on carry status : carry to status format : function : y y + 1 st 1 (when y = 15) st 0 (when y < 15) data of the y-register is incremented by one and results are returned to the y-register. carry data as results is transferred to the status. when the total is more than 15, the status is set. (27) da naming : decrement accumulator and status 1 on borrow status : carry to status format : function : a a - 1 st 1(when a 1) st 0 (when a = 0) data of the accumulator is decremented by one. as a result (by addition of fh), if a borrow is caused, the status is reset to 0 by logic. if the data is more than one, no borrow occurs and thus the status is set to 1 . www.datasheet.co.kr datasheet pdf - http://www..net/
page 31 of 36 adam24pxx 3. instruction (28) dy naming : decrement y-register and status 1 on not borrow status : carry to status format : function : y y -1 st 1 (when y 1) st 0 (when y = 0) data of the y-register is decremented by one. data of the y-register is decremented by one by addition of minus 1 (fh). carry data as results is transferred to the status. when the results is equal to 15, the status is set to indicate that no borrow has not occurred. (29) eorm naming : exclusive or memory and accumulator status : set format : function : a m(x,y) + a data of the accumulator is, through a exclusive or, subtracted from the memory word addressed by x and y- register. results are stored into the accumulator. (30) nega naming : negate accumulator and status 1 on zero status : carry to status format : function : a a + 1 st 1(when a = 0) st 0 (when a != 0) the 2`s complement of a word in the accumulator is obtained. the 2`s complement in the accumulator is calculated by adding one to the 1`s complement in the accumulator. results are stored into the accumulator. carry data is transferred to the status. when data of the accumulator is zero, a carry is caused to set the status to 1 . www.datasheet.co.kr datasheet pdf - http://www..net/
page 32 of 36 adam24pxx 3. instruction (31) alem naming : accumulator less equal memory status : carry to status format : function : a m(x,y) st 1 (when a m(x,y)) st 0 (when a > m(x,y)) data of the accumulator is, through a complement addition, subtracted from data in the memory location addressed by the x and y-register. carry data obtained is transferred to the status. when the status is 1 , it indicates that the data of the accumulator is less than or equal to the data of the memory word. neither of those data is not changed. (32) alei naming : accumulator less equal immediate status : carry to status format : function : a is t 1 (when a i) st 0 (when a > i) data of the accumulator and the constant are arithmetically compared. data of the accumulator is, through a complement addition, subtracted from the constant that exists in 4bit operand. carry data obtained is transferred to the status. the status is set when the accumulator value is less than or equal to the constant. data of the accumulator is left unchanged. (33) mnez naming : memory not equal zero status : comparison results to status format : function : m(x,y) 0s t 1(when m(x,y) 0) st 0 (when m(x,y) = 0) a memory word is compared with zero. data in the memory addressed by the x and y-register is logically compared with zero. comparison data is transferred to the status. unless it is zero, the status is set. www.datasheet.co.kr datasheet pdf - http://www..net/
page 33 of 36 adam24pxx 3. instruction (34) ynea naming : y-register not equal accumulator status : comparison results to status format : function : y as t 1 (when y a) st 0 (when y = a) data of y-register and accumulator are compared to check if they are not equal. data of the y-register and accumulator are logically compared. results are transferred to the status. unless they are equal, the status is set. (35) ynei naming : y-register not equal immediate status : comparison results to status format : operand : constant 0 i 15 function : y is t 1 (when y i) st 0 (when y = i) the constant of the y-register is logically compared with 4bit operand. results are transferred to the status. unless the operand is equal to the constant, the status is set. (36) lak naming : load accumulator from k status : set format : function : a k data on k are transferred to the accumulator (37) lar naming : load accumulator from r status : set format : function : a r data on r are transferred to the accumulator www.datasheet.co.kr datasheet pdf - http://www..net/
page 34 of 36 adam24pxx 3. instruction (38) so naming : set output register latch status : set format : function : d(y) 10 y 7 remout 1(pmr=5) y = 8 d0~d9 1 (high-z) y = 9 r(y) 1c h y dh r(y) 1 y = eh d0~d9, r2~r3 1 y = fh a single d output line is set to logic 1, if data of y-register is between 0 to 7. carrier frequency come out from remout port, if data of y-register is 8. all d output line is set to logic 1, if data of y-register is 9. when y is between ch and dh, one of r2 and r3 is set to logic 1. when y is eh, r2 and r3 is set to logic 1. when y is fh, all d output and r2 and r3 is set to logic 1. data of y-register is between 0 to 7, selects appropriate d output. data of y-register is 8, selects remout port. data of y-register is 9, selects all d port. data in y-register, when between ch and dh, selects an appropriate r port. data in y-register, when it is eh, selects all of r2~r3. data in y-register, when it is fh, selects all of d0~d9 and r2~r3. (38) ro naming : set output register latch status : set format : function : d(y) 00 y 7 remout 0(pmr=5) y = 8 d0~d9 0y = 9 r(y) 0c h y dh r(y) 0 y = eh d0~d9,r2~r3 0 y = fh a single d output line is set to logic 0, if data of y-register is between 0 to 7. remout port is set to logic 0, if data of y-register is 8. all d output line is set to logic 0, if data of y-register is 9. when y is between ch and dh, one of r2 and r3 is set to logic 0. when y is eh, r2 and r3 is set to logic 0. when y is fh, all d output and r2 and r3 is set to logic 0. data of y-register is between 0 to 7, selects appropriate d output. data of y-register is 8, selects remout port. data of y-register is 9, selects all d port. data in y-register, when between ch and dh, selects an appropriate r port. data in y-register, when it is eh, selects all of r2~r3. data in y-register, when it is fh, selects all of d0~d9 and r2~r3. www.datasheet.co.kr datasheet pdf - http://www..net/
page 35 of 36 adam24pxx 3. instruction (40) wdtr naming : watch dog timer reset status : set format : function : reset watch dog timer (wdt) normally, you should reset this counter before overflowed counter for dc watch dog timer. this instruction controls this reset signal. (41) stop naming : stop status : set format : function : operate the stop function stopped oscillator, and little current. (42) lpy naming : pulse mode set status : set format : function : pmr y selects a pulse signal outputted from remout port. (43) nop naming : no operation status : set format : function : no operation www.datasheet.co.kr datasheet pdf - http://www..net/
page 36 of 36 adam24pxx 3. instruction (1) all rams need to be initialized to any value in reset address for proper design. (2) make the output ports `high` after reset. (3) do not use wdtr instruction in subroutine. (4) when you try to read input port changed from external condition, you must secure chattering time more than 200us. (5) to decrease current consumption, make the output port as high in normal routine except for key scan strobe and stop mode. (6) we recommend you do not use all 64 rom bytes in a page. it?s recommend to add `br $` at fi rst and last address of each page. do not add `br $` at reset address which is first address of `00` page of `0` bank. (7) `nop` instruction should be follows stop instruction for pre-charge time of data bus line. ex) stop : stop instruction execution nop : nop instruction 3.4. guideline for s/w www.datasheet.co.kr datasheet pdf - http://www..net/

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