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features description applications tps65021 slvs613 ? october 2005 power management ic for li-ion powered systems 1.2 a, 97% efficient step-down converter for the tps65021 is an integrated power management system voltage (vdcdc1) ic for applications powered by one li-ion or li-polymer cell, and which require multiple power 1 a, up to 95% efficient step-down converter rails. the tps65021 provides three highly efficient, for memory voltage (vdcdc2) step-down converters targeted at providing the core 800 ma, 90% efficient step-down converter voltage, peripheral, i/o and memory rails in a for processor core (vdcdc3) processor based system. all three step-down 30 ma ldo/switch for real time clock converters enter a low-power mode at light load for maximum efficiency across the widest possible range (vrtc) of load currents. the tps65021 also integrates two 2 200 ma general-purpose ldo general-purpose 200 ma ldo voltage regulators, dynamic voltage management for processor which are enabled with an external input pin. each core ldo operates with an input voltage range between 1.5 v and 6.5 v, allowing them to be supplied from preselectable ldo voltage using two digital one of the step-down converters or directly from the input pins battery. the default output voltage of the ldos can externally adjustable reset delay time be digitally set to 4 different voltage combinations battery backup functionality using the defldo1 and defldo2 pins. the serial interface can be used for dynamic voltage scaling, separate enable pins for inductive converters masking interrupts, or for dis/enabling and setting the i 2 c? compatible serial interface ldo output voltages. the interface is compatible with 85- m a quiescent current the fast/standard mode i 2 c specification, allowing transfers at up to 400 khz. the tps65021 is low ripple pfm mode available in a 40-pin (rha) qfn package, and thermal shutdown protection operates over a free-air temperature of -40 c to 40-pin 6 mm x 6 mm qfn package 85 c. pda cellular/smart phone internet audio player digital still camera digital radio player split supply dsp and m p solutions: omap1610, omap1710, omap330, xscale bulverde, samsung arm-based processors, etc. intel pxa270, etc. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. powerpad is a trademark of texas instruments. i 2 c is a trademark of philips electronics. production data information is current as of publication date. copyright ? 2005, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. www .ti.com
absolute maximum ratings (1) dissipation ratings recommended operating conditions tps65021 slvs613 ? october 2005 these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. ordering information t a package (1) part number (2) ?40 c to 85 c 40 pin qfn (rha) tps65021rha (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti web site at www.ti.com . (2) the rha package is available in tape and reel. add the r suffix (tps65021rhar) to order quantities of 2500 parts per reel. add the t suffix (tps65021rhat) to order quantities of 250 parts per reel. over operating free-air temperature range (unless otherwise noted) value unit v i input voltage range on all pins except agnd and pgnd pins with respect to agnd ?0.3 to 7 v current at vindcdc1, l1, pgnd1, vindcdc2, l2, pgnd2, vindcdc3, l3, pgnd3 2000 ma peak current at all other pins 1000 ma continuous total power dissipation see dissipation rating table t a operating free-air temperature ?40 to 85 c t j maximum junction temperature 125 c t stg storage temperature ?65 to 150 c lead temperature 1,6 mm (1/16-inch) from case for 10 seconds 260 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability t a 25 c derating factor t a = 70 c t a = 85 c package power rating above t a = 25c power rating power rating rha (1) (2) 2.85 w 28 mw/ c 1.57 w 1.4 w (1) the thermal resistance junction to ambient of the rha package is 35 c/w measured on a high k board. (2) the thermal resistance junction to case (exposed pad) of the rha package is 5 c/w over operating free-air temperature range (unless otherwise noted) min nom max unit input voltage range step-down convertors v cc 2.5 6 v (vindcdc1, vindcdc2, vindcdc3) output voltage range for vdcdc1 step-down convertor (1) 0.6 vindcdc1 v o output voltage range for vdcdc2 (mem) step-down convertor (1) 0.6 vindcdc2 v output voltage range for vdcdc3 (core) step-down convertor (1) 0.6 vindcdc3 v i input voltage range for ldos (vinldo1, vinldo2) 1.5 6.5 v v o output voltage range for ldos (vldo1, vldo2) 1 vinldo1-2 v i o(dcdc2) output current at l1 1200 ma inductor at l1 (2) 2.2 3.3 m h c i(dcdc1) input capacitor at vindcdc1 (2) 10 m f c o(dcdc1) output capacitor at vdcdc1 (2) 10 22 m f i o(dcdc2) output current at l2 1000 ma (1) when using an external resistor divider at defdcdc3, defdcdc2, defdcdc1 (2) see applications section for more information. 2 www .ti.com
electrical characteristics tps65021 slvs613 ? october 2005 recommended operating conditions (continued) over operating free-air temperature range (unless otherwise noted) min nom max unit inductor at l2 (2) 2.2 3.3 m h c i(dcdc2) input capacitor at vindcdc2 (2) 10 m f c o(dcdc2) output capacitor at vdcdc2 (2) 10 22 m f i o(dcdc3) output current at l3 800 ma inductor at l3 (2) 2.2 3.3 m h c i(dcdc3) input capacitor at vindcdc3 (2) 10 m f c o(dcdc3) output capacitor at vdcdc3 (2) 10 22 m f c i(vcc) input capacitor at vcc (2) 1 m f c i(vinldo) input capacitor at vinldo (2) 1 m f c o(vldo1-2) output capacitor at vldo1, vldo2 (2) 2.2 m f i o(vldo1-2) output current at vldo1, vldo2 200 ma c o(vrtc) output capacitor at vrtc (2) 4.7 m f t a operating ambient temperature -40 85 c t j operating junction temperature -40 125 c resistor from vindcdc3, vindcdc2, vindcdc1 to vcc used for filtering (3) 1 10 w (3) up to 3 ma can flow into v cc when all 3 converters are running in pwm. this resistor causes the uvlo threshold to be shifted accordingly. vindcdc1 = vindcdc2 = vindcdc3 = vcc = vinldo = 3.6 v, vbackup = 3 v, t a = ?40 c to 85 c, typical values are at t a = 25 c (unless otherwise noted) parameter test conditions min typ max unit control signals : sclk, sdat (input), dcdc1_en, dcdc2_en, dcdc3_en, ldo_en, defldo1, defldo2 rpullup at sclk and sdat = 4.7 kr, v ih high level input voltage 1.3 vcc v pulled to vrtc rpullup at sclk and sdat = 4.7 kr, v il low level input voltage 0 0.4 v pulled to vrtc i h input bias current 0.01 0.1 m a control signals : hot_reset v ih high level input voltage 1.3 vcc v v il low level input voltage 0 0.4 v i ib input bias current 0.01 0.1 m a t glitch deglitch time at hot_reset 25 30 35 ms control signals : lowbat, pwrfail, respwron, int, sdat (output) v oh high level output voltage 6 v v ol low level output voltage i il = 5 ma 0 0.3 v duration of low pulse at respwron external capacitor 1 nf 100 ms resetpwron threshold vrtc falling ?3% 2.4 3% v resetpwron threshold vrtc rising ?3% 2.52 3% v 3 www .ti.com
electrical characteristics tps65021 slvs613 ? october 2005 vindcdc1 = vindcdc2 = vindcdc3 = vcc = vinldo = 3.6 v, vbackup = 3 v, t a = ?40 c to 85 c, typical values are at t a = 25 c (unless otherwise noted) parameter test conditions min typ max unit supply pins: vcc, vindcdc1, vindcdc2, vindcdc3 all 3 dcdc converters enabled, vcc = 3.6 v, vbackup = 3 v; zero load and no switching, ldos vvsysin = 0 v 85 100 enabled all 3 dcdc converters enabled, vcc = 3.6 v, vbackup = 3 v; zero load and no switching, ldos vvsysin = 0 v 78 90 operating quiescent off i (qpfm) m a current, pfm dcdc1 and dcdc2 converters vcc = 3.6 v, vbackup = 3 v; enabled, zero load and no vvsysin = 0 v 57 70 switching, ldos off dcdc1 converter enabled, zero vcc = 3.6 v, vbackup = 3 v; 43 55 load and no switching, ldos off vvsysin = 0 v all 3 dcdc converters enabled vcc = 3.6 v, vbackup = 3 v; 2 3 and running in pwm, ldos off vvsysin = 0 v dcdc1 and dcdc2 converters vcc = 3.6 v, vbackup = 3 v; current into vcc; i i enabled and running in pwm, vvsysin = 0 v 1.5 2.5 ma pwm ldos off dcdc1 converter enabled and vcc = 3.6 v, vbackup = 3 v; 0.85 2 running in pwm, ldos off vvsysin = 0 v vcc = 3.6 v, vbackup = 3 v; 23 33 m a vvsysin = 0 v vcc = 2.6 v, vbackup = 3 v; i (q) quiescent current all converters disabled, ldos off 3.5 5 m a vvsysin = 0 v vcc = 3.6 v, vbackup = 3 v; 43 m a vvsysin = 0 v 4 www .ti.com
electrical characteristics tps65021 slvs613 ? october 2005 vindcdc1 = vindcdc2 = vindcdc3 = vcc = vinldo = 3.6 v, vbackup = 3 v, t a = ?40 c to 85 c, typical values are at t a = 25 c (unless otherwise noted) parameter test conditions min typ max unit supply pins: vbackup, vsysin, vrtc vbackup = 3 v, vsysin = 0 v; i (q) operating quiescent current 20 33 m a vcc = 2.6 v, current into vbackup vbackup < v_vbackup, current into i (sd) operating quiescent current 2 3 m a vbackup vrtc ldo output voltage vsysin = vbackup = 0 v, i o = 0 ma 3 v i o output current for vrtc vsysin < 2.57 v and vbackup < 2.57 v 30 ma vrtc short-circuit current limit vrtc = gnd; vsysin = vbackup = 0 v 100 ma maximum output current at vrtc for vrtc > 2.6 v, v cc = 3 v; 30 ma respwron = 1 vsysin = vbackup = 0 v v o output voltage accuracy for vrtc vsysin = vbackup = 0 v; io = 0 ma -1% 1% line regulation for vrtc vcc = vrtc + 0.5 v to 6.5 v, i o = 5 ma -1% 1% i o = 1 ma to 30 ma; load regulation vrtc -3% 1% vsysin = vbackup = 0 v regulation time for vrtc load change from 10% to 90% 10 m s i lkg input leakage current at vsysin vsysin < v_vsysin 2 m a r ds(on) of vsysin switch 12.5 w r ds(on) of vbackup switch 12.5 w input voltage range at vbackup (1) 2.73 3.75 v input voltage range at vsysin (1) 2.73 3.75 v vsysin threshold vsysin falling ?3% 2.55 3% v vsysin threshold vsysin rising ?3% 2.65 3% v vbackup threshold vbackup falling ?3% 2.55 3% v vbackup threshold vbackup falling ?3% 2.65 3% v supply pin: vinldo i (q) operating quiescent current current per ldo into vinldo 16 30 m a total current for both ldos into vinldo, i (sd) shutdown current 0.1 1 m a vldo = 0 v (1) based on the requirements for the intel pxa270 processor. 5 www .ti.com
electrical characteristics tps65021 slvs613 ? october 2005 vindcdc1 = vindcdc2 = vindcdc3 = vcc = vinldo = 3.6 v, vbackup = 3 v, t a = ?40 c to 85 c, typical values are at t a = 25 c (unless otherwise noted) parameter test conditions min typ max unit vdcdc1 step-down converter v i input voltage range, vindcdc1 2.5 6.0 v i o maximum output current 1200 ma i (sd) shutdown supply current in vindcdc1 dcdc1_en = gnd 0.1 1 m a r ds(on) p-channel mosfet on-resistance vindcdc1 = v (gs) = 3.6 v 125 261 m w i lkg p-channel leakage current vindcdc1 = 6 v 2 m a r ds(on) n-channel mosfet on-resistance vindcdc1 = v (gs) = 3.6 v 130 260 m w i lkg n-channel leakage current v (ds) = 6 v 7 10 m a forward current limit (p- and n-channel) 2.5 v < v i(main) < 6 v 1.55 1.75 1.95 a f s oscillator frequency 1.3 1.5 1.7 mhz vindcdc1 = 3.3 v to 6 v; 3 v ?2% 2% 0 ma i o 1.2 a fixed output voltage fpwmdcdc1=0 vindcdc1 = 3.6 v to 6 v; 3.3 v ?2% 2% 0 ma i o 1.2 a vindcdc1 = 3.3 v to 6 v; 3 v ?1% 1% 0 ma i o 1.2 a fixed output voltage fpwmdcdc1=1 vindcdc1 = 3.6 v to 6 v; 3.3 v ?1% 1% 0 ma i o 1.2 a adjustable output voltage with resistor vindcdc1 = vdcdc1 +0.3 v (min 2.5 v) ?2% 2% divider at defdcdc1; fpwmdcdc1=0 to 6 v; 0 ma i o 1.2 a adjustable output voltage with resistor vindcdc1 = vdcdc1 +0.3 v (min 2.5 v) ?1% 1% divider at defdcdc1; fpwmdcdc1=1 to 6 v; 0 ma i o 1.2 a vindcdc1 = vdcdc1 + 0.3 v (min. 2.5 v) line regulation 0 %/v to 6 v; i o = 10 ma load regulation i o = 10 ma to 1200 ma 0.25 %/a vdcdc1 ramping from 5% to 95% of target soft start ramp time 750 m s value internal resistance from l1 to gnd 1 m w vdcdc1 discharge resistance dcdc1 discharge = 1 300 w 6 www .ti.com
electrical characteristics tps65021 slvs613 ? october 2005 vindcdc1 = vindcdc2 = vindcdc3 = vcc = vinldo = 3.6 v, vbackup = 3 v, t a = ?40 c to 85 c, typical values are at t a = 25 c (unless otherwise noted) parameter test conditions min typ max unit vdcdc2 step-down converter v i input voltage range, vindcdc2 2.5 6 v i o maximum output current 1000 ma i (sd) shutdown supply current in vindcdc2 dcdc2_en = gnd 0.1 1 m a r ds(on) p-channel mosfet on-resistance vindcdc2 = v (gs) = 3.6 v 140 300 m w i lkg p-channel leakage current vindcdc2 = 6 v 2 m a r ds(on) n-channel mosfet on-resistance vindcdc2 = v (gs) = 3.6 v 150 297 m w i lkg n-channel leakage current v (ds) = 6 v 7 10 m a i limf forward current limit (p- and n-channel) 2.5 v < vindcdc2 < 6 v 1.40 1.55 1.70 a f s oscillator frequency 1.3 1.5 1.7 mhz vindcdc2 = 2.5 v to 6 v; 1.8 v ?2% 2% 0 ma i o 1.0 a fixed output voltage fpwmdcdc2=0 vindcdc2 = 2.8 v to 6 v; 2.5 v ?2% 2% 0 ma i o 1 a vindcdc2 = 2.5 v to 6 v; 1.8 v ?2% 2% 0 ma i o 1 a fixed output voltage fpwmdcdc2=1 vindcdc2 = 2.8 v to 6 v; 2.5 v ?1% 1% 0 ma i o 1 a adjustable output voltage with resistor vindcdc2 = vdcdc2 +0.3 v (min 2.5 v) ?2% 2% divider at defdcdc2 fpwmdcdc2=0 to 6 v; 0 ma i o 1.0 a adjustable output voltage with resistor vindcdc2 = vdcdc2 +0.3 v (min 2.5 v) ?1% 1% divider at defdcdc2; fpwmdcdc2=1 to 6 v; 0 ma i o 1.0 a vindcdc2 = vdcdc2 + 0.3 v (min. 2.5 v) line regulation 0 %/v to 6 v; i o = 10 ma load regulation i o = 10 ma to 1 ma 0.25 %/a vdcdc2 ramping from 5% to 95% of target soft start ramp time 750 m s value internal resistance from l2 to gnd 1 m w vdcdc2 discharge resistance dcdc2 discharge =1 300 w 7 www .ti.com
electrical characteristics tps65021 slvs613 ? october 2005 vindcdc1 = vindcdc2 = vindcdc3 = vcc = vinldo = 3.6 v, vbackup = 3 v, t a = ?40 c to 85 c, typical values are at t a = 25 c (unless otherwise noted) parameter test conditions min typ max unit vdcdc3 step-down converter v i input voltage range, vindcdc3 2.5 6 v i o maximum output current 800 ma i (sd) shutdown supply current in vindcdc3 dcdc3_en = gnd 0.1 1 m a r ds(on) p-channel mosfet on-resistance vindcdc3 = v (gs) = 3.6 v 310 698 m w i lkg p-channel leakage current vindcdc3 = 6 v 0.1 2 m a r ds(on) n-channel mosfet on-resistance vindcdc3 = v (gs) = 3.6 v 220 503 m w i lkg n-channel leakage current v (ds) = 6 v 7 10 m a forward current limit (p- and n-channel) 2.5 v < vindcdc3 < 6 v 1.05 1.34 1.52 a f s oscillator frequency 1.3 1.5 1.7 mhz fixed output voltage vindcdc3 = 2.5 v to 6 v; ?2% 2% fpwmdcdc3=0 0 ma i o 800 ma all vdcdc3 fixed output voltage vindcdc3 = 2.5 v to 6 v; ?1% 1% fpwmdcdc3=1 0 ma i o 800 ma adjustable output voltage with resistor vindcdc3 = vdcdc3 +0.5 v (min 2.5 v) to ?2% 2% divider at defdcdc3 fpwmdcdc3=0 6 v; 0 ma i o 800 ma adjustable output voltage with resistor vindcdc3 = vdcdc3 +0.5 v (min 2.5 v) to ?1% 1% divider at defdcdc3; fpwmdcdc3=1 6 v; 0 ma i o 800 ma vindcdc3 = vdcdc3 + 0.3 v (min. 2.5 v) line regulation 0.0 %/v to 6 v; i o = 10 ma load regulation i o = 10 ma to 400 ma 0.25 %/a vdcdc3 ramping from 5% to 95% of target soft start ramp time 750 m s value internal resistance from l3 to gnd 1 m w vdcdc3 discharge resistance dcdc3 discharge =1 300 w 8 www .ti.com
electrical characteristics tps65021 slvs613 ? october 2005 vindcdc1 = vindcdc2 = vindcdc3 = vcc = vinldo = 3.6 v, vbackup = 3 v, t a = ?40 c to 85 c, typical values are at t a = 25 c (unless otherwise noted) parameter test conditions min typ max unit vldo1 and vldo2 low dropout regulators v i input voltage range for ldo1, 2 1.5 6.5 v v o ldo1 output voltage range 1 3.3 v v o ldo2 output voltage range 1 3.3 v v i = 1.8 v, v o = 1.3 v 200 maximum output current for ldo1, i o ma ldo2 v i = 1.5 v, v o = 1.3 v 120 ldo1 and ldo2 short circuit i (sc) v (ldo1) = gnd, v (ldo2) = gnd 400 ma current limit i o = 50 ma, vinldo = 1.8 v 120 minimum voltage drop at ldo1, i o = 50 ma, vinldo = 1.5 v 65 150 mv ldo2 i o = 200 ma, vinldo = 1.8 v 300 output voltage accuracy for ldo1, i o = 10 ma ?2% 1% ldo2 vinldo1,2 = vldo1,2 + 0.5 v (min. line regulation for ldo1, ldo2 ?1% 1% 2.5 v) to 6.5 v, i o = 10 ma load regulation for ldo1, ldo2 i o = 0 ma to 50 ma ?1% 1% regulation time for ldo1, ldo2 load change from 10% to 90% 10 m s analogic signals defdcdc1, defdcdc2, defdcdc3 v ih high level input voltage 1.3 vcc v v il low level input voltage 0 0.4 v input bias current 0.001 0.05 m a thermal shutdown t (sd) thermal shutdown increasing junction temperature 160 c thermal shudown hysteresis decreasing junction temperature 20 c internal undervoltage lock out uvlo internal uvlo vcc falling ?2% 2.35 2% v internal uvlo comparator v (uvlo_hyst) 120 mv hysteresis voltage detector comparators comparator threshold falling threshold ?1% 1 1% v (pwrfail_sns, lowbat_sns) hysteresis 40 50 60 mv propagation delay 25 mv overdrive 10 m s power good vdcdc1, vdcdc2, vdcdc3, vldo1, v (pgoodf) ?12% ?10% ?8% vldo2, decreasing vdcdc1, vdcdc2, vdcdc3, vldo1, v (pgoodr) ?7% ?5% ?3% vldo2, increasing 9 www .ti.com
tps65021 slvs613 ? october 2005 pin assignment (top view) terminal functions terminal i/o description name no. switching regulator section agnd1 40 analog ground connection. all analog ground pins are connected internally on the chip. agnd2 17 analog ground connection. all analog ground pins are connected internally on the chip. powerpad? ? connect the power pad to analog ground. input voltage for vdcdc1 step-down converter. this must be connected to the same voltage supply vindcdc1 6 i as vindcdc2, vindcdc3, and vcc. l1 7 switch pin of vdcdc1 converter. the vdcdc1 inductor is connected here. vdcdc1 9 i vdcdc1 feedback voltage sense input, connect directly to vdcdc1 pgnd1 8 power ground for vdcdc1 converter input voltage for vdcdc2 step-down converter. this must be connected to the same voltage supply vindcdc2 36 i as vindcdc1, vindcdc3, and vcc. l2 35 switch pin of vdcdc2 converter. the vdcdc2 inductor is connected here. vdcdc2 33 i vdcdc2 feedback voltage sense input, connect directly to vdcdc2 pgnd2 34 power ground for vdcdc2 converter input voltage for vdcdc3 step-down converter. this must be connected to the same voltage supply vindcdc3 5 i as vindcdc1, vindcdc2, and vcc. l3 4 switch pin of vdcdc3 converter. the vdcdc3 inductor is connected here. vdcdc3 2 i vdcdc3 feedback voltage sense input, connect directly to vdcdc3 pgnd3 3 power ground for vdcdc3 converter power supply for digital and analog circuitry of vdcdc1, vdcdc2, and vdcdc3 dc-dc converters. vcc 37 i this must be connected to the same voltage supply as vindcdc3, vindcdc1, and vindcdc2. also supplies serial interface block 10 www .ti.com 12 3 4 5 6 7 8 9 10 3029 28 27 26 25 24 23 22 21 1 1 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 defdcdc3 vdcdc3 pgnd3 l3 vindcdc3 vindcdc1 l1 pgnd1 vdcdc1 defdcdc1 hot_reset defldo1 defldo2 vsysin vbackup vrtc agnd2 vinldo vldo1 vldo2 sclksda t int respwron trespwrondcdc1_en dcdc2_en dcdc3_en ldo_en lowba t agnd1lowba t_sns pwrf ail_sns vccvindcdc2 l2 pgnd2 vdcdc2 defdcdc2 pwrf ail
tps65021 slvs613 ? october 2005 terminal functions (continued) terminal i/o description name no. input signal indicating default vdcdc1 voltage, 0 = 3 v, 1 = 3.3 v this pin can also be connected to defdcdc1 10 i a resistor divider between vdcdc1 and gnd. if the output voltage of the dcdc1 converter is set in a range from 0.6 v to vindcdc1 v input signal indicating default vdcdc2 voltage, 0 = 1.8 v, 1 = 2.5 v this pin can also be connected defdcdc2 32 i to a resistor divider between vdcdc2 and gnd. if the output voltage of the dcdc2 converter is set in a range from 0.6 v to vindcdc2 v input signal indicating default vdcdc3 voltage, 0 = 1.3 v, 1 = 1.55 v this pin can also be connected defdcdc3 1 i to a resistor divider between vdcdc3 and gnd. if the output voltage of the dcdc3 converter is set in a range from 0.6 v to vindcdc3 v dcdc1_en 25 i vdcdc1 enable pin. a logic high enables the regulator, a logic low disables the regulator. dcdc2_en 24 i vdcdc2 enable pin. a logic high enables the regulator, a logic low disables the regulator. dcdc3_en 23 i vdcdc3 enable pin. a logic high enables the regulator, a logic low disables the regulator. ldo regulator section vinldo 19 i i input voltage for ldo1 and ldo2 vldo1 20 o output voltage of ldo1 vldo2 18 o output voltage of ldo2 ldo_en 22 i enable input for ldo1 and ldo2. logic high enables the ldos, logic low disables the ldos vbackup 15 i connect the backup battery to this input pin. vrtc 16 o output voltage of the ldo/switch for the real time clock vsysin 14 i input of system voltage for vrtc switch defld01 12 i digital input, used to set default output voltage of ldo1 and ldo2 defld02 13 i digital input, used to set default output voltage of ldo1 and ldo2 control and i 2 c section hot_reset 11 i push button input used to reboot or wake-up processor via respwron output pin trespwron 26 i connect the timing capacitor to this pin to set the reset delay time: 1 nf ? 100 ms respwron 27 o open drain system reset output pwrfail 31 o open drain output. active low when pwrfail comparator indicates low vbat condition. low_bat 21 o open drain output of low_bat comparator int 28 o open drain output sclk 30 i serial interface clock line sdat 29 i/o serial interface data/address pwrfail_sns 38 i input for the comparator driving the pwrfail output lowbat_sns 39 i input for the comparator driving the low_bat output 11 www .ti.com
functional block diagram tps65021 slvs613 ? october 2005 12 www .ti.com dcdc2 step-down converter serial interface sclksda t dcdc3 step-down converter vldo1 vldo2 200-ma ldo 200-ma ldo thermal shutdown control vindcdc2 l2 vdcdc2 defdcdc2 vindcdc3 l3 vdcdc3 vinldo vldo1 vldo2 defdcdc3 uvlovref osc hot_reset respwron pwrf ail vcc pgnd2 pgnd3 agnd2 agnd1 defldo2 defldo1 dcdc1 step-down conver ter vindcdc1 l1 vdcdc1 defdcdc1 pgnd1 int pwrf ail_sns vrtc vbackup dcdc1_en dcdc3_en bba t switch vsysin lowba t_sns ldo_en dcdc2_en trespwron low_ba tt vcc
typical characteristics tps65021 slvs613 ? october 2005 graphs were taken using the evm with the following inductor/output capacitor combinations: converter inductor output capacitor output capacitor value vdcdc1 vlcf4020-2r2 c2012x5r0j106m 2 10 m f vdcdc2 vlcf4020-2r2 c2012x5r0j106m 2 10 m f vdcdc3 vlf4012at-2r2m1r5 c2012x5r0j106m 2 10 m f table 1. table of graphs figure h efficiency vs output current 1, 2, 3, 4, 5, 6, 7 line transient response 8, 9, 10 load transient response 11, 12, 13 vdcdc2 pfm operation 14 vdcdc2 low ripple pfm operation 15 vdcdc2 pwm operation 16 startup vdcdc1, vdcdc2 and vdcdc3 17 startup ldo1 and ldo2 18 line transient response 19, 20, 21 load transient response 22, 23, 24 dcdc1: efficiency dcdc1: efficiency vs vs output current output current figure 1. figure 2. 13 www .ti.com i - output current - ma o efficiency - % t = 25 c v = 3.3 v a o o pfm / pwm mode v = 3.8 v i v = 4.2 v i v = 5 v i 0.01 0.1 1 10 100 1 k 10 k i - output current - ma o efficiency - % t = 25 c v = 3.3 v a o o pwm mode v = 3.8 v i v = 4.2 v i v = 5 v i 0.01 0.1 1 10 100 1 k 10 k
tps65021 slvs613 ? october 2005 dcdc2: efficiency dcdc2: efficiency vs vs output current output current figure 3. figure 4. dcdc3: efficiency dcdc3: efficiency vs vs output current output current figure 5. figure 6. 14 www .ti.com i - output current - ma o efficiency - % t = 25 c v = 1.8 v a o o pwm / pfm mode v = 2.5 v i v = 5 v i 0.01 0.1 1 10 100 1 k 10 k v = 4.2 v i v = 3.8 v i i - output current - ma o efficiency - % t = 25 c v = 1.8 v a o o pwm mode v = 2.5 v i v = 5 v i v = 4.2 v i v = 3.8 v i 0.01 0.1 1 10 100 1 k 10 k i - output current - ma o efficiency - % t = 25 c v = 1.55 v a o o pwm / pfm mode v = 2.5 v i v = 3 v i v = 5 v i v = 4.2 v i v = 3.8 v i 0.1 1 10 100 1 k 10 k i - output current - ma o efficiency - % t = 25 c v = 1.55 v a o o pwm mode v = 2.5 v i v = 3 v i v = 5 v i v = 4.2 v i v = 3.8 v i 0.1 1 10 100 1 k 10 k
tps65021 slvs613 ? october 2005 dcdc3: efficiency vdcdc1 line transient response vs output current figure 7. figure 8. vdcdc2 line transient response vdcdc3 line transient response figure 9. figure 10. 15 www .ti.com c1 high4.74 v c1 low 3.08 v c2 pk-pk 85 mv = ch1 v ch2 v io = c2 mean3.2957 v i = 100 ma v = 3.6 v to 4.7 v v = 3 v pwm mode o io i - output current - ma o efficiency - % t = 25 c v = 1.3 v a o o low ripple pfm mode v = 2.5 v i v = 3 v i v = 3.8 v i v = 4.2 v i v = 5 v i 0.01 0.1 1 10 c1 high4.04 v c1 low 2.94 v c2 pk-pk 49.9 mv c2 mean1.79419 v = ch1 v ch2 v io = i = 100 ma v = 3 v to 4 v v = 1.8 v pwm mode o io c1 high4.05 v c1 low 2.95 v c2 pk-pk 46.0 mv = ch1 v ch2 v io = c2 mean1.59798 v i = 100 ma v = 3 v to 4 v v = 1.6 v pwm mode o io
tps65021 slvs613 ? october 2005 vdcdc1 load transient response vdcdc2 load transient response figure 11. figure 12. vdcdc3 load transient response vdcdc2 output voltage ripple figure 13. figure 14. 16 www .ti.com c2 pk-pk17.0 mv c2 mean1.80522 v v = 3.8 v v = 1.8 v io i = 1 ma t = 25 c pfm mode o a o c4 high730 ma c4 low 80 ma c2 pk-pk 80 mv c2 mean1.5931 v = ch2 v ch4 i o o = t = 25 c pwm mode a o iv io = 3.8 v v = 1.6 v o = 80 ma to 720 ma c4 high1.09 a c4 low120 ma c2 pk-pk 188 mv = ch2 v ch4 i o o = c2 mean3.3051 v pwm mode i = 120 ma to 1080 ma v = 3.8 v v = 3.3 v o io c4 high830 ma c4 low 90 ma c2 pk-pk 80 mv = ch2 v ch4 i o o = pwm mode iv io = 3.8 v v = 1.8 v o = 100 ma to 800 ma c2 mean1.7946 v
tps65021 slvs613 ? october 2005 vdcdc2 output voltage ripple vdcdc2 output voltage ripple figure 15. figure 16. startup vdcdc1, vdcdc2, and vdcdc3 startup ldo1 and ldo2 figure 17. figure 18. 17 www .ti.com v = 1.8 v i = 1 ma t = 25 c low ripple pfm mode o o a o v = 3.8 v i c2 pk-pk7.7 mv c2 mean1.79955 mv v = 3.8 v v = 1.8 v i = 1 ma t = 25 c pwm mode io o a o enable vdcdc1 vdcdc2 vdcdc3 enable ldo1 ldo2
tps65021 slvs613 ? october 2005 ldo1 line transient response ldo2 line transient response figure 19. figure 20. vrtc line transient response ldo1 load transient response figure 21. figure 22. 18 www .ti.com c1 high3.83 v c1 low3.29 v c2 pk-pk6.2 mv c2 mean1.09702 v = ch1 v ch2 v io = i = 25 ma v = 1.1 v t = 25 c o o a o c1 high4.51 v c1 low3.99 v c2 pk-pk6.1 mv = ch1 v ch2 v io = i = 25 ma v = 3.3 v t = 25 c o o a o c2 mean3.29828 v c1 high3.82 v c1 low3.28 v c2 pk-pk22.8 mv = ch1 v ch2 v io = i = 10 ma v = 3 v t = 25 c o o a o c2 mean2.98454 v c4 high48.9 ma c4 low2.1 ma c2 pk-pk42.5 mv = ch2 v ch4 o o = i v io a = 3.3 v v = 1.1 v t = 25 c o c2 mean1.09664 v
tps65021 slvs613 ? october 2005 ldo2 load transient response vrtc load transient response figure 23. figure 24. 19 www .ti.com c4 high47.8 ma c4 low-2.9 ma c2 pk-pk40.4 mv = ch2 v ch4 i o o = v io a = 4 v v = 3.3 v t = 25 c o c2 mean3.29821 v c4 high21.4 ma c4 low-1.4 ma c2 pk-pk76 mv = ch2 v ch4 i o o = v io a = 3.8 v v = 3 v t = 25 c o c2 mean2.9762 v
detailed description vrtc output and operation with or without backup battery step-down converters, vdcdc1, vdcdc2, and vdcdc3 tps65021 slvs613 ? october 2005 the vrtc pin is an always-on output, intended to supply up to 30 ma to a permanently required rail. this is the vcc_batt rail of the intel bulverde processor for example. in applications using a backup battery, the backup voltage can be either directly connected to the tps65021 vbackup pin if a li-ion cell is used, or via a boost converter (e.g. tps61070) if a single nimh battery is used. the voltage applied to the vbackup pin is fed through a pmos switch to the vrtc pin. the tps65021 asserts the respwron signal if vrtc drops below 2.4 v. this, together with 375 mv at 30 ma drop out for the pmos switch means that the voltage applied at vbackup must be greater than 2.775 v for normal system operation. when the voltage at the vsysin pin exceeds 2.65 v, the path from vbackup to vrtc is cut, and vrtc is supplied by a similar pmos switch from the voltage source connected to the vsysin input. typically this is the vdcdc1 converter but can be any voltage source within the appropriate range. in systems where no backup battery is used, the vbackup pin is connected to gnd. in this case, a low power ldo is enabled, supplied from vcc and capable of delivering 30 ma to the 3 v output. this ldo is disabled if the voltage at the vsysin input exceeds 2.65 v. vrtc is then supplied from the external source connected to this pin as previously described a. v_vsysin, v_vbackup thresholds: falling = 2.55 v, rising = 2.65 v 3% b. respwron thresholds: falling = 2.4 v, rising = 2.52 v 3% figure 25. the tps65021 incorporates three synchronous step-down converters operating typically at 1.5 mhz fixed frequency pulse width modulation (pwm) at moderate to heavy load currents. at light load currents, the converters automatically enter the power save mode (psm), and operate with pulse frequency modulation (pfm). the vdcdc1 converter is capable of delivering 1.2 a output current, the vdcdc2 converter is capable of delivering 1 a and the vdcdc3 converter is capable of delivering up to 800 ma. the converter output voltages can be programmed via the defdcdc1, defdcdc2 and defdcdc3 pins. the 20 www .ti.com respwron vr tc ldo v c c vr tc v r e f v r e f v r e f priority #3 priority #2 priority #1 en v_vsysin v_vbackup vbackup v_vbackup vsysin v_vsysin
power save mode operation tps65021 slvs613 ? october 2005 detailed description (continued) pins can either be connected to gnd, vcc, or to a resistor divider between the output voltage and gnd. the vdcdc1 converter defaults to 3 v or 3.3 v depending on the defdcdc1 configuration pin. if defdcdc1 is tied to ground, the default is 3 v. if it is tied to vcc, the default is 3.3 v. when the defdcdc1 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 v to vindcdc1 v. see the application information section for more details. the vdcdc2 converter defaults to 1.8 v or 2.5 v depending on the defdcdc2 configuration pin. if defdcdc2 is tied to ground, the default is 1.8 v. if it is tied to vcc, the default is 2.5 v. when the defdcdc2 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 v to vindcdc2 v. the vdcdc3 converter defaults to 1.3 v or 1.55 v depending on the defdcdc3 configuration pin. if defdcdc3 is tied to ground the default is 1.3 v. if it is tied to vcc, the default is 1.55 v. when the defdcdc3 pin is connected to a resistor divider, the output voltage can be set in the range of 0.6 v to vindcdc3 v. the core voltage can be reprogrammed via the serial interface in the range of 0.8 v to 1.6 v with a programmable slew rate. the converter is forced into pwm operation whilst any programmed voltage change is underway, whether the voltage is being increased or decreased. the defcore and defslew registers are used to program the output voltage and slew rate during voltage transitions. the step-down converter outputs (when enabled) are monitored by power good (pg) comparators, the outputs of which are available via the serial interface. the outputs of the dc-dc converters can be optionally discharged via on-chip 300- w resistors when the dc-dc converters are disabled. during pwm operation, the converters use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. at the beginning of each clock cycle initiated by the clock signal, the p-channel mosfet switch is turned on. the inductor current ramps up until the comparator trips and the control logic turns off the switch. the current limit comparator also turns off the switch if the current limit of the p-channel switch is exceeded. after the adaptive dead time used to prevent shoot through current, the n-channel mosfet rectifier is turned on, and the inductor current ramps down. the next cycle is initiated by the clock signal, again turning off the n-channel rectifier and turning on the p-channel switch. the three dc-dc converters operate synchronized to each other with the vdcdc1 converter as the master. a 180 phase shift between the vdcdc1 switch turn on and the vdcdc2 and a further 90 shift to the vdcdc3 switch turn on decreases the input rms current and smaller input capacitors can be used. this is optimized for a typical application where the vdcdc1 converter regulates a li-ion battery voltage of 3.7 v to 3.3 v, the vdcdc2 converter from 3.7 v to 2.5 v, and the vdcdc3 converter from 3.7 v to 1.5 v. the phase of the three converters can be changed using the con_ctrl register. as the load current decreases, the converters enter the power save mode operation. during psm, the converters operate in a burst mode (pfm mode) with a switching frequency between half of the switching frequency and switching frequency for one burst cycle. however, the frequency between different burst cycles depends on the actual load current and is typically far less than the switching frequency with a minimum quiescent current to maintain high efficiency. in order to optimize the converter efficiency at light load, the average current is monitored and if in pwm mode the inductor current remains below a certain threshold, then psm is entered. the typical threshold to enter psm is calculated as follows: 21 www .ti.com
(1) (2) low ripple mode soft start tps65021 slvs613 ? october 2005 detailed description (continued) during the psm the output voltage is monitored with a comparator, and by maximum skip burst width. as the output voltage falls below the threshold, set to the nominal v o , the p-channel switch turns on and the converter effectively delivers a constant current defined as follows. if the load is below the delivered current then the output voltage rises until the same threshold is crossed in the other direction. all switching activity ceases, reducing the quiescent current to a minimum until the output voltage has dropped below the threshold again. if the load current is greater than the delivered current, then the output voltage falls until it crosses the comp low threshold, set to 2% below nominal v o , or the skip burst exceeds 16 1/switching frequency. power save mode is exited and the converter returns to pwm mode. these control methods reduce the quiescent current to typically 14 m a per converter, and the switching activity to a minimum, thus achieving the highest converter efficiency. setting the comparator thresholds at the nominal output voltage at light load current results in a low output voltage ripple. the ripple depends on the comparator delay and the size of the output capacitor. increasing capacitor values makes the output ripple tend to zero. the psm is disabled through the i 2 c interface to force the individual converters to stay in fixed frequency pwm mode. setting bit 3 in register con-ctrl to 1 enables the low ripple mode for all of the dc-dc converters if operated in pfm mode. for an output current less than approximately 10 ma, the output voltage ripple in pfm mode is reduced, depending on the actual load current. the lower the actual output current on the converter, the lower the output ripple voltage. for an output current above 10 ma, there is only minor difference in output voltage ripple between pfm mode and low ripple pfm mode. as this feature also increases switching frequency, it is used to keep the switching frequency above the audible range in pfm mode down to a low output current. each of the three converters has an internal soft start circuit that limits the inrush current during start-up. the soft start is realized by using a very low current to initially charge the internal compensation capacitor. the soft start time is typically 750 m s if the output voltage ramps from 5% to 95% of the final target value. if the output is already precharged to some voltage when the converter is enabled, then this time is reduced proportionally. there is a short delay of typically 170 m s between the converter being enabled and switching activity actually starting. this is to allow the converter to bias itself properly, to recognize if the output is precharged, and if so to prevent discharging of the output while the internal soft start ramp catches up with the output voltage. 22 www .ti.com i = pf md c d c 1 e n t e r i = pf md c d c 2 e n t e r i = pf md c d c 3 e n t e r vindcdc1 vindcdc2 vindcdc3 24 w 26 w 39 w i = pf md c d c 1 l e a ve i = pf md c d c 2 l e a ve i = pf md c d c 3 l e a ve vindcdc1 vindcdc2 vindcdc3 18 w 20 w 29 w
100% duty cycle low dropout operation (3) active discharge when disabled power good monitoring low dropout voltage regulators power good monitoring tps65021 slvs613 ? october 2005 detailed description (continued) the tps65021 converters offer a low input to output voltage difference while still maintaining operation with the use of the 100% duty cycle mode. in this mode the p-channel switch is constantly turned on. this is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. the minimum input voltage required to maintain dc regulation depends on the load current and output voltage. it is calculated as: with: iout max = maximum load current (note: ripple current in the inductor is zero under these conditions) r ds(on) max = maximum p-channel switch r ds(on) r l = dc resistance of the inductor vout min = nominal output voltage minus 2% tolerance limit when the vdcdc1, vdcdc2, and vdcdc3 converters are disabled, due to an uvlo, en_x or overtemp condition, it is possible to actively pull down the outputs. this feature is disabled per default and is individually enabled via the con_ctrl2 register in the serial interface. when this feature is enabled, the vdcdc1, vdcdc2, and vdcdc3 outputs are discharged by a 300 w (typical) load which is active as long as the converters are disabled. all three step-down converters and both the ldo1 and ldo2 linear regulators have power good comparators. each comparator indicates when the relevant output voltage has dropped 10% below its target value with 5% hysteresis. the outputs of these comparators are available in the pgoodz register via the serial interface. an interrupt is generated when any voltage rail drops below the 10% threshold. the comparators are disabled when the converters are disabled and the relevant pgoodz register bits indicate that power is good. the low dropout voltage regulators are designed to operate well with low value ceramic input and output capacitors. they operate with input voltages down to 1.5 v. the ldos offer a maximum dropout voltage of 300 mv at rated output current. each ldo supports a current limit feature. both ldos are enabled by the en_ldo pin, both ldos can be disabled or programmed via the serial interface using the reg_ctrl and ldo_ctrl registers. the ldos also have reverse conduction prevention. this allows the possibility to connect external regulators in parallel in systems with a backup battery. the tps65021 step-down and ldo voltage regulators automatically power down when the vbat voltage drops below the uvlo threshold or when the junction temperature rises above 160 c. both the ldo1 and ldo2 linear regulators have power good comparators. each comparator indicates when the relevant output voltage has dropped 10% below its target value, with 5% hysteresis. the outputs of these comparators are available in the pgoodz register via the serial interface. an interrupt is generated when any voltage rail drops below the 10% threshold. the comparators are disabled when the ldos are disabled and the relevant pgoodz register bits indicate that power is good. 23 www .ti.com v i n min v o u t min i o u t max r d s ( o n ) max r l
undervoltage lockout power-up sequencing system reset + control signals tps65021 slvs613 ? october 2005 detailed description (continued) the undervoltage lockout circuit for the five regulators on the tps65021 prevents the device from malfunctioning at low-input voltages and from excessive discharge of the battery. it disables the converters and ldos. the uvlo circuit monitors the vcc pin, the threshold is set internally to 2.35 v with 5% (120 mv) hysteresis. note that when any of the dc-dc converters are running, there is an input current at the vcc pin, which is up to 3 ma when all three converters are running in pwm mode. this current needs to be taken into consideration if an external rc filter is used at the vcc pin to remove switching noise from the tps65021 internal analog circuitry supply. the tps65021 power-up sequencing is designed to be entirely flexible and customer driven. this is achieved by providing separate enable pins for each switch-mode converter, and a common enable signal for the ldos. the relevant control pins are described in table 2 . table 2. control pins and status outputs for dc-dc converters pin name input function output defines the default voltage of the vdcdc3 switching converter. defdcdc3 = 0 defaults vdcdc3 to defdcdc3 i 1.3 v, defdcdc3 = vcc defaults vdcdc3 to 1.55 v. defines the default voltage of the vdcdc2 switching converter. defdcdc2 = 0 defaults vdcdc2 to defdcdc2 i 1.8 v, defdcdc2 = vcc defaults vdcdc2 to 2.5 v. defines the default voltage of the vdcdc1 switching converter. defdcdc1 = 0 defaults vdcdc1 to 3 v, defdcdc1 i defdcdc1 = vcc defaults vdcdc1 to 3.3 v. dcdc3_en i set dcdc3_en = 0 to disable and dcdc3_en = 1 to enable the vdcdc3 converter dcdc2_en i set dcdc2_en = 0 to disable and dcdc2_en = 1 to enable the vdcdc2 converter dcdc1_en i set dcdc1_en = 0 to disable and dcdc1_en = 1 to enable the vdcdc1 converter the hot_reset pin generates a reset ( respwron) for the processor. hot_reset does not alter any tps65021 settings except the output voltage of vdcdc3. activating hot_reset sets the voltage of hot_reset i vdcdc3 to its default value defined with the defdcdc3 pin. hot_reset is internally de-bounced by the tps65021. respwron is held low when power is initially applied to the tps65021. the vrtc voltage is monitored: respwron o reswpron is low when vrtc < 2.4 v and remains low for a time defined by the external capacitor at the trespwron pin. respwron can also be forced low by activation of the hot_reset pin. trespwron i connect a capacitor here to define the reset time at the respwron pin. 1 nf typically gives 100 ms. the respwron signal can be used as a global reset for the application. it is an open drain output. the respwron signal is generated according to the power good comparator of vrtc, and remains low for t nrespwron seconds after vrtc has risen above 2.52 v (falling threshold is 2.4 v, 5% hysteresis). t nrespwron is set by an external capacitor at the trespwron pin. 1 nf gives typically 100 ms. respwron is also triggered by the hot_reset input. this input is internally debounced, with a filter time of typically 30 ms. the pwrfail and low_bat signals are generated by two voltage detectors using the pwrfail_sns and lowbat_sns input signals. each input signal is compared to a 1 v threshold (falling edge) with 5% (50 mv) hysteresis. the dcdc3 converter is reset to its default output voltage defined by the defdcdc3 input, when hot_reset is asserted. other i 2 c registers are not affected. generally, the dcdc3 converter is set to its default voltage with one of these conditions: hot_reset active, vrtc lower than its threshold voltage, undervoltage lockout (uvlo) condition, respwron active, both dcdc3-converter and dcdc1-converter disabled. in addition, the voltage of vdcdc3 changes to 1xxx0, if the vdcdc1 converter is disabled. where xxx is the state before vdcdc1 was disabled. 24 www .ti.com
defldo1 and defldo2 interrupt management and the int pin timing diagrams tps65021 slvs613 ? october 2005 these two pins are used to set the default output voltage of the two 200 ma ldos. the digital value applied to the pins is latched during power up and determines the initial output voltage according to table 3 . the voltage of both ldos can be changed during operation with the i 2 c interface as described in the interface description. table 3. defldo2 defldo1 vldo1 vldo2 0 0 1.1 v 1.3 v 0 1 1.5 v 1.3 v 1 0 2.6 v 2.8 v 1 1 3.15 v 3.3 v the int pin combines the outputs of the pgood comparators from each dc-dc converter and ldos. the int pin is used as a power_ok pin indicating when all enabled supplies are in regulation. if the pgoodz register is read via the serial interface, any active bits are then blocked from the int output pin. interrupts can be masked using the mask register; default operation is not to mask any interrupts since this gives the simple power_ok function. figure 26. hot_reset timing 25 www .ti.com t d eg l i t c h hot_reset respwron v dcdc3 o default voltage any voltage setwith i c interface 2 t n r espw r o n
tps65021 slvs613 ? october 2005 figure 27. power-up and power-down timing 26 www .ti.com v c c uvlo* vrtc t n r espw r o n endcdcx v dcdcx o respwron *... internal signal vsysin = vbackup = gnd; vinldo = v c c 0.8 v 1.9 v 2.52 v 3 v rampw ithin 800 s m enldo 2.47 v v ldox o 1.8 v 2.4 v 2.35 v 1.2 v 1.5 v 1.9 v slope depending on load
serial interface tps65021 slvs613 ? october 2005 figure 28. dvs timing the serial interface is compatible with the standard and fast mode i 2 c specifications, allowing transfers at up to 400 khz. the interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements and charger status to be monitored. register contents remain intact as long as vcc remains above 2 v. the tps65021 has a 7bit address: 1001000, other addresses are available upon contact with the factory. attempting to read data from the register addresses not listed in this section results in ffh being read out. for normal data transfer, data is allowed to change only when clk is low. changes when clk is high are reserved for indicating the start and stop conditions. during data transfer, the data line must remain stable 27 www .ti.com v c c endcdc1 t n r espw r o n v dcdc1 o v dcdc2 o v dcdc3 o respwron ramp w ithin 800 s m ramp w ithin 800 s m ramp w ithin 800 s m ramp w ithin 800 s m ramp w ithin 800 s m defcore register slope depending on load go bit in con_ctrl2 2.5 v or 1.8 v endcdc2 3.3 v or 3 v endcdc3 1.3 v or 1.55 v default v alue set higher output v oltage for dcdc3 programmed s lew rate cleared automatically 1.3 v or 1.55 v automatically set to default v alue
tps65021 slvs613 ? october 2005 whenever the clock line is high. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. when addressed, the tps65021 device generates an acknowledge bit after the reception of each byte. the master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge bit. the tps65021 device must pull down the data line during the acknowledge clock pulse so that the data line is a stable low during the high period of the acknowledge clock pulse. the data line is a stable low during the high period of the acknowledge?related clock pulse. setup and hold times must be taken into account. during read operations, a master must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. in this case, the slave tps65021 device must leave the data line high to enable the master to generate the stop condition figure 29. bit transfer on the serial interface figure 30. start and stop conditions figure 31. serial i/f write to tps65021 device 28 www .ti.com data line stable; data v alid da t a clk change of data allowed da t a clk ce s p st art condition st op condition sclk sda t start slave address register address data 0 a6 a5 a4 a0 r/w r7 r6 r5 r0 d7 d6 d5 d0 ack ack ack 0 0 0 stop note: sla ve = tps65020
tps65021 slvs613 ? october 2005 figure 32. serial i/f read from tps65021: protocol a figure 33. serial i/f read from tps65021: protocol b figure 34. serial i/f timing diagram 29 www .ti.com sclk sda t start repeated start slave drives the data master drives ack and stop slave address slave address registeraddress 0 a6 a6 a0 a0 r/w r/w r7 r0 d7 d0 ack ack ack ack 0 0 0 1 stop note: sla ve = tps65020 sclk sda start stop start slave drives the data master drives ack and stop slave address slave address registeraddress 0 0 0 0 1 stop note: sla ve = tps65020 a6 a6 a0 a0 r/w r/w r7 r0 d7 d0 ack ack ack ack clk da t a st a st a st o st o t h (st a ) t (b u f ) t (l o w ) t r t f t h (d a t a ) t s u (d a t a ) t s u (st a ) t h (st a ) t s u (st o ) t (h i g h )
tps65021 slvs613 ? october 2005 min max unit f max clock frequency 400 khz t wh(high) clock high time 600 ns t wl(low) clock low time 1300 ns t r data and clk rise time 300 ns t f data and clk fall time 300 ns t h(sta) hold time (repeated) start condition (after this period the first clock pulse is generated) 600 ns t h(data) setup time for repeated start condition 600 ns t h(data) data input hold time 0 ns t su(data) data input setup time 100 ns t su(sto) stop condition setup time 600 ns t (buf) bus free time 1300 ns version. register address: 00h (read only) version b7 b6 b5 b4 b3 b2 b1 b0 bit name and 0 0 1 0 0 0 0 0 function read/write r r r r r r r r 30 www .ti.com
tps65021 slvs613 ? october 2005 pgoodz. register address: 01h (read only) pgoodz b7 b6 b5 b4 b3 b2 b1 b0 bit name and lowbattz pgoodz pgoodz pgoodz pgoodz pgoodz pwrfailz function vdcdc1 vdcdc2 vdcdc3 ldo2 ldo1 lowbatt pgoodz pgoodz pgoodz pgoodz pgoodz set by signal pwrfail vdcdc1 vdcdc2 vdcdc3 ldo2 ldo1 default value lowbattz pgood pgood pgood pgood pgood pwrfailz loaded by: vdcdc1 vdcdc2 vdcdc3 ldo2 ldo1 read/write r r r r r r r r bit 7 pwrfailz: 0 = indicates that the pwrfail_sns input voltage is above the 1-v threshold. 1 = indicates that the pwrfail_sns input voltage is below the 1-v threshold. bit 6 lowbattz: 0 = indicates that the lowbatt_sns input voltage is above the 1-v threshold. 1 = indicates that the lowbatt_sns input voltage is below the 1-v threshold. bit 5 pgoodz vdcdc1: 0 = indicates that the vdcdc1 converter output voltage is within its nominal range. this bit is zero if the vdcdc1 converter is disabled. 1 = indicates that the vdcdc1 converter output voltage is below its target regulation voltage bit 4 pgoodz vdcdc2: 0 = indicates that the vdcdc2 converter output voltage is within its nominal range. this bit is zero if the vdcdc2 converter is disabled. 1 = indicates that the vdcdc2 converter output voltage is below its target regulation voltage bit 3 pgoodz vdcdc3: . 0 = indicates that the vdcdc3 converter output voltage is within its nominal range. this bit is zero if the vdcdc3 converter is disabled and during a dvm controlled output voltage transition 1 = indicates that the vdcdc3 converter output voltage is below its target regulation voltage bit 2 pgoodz ldo2: 0 = indicates that the ldo2 output voltage is within its nominal range. this bit is zero if ldo2 is disabled. 1 = indicates that ldo2 output voltage is below its target regulation voltage bit 1 pgoodz ldo1 0 = indicates that the ldo1 output voltage is within its nominal range. this bit is zero if ldo1 is disabled. 1 = indicates that the ldo1 output voltage is below its target regulation voltage 31 www .ti.com
tps65021 slvs613 ? october 2005 mask. register address: 02h (read/write) default value: c0h mask b7 b6 b5 b4 b3 b2 b1 b0 bit name and mask mask mask mask mask mask mask function pwrfailz lowbattz vdcdc1 vdcdc2 vdcdc3 ldo2 ldo1 default 1 1 0 0 0 0 0 0 default value uvlo uvlo uvlo uvlo uvlo uvlo uvlo loaded by: read/write r/w r/w r/w r/w r/w r/w r/w the mask register can be used to mask particular fault conditions from appearing at the int pin. mask = 1 masks pgoodz. reg_ctrl. register address: 03h (read/write) default value: ffh reg_ctrl b7 b6 b5 b4 b3 b2 b1 b0 bit name and vdcdc1 vdcdc2 vdcdc3 ldo2 ldo1 function enable enable enable enable enable default 1 1 1 1 1 1 1 1 set by signal dcdc1_enz dcdc2_enz dcdc3_enz ldo_enz ldo_enz default value uvlo uvlo uvlo uvlo uvlo loaded by: read/write r/w r/w r/w r/w r/w the reg_ctrl register can be used to disable and enable all power supplies via the serial interface. default is to allow all supplies to be on, providing the relevant enable pin is high. the following tables indicate how the enable pins and the reg_ctrl register are combined. the reg_ctrl bits are automatically reset to default when the corresponding enable pin is low. dcdc1 dcdc2 dcdc1_en pin reg_ctrl<5> dcdc2_en pin reg_ctrl<4> converter converter 0 x disabled 0 x disabled 1 0 disabled 1 0 disabled 1 1 enabled 1 1 enabled dcdc3 dcdc3_en pin reg_ctrl<3> ldo_en pin reg_ctrl<2> ldo2 converter 0 x disabled 0 x disabled 1 0 disabled 1 0 disabled 1 1 enabled 1 1 enabled ldo_en pin reg_ctrl<1> ldo1 0 x disabled 1 0 disabled 1 1 enabled 32 www .ti.com
tps65021 slvs613 ? october 2005 con_ctrl. register address: 04h (read/write) default value: b1h con_ctrl b7 b6 b5 b4 b3 b2 b1 b0 bit name and dcdc2 dcdc2 dcdc3 dcdc3 low fpwm fpwm fpwm function phase1 phase0 phase1 phase0 ripple dcdc2 dcdc1 dcdc3 default 1 0 1 1 0 0 0 1 default value uvlo uvlo uvlo uvlo uvlo uvlo uvlo uvlo loaded by: read/write r/w r/w r/w r/w r/w r/w r/w r/w the con_ctrl register is used to force any or all of the converters into forced pwm operation, when low output voltage ripple is vital. it is also used to control the phase shift between the three converters in order to minimize the input rms current, hence reduce the required input blocking capacitance. the dcdc1 converter is taken as the reference and consequently has a fixed zero phase shift. dcdc2 converter dcdc3 converter con_ctrl<7:6> con_ctrl<5:4> delayed by delayed by 00 zero 00 zero 01 1/4 cycle 01 1/4 cycle 10 ? cycle 10 ? cycle 11 3/4 cycle 11 3/4 cycle bit 3 low ripple: 0 = skip mode operation optimized for high efficiency for all converters 1 = skip mode operation optimized for low output voltage ripple for all converters bit 2 fpwm dcdc2: 0 = dcdc2 converter operates in pwm / pfm mode 1 = dcdc2 converter is forced into fixed frequency pwm mode bit 1 fpwm dcdc1: 0 = dcdc1 converter operates in pwm / pfm mode 1 = dcdc1 converter is forced into fixed frequency pwm mode bit 0 fpwm dcdc3: 0 = dcdc3 converter operates in pwm / pfm mode 1 = dcdc3 converter is forced into fixed frequency pwm mode 33 www .ti.com
tps65021 slvs613 ? october 2005 con_ctrl. register address: 05h (read/write) default value: 40h con_ctrl2 b7 b6 b5 b4 b3 b2 b1 b0 bit name and core adj dcdc2 dcdc1 dcdc3 go function allowed discharge discharge discharge default 0 1 0 0 0 0 0 0 default value uvlo + uvlo uvlo uvlo uvlo loaded by: done read/write r/w r/w r/w r/w r/w the con_ctrl2 register can be used to take control the inductive converters. bit 7 go: 0 = no change in the output voltage for the dcdc3 converter 1 = the output voltage of the dcdc3 converter is changed to the value defined in defcore with the slew rate defined in defslew. this bit is automatically cleared when the dvm transition is complete. the transition is considered complete in this case when the desired output voltage code has been reached, not when the vdcdc3 output voltage is actually in regulation at the desired voltage. bit 6 core adj allowed: 0 = the output voltage is set with the i 2 c register 1 = defdcdc3 is either connected to gnd or vcc or an external voltage divider. when connected to gnd or vcc, vdcdc3 defaults to 1.3 v or 1.55 v respectively at start-up bit 2? 0 0 = the output capacitor of the associated converter is not actively discharged when the converter is disabled 1 = the output capacitor of the associated converter is actively discharged when the converter is disabled. this decreases the fall time of the output voltage at light load 34 www .ti.com
tps65021 slvs613 ? october 2005 defcore. register address: 06h (read/write default value: 14h/1eh defcore b7 b6 b5 b4 b3 b2 b1 b0 bit name and core4 core3 core2 core1 core0 function default 0 0 0 1 defdcdc3 1 defdcdc3 0 default value reset(1) reset(1) reset(1) reset(1) reset(1) loaded by: read/write r/w r/w r/w r/w r/w reset(1): defcore is reset to its default value by one of these events: undervoltage lockout (uvlo) dcdc1 and dcdc3 disabled hot_reset pulled low respwron active vrtc below threshold core4 core3 core2 core1 core0 vdcdc3 core4 core3 core2 core1 core0 vdcdc3 0 0 0 0 0 0.8 v 1 0 0 0 0 1.2 v 0 0 0 0 1 0.825 v 1 0 0 0 1 1.225 v 0 0 0 1 0 0.85 v 1 0 0 1 0 1.25 v 0 0 0 1 1 0.875 v 1 0 0 1 1 1.275 v 0 0 1 0 0 0.9 v 1 0 1 0 0 1.3 v 0 0 1 0 1 0.925 v 1 0 1 0 1 1.325 v 0 0 1 1 0 0.95 v 1 0 1 1 0 1.35 v 0 0 1 1 1 0.975 v 1 0 1 1 1 1.375 v 0 1 0 0 0 1 v 1 1 0 0 0 1.4 v 0 1 0 0 1 1.025 v 1 1 0 0 1 1.425 v 0 1 0 1 0 1.05 v 1 1 0 1 0 1.45 v 0 1 0 1 1 1.075 v 1 1 0 1 1 1.475 v 0 1 1 0 0 1.1 v 1 1 1 0 0 1.5 v 0 1 1 0 1 1.125 v 1 1 1 0 1 1.525 v 0 1 1 1 0 1.15 v 1 1 1 1 0 1.55 v 0 1 1 1 1 1.175 v 1 1 1 1 1 1.6 v defslew. register address: 07h (read/write) default value: 06h defslew b7 b6 b5 b4 b3 b2 b1 b0 bit name and slew2 slew1 slew0 function default 1 1 0 default value uvlo uvlo uvlo loaded by: read/write r/w r/w r/w slew2 slew1 slew0 vdcdc3 slew rate 0 0 0 0.15 mv/ m s 0 0 1 0.3 mv/ m s 0 1 0 0.6 mv/ m s 0 1 1 1.2 mv/ m s 1 0 0 2.4 mv/ m s 1 0 1 4.8 mv/ m s 1 1 0 9.6 mv/ m s 1 1 1 immediate 35 www .ti.com
design procedure inductor selection for the dc-dc converters (4) (5) tps65021 slvs613 ? october 2005 ldo_ctrl. register address: 08h (read/write) default value: set with defldo1 and defldo2 ldo_ctrl b7 b6 b5 b4 b3 b2 b1 b0 bit name and ldo2_2 ldo2_1 ldo2_0 ldo1_2 ldo1_1 ldo1_0 function default defldox defldox defldox defldox defldox defldox default value uvlo uvlo uvlo uvlo uvlo uvlo loaded by: read/write r/w r/w r/w r/w r/w r/w the ldo_ctrl registers can be used to set the output voltage of ldo1 and ldo2. the default voltage is set with defldo1 and defldo2 pins as described in table 3 . ldo1 output ldo2 output ldo1_2 ldo1_1 ldo1_0 ldo2_2 ldo2_1 ldo2_0 voltage voltage 0 0 0 1 v 0 0 0 1.05 v 0 0 1 1.1 v 0 0 1 1.2 v 0 1 0 1.35 v 0 1 0 1.3 v 0 1 1 1.5 v 0 1 1 1.8 v 1 0 0 2.2 v 1 0 0 2.5 v 1 0 1 2.6 v 1 0 1 2.8 v 1 1 0 2.85 v 1 1 0 3 v 1 1 1 3.15 v 1 1 1 3.3 v each of the converters in the tps65021 typically use a 3.3 m h output inductor. larger or smaller inductor values are used to optimize the performance of the device for specific operation conditions. the selected inductor has to be rated for its dc resistance and saturation current. the dc resistance of the inductance influences directly the efficiency of the converter. therefore, an inductor with lowest dc resistance should be selected for highest efficiency. for a fast transient response, a 2.2- m h inductor in combination with a 22- m f output capacitor is recommended. equation 4 calculates the maximum inductor current under static load conditions. the saturation current of the inductor should be rated higher than the maximum inductor current as calculated with equation 4 . this is needed because during heavy load transient the inductor current rises above the value calculated under equation 4 . with: f = switching frequency (1.5 mhz typical) l = inductor value d i l = peak-to-peak inductor ripple current i lmax = maximum inductor current the highest inductor current occurs at maximum vin. open core inductors have a soft saturation characteristic, and they can usually handle higher inductor currents versus a comparable shielded inductor. 36 www .ti.com i l v o u t 1 v o u t v i n l ? i l m a x i o u t m a x i l 2
output capacitor selection (6) (7) tps65021 slvs613 ? october 2005 a more conservative approach is to select the inductor current rating just for the maximum switch current of the tps65021 (2 a for the vdcdc1 and vdcdc2 converters, and 1.3 a for the vdcdc3 converter). the core material from inductor to inductor differs and has an impact on the efficiency especially at high switching frequencies. see table 4 and the typical applications for possible inductors. table 4. tested inductors device inductor type component supplier value 3.3 m h cdrh2d14np-3r3 sumida 3.3 m h lps3010-332 coilcraft dcdc3 converter 3.3 m h vlf4012at-3r3m1r3 tdk 2.2 m h vlf4012at-2r2m1r5 tdk 3.3 m h cdrh2d18/hpnp-3r3 sumida dcdc2 converter 3.3 m h vlf4012at-3r3m1r3 tdk 2.2 m h vlcf4020-2r2 tdk 3.3 m h cdrh3d14/hpnp-3r2 sumida 3.3 m h cdrh4d28c-3r2 sumida dcdc1 converter 3.3 m h mss5131-332 coilcraft 2.2 m h vlcf4020-2r2 tdk the advanced fast response voltage mode control scheme of the inductive converters implemented in the tps65021 allow the use of small ceramic capacitors with a typical value of 10 m f for each converter without having large output voltage under and overshoots during heavy load transients. ceramic capacitors having low esr values have the lowest output voltage ripple and are recommended. see table 5 for recommended components. if ceramic output capacitors are used, the capacitor rms ripple current rating always meets the application requirements. just for completeness, the rms ripple current is calculated as: at nominal load current, the inductive converters operate in pwm mode. the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor esr plus the voltage ripple caused by charging and discharging the output capacitor: where the highest output voltage ripple occurs at the highest input voltage vin. at light load currents, the converters operate in psm and the output voltage ripple is dependent on the output capacitor value. the output voltage ripple is set by the internal comparator delay and the external capacitor. the typical output voltage ripple is less than 1% of the nominal output voltage. 37 www .ti.com i r msc o u t = v o u t x 1 - v o u t v i n l x | x 1 2 x 3 ? d v o u t = v o u t x 1 - v o u t v i n l x | x + esr ( ) 1 8 x c x o u t |
input capacitor selection output voltage selection tps65021 slvs613 ? october 2005 because of the nature of the buck converter having a pulsating input current, a low esr input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. each dc-dc converter requires a 10- m f ceramic input capacitor on its input pin vindcdcx. the input capacitor is increased without any limit for better input voltage filtering. the vcc pin is separated from the input for the dc-dc converters. a filter resistor of up to 10r and a 1- m f capacitor is used for decoupling the vcc pin from switching noise. note that the filter resistor may affect the uvlo threshold since up to 3 ma can flow via this resistor into the vcc pin when all converters are running in pwm mode. table 5. possible capacitors capacitor value case size component supplier comments 22 m f 1206 tdk c3216x5r0j226m ceramic 22 m f 1206 taiyo yuden jmk316bj226ml ceramic 22 m f 0805 tdk c2012x5r0j226mt ceramic 22 m f 0805 taiyo yuden jmk212bj226mg ceramic 10 m f 0805 taiyo yuden jmk212bj106m ceramic 10 m f 0805 tdk c2012x5r0j106m ceramic the defdcdc1, defdcdc2, and defdcdc3 pins are used to set the output voltage for each step-down converter. see table 6 for the default voltages if the pins are pulled to gnd or to vcc. if a different voltage is needed, an external resistor divider can be added to the defdcdcx pin as shown in table 6 . the output voltage of vdcdc3 is set with the i 2 c interface. if the voltage is changed from the default, using the defcore register, the output voltage only depends on the register value. any resistor divider at defdcdc3 does not change the voltage set with the register. table 6. pin level default output voltage vcc 3.3 v defdcdc1 gnd 3 v vcc 2.5 v defdcdc2 gnd 1.8 v vcc 1.55 v defdcdc3 gnd 1.3 v using an external resistor divider at defdcdcx: 38 www .ti.com vdcdc3 dcdc3_en defdcdc3 agnd pgnd l3 r1r2 v o l c o v c c vindcdc3 c i 1 f m 10 r v (b a t)
(8) vrtc output ldo1 and ldo2 trespwron vcc-filter tps65021 slvs613 ? october 2005 when a resistor divider is connected to defdcdcx, the output voltage can be set from 0.6 v up to the input voltage v (bat) . the total resistance (r1+r2) of the voltage divider should be kept in the 1-mr range in order to maintain a high efficiency at light load. v (defdcdcx) = 0.6 v the vrtc output is typically connected to the vcc_batt pin of a intel pxa270 processor. during power-up of the processor, the tps65021 internally switches from the ldo or the backup battery to the system voltage connected at the vsysin pin (see figure 25 ). it is recommended to add a capacitor of 4.7- m f minimum to the vrtc pin. the ldos in the tps65021 are general-purpose ldos which are stable using ceramics capacitors. the minimum output capacitor required is 2.2 m f. the ldos output voltage can be changed to different voltages between 1 v and 3.3 v using the i 2 c interface. therefore, they can also be used as general-purpose ldos in applications powering processors different from pxa270. the supply voltage for the ldos needs to be connected to the vinldo pin, giving the flexibility to connect the lowest voltage available in the system and provides the highest efficiency. this is the input to a capacitor that defines the reset delay time after the voltage at vrtc rises above 2.52 v. the timing is generated by charging and discharging the capacitor with a current of 2 m a between a threshold of 0.25 v and 1 v for 128 cycles. a 1-nf capacitor gives a delay time of 100 ms. an rc filter connected at the vcc input is used to keep noise from the internal supply for the bandgap and other analog circuitry. a typical value of 10r and 1 m f is used to filter the switching spikes, generated by the dc-dc converters. a larger resistor than 10r should not be used because the current into vcc of up to 3 ma causes a voltage drop at the resistor causing the undervoltage lockout circuitry connected at vcc internally to switch off too early. 39 www .ti.com v o u t v d e f d c d c 3 r 1 r 2 r 2 r 1 r 2 v o u t v d e f d c d c 3 r 2
application information typical configuration for the intel bulverde processor tps65021 slvs613 ? october 2005 40 www .ti.com vcc_core vcc_batt vcc_iovcc_lcd vcc_mem vcc_bbvcc_usim vcc_sram vcc_pll sys_en pwr_en 3 v3 v; 3.3 v 1.8 v; 2.5 v; 3 v; 3.3 v 1.8 v; 2.5 v; 3 v; 3.3 v 1.8 v; 2.5 v; 3 v; 3.3 v1.8 v; 3 v 1.3 v 1.1 v v ariable 0.85 v to 1.4 v ldo1 l3 l1 vr tc dcdc2_en ldo_en ldo2 nbatt_fault nreset nvcc_fault tps65021 l2 int respwron dcdc3_en pwrf ail dcdc1_en defdcdc3 defdcdc2 defdcdc1 v c c sclk sda t vr tc 4.7 k w 4.7 k w lowba t_sns pwrf ail_sns vbackup 3 v backup battery vindcdc1vindcdc2 vindcdc3 v c c v c c v c c 10 r 1 f m 10 f m 10 f m 10 f m trespwron hot_reset vsysin defldo2 defldo1 vdcdc1 sclksda t vin_ldo low_ba tt vdcdc1 vdcdc2 vdcdc3 22 f m 22 f m 22 f m 2.2 h m 2.2 h m 2.2 h m 2.2 f m 2.2 f m 4.7 f m 1 nf 1 mr gndgnd

packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) tps65021rhar active qfn rha 40 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr TPS65021RHARG4 active qfn rha 40 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr tps65021rhat active qfn rha 40 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr tps65021rhatg4 active qfn rha 40 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs) or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 16-dec-2005 addendum-page 1

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