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stel-1377q/s 2 the stel-1377q is a complete quadrature direct digital frequency synthesizer (dds) in a single dil package measuring only 3.75 x 1.6". the STEL-1377S provides a single ended output only. the stel-1377 makes it possible to use dds technology in applications requiring quadrature outputs as well as frequency and phase modulation in a small package. the stel-1377 is a printed circuit unit using the stel- 1177 pm and fm numerically controlled oscillator (nco) chip driving two high-speed 10-bit dacs (sony cx20201a-1) to generate quadrature analog output signals. surface mount technology (smt) components are used throughout. the device is guaranteed to operate at clock frequencies up to 60 mhz over the temperature range of 0-70 c, giving an output frequency range of 0 to over 25 mhz, with a frequency resolution of 14 millihz at a clock frequency of 60 mhz. in addition, the device features phase and frequency modulation capabilities at extremely high modulation rates, up to 25% of the clock frequency. for more detailed information on the stel-1177 nco please refer to the stel-1177 data sheet. for more information on the dac please refer to the sony cx20201a-1 data sheet. the output frequency is directly related to the clock frequency by the following: f c x d -phase f o = 2 32 where: f o is the frequency of the output signal and: f c is the clock frequency. features n high maximum clock frequency - up to 60 mhz n high output bandwidth - up to 25 mhz output frequency n high frequencyCresolution - 32 bits, 14 millihz @ 60 mhz n high speed frequency hopping or modulation - maximum update rate 15 mhz n precision phase modulation - 12 bits, 0.09 resolution can be used for linear pm or pulse-shaped psk at up to 15 mhz n precision frequency modulation - 16 bits resolution, can be used for linear fm or pulse-shaped fsk n sine and cosine outputs (stel-1377q) or single ended output (STEL-1377S) for lower power consumption n high-speed, low glitch ecl dacs n high spectral purity - C65 dbc spurious typical n 3.75" by 1.6" by 0.4" block diagram clock ecl/cmos level shifter vref stel- 1177 nco 10-bit dac sin out 8 data addr wrstb frld reset cmos-ecl trans- lators phld frsel phsel 10-bit dac cos out (stel- 1377q only) 10 cmos-ecl trans- lators 16 fmod fmad rate simld fmld fmsub fmsync 2 2 4 10 10 10
3 stel-1377q/s pin configuration package: 63-pin dip 49 phld 50 wrstb 51 phsel 52 v dd 53 csel 54 v ss 55 cin 56 v dd 57 dv ee (dac) 58 av ee (dac) 59 v ss 60 out (sin) 61 v ee 62 v ref 63 out (cos) (stel-1377q only) pin connections 1 clock 2v ee 3 rate 0 4 rate 1 5 fmld 6 fmsub 7 fmaddr 0 8 fmaddr 1 9 fmod 0 10 fmod 1 11 fmod 2 12 fmod 3 13 fmod 4 14 fmod 5 15 fmod 6 16 fmod 7 17 fmod 8 18 fmod 9 19 fmod 10 20 fmod 11 21 fmod 12 22 fmod 13 23 fmod 14 24 fmod 15 25 simld 26 n.c. 27 n.c. 28 n.c. 29 n.c. 30 n.c. 31 n.c. 32 data 7 33 data 6 34 data 5 35 data 4 36 data 3 37 data 2 38 data 1 39 data 0 40 addr 0 41 addr 1 42 addr 2 43 addr 3 44 frsel 45 fmsync 46 v ss 47 frld 48 reset 33 34 35 3.75" .01" 1.6" .01" 0.4" max . 0.2" max . 0.1" .005" pin d iame te r: 0.018" .002" 1.5" .01" c omp onent area, unencap sulated 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 20 19 21 22 23 24 25 26 27 28 29 30 31 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 32
stel-1377q/s 4 circuit description the frequency of the nco is determined by the number stored in the d -phase register which is programmed from the interface bus. the number stored in the d -phase register is added to the current contents of the accumulator every clock cycle to generate a monotonically increasing phase angle. by modulating this number the frequency of the nco can be modulated. the nco generates digitized sine and cosine functions by addressing sine and cosine lookup tables with the phase accumulator. phase modulation data is added to the accumulator output before the lookup tables. please refer to the stel-1177 data sheet for information on programming the nco. the nco output is passed through cmos to ecl level translators and loaded synchronously into two high- speed 10-bit dacs. the full-scale outputs of the dacs is determined by the voltage on the vref input, and this can be used to amplitude modulate the output signals. function block description nco block the nco block is the core of the stel-1377 dds. it consists of a front-end which may be programmed from the control inputs. the nco is described fully in the stel-1177 data sheet. please refer to this data sheet for more detailed information. level translator block the outputs of the nco block are cmos level digital signals. these are translated to ecl levels for optimum operation of the dac. clock generation block the clock generation block generates the different clocks required for the nco and dac blocks from the incoming ecl or sinusoidal clock signal. dac block the dac block consists of the sony cx20201a-1 digital to analog converters and the necessary supporting circuitry. input signals reset the reset input is asynchronous and active low, and clears all the registers in the device. when reset goes low, all registers are cleared within 20 nsecs, and normal operation will resume after this signal returns high. the outputs will go to the zero level during the reset, and thereafter will remain at the value corresponding to zero phase until new frequency or modulation (either frequency or phase) data is loaded with the frld , fmld , or phld inputs after the reset returns high. clock all synchronous functions performed within the nco are referenced to the rising edge of the clock input. the clock signal should be a square wave or sine wave at a maximum frequency of 60 mhz. a non- repetitive clock waveform is permissible as long as the minimum duration positive or negative pulse on the waveform is always greater than 5 nanoseconds. csel the c hip sel ect input is used to control the writing of data into the chip. it is active low. when this input is high all data writing via the data 7-0 bus is inhibited. data 7 through data 0 the 8-bit data 7-0 bus is used to program the two 32- bit d -phase registers and the two 12-bit phase modulation registers. data 0 is the least significant bit of the bus. the data programmed into the d -phase registers in this way determines the carrier frequency of the nco. addr 3 through addr 0 the four address lines addr 3-0 control the use of the data 7-0 bus for writing frequency data to the d -phase buffer registers, and phase data to the phase buffer registers, as shown in the table: addr 3 addr 1 addr 0 register field 000 d -phase bits 0 (lsb)C7 001 d -phase bits 8C15 010 d -phase bits 16C23 011 d -phase bits 24C31 1 0 0 sine bits 0(lsb)C3* 1 0 1 sine bits 4-11* 1 1 0 cosine bits 0(lsb)C3* 1 1 1 cosine bits 4-11* addr 3 addr 2 register selected 00 d -phase buffer register 'a' 01 d -phase buffer register 'b' 1 x phase buffer registers note: the phase buffer registers are 12-bit registers. when the least significant bytes of these registers are selected ( addr 3-0 =1xx0), data 7-4 is written into
5 stel-1377q/s bits 3C0 of the registers. in all cases, it is not necessary to reload unchanged bytes, and the byte loading sequence may be random. wrstb the wr ite st ro b e input is used to latch the data on the data 7-0 bus into the device. on the rising edge of the wrstb input, the information on the 8-bit data bus is transferred to the buffer register selected by the addr 3-0 bus. frsel the f requency r egister sel ect line is used to control the mux which selects the d -phase buffer register in use. when this signal is high d -phase buffer register 'a' is selected as the source for the d -phase alu, and the frequency corresponding to the data stored in this register will be generated by the nco after the next falling edge on the frld input. when this line is low, d -phase buffer register 'b' is selected as the source. frld the fr equency l oa d input is used to control the transfer of the data from the d -phase buffer registers to the d -phase alu. the data at the output of the mux block must be valid during the clock cycle following the falling edge of frld . the data is then transferred during the subsequent cycle. the frequency of the nco output will change 19 clock cycles after the frld command due to pipelining delays. phsel the ph ase source sel ect input selects the sources of data for the phase alus. when it is high the sources are the sine and cosine phase buffer registers. they are loaded from the data 7-0 bus by setting address line addr 3 high, as shown in the tables. when phsel is low, the sources for the phase modulation data are the data 7-0 and addr 3-0 inputs, and the data will be loaded independently of the states of wrstb and csel . the data on these 12 lines is presented directly as a parallel 12-bit word to both phase alus, allowing high-speed phase modulation. the 12-bit value is latched into the phase alus by means of the phld input. the data on the addr 3-0 lines is mapped onto phase bits 3 to 0 and the data on the data 7-0 lines are mapped onto phase bits 11 to 4 in this case. when using the parallel phase load mode csel and/or wrstb should remain high to ensure that the phase data is not written into the phase and frequency buffer registers of the stel-1377. phld the ph ase l oa d input is used to control the latching of the phase modulation data into the phase alus. the 12-bit data at the output of the phase modulation control block must be valid during the clock cycle following the falling edge of phld . the data is then transferred during the subsequent cycle. the 12-bit phase data is added to the 12 most significant bits of the accumulator output, so that the msb of the phase data represents a 180 phase change. the source of this data will be determined by the state of phsel . the phase of the nco output will change 12 clock cycles after the phld command, due to pipelining delays. fmod 15 through fmod 0 the f requency mod ulation bus is a 16-bit bus on which the fm data is loaded into the stel-1177. the data should be a 16-bit unsigned number. fmsub the fm sub tract input controls the add/subtract operation of the d -phase alu. when it is high the fm data on the fmod 15-0 bus will be subtracted from the carrier frequency, and when it is low the fm data will be added to the carrier frequency. in this way the fm data can be treated as a 17-bit signed-magnitude number, where the fmsub signal is the sign bit. fmaddr 1 through fmaddr 0 the two inputs fmaddr 1-0 set the deviation of the frequency modulation by controlling the significance of the fm data in relation to the carrier frequency data. the fm data word will be multiplied by 2 0 , 2 4 , 2 8 , or 2 12 according to the state of fmaddr 1-0 , and the consequent resolution and maximum values of the deviation are shown in the table below. the deviations and resolutions shown are for a clock frequency of 60 mhz. fm- fm- mult. factor maximum resol- addr 1 addr 0 of fm data deviation ution 00 2 0 915 hz 14 mhz 01 2 4 14.6 khz 0.22 hz 10 2 8 234 khz 3.6 hz 11 2 12 3.75 mhz 57 hz fmld the fm l oa d input controls the writing of the frequency modulation data on the fmod 15-0 bus and the fmsub input into the device. when rate 1-0 = 00 the data at the output of the frequency modulation control block must be valid during the clock cycle following the falling edge of fmld . the data is then transferred during the subsequent cycle. when rate 1-0 = 01, 10 or 11 are selected the fm data will be loaded automatically without the use of the fmld input. note that fmld must be held low during automatic operation, otherwise the loading will be inhibited.
stel-1377q/s 6 simld the sim ultaneous l oa d input allows the carrier frequency data from the mux block and the fm data to be updated simultaneously. when simld is low, only the fm data will be updated after a falling edge on fmld . when this input is high, both the fm data and carrier frequency data will be updated simultaneously. when simld is low at least four clock cycles are required between falling edges of fmld and frld to ensure glitch-free changes in the outputs. rate 1-0 the rate 1-0 signals control the rate at which the fm data on the fmod 15-0 bus is added to or subtracted from the carrier frequency, as shown in the table below: rate 1 rate 0 modulation update rate 0 0 manual, with fmld signal 0 1 every 4th clock cycle 1 0 every 8th clock cycle 1 1 every 16th clock cycle cin the c arry in put is an arithmetic carry to the least significant bit of the accumulator. normal operation of the nco requires that cin be set at a logic 0. when cin is set at a logic 1 the effective value of the d -phase register is increased by one. this allows the resolution of the accumulator to be expanded for higher frequency resolution. output signals out (sin) and out (cos) the signals appearing on the out pins are the analog outputs of the dacs. they are stepped sinewaves, where the number of steps in each cycle of the output is equal to the ratio of the clock frequency to the output frequency. when this number is not an integer the steps will not repeat from one cycle to the next, but the fundamental component of the output signal will always be a sinewave at the desired frequency. there will be a dc offset on the output signal. the outputs can be capacitively coupled if operation down to very low frequencies is not required, otherwise offset compensation should be provided externally. fmsync the fm sync output indicates the instant in time when the fm data on the fmod bus is written into the device. the fmsync output is normally high and goes low for one clock cycle at a frequency depending on the state of the rate 1-0 inputs. in the automatic modulation modes ( rate 1-0 1 00) the data on the fmod 15-0 bus will be written into the fm buffer register on the rising edge of the clock following the falling edge of fmsync . this signal can be used to synchronize the updating of the fm data externally. applications information since the stel-1377 combines high-speed digital and analog circuits, care must be taken to minimize the effects of noise from the digital circuit on the analog output. the following precautions will help in this area: 1. use ground and power planes on the printed circuit board. separate analog and digital ground planes will also help. 2. decouple the dv ee (dac) and av ee (dac) line from the v ee supply with 0.3 to 1 m h inductors. 3. decouple all the power supply pins and the vref pin to the appropriate ground plane with 1000 pf and 0.1 m f ceramic capacitors mounted as closely as possible to the pins. the clock input can be either a sine wave or a square wave, the input buffer will square up a sinusoidal input. the input is capacitively coupled internally. an ecl level signal or a sine wave at about C5 to +5 dbm (50 w ) is recommended. the bias circuit shown can be used to generate a stable vref. if high stability, which translates directly into output level stability, is not a requirement a much simpler circuit can be realized by replacing the 2.7k w and 2.2k w resistors and the reference diode with a single 8.2k w resistor from vref to the analog ground. the output level can be varied by adjusting the bias voltage with the 2k w pot in either case. 62 59 58 stel-1377 ana. gnd 2 k vref v ss av ee 2, 61, 57 v ee , dv ee C5.2 v (ana.) 2.7 k 2.2 k 2.5 v C5.2 v (dig.) dig. gnd v ss 46, 54 v dd 52, 56 +5 v recommended bias circuit for vref
7 stel-1377q/s electrical characteristics absolute maximum ratings warning: stresses greater than those shown below may cause permanent damage to the device. exposure of the device to these conditions for extended periods may also affect device reliability. symbol parameter range units t stg storage temperature C65 to +150 c t a operating temperature C40 to +85 c v ddmax max. voltage between v cc and v ss +7 to C0.7 volts v eemax max. voltage between v ee and v ss C7 to +0.7 volts v i/o(max) max. voltage on any input pin v dd +0.7 volts v i/o(min) min. voltage on any input pin v ss C0.7 volts recommended operating conditions (the v ss pins should be connected to ground) symbol parameter range units v dd supply voltage, +5 volts +5 10% volts v ee supply voltage, C5.2 volts C5.2 10% volts t a operating temperature (ambient) 0 to +70 c d.c. characteristics (operating conditions: v dd = 5.0 v 5%, v ee = C5.2 v 5%, t a = 25 c) symbol parameter min. typ. max. units conditions i dd supply current, +5 volts 700 ma @ 60 mhz clock (/q) i ee supply current, C5.2 volts 950 ma @ 60 mhz clock (/q) v ih(min) min. high level input voltage 2.0 volts guaranteed logic '1' v il(max) max. low level input voltage 0.8 volts guaranteed logic '0' i ih(max) max. high level input current 10 m av in = +5.0 volts i il(max) max. low level input current C10 m av in = 0 volts v clk clock input voltage 0.4 1.0 volts peak to peak output characteristics symbol parameter min. typ. max. units conditions p o(max) max. output power C5 dbm tc fs full-scale output temp. coefficient 0.06 0.12 % 50 w load ge output glitch energy 15 pv.sec. err (i) output integral linearity C0.1 +0.1 % of full-scale output v spur spurious signal level C65 dbc f out < .25 x f clk v spur spurious signal level C62 dbc .25 x f clk < f out < .33 x f clk v spur spurious signal level C60 dbc .33 x f clk < f out < .45 x f clk
stel-1377q/s 8 dds frequency change sequence a.c. characteristics (operating conditions: v dd =5.0 v 5%, v ee =C5.2 v 5%, t a =25 c) symbol parameter min. typ. max. units conditions t rs reset pulse width 20 nsec. t su data , addr or csel 5 nsec. to wrstb or phld setup and frld , phld , fmld or fmod to clock setup t hd data , addr or csel 5 nsec. to wrstb or phld setup and frld , phld , fmld or fmod to clock hold t ch clock high 5 nsec. f clk = 60 mhz t cl clock low 5 nsec. f clk = 60 mhz t w wrstb , frld , phld or fmld pulse width 5 nsec. new frequency old frequency 1 2 3 20 clock edges don't care out frld fsync clock wrstb csel addr 3-0 don't care data 7-0 t su 19 20 t hd t w t su t w t cl t ch don't care don't care
9 stel-1377q/s dds phase change sequence 2. phsel = 1. bus loading 1. phsel = 0. direct loading new phase old phase 1 2 3 13 clock edges 12 13 don't care don't care phld clock data 7-0 addr 3-0 out t su t su t w t hd data 7-0 1 2 3 13 clock edges 12 13 don't care don't care phld clock wrstb csel addr 3-0 don't care don't care new phase old phase out t su t w t hd t su t w
stel-1377q/s 10 1. rate = 00. manual loading nco frequency modulation sequence fmod 15-0 new frequency old frequency don't care don't care fmld clock valid 20 clock edges fmsync sync t hd t su t w t su t cd out don't care don't care clock fmsync valid don't care valid 4 clock cycles fmld fmod 15-0 sine 11-0 cos 11-0 t hd t su 2. rate 1 00.automatic loading (rate = 01 shown)
11 stel-1377q/s
stel-1377q/s 12 spectral purity when an nco is used with a digital to analog converter (dac) to generate an analog waveform the spectral purity of the synthesized waveform is a function of many variables, including the phase and amplitude quantization, the ratio of the clock frequency to output frequency, and the dynamic characteristics of the dac. the sine signals generated by the stel-1177 have 12 bits of amplitude resolution and 13 bits of phase resolution which results in spurious levels which are theoretically at least 75 db down. the highest output frequency the nco can generate is half the clock frequency (f c /2), and the spurious components at frequencies greater than f c /2 can be removed by filtering. as the output frequency f o of the nco approaches f c /2, the "image" spur at f c C f o (created by the sampling process) also approaches f c /2 from above. if the programmed output frequency is very close to f c /2 it will be virtually impossible to remove this image spur by filtering. for this reason, the maximum practical output frequency of the nco should be limited to about 40% of the clock frequency. a spectral plot of the nco output after conversion with a dac (sony cx20202a-1) is shown below. in this case, the clock frequency is 60 mhz and the output frequency is programmed to 6.789 mhz. the maximum non-harmonic spur level observed over the output frequency range shown in this case is C70 dbc. the spur levels are limited by the dynamic linearity of the dac. it is important to remember that when the output frequency exceeds 25% of the clock frequency, the second harmonic frequency will be higher than the nyquist frequency, 50% of the clock frequency. when this happens, the image of the harmonic at the frequency f c C 2f o , which is not harmonically related to the output signal, will become intrusive since its frequency falls as the output frequency rises, eventually crossing the fundamental output when its frequency crosses through f c /3. the same phenomenon occurs with the third harmonic when the frequency crosses through f c /4. typical spectrum center frequency: 10.0 mhz frequency span: 20.0 mhz reference level: C5 dbm resolution bandwidth: 1 khz scale: log, 10 db/div output frequency: 6.789 mhz clock frequency: 60 mhz

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