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34 .807ireless important notice dear customer, as from august 2 nd 2008, the wireless operations of nxp have moved to a new company, st-nxp wireless. as a result, the following changes are applicable to the attached document. company name - nxp b.v. is replaced with st-nxp wireless . copyright - the copyright notice at the bottom of each page ?? nxp b.v. 200x. all rights reserved?, shall now read: ?? st-nxp wireless 200x - all rights reserved?. web site - http://www.nxp.com is replaced with http://www.stnwireless.com contact information - the list of sales offices previo usly obtained by sending an email to salesaddresses@nxp.com , is now found at http://www.stnwireless.com under contacts. if you have any questions related to the document, please contact our nearest sales office. thank you for your cooperation and understanding. st-nxp wireless 34 .807ireless www.stnwireless.com
1. general description the isp1564 is a peripheral component interconnect (pci)-based, single-chip universal serial bus (usb) host controller. it integrates one original usb open host controller interface (ohci) core, one hi-speed usb enhanced host controller interface (ehci) core, and two transceivers that are compliant with hi-speed usb and original usb. the functional parts of the isp1564 are fully compliant with universal serial bus speci?cation rev. 2.0 , open host controller interface speci?cation for usb rev. 1.0a , enhanced host controller interface speci?cation for universal serial bus rev. 1.0 , pci local bus speci?cation rev. 2.2 , and pci bus power management interface speci?cation rev. 1.1 . the isp1564 is pin-to-pin and function compatible with the nxp isp1562, subject to the structure of the software. integrated high performance usb transceivers allow the isp1564 to handle all hi-speed usb transfer speed modes: high-speed (480 mbit/s), full-speed (12 mbit/s) and low-speed (1.5 mbit/s). the isp1564 provides two downstream ports, allowing simultaneous connection of usb devices at different speeds. the isp1564 is fully compatible with various operating system drivers, such as microsoft windows standard ohci and ehci drivers that are present in windows xp, windows 2000 and red hat linux. the isp1564 directly interfaces to any 32-bit, 33 mhz pci bus. its pci pins can source 3.3 v. the isp1564 is ideally suited for use in hi-speed usb mobile applications and embedded solutions. 2. features n complies with universal serial bus speci?cation rev. 2.0 n complies with pci local bus speci?cation rev. 2.2 n supports data transfer at high-speed (480 mbit/s), full-speed (12 mbit/s) and low-speed (1.5 mbit/s) n one original usb ohci core is compliant with open host controller interface speci?cation for usb rev. 1.0a n one hi-speed usb ehci core is compliant with enhanced host controller interface speci?cation for universal serial bus rev. 1.0 isp1564 hi-speed usb pci host controller rev. 02 13 november 2008 product data sheet
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 2 of 98 nxp semiconductors isp1564 hs usb pci host controller n supports pci 32-bit, 33 mhz interface compliant with pci local bus speci?cation rev. 2.2 , with support for d3 cold standby and wake-up modes; all i/o pins are 3.3 v standard n compliant with pci bus power management interface speci?cation rev. 1.1 for all hosts (ehci and ohci), and supports all power states: d0, d1, d2, d3 hot and d3 cold n clkrun support for mobile applications, such as internal notebook design n con?gurable subsystem id and subsystem vendor id through external eeprom n external eeprom can be programmed using the external pci interface; refer to appendix i of pci local bus speci?cation rev. 2.2 n digital and analog power separation for better electromagnetic interference (emi) and electrostatic discharge (esd) protection n supports hot plug and play and remote wake-up of peripherals n supports individual power switching and individual overcurrent protection for downstream ports n supports partial dynamic port-routing capability for downstream ports that allows sharing of the same physical downstream ports between the original usb host controller and the hi-speed usb host controller n uses 12 mhz crystal oscillator to reduce system cost and emi emissions n supports dual power supply: pci v aux(3v3) and v cc n operates at +3.3 v power supply input n low power consumption n full industrial operating temperature range from - 40 cto+85 c n available in lqfp100 and tfbga100 packages 3. applications n digital consumer appliances: u portable consumer u home entertainment n notebook n pci add-on card n pc motherboard 4. ordering information table 1. ordering information type number package name description pitch version ISP1564HL lqfp100 plastic low pro?le quad ?at package; 100 leads; body 14 14 1.4 mm 0.5 mm sot407-1 isp1564et tfbga100 plastic thin ?ne-pitch ball grid array package; 100 balls; body 9 9 0.7 mm 0.8 mm sot926-1
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 3 of 98 nxp semiconductors isp1564 hs usb pci host controller 5. block diagram remark: the ?gure shows the lqfp pinout. for the tfbga ballout, see t ab le 2 . fig 1. block diagram 78 74 5 7 96 97 99 75 79 83 85 isp1564 32-bit, 33 mhz pci bus xtal1 xtal2 original usb atx hi-speed usb atx atx1 original usb atx hi-speed usb atx atx2 configuration space pci core pci master pci slave configuration function 0 configuration function 2 xosc pll por v cc(i/o) detect ad[31:0] c/be[3:0]# req# gnt# idsel inta# frame# devsel# irdy# clkrun# par perr# serr# trdy# stop# rst# global control port router scl sda v cc(io) oc1_n pwe1_n dm1 dp1 rref core reset_n 1, 17, 46, 61, 72, 82, 84, 89, 91 81 pme# clk 004aaa790 gnda gnd reg(1v8) voltage regulator v cc core 87 88 90 92 oc2_n pwe2_n dm2 dp2 ram ohci (function 0) ram ehci (function 2) 19, 32, 49, 64, 76, 94, 95 4 8 9 10, 12 to 15, 20 to 22, 26 to 31, 33, 34, 50 to 54, 56, 57, 59, 62, 63, 65 to 70 11, 25, 40, 55, 71 18, 43, 58 23, 35, 48, 60 24 36 37 38 39 41 42 44 45 47 v cc(reg) 16 v cc(io)aux 77, 98, 100 v cca(aux) 86, 93 32 v cc(aux) voltage regulator (v aux ) v aux(1v8) core aux(1v8) 2, 73 3 gnd _rref 80 sys_tune 6
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 4 of 98 nxp semiconductors isp1564 hs usb pci host controller 6. pinning information 6.1 pinning fig 2. pin con?guration lqfp100 (top view) ISP1564HL gnda xtal2 aux(1v8) xtal1 v cc(aux) aux(1v8) inta# gnda rst# v cc(io) sys_tune ad[0] clk ad[1] gnt# ad[2] req# ad[3] ad[31] ad[4] v cc(io) ad[5] ad[30] gnd ad[29] ad[6] ad[28] ad[7] ad[26] ad[10] ad[25] v cc(io) ad[24] ad[11] c/be[3]# ad[12] idsel ad[27] v cc(reg) gnda reg(1v8) gnd ad[13] gnda c/be[0]# ad[8] reg(1v8) ad[9] v cc(io) ad[14] ad[23] v cc(io)aux ad[22] pme# ad[21] v cc(io)aux ad[20] sda ad[19] scl ad[18] gnd gnd gnd ad[17] v cca(aux) ad[16] dp2 c/be[2]# gnda frame# dm2 irdy# gnda trdy# pwe2_n devsel# oc2_n serr# rref gnda gnd_rref par pwe1_n c/be[1]# oc1_n gnd v cc(io) stop# clkrun# reg(1v8) perr# v cc(io)aux v cca(aux) dp1 gnda dm1 gnda ad[15] gnd 004aaa791 1 2 3 4 5 6 7 8 9 10 11 12 13 14 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 56 55 54 53 52 51 15 16 17 18 19 61 60 59 58 57 26 27 28 29 30 31 32 33 34 35 36 37 38 39 45 46 47 48 49 50 10 0 99 98 97 96 95 94 93 92 91 90 89 88 87 81 80 79 78 77 76 40 41 42 43 44 86 85 84 83 82
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 5 of 98 nxp semiconductors isp1564 hs usb pci host controller 6.2 pin description fig 3. pin con?guration tfbga100 (top view) 004aaa815 isp1564et transparent top view j g k h f e d c b a 246810 13579 ball a1 index area table 2. pin description symbol [1] pin type [2] description lqfp100 tfbga100 gnda 1 b1 - analog ground aux(1v8) 2 c2 - 1.8 v auxiliary output voltage; only for voltage conditioning; cannot be used to supply power to external components; see section 7.8 v cc(aux) 3 c1 - auxiliary supply voltage; see section 7.8 inta# 4 d1 o pci interrupt pci pad; 3.3 v signaling; open-drain rst# 5 c3 i pci reset; used to bring pci-speci?c registers, sequencers and signals to a consistent state 3.3 v input pad; cmos sys_tune 6 c6 i used for system tuning; for connection details, see section 11.4 and t ab le 118 clk 7 d2 i pci system clock; see t ab le 128 pci pad; 3.3 v signaling gnt# 8 d3 i pci grant; indicates to the agent that access to the bus is granted pci pad; 3.3 v signaling req# 9 d4 o pci request; indicates to the arbitrator that the agent wants to use the bus pci pad; 3.3 v signaling ad[31] 10 e1 i/o bit 31 of multiplexed pci address and data pci pad; 3.3 v signaling v cc(io) 11 e2 - i/o pads supply voltage; see section 7.8 ad[30] 12 e3 i/o bit 30 of multiplexed pci address and data pci pad; 3.3 v signaling
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 6 of 98 nxp semiconductors isp1564 hs usb pci host controller ad[29] 13 e4 i/o bit 29 of multiplexed pci address and data pci pad; 3.3 v signaling ad[28] 14 e5 i/o bit 28 of multiplexed pci address and data pci pad; 3.3 v signaling ad[27] 15 f3 i/o bit 27 of multiplexed pci address and data pci pad; 3.3 v signaling v cc(reg) 16 f1 - regulator supply voltage; see section 7.8 gnda 17 g1 - analog ground reg(1v8) 18 g2 - 1.8 v regulator output voltage; only for voltage conditioning; cannot be used to supply power to external components; see section 7.8 gnd 19 f4 - ground ad[26] 20 f2 i/o bit 26 of multiplexed pci address and data pci pad; 3.3 v signaling ad[25] 21 g3 i/o bit 25 of multiplexed pci address and data pci pad; 3.3 v signaling ad[24] 22 h1 i/o bit 24 of multiplexed pci address and data pci pad; 3.3 v signaling c/be[3]# 23 h2 i/o byte 3 of multiplexed pci bus command and byte enable pci pad; 3.3 v signaling idsel 24 j1 i pci initialization device select; used as a chip select during con?guration read and write transactions pci pad; 3.3 v signaling v cc(io) 25 j2 - i/o pads supply voltage; see section 7.8 ad[23] 26 k1 i/o bit 23 of multiplexed pci address and data pci pad; 3.3 v signaling ad[22] 27 k2 i/o bit 22 of multiplexed pci address and data pci pad; 3.3 v signaling ad[21] 28 h3 i/o bit 21 of multiplexed pci address and data pci pad; 3.3 v signaling ad[20] 29 j3 i/o bit 20 of multiplexed pci address and data pci pad; 3.3 v signaling ad[19] 30 k3 i/o bit 19 of multiplexed pci address and data pci pad; 3.3 v signaling ad[18] 31 g4 i/o bit 18 of multiplexed pci address and data pci pad; 3.3 v signaling gnd 32 h4 - ground ad[17] 33 j4 i/o bit 17 of multiplexed pci address and data pci pad; 3.3 v signaling ad[16] 34 k4 i/o bit 16 of multiplexed pci address and data pci pad; 3.3 v signaling table 2. pin description continued symbol [1] pin type [2] description lqfp100 tfbga100
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 7 of 98 nxp semiconductors isp1564 hs usb pci host controller c/be[2]# 35 f5 i/o byte 2 of multiplexed pci bus command and byte enable pci pad; 3.3 v signaling frame# 36 g5 i/o pci cycle frame; driven by the master to indicate the beginning and duration of an access pci pad; 3.3 v signaling irdy# 37 h5 i/o pci initiator ready; indicates the ability of the initiating agent to complete the current data phase of a transaction pci pad; 3.3 v signaling trdy# 38 j5 i/o pci target ready; indicates the ability of the target agent to complete the current data phase of a transaction pci pad; 3.3 v signaling devsel# 39 h6 i/o pci device select; indicates if any device is selected on the bus pci pad; 3.3 v signaling v cc(io) 40 k5 - i/o pads supply voltage; see section 7.8 stop# 41 g6 i/o pci stop; indicates that the current target is requesting the master to stop the current transaction pci pad; 3.3 v signaling clkrun# 42 k6 i/o pci clkrun signal; pull down to ground through a 10 k w resistor pci pad; 3.3 v signaling; open-drain reg(1v8) 43 j6 - 1.8 v regulator output voltage; only for voltage conditioning; cannot be used to supply power to external components; see section 7.8 perr# 44 j7 i/o pci parity error; used to report data parity errors during all pci transactions, except a special cycle pci pad; 3.3 v signaling serr# 45 j8 o pci system error; used to report address parity errors and data parity errors on the special cycle command, or any other system error in which the result will be catastrophic pci pad; 3.3 v signaling; open-drain gnda 46 k7 - analog ground par 47 k8 i/o pci parity pci pad; 3.3 v signaling c/be[1]# 48 k9 i/o byte 1 of multiplexed pci bus command and byte enable pci pad; 3.3 v signaling gnd 49 h7 - ground ad[15] 50 k10 i/o bit 15 of multiplexed pci address and data pci pad; 3.3 v signaling ad[14] 51 j10 i/o bit 14 of multiplexed pci address and data pci pad; 3.3 v signaling ad[13] 52 h10 i/o bit 13 of multiplexed pci address and data pci pad; 3.3 v signaling ad[12] 53 h9 i/o bit 12 of multiplexed pci address and data pci pad; 3.3 v signaling table 2. pin description continued symbol [1] pin type [2] description lqfp100 tfbga100
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 8 of 98 nxp semiconductors isp1564 hs usb pci host controller ad[11] 54 h8 i/o bit 11 of multiplexed pci address and data pci pad; 3.3 v signaling v cc(io) 55 j9 - i/o pads supply voltage; see section 7.8 ad[10] 56 g7 i/o bit 10 of multiplexed pci address and data pci pad; 3.3 v signaling ad[9] 57 g8 i/o bit 9 of multiplexed pci address and data pci pad; 3.3 v signaling reg(1v8) 58 g9 - 1.8 v regulator output voltage; only for voltage conditioning; cannot be used to supply power to external components; see section 7.8 ad[8] 59 f10 i/o bit 8 of multiplexed pci address and data pci pad; 3.3 v signaling c/be[0]# 60 f6 i/o byte 0 of multiplexed pci bus command and byte enable pci pad; 3.3 v signaling gnda 61 g10 - analog ground ad[7] 62 f9 i/o bit 7 of multiplexed pci address and data pci pad; 3.3 v signaling ad[6] 63 f8 i/o bit 6 of multiplexed pci address and data pci pad; 3.3 v signaling gnd 64 f7 - ground ad[5] 65 e7 i/o bit 5 of multiplexed pci address and data pci pad; 3.3 v signaling ad[4] 66 e8 i/o bit 4 of multiplexed pci address and data pci pad; 3.3 v signaling ad[3] 67 e10 i/o bit 3 of multiplexed pci address and data pci pad; 3.3 v signaling ad[2] 68 d10 i/o bit 2 of multiplexed pci address and data pci pad; 3.3 v signaling ad[1] 69 d9 i/o bit 1 of multiplexed pci address and data pci pad; 3.3 v signaling ad[0] 70 d8 i/o bit 0 of multiplexed pci address and data pci pad; 3.3 v signaling v cc(io) 71 e9 - i/o pads supply voltage; see section 7.8 gnda 72 c10 - analog ground aux(1v8) 73 b9 - 1.8 v auxiliary output voltage; only for voltage conditioning; cannot be used to supply power to external components; see section 7.8 xtal1 74 b10 ai crystal oscillator input; this can also be a 12 mhz clock input at 1.8 v xtal2 75 a10 ao crystal oscillator output (12 mhz); leave open when clock is used gnd 76 c8 - ground v cc(io)aux 77 a9 - i/o pads auxiliary supply voltage; see section 7.8 oc1_n 78 c9 i overcurrent sense input for the usb downstream port 1 (digital); when not in use, connect this pin to 3.3 v 3.3 v input pad; cmos table 2. pin description continued symbol [1] pin type [2] description lqfp100 tfbga100
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 9 of 98 nxp semiconductors isp1564 hs usb pci host controller [1] symbol names ending with # represent active low signals for pci pins, for example: name#. symbol names ending with underscore n represent active low signals for usb pins, for example: name_n. [2] i = input; o = output; i/o = input/output; ai/o = analog input/output; ai = analog input; ao = analog output. [3] connect to ground if i 2 c-bus is not used. pwe1_n 79 d7 o power enable for the usb downstream port 1 3.3 v output pad; 3 ns slew rate control; cmos; open-drain gnd_rref 80 a8 - ground for external resistor on pin rref rref 81 b8 ai/o analog connection for the external resistor (11 k w 1%) gnda 82 c7 - analog ground dm1 83 a7 ai/o d - ; analog connection for the usb downstream port 1; pull down to ground through a 15 k w resistor, even when the port is not used gnda 84 b7 - analog ground dp1 85 a6 ai/o d+; analog connection for the usb downstream port 1; pull down to ground through a 15 k w resistor, even when the port is not used v cca(aux) 86 b6 - auxiliary analog supply voltage; see section 7.8 oc2_n 87 e6 i overcurrent sense input for the usb downstream port 2 (digital); when not in use, connect this pin to 3.3 v 3.3 v input pad; cmos pwe2_n 88 d6 o power enable for the usb downstream port 2 3.3 v output pad; 3 ns slew rate control; cmos; open-drain gnda 89 c5 - analog ground dm2 90 a5 ai/o d - ; analog connection for the usb downstream port 2; pull down to ground through a 15 k w resistor, even when the port is not used gnda 91 b5 - analog ground dp2 92 a4 ai/o d+; analog connection for the usb downstream port 2; pull down to ground through a 15 k w resistor, even when the port is not used v cca(aux) 93 b4 - auxiliary analog supply voltage; see section 7.8 gnd 94 b2 - ground gnd 95 d5 - ground scl 96 b3 i/o i 2 c-bus clock; pull up to 3.3 v through a 10 k w resistor [3] i 2 c-bus pad; clock signal sda 97 a3 i/o i 2 c-bus data; pull up to 3.3 v through a 10 k w resistor [3] i 2 c-bus pad; data signal v cc(io)aux 98 a2 - i/o pads auxiliary supply voltage; see section 7.8 pme# 99 a1 o pci power management event; used by a device to request a change in the device or system power state pci pad; 3.3 v signaling; open-drain v cc(io)aux 100 c4 - i/o pads auxiliary supply voltage; see section 7.8 table 2. pin description continued symbol [1] pin type [2] description lqfp100 tfbga100
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 10 of 98 nxp semiconductors isp1564 hs usb pci host controller 7. functional description 7.1 ohci host controller an ohci host controller per port transfers data to devices at the original usb de?ned bit rate of 12 mbit/s or 1.5 mbit/s. 7.2 ehci host controller the ehci host controller transfers data to a hi-speed usb compliant device at the hi-speed usb de?ned bit rate of 480 mbit/s. when the ehci host controller has the ownership of a port, ohci host controllers are not allowed to modify the port register. all additional port bit de?nitions required for the enhanced host controller are not visible to the ohci host controller. 7.3 dynamic port-routing logic the port-routing feature allows sharing of the same physical downstream ports between the original usb host controller and the hi-speed usb host controller. this requirement of enhanced host controller interface speci?cation for universal serial bus rev. 1.0 provides ports that are multiplexed with the ports of the ohci. the ehci is responsible for the port-routing switching mechanism. two register bits are used for ownership switching. during power-on and system reset, the default ownership of all downstream ports is the ohci. the enhanced host controller driver (hcd) controls the ownership during normal functionality. 7.4 hi-speed usb analog transceivers the hi-speed usb analog transceivers directly interface to the usb cables through integrated termination resistors. these transceivers can transmit and receive serial data at all data rates: high-speed (480 mbit/s), full-speed (12 mbit/s) and low-speed (1.5 mbit/s). 7.5 power management the isp1564 provides an advanced power management capability interface that is compliant with pci bus power management interface speci?cation rev. 1.1 . power is controlled and managed by the interaction between drivers and pci registers. for a detailed description on power management, see section 10 . 7.6 phase-locked loop (pll) a 12 mhz-to-30 mhz and 48 mhz clock multiplier pll is integrated on-chip. this allows the use of a low-cost 12 mhz crystal, which also minimizes emi.
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 11 of 98 nxp semiconductors isp1564 hs usb pci host controller 7.7 power-on reset (por) figure 4 shows a possible curve of v i(vaux3v3) and v i(vreg3v3) with dips at t2 to t3 and t4 to t5. at t0, por will start with 1. at t1, the detector passes through the trip level. another delay will be added before por drops to 0 to ensure that the length of the generated detector pulse, por, is large enough to reset asynchronous ?ip-?ops. if the dip is too short (t4 to t5 < 11 m s), por will not react and will stay low. 7.8 power supply figure 5 shows the isp1564 power supply connection. v por(trip) is typically 0.9 v. fig 4. power-on reset 004aab194 v i(vaux3v3), v i(vreg3v3) t0 t1 t2 t3 t4 t5 v por(trip) por
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 12 of 98 nxp semiconductors isp1564 hs usb pci host controller 8. pci 8.1 pci interface the pci interface has two functions. function #0 is for the ohci host controller and function #2 is for the ehci host controller. these functions support both master and target accesses, and share the same pci interrupt signal inta#. these functions provide memory-mapped, addressable operational registers as required in open host controller interface speci?cation for usb rev. 1.0a and enhanced host controller interface speci?cation for universal serial bus rev. 1.0 . remark: the 100 nf capacitor is needed on each individual pin, and is not shared among the listed pins. remark: the ?gure shows the lqfp pinout. for the tfbga ballout, see t ab le 2 . (1) if v aux(3v3) is not present on pci, the pin must be connected to pci 3.3 v. (2) this electrolytic or tantalum capacitor must be of low esr type (0.2 w to 2 w ). (3) the use of ferrite bead is optional. can be directly tied to ground. (4) this electrolytic or tantalum capacitor is needed only on pin 2. (5) this electrolytic or tantalum capacitor is needed only on pin 18. fig 5. power supply connection 004aaa792 16 isp1564 v cc(reg) aux(1v8) 2, 73 4.7 m f (2)(4) 100 nf 100 nf reg(1v8) 18, 43, 58 4.7 m f (2)( 5 ) 100 nf gnda 1, 17, 46, 61, 72, 82, 84, 89, 91 v cca(aux) 86, 93 100 nf v cc(io)aux 77, 98, 100 100 nf v cc(aux) 3 100 nf 11, 25, 40, 55, 71 v cc(io) 100 nf pci 3.3 v pci 3.3 v pci v aux(3v3) (1) pci v aux(3v3) (1) pci v aux(3v3) (1) 80 gnd_rref (3) 19, 32, 49, 64, 76, 94, 95 gnd
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 13 of 98 nxp semiconductors isp1564 hs usb pci host controller each function has its own con?guration space. the pci enumerator must allocate the memory address space for each of these functions. power management is implemented in each pci function and all power states are provided. this allows the system to achieve low power consumption by switching off the functions that are not required. 8.1.1 pci con?guration space pci local bus speci?cation rev. 2.2 requires that each of the two pci functions of the isp1564 provides its own pci con?guration registers, which can vary in size. in addition to the basic pci con?guration header registers, these functions implement capability registers to support power management. the registers of each of these functions are accessed by the respective driver. section 8.2 provides a detailed description of various pci con?guration registers. 8.1.2 pci initiator and target a pci initiator initiates pci transactions to the pci bus. a pci target responds to pci transactions as a slave. in the isp1564, the open host controller and the enhanced host controller function as both initiators or targets of pci transactions issued by the host cpu. all usb host controllers have their own operational registers that can be accessed by the system driver software. drivers use these registers to con?gure the host controller hardware system, issue commands to it, and monitor the status of the current hardware operation. the host controller plays the role of a pci target. all operational registers of the host controllers are the pci transaction targets of the cpu. normal usb transfers require the host controller to access system memory ?elds, which are allocated by usb hcds and pci drivers. the host controller hardware interacts with the hcd by accessing these buffers. the host controller works as an initiator in this case and becomes a pci master. 8.2 pci con?guration registers ohci usb host controllers and the ehci usb host controller contain two sets of software-accessible hardware registers: pci con?guration registers and memory-mapped host controller registers. a set of con?guration registers is implemented for each of the two pci functions of the isp1564, see t ab le 3 . remark: in addition to the normal pci header, from offset index 00h to 3fh, implementation-speci?c registers are de?ned to support power management and function-speci?c features. the hcd does not usually interact with the pci con?guration space. the con?guration space is used only by the pci enumerator to identify the usb host controller and assign appropriate system resources by reading the vendor id (vid) and the device id (did).
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 14 of 98 nxp semiconductors isp1564 hs usb pci host controller [1] reset values that are highlighted (for example, 0 ) indicate read and write accesses; and reset values that are not highlighted (for example, 0) indicate read-only. [2] see section 8.2.3.4 . 8.2.1 pci con?guration header registers the enhanced host controller implements normal pci header register values, except the values for the memory-mapping base address register, serial bus number and device id. table 3. pci con?guration space registers of ohci and ehci address bits 31 to 24 bits 23 to 16 bits 15 to 8 bits 7 to 0 reset value [1] func0 ohci func2 ehci pci con?guration header registers 00h device id[15:0] vendor id[15:0] 1561 1131h 1562 1131h 04h status[15:0] command[15:0] 0210 0000 h 0210 0000 h 08h class code[23:0] revision id[7:0] 0c03 1011h 0c03 2011h 0ch reserved header type[7:0] latency timer[7:0] cacheline size[7:0] 0080 0000 h 0080 0000 h 10h base address 0[31:0] 0000 0 000h 0000 00 00h 14h reserved 0000 0000h 0000 0000h 18h 1ch 20h 24h 28h 2ch subsystem id[15:0] subsystem vendor id[15:0] 1561 1131h 1562 1131h 30h reserved 0000 0000h 0000 0000h 34h reserved capabilities pointer[7:0] 0000 00dch 0000 00dch 38h reserved 0000 0000h 0000 0000h 3ch max_lat[7:0] min_gnt[7:0] interrupt pin[7:0] interrupt line[7:0] 2a01 0100 h 1002 0100 h 40h reserved retry timeout trdy timeout 0000 0000 h 0000 0000 h enhanced host controller-speci?c pci registers 60h portwakecap[15:0] fladj[7:0] sbrn[7:0] - 0007 20 20h power management registers dch pmc[15:0] next_item_ptr [7:0] cap_id[7:0] d282 0001h fe82 e401h e0h data[7:0] pmcsr_bse [7:0] pmcsr[15:0] 0000 xx00 h [2] 0000 xx00 h [2] vpd speci?c registers e4h vpd_addr[15:0] vpd_next_item _ptr[7:0] vpd_cap_id [7:0] - 0000 0003h e8h vpd_data[31:0] - 0000 0000h
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 15 of 98 nxp semiconductors isp1564 hs usb pci host controller 8.2.1.1 vendor id register this read-only register identi?es the manufacturer of the device. pci special interest group (pci-sig) assigns valid vendor identi?ers to ensure the uniqueness of the identi?er. the bit description is shown in t ab le 4 . 8.2.1.2 device id register this is a 2-byte read-only register that identi?es a particular device. the identi?er is allocated by nxp semiconductors. t ab le 5 shows the bit description of the register. [1] x is 1h for ohci; x is 2h for ehci. 8.2.1.3 command register this is a 2-byte register that provides coarse control over the ability of a device to generate and respond to pci cycles. the bit allocation of the command register is given in t ab le 6 . when logic 0 is written to this register, the device is logically disconnected from the pci bus for all accesses, except con?guration accesses. all devices are required to support this base level of functionality. individual bits in the command register may or may not support this base level of functionality. [1] the reserved bits must always be written with the reset value. table 4. vid - vendor id register (address 00h) bit description legend: * reset value bit symbol access value description 15 to 0 vid[15:0] r 1131h* vendor id : this read-only register value is assigned to nxp semiconductors by pci-sig as 1131h. table 5. did - device id register (address 02h) bit description legend: * reset value bit symbol access value description 15 to 0 did[15:0] r 156xh* [1] device id : this register value is de?ned by nxp semiconductors to identify the usb host controller ic product. table 6. command register (address 04h) bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved [1] fbbe serre reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol sctrl per vgaps mwie sc bm ms ios reset 00000000 access r r/w r r/w r r/w r/w r/w
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 16 of 98 nxp semiconductors isp1564 hs usb pci host controller table 7. command register (address 04h) bit description bit symbol description 15 to 10 reserved - 9 fbbe fast back-to-back enable : this bit controls whether a master can do fast back-to-back transactions to various devices. the initialization software must set this bit if all targets are fast back-to-back capable. 0 fast back-to-back transactions are only allowed to the same agent (value after rst#). 1 the master is allowed to generate fast back-to-back transactions to different agents. 8 serre serr# enable : this bit is an enable bit for the serr# driver. all devices that have an serr# pin must implement this bit. address parity errors are reported only if this bit and the per bit are logic 1. 0 disable the serr# driver. 1 enable the serr# driver. 7 sctrl stepping control : this bit controls whether a device does address and data stepping. devices that never do stepping must clear this bit. devices that always do stepping must set this bit. devices that can do either, must make this bit read or write, and initialize it to logic 1 after rst#. 6 per parity error response : this bit controls the response of a device to parity errors. when the bit is set, the device must take its normal action when a parity error is detected. when the bit is logic 0, the device sets dpe (bit 15 in the status register) when an error is detected, but does not assert perr# and continues normal operation. the state of this bit after rst# is logic 0. devices that check parity must implement this bit. devices are required to generate parity, even if parity checking is disabled. 5 vgaps vga palette snoop : this bit controls how vga compatible and graphics devices handle accesses to vga palette registers. 0 the device must treat palette write accesses like all other accesses. 1 palette snooping is enabled, that is, the device does not respond to palette register writes and snoops data. vga compatible devices must implement this bit. 4 mwie memory write and invalidate enable : this is an enable bit for using the memory write and invalidate command. 0 memory writes must be used instead. state after rst# is logic 0. 1 masters may generate the command. this bit must be implemented by master devices that can generate the memory write and invalidate command. 3sc special cycles : controls the action of a device on special cycle operations. 0 causes the device to ignore all special cycle operations. state after rst# is logic 0. 1 allows the device to monitor special cycle operations. 2bm bus master : controls the ability of a device to act as a master on the pci bus. 0 disables the device from generating pci accesses. state after rst# is logic 0. 1 allows the device to behave as a bus master. 1ms memory space : controls the response of a device to memory space accesses. 0 disables the device response. state after rst# is logic 0. 1 allows the device to respond to memory space accesses. 0 ios io space : controls the response of a device to i/o space accesses. 0 disables the device response. state after rst# is logic 0. 1 allows the device to respond to i/o space accesses.
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 17 of 98 nxp semiconductors isp1564 hs usb pci host controller 8.2.1.4 status register the status register is a 2-byte read-only register used to record status information on pci bus-related events. for bit allocation, see t ab le 8 . table 8. status register (address 06h) bit allocation bit 15 14 13 12 11 10 9 8 symbol dpe sse rma rta sta devselt[1:0] mdpe reset 00000010 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol fbbc reserved 66mc cl reserved reset 00010000 access rrrrrrrr table 9. status register (address 06h) bit description bit symbol description 15 dpe detected parity error : this bit must be set by the device whenever it detects a parity error, even if the parity error handling is disabled. 14 sse signaled system error : this bit must be set whenever the device asserts serr#. devices that never assert serr# do not need to implement this bit. 13 rma received master abort : this bit must be set by a master device whenever its transaction, except for special cycle, is terminated with master abort. all master devices must implement this bit. 12 rta received target abort : this bit must be set by a master device whenever its transaction is terminated with target abort. all master devices must implement this bit. 11 sta signaled target abort : this bit must be set by a target device whenever it terminates a transaction with target abort. devices that never signal target abort do not need to implement this bit. 10 to 9 devselt [1:0] devsel timing : these bits encode the timing of devsel#. there are three allowable timing to assert devsel#: 00b fast 01b medium 10b slow 11b reserved these bits are read-only and must indicate the slowest time that a device asserts devsel# for any bus command, except con?guration read and con?guration write. 8 mdpe master data parity error : this bit is implemented by bus masters. it is set when the following three conditions are met: ? the bus agent asserted perr# itself, on a read; or observed perr# asserted, on a write. ? the agent setting the bit acted as the bus master for the operation in which error occurred. ? per (bit 6 in the command register) is set. 7 fbbc fast back-to-back capable : this read-only bit indicates whether the target is capable of accepting fast back-to-back transactions when the transactions are not to the same agent. this bit can be set to logic 1, if the device can accept these transactions; and must be set to logic 0 otherwise. 6 reserved -
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 18 of 98 nxp semiconductors isp1564 hs usb pci host controller 8.2.1.5 revision id register this 1-byte read-only register indicates a device-speci?c revision identi?er. the value is chosen by the vendor. this ?eld is a vendor-de?ned extension of the device id. the revision id register bit description is given in t ab le 10 . 8.2.1.6 class code register class code is a 24-bit read-only register used to identify the generic function of the device, and in some cases, a speci?c register-level programming interface. t ab le 11 shows the bit allocation of the register. the class code register is divided into three byte-size ?elds. the upper byte is a base class code that broadly classi?es the type of function the device performs. the middle byte is a sub-class code that identi?es more speci?cally the function of the device. the lower byte identi?es a speci?c register-level programming interface, if any, so that device-independent software can interact with the device. [1] x is 1h for ohci; x is 2h for ehci. 5 66mc 66 mhz capable : this read-only bit indicates whether this device is capable of running at 66 mhz. 0 33 mhz 1 66 mhz 4cl capabilities list : this read-only bit indicates whether this device implements the pointer for a new capabilities linked list at offset 34h. 0 no new capabilities linked list is available. 1 the value read at offset 34h is a pointer in con?guration space to a linked list of new capabilities. 3 to 0 reserved - table 9. status register (address 06h) bit description continued bit symbol description table 10. revid - revision id register (address 08h) bit description legend: * reset value bit symbol access value description 7 to 0 revid[7:0] r 11h* revision id : this byte speci?es the design revision number of functions. table 11. class code register (address 09h) bit allocation bit 23 22 21 20 19 18 17 16 symbol bcc[7:0] reset 0ch access rrrrrrrr bit 15 14 13 12 11 10 9 8 symbol scc[7:0] reset 03h access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol rlpi[7:0] reset x0h [1] access rrrrrrrr
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 19 of 98 nxp semiconductors isp1564 hs usb pci host controller 8.2.1.7 cacheline size register the cacheline size register is a read and write single-byte register that speci?es the system cacheline size in units of dwords. this register must be implemented by master devices that can generate the memory write and invalidate command. the value in this register is also used by master devices to determine whether to use the read, read line or read multiple command to access the memory. slave devices that want to allow memory bursting using cacheline-wrap addressing mode must implement this register to know when a burst sequence wraps to the beginning of the cacheline. this ?eld must be initialized to logic 0 on activation of rst#. t ab le 13 shows the bit description of the cacheline size register. 8.2.1.8 latency timer register this register speci?es, in units of pci bus clocks, the value of the latency timer for the pci bus master. t ab le 14 shows the bit description of the latency timer register. remark: it is recommended that you set the value of the latency timer register to 20h. 8.2.1.9 header type register the header type register identi?es the layout of the second part of the prede?ned header, beginning at byte 10h in con?guration space. it also identi?es whether the device contains multiple functions. for bit allocation, see t ab le 15 . table 12. class code register (address 09h) bit description bit symbol description 23 to 16 bcc[7:0] base class code : 0ch is the base class code assigned to this byte. it implies a serial bus controller. 15 to 8 scc[7:0] sub-class code : 03h is the sub-class code assigned to this byte. it implies the usb host controller. 7 to 0 rlpi[7:0] register-level programming interface : 10h is the programming interface code assigned to ohci, which is usb 1.1 speci?cation compliant. 20h is the programming interface code assigned to ehci, which is usb 2.0 speci?cation compliant. table 13. cls - cacheline size register (address 0ch) bit description legend: * reset value bit symbol access value description 7 to 0 cls[7:0] r/w 00h* cacheline size : this byte identi?es the system cacheline size. table 14. lt - latency timer register (address 0dh) bit description legend: * reset value bit symbol access value description 7 to 0 lt[7:0] r/w 00h* latency timer : this byte identi?es the latency timer. table 15. header type register (address 0eh) bit allocation bit 7 6 5 4 3 2 1 0 symbol mfd ht[6:0] reset 10000000 access rrrrrrrr
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 20 of 98 nxp semiconductors isp1564 hs usb pci host controller 8.2.1.10 base address register 0 power-up software must build a consistent address map before booting the machine to an operating system. this means it must determine how much memory is in the system, and how much address space the i/o controllers in the system require. after determining this information, power-up software can map the i/o controllers into reasonable locations and proceed with system boot. to do this mapping in a device-independent manner, base registers for this mapping are placed in the prede?ned header portion of con?guration space. bit 0 in all base address registers is read-only and used to determine whether the register maps into memory or i/o space. base address registers that map to memory space must return logic 0 in bit 0. base address registers that map to i/o space must return logic 1 in bit 0. the bit description of the bar0 register is given in t ab le 17 . 8.2.1.11 subsystem vendor id register the subsystem vendor id register is used to uniquely identify the expansion board or subsystem where the pci device resides. this register allows expansion board vendors to distinguish their boards, even though the boards may have the same vendor id and device id. subsystem vendor ids are assigned by pci-sig to maintain uniqueness. the bit description of the subsystem vendor id register is given in t ab le 18 . 8.2.1.12 subsystem id register subsystem id values are vendor speci?c. the bit description of the subsystem id register is given in t ab le 19 . table 16. header type register (address 0eh) bit description bit symbol description 7 mfd multi-function device : this bit identi?es a multifunction device. 0 the device has a single function. 1 the device has multiple functions. 6 to 0 ht[6:0] header type : these bits identify the layout of the part of the prede?ned header, beginning at byte 10h in con?guration space. table 17. bar0 - base address register 0 (address 10h) bit description legend: * reset value bit symbol access value description 31 to 0 bar0[31:0] r/w 0000 0000h* base address to memory-mapped host controller register space : the memory size required by ohci and ehci are 4 kb and 256 bytes, respectively. therefore, bar0[31:12] is assigned to the ohci port, and bar0[31:8] is assigned to the ehci port. table 18. svid - subsystem vendor id register (address 2ch) bit description legend: * reset value bit symbol access value description 15 to 0 svid[15:0] r 1131h* subsystem vendor id : 1131h is the subsystem vendor id assigned to nxp semiconductors.
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 21 of 98 nxp semiconductors isp1564 hs usb pci host controller [1] x is 1h for ohci; x is 2h for ehci. 8.2.1.13 capabilities pointer register this register is used to point to a linked list of new capabilities implemented by the device. this register is only valid if cl (bit 4 in the status register) is set. if implemented, bit 1 and bit 0 are reserved and must be set to 00b. software must mask these bits off before using this register as a pointer in con?guration space to the ?rst entry of a linked list of new capabilities. the bit description of the register is given in t ab le 20 . 8.2.1.14 interrupt line register this is a 1-byte register used to communicate interrupt line routing information. this register must be implemented by any device or device function that uses an interrupt pin. the interrupt allocation is done by the bios. the post software needs to write the routing information to this register because it initializes and con?gures the system. the value in this register speci?es which input of the system interrupt controller(s) the interrupt pin of the device is connected. this value is used by device drivers and operating systems to determine priority and vector information. values in this register are system architecture speci?c. the bit description of the register is given in t ab le 21 . 8.2.1.15 interrupt pin register this 1-byte register is use to specify which interrupt pin the device or device function uses. a value of 1h corresponds to inta#, 2h corresponds to intb#, 3h corresponds to intc#, and 4h corresponds to intd#. devices or functions that do not use the interrupt pin must set this register to logic 0. the bit description is given in t ab le 22 . table 19. sid - subsystem id register (address 2eh) bit description legend: * reset value bit symbol access value description 15 to 0 sid[15:0] r 156xh* [1] subsystem id : for the isp1564, nxp semiconductors has de?ned ohci functions as 1561h, and the ehci function as 1562h. table 20. cp - capabilities pointer register (address 34h) bit description legend: * reset value bit symbol access value description 7 to 0 cp[7:0] r dch* capabilities pointer : ehci ef?ciently manages power using this register. this power management register is allocated at offset dch. only one host controller is needed to manage power in the isp1564. table 21. il - interrupt line register (address 3ch) bit description legend: * reset value bit symbol access value description 7 to 0 il[7:0] r/w 00h* interrupt line : indicates which irq is used to report interrupt from the isp1564. table 22. ip - interrupt pin register (address 3dh) bit description legend: * reset value bit symbol access value description 7 to 0 ip[7:0] r 01h* interrupt pin : inta# is the default interrupt pin used by the isp1564.
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 22 of 98 nxp semiconductors isp1564 hs usb pci host controller 8.2.1.16 min_gnt and max_lat registers the minimum grant (min_gnt) and maximum latency (max_lat) registers are used to specify the desired settings of the device for latency timer values. for both registers, the value speci?es a period of time in units of 250 ns. logic 0 indicates that the device has no major requirements for setting latency timers. the min_gnt register bit description is given in t ab le 23 . [1] x is 1h for ohci; x is 2h for ehci. the max_lat register bit description is given in t ab le 24 . [1] xx is 2ah for ohci; xx is 10h for ehci. 8.2.1.17 trdy timeout register this is a read and write register at address 40h. the default and recommended value is 00h, trdy time-out disabled. this value can, however, be modi?ed. it is an implementation-speci?c register, and not a standard pci con?guration register. the trdy timer is 13 bits: the lower 5 bits are ?xed as logic 0, and the upper 8 bits are determined by the trdy timeout register value. the time-out is calculated by multiplying the 13-bit timer with the pci clk cycle time. this register determines the maximum trdy delay, without asserting the ue (unrecoverable error) bit. if trdy is longer than the delay determined by this register value, then the ue bit will be set. 8.2.1.18 retry timeout register the default value of this read and write register is 00h, and is located at address 41h. this value can, however, be modi?ed. programming this register as 00h means that retry time-out is disabled. this is an implementation-speci?c register, and not a standard pci con?guration register. the time-out is determined by multiplying the register value with the pci clk cycle time. this register determines the maximum number of pci retires before the ue bit is set. if the number of retries is longer than the delay determined by this register value, then the ue bit will be set. table 23. min_gnt - minimum grant register (address 3eh) bit description legend: * reset value bit symbol access value description 7 to 0 min_gnt[7:0] r 0xh* [1] min_gnt : it is used to specify how long a burst period the device needs, assuming a clock rate of 33 mhz. table 24. max_lat - maximum latency register (address 3fh) bit description legend: * reset value bit symbol access value description 7 to 0 max_lat[7:0] r xxh* [1] max_lat : it is used to specify how often the device needs to gain access to the pci bus.
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 23 of 98 nxp semiconductors isp1564 hs usb pci host controller 8.2.2 enhanced host controller-speci?c pci registers in addition to pci con?guration header registers, ehci needs some additional pci con?guration space registers to indicate the serial bus release number, downstream port wake-up event capability, and adjust the usb bus frame length for start-of-frame (sof). the ehci-speci?c pci registers are given in t ab le 25 . 8.2.2.1 sbrn register the serial bus release number (sbrn) register is a 1-byte register, and the bit description is given in t ab le 26 . this register contains the release number of the usb speci?cation with which this usb host controller module is compliant. 8.2.2.2 fladj register this feature is used to adjust any offset from the clock source that generates the clock that drives the sof counter. when a new value is written to these six bits, the length of the frame is adjusted. the bit allocation of the frame length adjustment (fladj) register is given in t ab le 27 . [1] the reserved bits must always be written with the reset value. table 25. ehci-speci?c pci registers offset register 60h serial bus release number (sbrn) 61h frame length adjustment (fladj) 62h to 63h port wake capability (portwakecap) table 26. sbrn - serial bus release number register (address 60h) bit description legend: * reset value bit symbol access value description 7 to 0 sbrn[7:0] r 20h* serial bus speci?cation release number : this register value is to identify universal serial bus speci?cation rev. 2.0 . all other combinations are reserved. table 27. fladj - frame length adjustment register (address 61h) bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved [1] fladj[5:0] reset 00100000 access r/w r/w r/w r/w r/w r/w r/w r/w table 28. fladj - frame length adjustment register (address 61h) bit description bit symbol description 7 to 6 reserved - 5 to 0 fladj[5:0] frame length timing value : each decimal value change to this register corresponds to 16 high-speed bit times. the sof cycle time, number of sof counter clock periods to generate a sof microframe length, is equal to 59488 + value in this ?eld. the default value is decimal 32 (20h), which gives an sof cycle time of 60000. see t ab le 29 .
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 24 of 98 nxp semiconductors isp1564 hs usb pci host controller 8.2.2.3 portwakecap register port wake capability (portwakecap) is a 2-byte register used to establish a policy about which ports are for wake events; see t ab le 30 . bit positions 15 to 1 in the mask correspond to a physical port implemented on the current ehci controller. logic 1 in a bit position indicates that a device connected below the port can be enabled as a wake-up device and the port may be enabled for disconnect or connect, or overcurrent events as wake-up events. this is an information only mask register. the bits in this register do not affect the actual operation of the ehci host controller. the system-speci?c policy can be established by bios initializing this register to a system-speci?c value. the system software uses the information in this register when enabling devices and ports for remote wake-up. 8.2.3 power management registers 8.2.3.1 cap_id register the capability identi?er (cap_id) register when read by the system software as 01h indicates that the data structure currently being pointed to is the pci power management data structure. each function of a pci device may have only one item in its capability list with cap_id set to 01h. the bit description of the register is given in t ab le 32 . table 29. fladj value vs. sof cycle time fladj value sof cycle time (480 mhz) 0 (00h) 59488 1 (01h) 59504 2 (02h) 59520 :: 31 (1fh) 59984 32 (20h) 60000 :: 62 (3eh) 60480 63 (3fh) 60496 table 30. portwakecap - port wake capability register (address 62h) bit description legend: * reset value bit symbol access value description 15 to 0 portwakecap[15:0] r/w 0007h* port wake-up capability mask : ehci does not implement this feature. table 31. power management registers offset register value read from address 34h + 0h capability identi?er (cap_id) value read from address 34h + 1h next item pointer (next_item_ptr) value read from address 34h + 2h power management capabilities (pmc) value read from address 34h + 4h power management control/status (pmcsr) value read from address 34h + 6h power management control/status pci-to-pci bridge support extensions (pmcsr_bse) value read from address 34h + 7h data
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 25 of 98 nxp semiconductors isp1564 hs usb pci host controller 8.2.3.2 next_item_ptr register the next item pointer (next_item_ptr) register describes the location of the next item in the functions capability list. the value given is an offset into the functions pci con?guration space. if the function does not implement any other capabilities de?ned by the pci-sig for inclusion in the capabilities list, or if power management is the last item in the list, then this register must be set to 00h. see t ab le 33 . [1] reset value for ohci is 00h and for ehci is e4h. 8.2.3.3 pmc register the power management capabilities (pmc) register is a 2-byte register, and the bit allocation is given in t ab le 34 . this register provides information on the capabilities of the function related to power management. [1] x is 0 for ohci; x is 1 for ehci. table 32. cap_id - capability identi?er register bit description address: value read from address 34h + 0h legend: * reset value bit symbol access value description 7 to 0 cap_id[7:0] r 01h* id : this ?eld when 01h identi?es the linked list item as being pci power management registers. table 33. next_item_ptr - next item pointer register bit description address: value read from address 34h + 1h legend: * reset value bit symbol access value description 7 to 0 next_item_ ptr[7:0] r- [1] * next item pointer : this ?eld provides an offset into the functions pci con?guration space, pointing to the location of the next item in the functions capability list. table 34. pmc - power management capabilities register bit allocation address: value read from address 34h + 2h bit 15 14 13 12 11 10 9 8 symbol pme_s[4:0] d2_s d1_s aux_c reset 11x [1] 1x [1] x [1] 10 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol aux_c[1:0] dsi reserved pmi ver[2:0] reset 10000010 access rrrrrrrr
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 26 of 98 nxp semiconductors isp1564 hs usb pci host controller table 35. pmc - power management capabilities register bit description address: value read from address 34h + 2h bit symbol description 15 to 11 pme_s [4:0] pme support : these bits indicate the power states in which the function may assert pme#. logic 0 for any bit indicates that the function is not capable of asserting the pme# signal while in that power state. pme_s[0] pme# can be asserted from d0 pme_s[1] pme# can be asserted from d1 pme_s[2] pme# can be asserted from d2 pme_s[3] pme# can be asserted from d3 hot pme_s[4] pme# can be asserted from d3 cold 10 d2_s d2 support : if this bit is logic 1, this function supports the d2 power management state. functions that do not support d2 must always return logic 0 for this bit. 9 d1_s d1 support : if this bit is logic 1, this function supports the d1 power management state. functions that do not support d1 must always return logic 0 for this bit. 8 to 6 aux_c [2:0] auxiliary current : this three-bit ?eld reports the v aux(3v3) auxiliary current requirements for the pci function. if the data register is implemented by this function: ? a read from this ?eld needs to return a value of 000b. ? the data register takes precedence over this ?eld for v aux(3v3) current requirement reporting. if the pme# generation from d3 cold is not supported by the function (pmc[15] = 0), this ?eld must return a value of 000b when read. for functions that support pme# from d3 cold and do not implement the data register, bit assignments corresponding to the maximum current required for v aux(3v3) are: 111b 375 ma 110b 320 ma 101b 270 ma 100b 220 ma 011b 160 ma 010b 100 ma 001b 55 ma 000b 0 (self powered) 5 dsi device speci?c initialization : this bit indicates whether special initialization of this function is required, beyond the standard pci con?guration header, before the generic class device driver can use it. this bit is not used by some operating systems. for example, microsoft windows and windows nt do not use this bit to determine whether to use d3. instead, it is determined using the capabilities of the driver. logic 1 indicates that the function requires a device-speci?c initialization sequence, following transition to d0 un-initialized state. 4 reserved - 3 pmi pme clock : 0 indicates that no pci clock is required for the function to generate pme#. 1 indicates that the function relies on the presence of the pci clock for the pme# operation. functions that do not support the pme# generation in any state must return logic 0 for this ?eld. 2 to 0 ver[2:0] version : a value of 010b indicates that this function complies with pci bus power management interface speci?cation rev. 1.1 .
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 27 of 98 nxp semiconductors isp1564 hs usb pci host controller 8.2.3.4 pmcsr register the power management control/status (pmcsr) register is a 2-byte register used to manage the power management state of the pci function, as well as to allow and monitor power management events (pmes). the bit allocation of the register is given in t ab le 36 . [1] sticky bit, if the function supports pme# from d3 cold , then x is indeterminate at the time of initial operating system boot; x is 0 if the function does not support pme# from d3 cold . [2] the reserved bits must always be written with the reset value. table 36. pmcsr - power management control/status register bit allocation address: value read from address 34h + 4h bit 15 14 13 12 11 10 9 8 symbol pmes ds[1:0] d_s[3:0] pmee reset x [1] 000000x [1] access r/w r r r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved [2] ps[1:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 37. pmcsr - power management control/status register bit description address: value read from address 34h + 4h bit symbol description 15 pmes pme status : this bit is set when the function normally asserts the pme# signal independent of the state of the pmee bit. writing logic 1 to this bit clears it and causes the function to stop asserting pme#, if enabled. writing logic 0 has no effect. this bit defaults to logic 0, if the function does not support the pme# generation from d3 cold . if the function supports the pme# generation from d3 cold , then this bit is sticky and must be explicitly cleared by the operating system each time the operating system is initially loaded. 14 to 13 ds[1:0] data scale : this two-bit read-only ?eld indicates the scaling factor when interpreting the value of the data register. the value and meaning of this ?eld vary, depending on which data value is selected by the d_s ?eld. this ?eld is a required component of the data register (offset 7) and must be implemented, if the data register is implemented. if the data register is not implemented, this ?eld must return 00b when pmcsr is read. 12 to 9 d_s [3:0] data select : this four-bit ?eld selects the data that is reported through the data register and the d_s ?eld. this ?eld is a required component of the data register (offset 7) and must be implemented, if the data register is implemented. if the data register is not implemented, this ?eld must return 00b when pmcsr is read.
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 28 of 98 nxp semiconductors isp1564 hs usb pci host controller 8.2.3.5 pmcsr_bse register the pmcsr pci-to-pci bridge support extensions (pmcsr_bse) register supports pci bridge-speci?c functionality and is required for all pci-to-pci bridges. the bit allocation of this register is given in t ab le 38 . 8 pmee pme enabled : logic 1 allows the function to assert pme#. when it is logic 0, pme# assertion is disabled. this bit defaults to logic 0, if the function does not support the pme# generation from d3 cold . if the function supports pme# from d3 cold , then this bit is sticky and must explicitly be cleared by the operating system each time the operating system is initially loaded. 7 to 2 reserved - 1 to 0 ps[1:0] power state : this two-bit ?eld is used to determine the current power state of the ehci function and to set the function into a new power state. the de?nition of the ?eld values is given as: 00b d0 01b d1 10b d2 11b d3 hot if the software attempts to write an unsupported, optional state to this ?eld, the write operation must complete normally on the bus; however, data is discarded and no status change occurs. table 37. pmcsr - power management control/status register bit description continued address: value read from address 34h + 4h bit symbol description table 38. pmcsr_bse - pmcsr pci-to-pci bridge support extensions register bit allocation address: value read from address 34h + 6h bit 7 6 5 4 3 2 1 0 symbol bpcc_en b2_b3# reserved reset 00000000 access rrrrrrrr table 39. pmcsr_bse - pmcsr pci-to-pci bridge support extensions register bit description address: value read from address 34h + 6h bit symbol description 7 bpcc_en bus power or clock control enable : 1 indicates that the bus power or clock control mechanism as de?ned in t ab le 40 is enabled. 0 indicates that the bus power or control policies as de?ned in t ab le 40 are disabled. when the bus power or clock control mechanism is disabled, the bridges pmcsr power state (ps) ?eld cannot be used by the system software to control the power or clock of the bridges secondary bus. 6 b2_b3# b2 or b3 support for d3 hot : the state of this bit determines the action that is to occur as a direct result of programming the function to d3 hot . 1 indicates that when the bridge function is programmed to d3 hot , its secondary buss pci clock will be stopped (b2). 0 indicates that when the bridge function is programmed to d3 hot , its secondary bus will have its power removed (b3). this bit is only meaningful if bit 7 (bpcc_en) is logic 1. 5 to 0 reserved -
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 29 of 98 nxp semiconductors isp1564 hs usb pci host controller 8.2.3.6 data register the data register is an optional, 1-byte register that provides a mechanism for the function to report state dependent operating data, such as power consumed or heat dissipated. t ab le 41 shows the bit description of the register. 8.2.4 vpd register 8.2.4.1 vpd_cap_id register the capability identi?er (cap_id) register when read by the system software as 03h indicates that the data structure currently being pointed to is the vpd_data structure. the bit description of the register is given in t ab le 43 . 8.2.4.2 vpd_next_item_ptr register the next item pointer (next_item_ptr) register describes the location of the next item in the functions capability list. the value given is an offset into the functions pci con?guration space. if the function does not implement any other capabilities de?ned by the pci-sig for inclusion in the capabilities list, or if the power management is the last item in the list, then this register must be set to 00h. see t ab le 44 . table 40. pci bus power and clock control originating devices bridge pm state secondary bus pm state resultant actions by bridge (either direct or indirect) d0 b0 none d1 b1 none d2 b2 clock stopped on secondary bus d3 hot b2, b3 clock stopped and pci v cc removed from secondary bus (b3 only); for de?nition of b2_b3#, see t ab le 39 d3 cold b3 none table 41. data register bit description address: value read from address 34h + 7h legend: * reset value bit symbol access value description 7 to 0 data[7:0] r 00h* data : this register is used to report the state dependent data requested by the d_s ?eld of the pmcsr register. the value of this register is scaled by the value reported by the ds ?eld of the pmcsr register. table 42. vpd speci?c registers offset register value read from address 34h + 8h vital product data capability identi?er (vpd_cap_id) value read from address 34h + 9h vital product data next item pointer (vpd_next_item_ptr) value read from address 34h + ah vital product data address (vpd_addr) value read from address 34h + ch vital product data data (vpd_data) table 43. vpd_cap_id - vital product data capability identi?er register bit description address: value read from address 34h + 8h legend: * reset value bit symbol access value description 7 to 0 vpd_cap_id[7:0] r 03h* vpd capability id : capability structure id; for details, refer to appendix i of pci local bus speci?cation rev. 2.2
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 30 of 98 nxp semiconductors isp1564 hs usb pci host controller 8.2.4.3 vpd_addr register the dword-aligned byte address of the vpd to be accessed. this is a r/w register, and the initial value at power-up is indeterminate. the bit description of the register is given in t ab le 45 . [1] for details on these bits, refer to appendix i, pci local bus speci?cation rev. 2.2 . 8.2.4.4 vpd_data register vpd data can be read or written through this register. the bit description of the register is given in t ab le 47 . table 44. vpd_next_item_ptr - vital product data next item pointer register bit description address: value read from address 34h + 9h legend: * reset value bit symbol access value description 7 to 0 vpd_next_item _ptr[7:0] r 00h* vpd next item pointer : pointer to the next capability structure, or 00h if this is the last structure in the capability list; for details, refer to appendix i of pci local bus speci?cation rev. 2.2 table 45. vpd_addr - vital product data address register bit allocation address: value read from address 34h + 9ah bit 7 6 5 4 3 2 1 0 symbol f vpd_addr[6:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 46. vpd_addr - vital product data address register bit description address: value read from address 34h + 9h bit symbol description [1] 7f flag : a ?ag used to indicate when the transfer of data between the vpd data register and the storage component is completed. 6 to 0 vpd_addr[6:0] vpd address : dword-aligned byte address of the vpd to be accessed. table 47. vpd_data - vital product data data bit description address: value read from address 34h + ch legend: * reset value bit symbol access value description 31 to 0 vpd_data[7:0] r/w 00h* vpd data : vpd data can be read through this register; for details, refer to appendix i of pci local bus speci?cation rev. 2.2
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 31 of 98 nxp semiconductors isp1564 hs usb pci host controller 9. i 2 c-bus interface a simple i 2 c-bus interface is provided in the isp1564 to read customized vendor id, product id and some other con?guration bits from an external eeprom. the i 2 c-bus interface is for bidirectional communication between ics using two serial bus wires: sda (data) and scl (clock). both lines are driven by open-drain circuits and must be connected to the positive supply voltage through pull-up resistors when in use; otherwise, they must be connected to ground. 9.1 protocol the i 2 c-bus protocol de?nes the following conditions: ? bus free : both sda and scl are high ? start : a high-to-low transition on sda, while scl is high ? stop : a low-to-high transition on sda, while scl is high ? data valid : after a start condition, data on sda is stable during the high period of scl; data on sda may only change while scl is low each device on the i 2 c-bus has a unique slave address, which the master uses to select a device for access. the master starts a data transfer using a start condition and ends it by generating a stop condition. transfers can only be initiated when the bus is free. the receiver must acknowledge each byte by using a low level on sda during the ninth clock pulse on scl. for detailed information, refer to the i 2 c-bus speci?cation version 2.1 . 9.2 hardware connections the isp1564 can be connected to an external eeprom through the i 2 c-bus interface. the hardware connections are shown in figure 6 . fig 6. eeprom connection diagram 004aaa793 sda scl a1 a2 a0 sda scl v aux(3v3) r p r p v aux(3v3) isp1564 usb host 24c01 eeprom or equivalent i 2 c-bus
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 32 of 98 nxp semiconductors isp1564 hs usb pci host controller the slave address that the isp1564 uses to access the eeprom is 101 0000b. page mode addressing is not supported. therefore, pins a0, a1 and a2 of the eeprom must be connected to ground (logic 0). 9.3 information loading from eeprom figure 7 shows the content of the eeprom memory. if the eeprom is not present, the default values of device id, vendor id, subsystem vid and subsystem did assigned to nxp semiconductors by pci-sig will be loaded. for default values, see t ab le 3 . 9.4 eeprom programming to simplify the manufacturing of products based on the isp1564, which requires changing of subsystem did and vid, information can be written in-circuit to the eeprom through the pci bus. reading and writing of the eeprom is achieved by the mechanism described in appendix i of pci local bus speci?cation rev. 2.2 . remark: the vpd data structure described in appendix i of pci local bus speci?cation rev. 2.2 is not adopted and only the read write mechanism is adopted in the isp1564. 10. power management 10.1 pci bus power states the pci bus can be characterized by one of the four power management states: b0, b1, b2 and b3. b0 state (pci clock = 33 mhz, pci bus power = on) this corresponds to the bus being fully operational. l = low; h = high. fig 7. information loading from eeprom 004aaa930 subsystem vendor id (l) 0 1 3 4 6 5 2 subsystem vendor id (h) subsystem device id (l) - ohci subsystem device id (h) - ohci subsystem device id (l) - ehci subsystem device id (h) - ehci reserved - ffh signature 15h - loads subsystem vendor id, device id 1ah - loads default values defined by nxp semiconductors 7 address
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 33 of 98 nxp semiconductors isp1564 hs usb pci host controller b1 state (pci clock = intermittent clock operation mode, pci bus power = on) when a pci bus is in b1, pci v cc is still applied to all devices on the bus. no bus transactions, however, are allowed to take place on the bus. the b1 state indicates a perpetual idle state on the pci bus. b2 state (pci clock = stop, pci bus power = on) pci v cc is still applied on the bus, but the clock is stopped and held in the low state. b3 state (pci clock = stop, pci bus power = off) pci v cc is removed from all devices on the pci bus segment. 10.2 usb bus states reset state when the usb bus is in the reset state, the usb system is stopped. operational state when the usb bus is in the active state, the usb system is operating normally. suspend state when the usb bus is in the suspend state, the usb system is stopped. resume state when the usb bus is in the resume state, the usb system is operating normally.
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 34 of 98 nxp semiconductors isp1564 hs usb pci host controller 11. usb host controller registers each host controller contains a set of on-chip operational registers that are mapped to un-cached memory of the system addressable space. this memory space must begin on a dword (32-bit) boundary. the size of the allocated space is de?ned by the initial value in the base address register 0. hcds must interact with these registers to implement usb functionality. after the pci enumeration driver ?nishes the pci device con?guration, the new base address of these memory-mapped operational registers is de?ned in bar0. the hcd can access these registers by using the address of base address value + offset. t ab le 48 contains a list of host controller registers. for the ohci host controller, there are only operational registers for the usb operation. for the enhanced host controller, there are two types of registers: one set of read-only capability registers, and one set of read and write operational registers. table 48. usb host controller registers address ohci register reset value func0 ohci [1] ehci register reset value func2 ehci [1] 00h hcrevision 0000 0 010 h caplength/hciversion [2] 0100 0020 h 04h hccontrol 0000 0000h hcsparams 0000 1292 h 08h hccommandstatus 0000 0000h hccparams 0000 0012 h 0ch hcinterruptstatus 0000 0000h hcsp-portroute1[31:0] 0000 1010 h 10h hcinterruptenable 0000 0000h hcsp-portroute2[59:32] 0000 0000 h 14h hcinterruptdisable 0000 0000h reserved - 18h hchcca 0000 0000h reserved - 1ch hcperiodcurrented 0000 0000h reserved - 20h hccontrolheaded 0000 0000h usbcmd 0008 0000h 24h hccontrolcurrented 0000 0000h usbsts 0000 1000h 28h hcbulkheaded 0000 0000h usbintr 0000 0000h 2ch hcbulkcurrented 0000 0000h frindex 0000 0000h 30h hcdonehead 0000 0000h reserved - 34h hcfminterval 0000 2edfh periodiclistbase 0000 0000h 38h hcfmremaining 0000 0000h asynclistaddr 0000 0000h 3ch hcfmnumber 0000 0000h reserved - 40h hcperiodicstart 0000 0000h reserved - 44h hclsthreshold 0000 0628h reserved - 48h hcrhdescriptora ff00 0902 h reserved - 4ch hcrhdescriptorb 0006 0000h reserved - 50h hcrhstatus 0000 0000h reserved - 54h hcrhportstatus[1] 0000 0000h reserved - 58h hcrhportstatus[2] 0000 0000h reserved - 5ch reserved - reserved - 60h reserved - configflag 0000 0000h
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 35 of 98 nxp semiconductors isp1564 hs usb pci host controller [1] reset values that are highlighted, for example, 0 , are the isp1564 implementation-speci?c reset values; and reset values that are not highlighted, for example, 0, are compliant with the ohci and ehci speci?cations. [2] hciversion is 0100h when subsystem id and subsystem vendor id are con?gured through the external eeprom, or when scl is pulled down. otherwise, it is 0095h. 11.1 ohci usb host controller operational registers ohci hcds must communicate with these registers to implement usb data transfers. based on their functions, these registers are classi?ed into four partitions: ? control and status ? memory pointer ? frame counter ? root hub 11.1.1 hcrevision register 64h reserved - portsc1 0000 0000h 68h reserved - portsc2 0000 0000h 6ch reserved - system tuning 0000 0000h 70h reserved - reserved - table 48. usb host controller registers continued address ohci register reset value func0 ohci [1] ehci register reset value func2 ehci [1] table 49. hcrevision - host controller revision register bit allocation address: content of the base address register + 00h bit 31 30 29 28 27 26 25 24 symbol reserved reset 00000000 access rrrrrrrr bit 23 22 21 20 19 18 17 16 symbol reserved reset 00000000 access rrrrrrrr bit 15 14 13 12 11 10 9 8 symbol reserved reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol rev[7:0] reset 00010000 access rrrrrrrr
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 36 of 98 nxp semiconductors isp1564 hs usb pci host controller 11.1.2 hccontrol register this register de?nes the operating modes for the host controller. all the ?elds in this register, except hcfs and rwc, are modi?ed only by the hcd. the bit allocation is given in t ab le 51 . [1] the reserved bits must always be written with the reset value. table 50. hcrevision - host controller revision register bit description address: content of the base address register + 00h bit symbol description 31 to 8 reserved - 7 to 0 rev[7:0] revision : this read-only ?eld contains the bcd representation of the version of the hci speci?cation that is implemented by this host controller. for example, a value of 11h corresponds to version 1.1. all of the host controller implementations that are compliant with this speci?cation must have a value of 10h. table 51. hccontrol - host controller control register bit allocation address: content of the base address register + 04h bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] rwe rwc ir reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol hcfs[1:0] ble cle ie ple cbsr[1:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 37 of 98 nxp semiconductors isp1564 hs usb pci host controller table 52. hccontrol - host controller control register bit description address: content of the base address register + 04h bit symbol description 31 to 11 reserved - 10 rwe remote wake-up enable : this bit is used by the hcd to enable or disable the remote wake-up feature on detecting upstream resume signaling. when this bit and rd (bit 3) in the hcinterruptstatus register are set, a remote wake-up is signaled to the host system. setting this bit has no impact on the generation of hardware interrupt. 9rwc remote wake-up connected : this bit indicates whether the host controller supports remote wake-up signaling. if remote wake-up is supported and used by the system, it is the responsibility of the system ?rmware to set this bit during post. the host controller clears the bit on a hardware reset but does not alter it on a software reset. remote wake-up signaling of the host system is host-bus-speci?c and is not described in this speci?cation. 8ir interrupt routing : this bit determines the routing of interrupts generated by events registered in hcinterruptstatus. if clear, all interrupts are routed to the normal host bus interrupt mechanism. if set, interrupts are routed to the system management interrupt. the hcd clears this bit on a hardware reset, but it does not alter this bit on a software reset. the hcd uses this bit as a tag to indicate the ownership of the host controller. 7 to 6 hcfs [1:0] host controller functional state for usb: 00b usbreset 01b usbresume 10b usboperational 11b usbsuspend a transition to usboperational from another state causes sof generation to begin 1 ms later. the hcd may determine whether the host controller has begun sending sofs by reading sf (bit 2) in hcinterruptstatus. this ?eld may be changed by the host controller only when in the usbsuspend state. the host controller may move from the usbsuspend state to the usbresume state after detecting the resume signaling from a downstream port. the host controller enters usbsuspend after a software reset; it enters usbreset after a hardware reset. the latter also resets the root hub and asserts subsequent reset signaling to downstream ports. 5 ble bulk list enable : this bit is set to enable the processing of the bulk list in the next frame. if cleared by the hcd, processing of the bulk list does not occur after the next sof. the host controller checks this bit whenever it wants to process the list. when disabled, the hcd may modify the list. if hcbulkcurrented is pointing to an endpoint descriptor (ed) to be removed, the hcd must advance the pointer by updating hcbulkcurrented before re-enabling processing of the list.
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 38 of 98 nxp semiconductors isp1564 hs usb pci host controller 11.1.3 hccommandstatus register the hccommandstatus register is used by the host controller to receive commands issued by the hcd. it also re?ects the current status of the host controller. to the hcd, it appears as a write to set register. the host controller must ensure that bits written as logic 1 become set in the register while bits written as logic 0 remain unchanged in the register. the hcd may issue multiple distinct commands to the host controller without concern for corrupting previously issued commands. the hcd has normal read access to all bits. the soc[1:0] ?eld (bits 17 and 16 in the hccommandstatus register) indicates the number of frames with which the host controller has detected the scheduling overrun error. this occurs when the periodic list does not complete before eof. when a scheduling overrun error is detected, the host controller increments the counter and sets so (bit 0 in the hcinterruptstatus register). t ab le 53 shows the bit allocation of the hccommandstatus register. 4 cle control list enable : this bit is set to enable the processing of the control list in the next frame. if cleared by the hcd, processing of the control list does not occur after the next sof. the host controller must check this bit whenever it wants to process the list. when disabled, the hcd may modify the list. if hccontrolcurrented is pointing to an ed to be removed, the hcd must advance the pointer by updating hccontrolcurrented before re-enabling processing of the list. 3ie isochronous enable : this bit is used by the hcd to enable or disable processing of isochronous eds. while processing the periodic list in a frame, the host controller checks the status of this bit when it ?nds an isochronous ed (f = 1). if set (enabled), the host controller continues processing eds. if cleared (disabled), the host controller halts processing of the periodic list, which now contains only isochronous eds, and begins processing bulk or control lists. setting this bit is guaranteed to take effect in the next frame and not the current frame. 2 ple periodic list enable : this bit is set to enable the processing of the periodic list in the next frame. if cleared by the hcd, processing of the periodic list does not occur after the next sof. the host controller must check this bit before it starts processing the list. 1 to 0 cbsr [1:0] control bulk service ratio : this speci?es the service ratio of control eds over bulk eds. before processing any of the nonperiodic lists, the host controller must compare the ratio speci?ed with its internal count on how many nonempty control eds are processed, in determining whether to continue serving another control ed or switching to bulk eds. the internal count must be retained when crossing the frame boundary. after a reset, the hcd is responsible to restore this value. 00b 1 : 1 01b 2 : 1 10b 3 : 1 11b 4 : 1 table 52. hccontrol - host controller control register bit description continued address: content of the base address register + 04h bit symbol description table 53. hccommandstatus - host controller command status register bit allocation address: content of the base address register + 08h bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 39 of 98 nxp semiconductors isp1564 hs usb pci host controller [1] the reserved bits must always be written with the reset value. bit 23 22 21 20 19 18 17 16 symbol reserved [1] soc[1:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved [1] ocr blf clf hcr reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 54. hccommandstatus - host controller command status register bit description address: content of the base address register + 08h bit symbol description 31 to 18 reserved - 17 to 16 soc[1:0] scheduling overrun count : the bit is incremented on each scheduling overrun error. it is initialized to 00b and wraps around at 11b. it must be incremented when a scheduling overrun is detected, even if so (bit 0 in hcinterruptstatus) is already set. this is used by the hcd to monitor any persistent scheduling problems. 15 to 4 reserved - 3 ocr ownership change request : this bit is set by an os hcd to request a change of control of the host controller. when set, the host controller must set oc (bit 30 in hcinterruptstatus). after the changeover, this bit is cleared and remains so until the next request from the os hcd. 2 blf bulk list filled : this bit is used to indicate whether there are any transfer descriptors (tds) on the bulk list. it is set by the hcd whenever it adds a td to an ed in the bulk list. when the host controller begins to process the head of the bulk list, it checks bulk-filled (bf). if blf is logic 0, the host controller does not need to process the bulk list. if blf is logic 1, the host controller must start processing the bulk list and set bf to logic 0. if the host controller ?nds a td on the list, then the host controller must set blf to logic 1, causing the bulk list processing to continue. if no td is found on the bulk list, and if the hcd does not set blf, then blf is still logic 0 when the host controller completes processing the bulk list and the bulk list processing stops. 1 clf control list filled : this bit is used to indicate whether there are any tds on the control list. it is set by the hcd whenever it adds a td to an ed in the control list. when the host controller begins to process the head of the control list, it checks clf. if clf is logic 0, the host controller does not need to process the control list. if control-filled (cf) is logic 1, the host controller needs to start processing the control list and set clf to logic 0. if the host controller ?nds a td on the list, then the host controller must set clf to logic 1, causing the control list processing to continue. if no td is found on the control list, and if the hcd does not set clf, then clf is still logic 0 when the host controller completes processing the control list and the control list processing stops. 0 hcr host controller reset : this bit is set by the hcd to initiate a software reset of the host controller. regardless of the functional state of the host controller, it moves to the usbsuspend state in which most of the operational registers are reset, except those stated otherwise; for example, ir (bit 8) in the hccontrol register, and no host bus accesses are allowed. this bit is cleared by the host controller on completing the reset operation. the reset operation must be completed within 10 m s. this bit, when set, must not cause a reset to the root hub and no subsequent reset signaling must be asserted to its downstream ports.
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 40 of 98 nxp semiconductors isp1564 hs usb pci host controller 11.1.4 hcinterruptstatus register this is a 4-byte register that provides the status of the events that cause hardware interrupts. the bit allocation of the register is given in t ab le 55 . when an event occurs, the host controller sets the corresponding bit in this register. when a bit becomes set, a hardware interrupt is generated, if the interrupt is enabled in the hcinterruptenable register (see t ab le 57 ) and the mie (master interrupt enable) bit is set. the hcd may clear speci?c bits in this register by writing logic 1 to the bit positions to be cleared. the hcd may not set any of these bits. the host controller does not clear the bit. [1] the reserved bits must always be written with the reset value. table 55. hcinterruptstatus - host controller interrupt status register bit allocation address: content of the base address register + 0ch bit 31 30 29 28 27 26 25 24 symbol reserved [1] oc reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved [1] rhsc fno ue rd sf wdh so reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 56. hcinterruptstatus - host controller interrupt status register bit description address: content of the base address register + 0ch bit symbol description 31 reserved - 30 oc ownership change : this bit is set by the host controller when hcd sets ocr (bit 3) in the hccommandstatus register. this event, when unmasked, will always immediately generate a system management interrupt (smi). this bit is forced to logic 0 when the smi# pin is not implemented. 29 to 7 reserved - 6 rhsc root hub status change : this bit is set when the content of hcrhstatus or the content of any of hcrhportstatus[numberofdownstreamport] has changed.
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 41 of 98 nxp semiconductors isp1564 hs usb pci host controller 11.1.5 hcinterruptenable register each enable bit in the hcinterruptenable register corresponds to an associated interrupt bit in the hcinterruptstatus register. the hcinterruptenable register is used to control which events generate a hardware interrupt. a hardware interrupt is requested on the host bus if the following conditions occur: ? a bit is set in the hcinterruptstatus register. ? the corresponding bit in the hcinterruptenable register is set. ? the mie (master interrupt enable) bit is set. writing logic 1 to a bit in this register sets the corresponding bit, whereas writing logic 0 to a bit in this register leaves the corresponding bit unchanged. on a read, the current value of this register is returned. the bit allocation is given in t ab le 57 . 5 fno frame number over?ow : this bit is set when the most signi?cant bit (msb) of hcfmnumber (bit 15) changes value, or after hccaframenumber is updated. 4ue unrecoverable error : this bit is set when the host controller detects a system error not related to usb. the host controller must not proceed with any processing or signaling before the system error is corrected. the hcd clears this bit after the host controller is reset. 3rd resume detected : this bit is set when the host controller detects that a device on the usb is asserting resume signaling. this bit is set by the transition from no resume signaling to resume signaling. this bit is not set when the hcd sets the usbresume state. 2sf start-of-frame : at the start of each frame, this bit is set by the host controller and an sof token is generated at the same time. 1 wdh write-back done head : this bit is immediately set after the host controller has written hcdonehead to hccadonehead. further, updates of hccadonehead occur only after this bit is cleared. the hcd must only clear this bit after it has saved the content of hccadonehead. 0so scheduling overrun : this bit is set when usb schedules for current frame overruns and after the update of hccaframenumber. a scheduling overrun increments the soc[1:0] ?eld (bits 17 to 16 of hccommandstatus). table 56. hcinterruptstatus - host controller interrupt status register bit description continued address: content of the base address register + 0ch bit symbol description table 57. hcinterruptenable - host controller interrupt enable register bit allocation address: content of the base address register + 10h bit 31 30 29 28 27 26 25 24 symbol mie oc reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 42 of 98 nxp semiconductors isp1564 hs usb pci host controller [1] the reserved bits must always be written with the reset value. 11.1.6 hcinterruptdisable register each disable bit in the hcinterruptdisable register corresponds to an associated interrupt bit in the hcinterruptstatus register. the hcinterruptdisable register is coupled with the hcinterruptenable register. therefore, writing logic 1 to a bit in this register clears the corresponding bit in the hcinterruptenable register, whereas writing logic 0 to a bit in this register leaves the corresponding bit in the hcinterruptenable register unchanged. on a read, the current value of the hcinterruptenable register is returned. bit 7 6 5 4 3 2 1 0 symbol reserved [1] rhsc fno ue rd sf wdh so reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 58. hcinterruptenable - host controller interrupt enable register bit description address: content of the base address register + 10h bit symbol description 31 mie master interrupt enable : 0 ignore 1 enables interrupt generation by events speci?ed in other bits of this register. 30 oc ownership change : 0 ignore 1 enables interrupt generation because of ownership change. 29 to 7 reserved - 6 rhsc root hub status change : 0 ignore 1 enables interrupt generation because of root hub status change. 5 fno frame number over?ow : 0 ignore 1 enables interrupt generation because of frame number over?ow. 4ue unrecoverable error : 0 ignore 1 enables interrupt generation because of unrecoverable error. 3rd resume detect : 0 ignore 1 enables interrupt generation because of resume detect. 2sf start-of-frame : 0 ignore 1 enables interrupt generation because of start-of-frame. 1 wdh hcdonehead write-back : 0 ignore 1 enables interrupt generation because of hcdonehead write-back. 0so scheduling overrun : 0 ignore 1 enables interrupt generation because of scheduling overrun.
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 43 of 98 nxp semiconductors isp1564 hs usb pci host controller the register contains 4 bytes, and the bit allocation is given in t ab le 59 . [1] the reserved bits must always be written with the reset value. table 59. hcinterruptdisable - host controller interrupt disable register bit allocation address: content of the base address register + 14h bit 31 30 29 28 27 26 25 24 symbol mie oc reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved [1] rhsc fno ue rd sf wdh so reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 60. hcinterruptdisable - host controller interrupt disable register bit description address: content of the base address register + 14h bit symbol description 31 mie master interrupt enable : 0 ignore 1 disables interrupt generation because of events speci?ed in other bits of this register. this ?eld is set after a hardware or software reset. interrupts are disabled. 30 oc ownership change : 0 ignore 1 disables interrupt generation because of ownership change. 29 to 7 reserved - 6 rhsc root hub status change : 0 ignore 1 disables interrupt generation because of root hub status change. 5 fno frame number over?ow : 0 ignore 1 disables interrupt generation because of frame number over?ow. 4ue unrecoverable error : 0 ignore 1 disables interrupt generation because of unrecoverable error.
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 44 of 98 nxp semiconductors isp1564 hs usb pci host controller 11.1.7 hchcca register the hchcca register contains the physical address of host controller communication area (hcca). the bit allocation is given in t ab le 61 . the hcd determines alignment restrictions by writing all 1s to hchcca and reading the content of hchcca. the alignment is evaluated by examining the number of zeroes in lower order bits. the minimum alignment is 256 bytes; therefore, bits 0 through 7 will always return logic 0 when read. this area is used to hold control structures and the interrupt table that are accessed by both the host controller and the hcd. [1] the reserved bits must always be written with the reset value. 3rd resume detect : 0 ignore 1 disables interrupt generation because of resume detect. 2sf start-of-frame : 0 ignore 1 disables interrupt generation because of start-of-frame. 1 wdh hcdonehead write-back : 0 ignore 1 disables interrupt generation because of hcdonehead write-back. 0so scheduling overrun : 0 ignore 1 disables interrupt generation because of scheduling overrun. table 60. hcinterruptdisable - host controller interrupt disable register bit description continued address: content of the base address register + 14h bit symbol description table 61. hchcca - host controller communication area register bit allocation address: content of the base address register + 18h bit 31 30 29 28 27 26 25 24 symbol hcca[23:16] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol hcca[15:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol hcca[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 45 of 98 nxp semiconductors isp1564 hs usb pci host controller 11.1.8 hcperiodcurrented register the hcperiodcurrented register contains the physical address of the current isochronous or interrupt ed. t ab le 63 shows the bit allocation of the register. 11.1.9 hccontrolheaded register the hccontrolheaded register contains the physical address of the ?rst ed of the control list. the bit allocation is given in t ab le 65 . table 62. hchcca - host controller communication area register bit description address: content of the base address register + 18h bit symbol description 31 to 8 hcca[23:0] host controller communication area base address : this is the base address of the hcca. 7 to 0 reserved - table 63. hcperiodcurrented - host controller period current endpoint descriptor register bit allocation address: content of the base address register + 1ch bit 31 30 29 28 27 26 25 24 symbol pced[27:20] reset 00000000 access rrrrrrrr bit 23 22 21 20 19 18 17 16 symbol pced[19:12] reset 00000000 access rrrrrrrr bit 15 14 13 12 11 10 9 8 symbol pced[11:4] reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol pced[3:0] reserved reset 00000000 access rrrrrrrr table 64. hcperiodcurrented - host controller period current endpoint descriptor register bit description address: content of the base address register + 1ch bit symbol description 31 to 4 pced[27:0] period current ed : this is used by the host controller to point to the head of one of the periodic lists that must be processed in the current frame. the content of this register is updated by the host controller after a periodic ed is processed. the hcd may read the content in determining which ed is being processed at the time of reading. 3 to 0 reserved -
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 46 of 98 nxp semiconductors isp1564 hs usb pci host controller 11.1.10 hccontrolcurrented register the hccontrolcurrented register contains the physical address of the current ed of the control list. the bit allocation is given in t ab le 67 . table 65. hccontrolheaded - host controller control head endpoint descriptor register bit allocation address: content of the base address register + 20h bit 31 30 29 28 27 26 25 24 symbol ched[27:20] reset 00000000 access rrrrrrrr bit 23 22 21 20 19 18 17 16 symbol ched[19:12] reset 00000000 access rrrrrrrr bit 15 14 13 12 11 10 9 8 symbol ched[11:4] reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol ched[3:0] reserved reset 00000000 access rrrrrrrr table 66. hccontrolheaded - host controller control head endpoint descriptor register bit description address: content of the base address register + 20h bit symbol description 31 to 4 ched[27:0] control head ed : the host controller traverses the control list, starting with the hccontrolheaded pointer. the content is loaded from hcca during the initialization of the host controller. 3 to 0 reserved - table 67. hccontrolcurrented - host controller control current endpoint descriptor register bit allocation address: content of the base address register + 24h bit 31 30 29 28 27 26 25 24 symbol cced[27:20] reset 00000000 access rrrrrrrr bit 23 22 21 20 19 18 17 16 symbol cced[19:12] reset 00000000 access rrrrrrrr bit 15 14 13 12 11 10 9 8 symbol cced[11:4] reset 00000000 access rrrrrrrr
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 47 of 98 nxp semiconductors isp1564 hs usb pci host controller 11.1.11 hcbulkheaded register this register (see t ab le 69 ) contains the physical address of the ?rst ed of the bulk list. [1] the reserved bits must always be written with the reset value. bit 7 6 5 4 3 2 1 0 symbol cced[3:0] reserved reset 00000000 access rrrrrrrr table 68. hccontrolcurrented - host controller control current endpoint descriptor register bit description address: content of the base address register + 24h bit symbol description 31 to 4 cced[27:0] control current ed : this pointer is advanced to the next ed after serving the present. the host controller must continue processing the list from where it left in the last frame. when it reaches the end of the control list, the host controller checks clf (bit 1 of hccommandstatus). if set, it copies the content of hccontrolheaded to hccontrolcurrented and clears the bit. if not set, it does nothing. the hcd is allowed to modify this register only when cle (bit 4 in the hccontrol register) is cleared. when set, the hcd only reads the instantaneous value of this register. initially, this is set to logic 0 to indicate the end of the control list. 3 to 0 reserved - table 69. hcbulkheaded - host controller bulk head endpoint descriptor register bit allocation address: content of the base address register + 28h bit 31 30 29 28 27 26 25 24 symbol bhed[27:20] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol bhed[19:12] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol bhed[11:4] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol bhed[3:0] reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 70. hcbulkheaded - host controller bulk head endpoint descriptor register bit description address: content of the base address register + 28h bit symbol description 31 to 4 bhed[27:0] bulk head ed : the host controller traverses the bulk list starting with the hcbulkheaded pointer. the content is loaded from hcca during the initialization of the host controller. 3 to 0 reserved -
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 48 of 98 nxp semiconductors isp1564 hs usb pci host controller 11.1.12 hcbulkcurrented register this register contains the physical address of the current endpoint of the bulk list. the endpoints are ordered according to their insertion to the list because the bulk list must be served in a round-robin fashion. the bit allocation is given in t ab le 71 . [1] the reserved bits must always be written with the reset value. 11.1.13 hcdonehead register the hcdonehead register contains the physical address of the last completed td that was added to the done queue. in a normal operation, the hcd need not read this register because its content is periodically written to the hcca. t ab le 73 contains the bit allocation of the register. table 71. hcbulkcurrented - host controller bulk current endpoint descriptor register bit allocation address: content of the base address register + 2ch bit 31 30 29 28 27 26 25 24 symbol bced[27:20] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol bced[19:12] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol bced[11:4] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol bced[3:0] reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 72. hcbulkcurrented - host controller bulk current endpoint descriptor register bit description address: content of the base address register + 2ch bit symbol description 31 to 4 bced[27:0] bulk current ed : this is advanced to the next ed after the host controller has served the current ed. the host controller continues processing the list from where it left off in the last frame. when it reaches the end of the bulk list, the host controller checks clf (bit 1 of hccommandstatus). if the clf bit is not set, nothing is done. if the clf bit is set, it copies the content of hcbulkheaded to hcbulkcurrented and clears the clf bit. the hcd can modify this register only when ble (bit 5 in the hccontrol register) is cleared. when hccontrol is set, the hcd reads the instantaneous value of this register. this is initially set to logic 0 to indicate the end of the bulk list. 3 to 0 reserved -
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 49 of 98 nxp semiconductors isp1564 hs usb pci host controller [1] the reserved bits must always be written with the reset value. 11.1.14 hcfminterval register this register contains a 14-bit value that indicates the bit time interval in a frame, that is, between two consecutive sofs, and a 15-bit value indicating the full-speed maximum packet size that the host controller may transmit or receive, without causing a scheduling overrun. the hcd may carry out minor adjustment on fi (frame interval) by writing a new value over the present at each sof. this provides the possibility for the host controller to synchronize with an external clocking resource and to adjust any unknown local clock offset. the bit allocation of the register is given in t ab le 75 . table 73. hcdonehead - host controller done head register bit allocation address: content of the base address register + 30h bit 31 30 29 28 27 26 25 24 symbol dh[27:20] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol dh[19:12] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol dh[11:4] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol dh[3:0] reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 74. hcdonehead - host controller done head register bit description address: content of the base address register + 30h bit symbol description 31 to 4 dh[27:0] done head : when a td is completed, the host controller writes the content of hcdonehead to the nexttd ?eld of the td. the host controller then overwrites the content of hcdonehead with the address of this td. this is set to logic 0 whenever the host controller writes the content of this register to hcca. 3 to 0 reserved - table 75. hcfminterval - host controller frame interval register bit allocation address: content of the base address register + 34h bit 31 30 29 28 27 26 25 24 symbol fit fsmps[14:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 50 of 98 nxp semiconductors isp1564 hs usb pci host controller [1] the reserved bits must always be written with the reset value. 11.1.15 hcfmremaining register this register is a 14-bit down counter showing the bit time remaining in the current frame. t ab le 77 contains the bit allocation of this register. bit 23 22 21 20 19 18 17 16 symbol fsmps[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] fi[13:8] reset 00101110 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol fi[7:0] reset 11011111 access r/w r/w r/w r/w r/w r/w r/w r/w table 76. hcfminterval - host controller frame interval register bit description address: content of the base address register + 34h bit symbol description 31 fit frame interval toggle : the hcd toggles this bit whenever it loads a new value to frame interval. 30 to 16 fsmps[14:0] fs largest data packet : this ?eld speci?es the value that is loaded into the largest data packet counter at the beginning of each frame. the counter value represents the largest amount of data in bits that can be sent or received by the host controller in a single transaction at any given time, without causing a scheduling overrun. the ?eld value is calculated by the hcd. 15 to 14 reserved - 13 to 0 fi[13:0] frame interval : this speci?es the interval between two consecutive sofs in bit times. the nominal value is set to 11,999. the hcd must store the current value of this ?eld before resetting the host controller to reset this ?eld to its nominal value. the hcd can then restore the stored value on completing the reset sequence. table 77. hcfmremaining - host controller frame remaining register bit allocation address: content of the base address register + 38h bit 31 30 29 28 27 26 25 24 symbol frt reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 51 of 98 nxp semiconductors isp1564 hs usb pci host controller [1] the reserved bits must always be written with the reset value. 11.1.16 hcfmnumber register this register is a 16-bit counter, and the bit allocation is given in t ab le 79 . it provides a timing reference among events happening in the host controller and the hcd. the hcd may use the 16-bit value speci?ed in this register and generate a 32-bit frame number, without requiring frequent access to the register. bit 15 14 13 12 11 10 9 8 symbol reserved [1] fr[13:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol fr[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 78. hcfmremaining - host controller frame remaining register bit description address: content of the base address register + 38h bit symbol description 31 frt frame remaining toggle : this bit is loaded from fit (bit 31 of hcfminterval) whenever fr[13:0] reaches 0. this bit is used by the hcd for the synchronization between fi[13:0] (bits 13 to 0 of hcfminterval) and fr[13:0]. 30 to 14 reserved - 13 to 0 fr[13:0] frame remaining : this counter is decremented at each bit time. when it reaches 0, it is reset by loading the fi[13:0] value speci?ed in hcfminterval at the next bit time boundary. when entering the usboperational state, the host controller reloads the content with fi[13:0] of hcfminterval and uses the updated value from the next sof. table 79. hcfmnumber - host controller frame number register bit allocation address: content of the base address register + 3ch bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] fn[13:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 52 of 98 nxp semiconductors isp1564 hs usb pci host controller [1] the reserved bits must always be written with the reset value. 11.1.17 hcperiodicstart register this register has a 14-bit programmable value that determines when is the earliest time for the host controller to start processing the periodic list. for bit allocation, see t ab le 81 . [1] the reserved bits must always be written with the reset value. bit 7 6 5 4 3 2 1 0 symbol fn[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 80. hcfmnumber - host controller frame number register bit description address: content of the base address register + 3ch bit symbol description 31 to 14 reserved - 13 to 0 fn[13:0] frame number : incremented when hcfmremaining is reloaded. it must be rolled over to 0h after ffffh. automatically incremented when entering the usboperational state. the content is written to hcca after the host controller has incremented frame number at each frame boundary and sent an sof but before the host controller reads the ?rst ed in that frame. after writing to hcca, the host controller sets sf (bit 2 in hcinterruptstatus). table 81. hcperiodicstart - host controller periodic start register bit allocation address: content of the base address register + 40h bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] p_s[13:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol p_s[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 53 of 98 nxp semiconductors isp1564 hs usb pci host controller 11.1.18 hclsthreshold register this register contains an 11-bit value used by the host controller to determine whether to commit to the transfer of a maximum of 8-byte low-speed packet before eof. neither the host controller nor the hcd can change this value. for bit allocation, see t ab le 83 . [1] the reserved bits must always be written with the reset value. 11.1.19 hcrhdescriptora register this register is the ?rst of two registers describing the characteristics of the root hub. reset values are implementation-speci?c. table 82. hcperiodicstart - host controller periodic start register bit description address: content of the base address register + 40h bit symbol description 31 to 14 reserved - 13 to 0 p_s[13:0] periodic start : after a hardware reset, this ?eld is cleared. it is then set by the hcd during the host controller initialization. the value is roughly calculated as 10 % of hcfminterval. a typical value is 3e67h. when hcfmremaining reaches the value speci?ed, processing of the periodic lists have priority over control or bulk processing. the host controller, therefore, starts processing the interrupt list after completing the current control or bulk transaction that is in progress. table 83. hclsthreshold - host controller low-speed threshold register bit allocation address: content of the base address register + 44h bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] lst[11:8] reset 00000110 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol lst[7:0] reset 00101000 access r/w r/w r/w r/w r/w r/w r/w r/w table 84. hclsthreshold - host controller low-speed threshold register bit description address: content of the base address register + 44h bit symbol description 31 to 12 reserved - 11 to 0 lst[11:0] ls threshold : this ?eld contains a value that is compared to the fr[13:0] ?eld, before initiating a low-speed transaction. the transaction is started only if fr 3 this ?eld. the value is calculated by the hcd, considering the transmission and set-up overhead.
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 54 of 98 nxp semiconductors isp1564 hs usb pci host controller t ab le 85 contains the bit allocation of the hcrhdescriptora register. [1] the reserved bits must always be written with the reset value. table 85. hcrhdescriptora - host controller root hub descriptor a register bit allocation address: content of the base address register + 48h bit 31 30 29 28 27 26 25 24 symbol potpgt[7:0] reset 11111111 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] nocp ocpm dt nps psm reset 00001001 access r/w r/w r/w r/w r/w r r/w r/w bit 7 6 5 4 3 2 1 0 symbol ndp[7:0] reset 00000010 access rrrrrrrr table 86. hcrhdescriptora - host controller root hub descriptor a register bit description address: content of the base address register + 48h bit symbol description 31 to 24 potpgt [7:0] power on to power good time : this byte speci?es the duration the hcd must wait before accessing a powered-on port of the root hub. it is implementation-speci?c. the unit of time is 2 ms. the duration is calculated as potpgt 2ms. 23 to 13 reserved - 12 nocp no overcurrent protection : this bit describes how the overcurrent status for root hub ports are reported. when this bit is cleared, the ocpm bit speci?es global or per-port reporting. 0 overcurrent status is collectively reported for all downstream ports. 1 no overcurrent protection supported. 11 ocpm overcurrent protection mode : this bit describes how the overcurrent status for root hub ports are reported. at reset, this ?elds re?ects the same mode as power switching mode. this ?eld is valid only if the nocp bit is cleared. 0 overcurrent status is collectively reported for all downstream ports. 1 overcurrent status is reported on a per-port basis. 10 dt device type : this bit speci?es that the root hub is not a compound device. the root hub is not permitted to be a compound device. this ?eld must always read logic 0.
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 55 of 98 nxp semiconductors isp1564 hs usb pci host controller 11.1.20 hcrhdescriptorb register the hcrhdescriptorb register is the second of two registers describing the characteristics of the root hub. the bit allocation is given in t ab le 87 . these ?elds are written during initialization to correspond to the system implementation. reset values are implementation-speci?c. 9 nps no power switching : this bit is used to specify whether power switching is supported or ports are always powered. it is implementation-speci?c. when this bit is cleared, the psm bit speci?es global or per-port switching. 0 ports are power switched. 1 ports are always powered on when the host controller is powered on. 8 psm power switching mode : this bit is used to specify how the power switching of root hub ports is controlled. it is implementation-speci?c. this ?eld is only valid if the nps ?eld is cleared. 0 all ports are powered at the same time. 1 each port is individually powered. this mode allows port power to be controlled by either the global switch or per-port switching. if the ppcm (port power control mask) bit is set, the port responds only to port power commands (set/clear port power). if the port mask is cleared, then the port is controlled only by the global power switch (set/clear global power). 7 to 0 ndp[7:0] number downstream ports : these bits specify the number of downstream ports supported by the root hub. it is implementation-speci?c. the minimum number of ports is 1. the maximum number of ports supported by ohci is 15. table 86. hcrhdescriptora - host controller root hub descriptor a register bit description continued address: content of the base address register + 48h bit symbol description table 87. hcrhdescriptorb - host controller root hub descriptor b register bit allocation address: content of the base address register + 4ch bit 31 30 29 28 27 26 25 24 symbol ppcm[15:0] reset 00000000 access r/w r/w r/w r/w r r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol ppcm[7:0] reset 00000110 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol dr[15:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol dr[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 56 of 98 nxp semiconductors isp1564 hs usb pci host controller 11.1.21 hcrhstatus register this register is divided into two parts. the lower word of a dword represents the hub status ?eld, and the upper word represents the hub status change ?eld. reserved bits must always be written as logic 0. t ab le 89 shows the bit allocation of the register. [1] the reserved bits must always be written with the reset value. table 88. hcrhdescriptorb - host controller root hub descriptor b register bit description address: content of the base address register + 4ch bit symbol description 31 to 16 ppcm[15:0] port power control mask : each bit indicates whether a port is affected by a global power control command when power switching mode is set. when set, only the power state of the port is affected by per-port power control (set/clear port power). when cleared, the port is controlled by the global power switch (set/clear global power). if the device is con?gured to global switching mode (power switching mode = 0), this ?eld is not valid. bit 0 reserved bit 1 ganged-power mask on port 1 bit 2 ganged-power mask on port 2 15 to 0 dr[15:0] device removable : each bit is dedicated to a port of the root hub. when cleared, the attached device is removable. when set, the attached device is not removable. bit 0 reserved bit 1 device attached to port 1 bit 2 device attached to port 2 table 89. hcrhstatus - host controller root hub status register bit allocation address: content of the base address register + 50h bit 31 30 29 28 27 26 25 24 symbol crwe reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] ccic lpsc reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol drwe reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved [1] oci lps reset 00000000 access r/w r/w r/w r/w r/w r/w r rw
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 57 of 98 nxp semiconductors isp1564 hs usb pci host controller 11.1.22 hcrhportstatus[2:1] register the hcrhportstatus[2:1] register is used to control and report port events on a per-port basis. numberdownstreamports represents the number of hcrhportstatus registers that are implemented in hardware. the lower word re?ects the port status. the upper word re?ects status change bits. some status bits are implemented with special write behavior. if a transaction, token through handshake, is in progress when a write to change port status occurs, the resulting port status change is postponed until the transaction completes. always write logic 0 to the reserved bits. the bit allocation of the register is given in t ab le 91 . table 90. hcrhstatus - host controller root hub status register bit description address: content of the base address register + 50h bit symbol description 31 crwe on write clear remote wake-up enable : 0 no effect 1 clears drwe (device remote wake-up enable) 30 to 18 reserved - 17 ccic overcurrent indicator change : this bit is set by hardware when a change has occurred to the oci bit of this register. 0 no effect 1 the hcd clears this bit. 16 lpsc on read local power status change : the root hub does not support the local power status feature. therefore, this bit is always logic 0. on write set global power : in global power mode (power switching mode = 0), logic 1 is written to this bit to turn on power to all ports (clear port power status). in per-port power mode, it sets port power status only on ports whose port power control mask bit is not set. writing logic 0 has no effect. 15 drwe on read device remote wake-up enable : this bit enables bit connect status change (csc) as a resume event, causing a state transition from usbsuspend to usbresume and setting the resume detected interrupt. 0 csc is not a remote wake-up event. 1 csc is a remote wake-up event. on write set remote wake-up enable : writing logic 1 sets drwe (device remote wake-up enable). writing logic 0 has no effect. 14 to 2 reserved - 1 oci overcurrent indicator : this bit reports overcurrent conditions when global reporting is implemented. when set, an overcurrent condition exists. when cleared, all power operations are normal. if the per-port overcurrent protection is implemented, this bit is always logic 0. 0 lps on read local power status : the root hub does not support the local power status feature. therefore, this bit is always read as logic 0. on write clear global power : in global power mode (power switching mode = 0), logic 1 is written to this bit to turn off power to all ports (clear port power status). in per-port power mode, it clears port power status only on ports whose port power control mask bit is not set. writing logic 0 has no effect.
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 58 of 98 nxp semiconductors isp1564 hs usb pci host controller [1] the reserved bits must always be written with the reset value. table 91. hcrhportstatus[2:1] - host controller root hub port status[2:1] register bit allocation address: content of the base address register + 54h bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] prsc ocic pssc pesc csc reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] lsda pps reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved [1] prs poci pss pes ccs reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 92. hcrhportstatus[2:1] - host controller root hub port status[2:1] register bit description address: content of the base address register + 54h bit symbol description 31 to 21 reserved - 20 prsc port reset status change : this bit is set at the end of the 10 ms port reset signal. the hcd can write logic 1 to clear this bit. writing logic 0 has no effect. 0 port reset is not complete. 1 port reset is complete. 19 ocic port overcurrent indicator change : this bit is valid only if overcurrent conditions are reported on a per-port basis. this bit is set when the root hub changes the poci (port overcurrent indicator) bit. the hcd can write logic 1 to clear this bit. writing logic 0 has no effect. 0 no change in poci. 1 poci has changed. 18 pssc port suspend status change : this bit is set when the resume sequence is completed. this sequence includes the 20 ms resume pulse, ls eop and 3 ms re-synchronization delay. the hcd can write logic 1 to clear this bit. writing logic 0 has no effect. this bit is also cleared when reset status change is set. 0 resume is not completed. 1 resume is completed. 17 pesc port enable status change : this bit is set when hardware events cause the pes (port enable status) bit to be cleared. changes from the hcd writes do not set this bit. the hcd can write logic 1 to clear this bit. writing logic 0 has no effect. 0 no change in pes. 1 change in pes.
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 59 of 98 nxp semiconductors isp1564 hs usb pci host controller 16 csc connect status change : this bit is set whenever a connect or disconnect event occurs. the hcd can write logic 1 to clear this bit. writing logic 0 has no effect. if ccs (current connect status) is cleared when a set port reset, set port enable or set port suspend write occurs, this bit is set to force the driver to re-evaluate the connection status because these writes must not occur if the port is disconnected. 0 no change in ccs. 1 change in ccs. remark: if the deviceremovable[ndp] bit is set, this bit is set only after a root hub reset to inform the system that the device is attached. 15 to 10 reserved - 9 lsda on read low-speed device attached : this bit indicates the speed of the device attached to this port. when set, a low-speed device is attached to this port. when cleared, a full-speed device is attached to this port. this ?eld is valid only when ccs is set. 0 port is not suspended. 1 port is suspended. on write clear port power : the hcd can clear the pps (port power status) bit by writing logic 1 to this bit. writing logic 0 has no effect. 8 pps on read port power status : this bit re?ects the port power status, regardless of the type of power switching implemented. this bit is cleared if an overcurrent condition is detected. the hcd can set this bit by writing set port power or set global power. the hcd can clear this bit by writing clear port power or clear global power. power switching mode and portpowercontrolmask[ndp] determine which power control switches are enabled. in global switching mode (power switching mode = 0), only set/clear global power controls this bit. in the per-port power switching (power switching mode = 1), if the portpowercontrolmask[ndp] bit for the port is set, only set/clear port power commands are enabled. if the mask is not set, only set/clear global power commands are enabled. when port power is disabled, bits ccs (current connect status), pes (port enable status), pss (port suspend status) and prs (port reset status) must be reset. 0 port power is off. 1 port power is on. on write set port power : the hcd can write logic 1 to set the pps (port power status) bit. writing logic 0 has no effect. remark: this bit always reads logic 1 if power switching is not supported. 7 to 5 reserved - 4 prs on read port reset status : when this bit is set by a write to set port reset, port reset signaling is asserted. when reset is completed and prsc is set, this bit is cleared. 0 port reset signal is inactive. 1 port reset signal is active. on write set port reset : the hcd can set the port reset signaling by writing logic 1 to this bit. writing logic 0 has no effect. if ccs is cleared, this write does not set prs (port reset status) but instead sets ccs. this informs the driver that it attempted to reset a disconnected port. table 92. hcrhportstatus[2:1] - host controller root hub port status[2:1] register bit description continued address: content of the base address register + 54h bit symbol description
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 60 of 98 nxp semiconductors isp1564 hs usb pci host controller 11.2 ehci controller capability registers other than the ohci host controller, there are some registers in ehci that de?ne the capability of ehci. the address range of these registers is located before operational registers. 11.2.1 caplength/hciversion register the bit allocation of this 4-byte register is given in t ab le 93 . 3 poci on read port overcurrent indicator : this bit is valid only when the root hub is con?gured to show overcurrent conditions are reported on a per-port basis. if the per-port overcurrent reporting is not supported, this bit is set to logic 0. if cleared, all power operations are normal for this port. if set, an overcurrent condition exists on this port. 0 no overcurrent condition. 1 overcurrent condition detected. on write clear suspend status : the hcd can write logic 1 to initiate a resume. writing logic 0 has no effect. a resume is initiated only if pss (port suspend status) is set. 2 pss on read port suspend status : this bit indicates whether the port is suspended or is in the resume sequence. it is set by a set suspend state write and cleared when pssc (port suspend status change) is set at the end of the resume interval. this bit is not set if ccs (current connect status) is cleared. this bit is also cleared when prsc is set at the end of the port reset or when the host controller is placed in the usbresume state. if an upstream resume is in progress, it will propagate to the host controller. 0 port is not suspended. 1 port is suspended. on write set port suspend : the hcd can set the pss (port suspend status) bit by writing logic 1 to this bit. writing logic 0 has no effect. if ccs is cleared, this write does not set pss; instead it sets css. this informs the driver that it attempted to suspend a disconnected port. 1 pes on read port enable status : this bit indicates whether the port is enabled or disabled. the root hub may clear this bit when an overcurrent condition, disconnect event, switched-off power or operational bus error is detected. this change also causes port enabled status change to be set. the hcd can set this bit by writing set port enable and clear it by writing clear port enable. this bit cannot be set when ccs (current connect status) is cleared. this bit is also set on completing a port reset when reset status change is set or on completing a port suspend when suspend status change is set. 0 port is disabled. 1 port is enabled. on write set port enable : the hcd can set pes (port enable status) by writing logic 1. writing logic 0 has no effect. if ccs is cleared, this write does not set pes, but instead sets csc (connect status change). this informs the driver that it attempted to enable a disconnected port. 0 ccs on read current connect status : this bit re?ects the current state of the downstream port. 0 no device is connected. 1 device is connected. on write clear port enable : the hcd can write logic 1 to this bit to clear the pes (port enable status) bit. writing logic 0 has no effect. the ccs bit is not affected by any write. remark: this bit always reads logic 1 when the attached device is nonremovable (deviceremovable[ndp]). table 92. hcrhportstatus[2:1] - host controller root hub port status[2:1] register bit description continued address: content of the base address register + 54h bit symbol description
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 61 of 98 nxp semiconductors isp1564 hs usb pci host controller 11.2.2 hcsparams register the host controller structural parameters (hcsparams) register is a set of ?elds that are structural parameters. the bit allocation is given in t ab le 95 . table 93. caplength/hciversion - capability length/host controller interface version number register bit allocation address: content of the base address register + 00h bit 31 30 29 28 27 26 25 24 symbol hciversion[15:8] reset 00000001 access rrrrrrrr bit 23 22 21 20 19 18 17 16 symbol hciversion[7:0] reset 00000000 access rrrrrrrr bit 15 14 13 12 11 10 9 8 symbol reserved reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol caplength[7:0] reset 00100000 access rrrrrrrr table 94. caplength/hciversion - capability length/host controller interface version number register bit description address: content of the base address register + 00h bit symbol description 31 to 16 hciversion [15:0] host controller interface version number : this ?eld contains a bcd encoded version number of the interface to which the host controller interface conforms. 15 to 8 reserved - 7 to 0 caplength [7:0] capability register length : this is used as an offset. it is added to the register base to ?nd the beginning of the operational register space. table 95. hcsparams - host controller structural parameters register bit allocation address: content of the base address register + 04h bit 31 30 29 28 27 26 25 24 symbol reserved reset 00000000 access rrrrrrrr bit 23 22 21 20 19 18 17 16 symbol reserved reset 00000000 access rrrrrrrr
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 62 of 98 nxp semiconductors isp1564 hs usb pci host controller 11.2.3 hccparams register the host controller capability parameters (hccparams) register is a 4-byte register, and the bit allocation is given in t ab le 97 . bit 15 14 13 12 11 10 9 8 symbol n_cc[3:0] n_pcc[3:0] reset 00010010 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol prr reserved ppc n_ports[3:0] reset 10010010 access rrrrrrrr table 96. hcsparams - host controller structural parameters register bit description address: content of the base address register + 04h bit symbol description 31 to 16 reserved - 15 to 12 n_cc [3:0] number of companion controller : this ?eld indicates the number of companion controllers associated with this hi-speed usb host controller. a value of zero in this ?eld indicates there are no companion host controllers. port-ownership hand-off is not supported. only high-speed devices are supported on the host controller root ports. a value larger than zero in this ?eld indicates there are companion original usb host controller(s). port-ownership hand-offs are supported. 11 to 8 n_pcc [3:0] number of ports per companion controller : this ?eld indicates the number of ports supported per companion host controller. it is used to indicate the port routing con?guration to the system software. for example, if n_ports has a value of 6 and n_cc has a value of 2, then n_pcc can have a value of 3. the convention is that the ?rst n_pcc ports are assumed to be routed to companion controller 1, the next n_pcc ports to companion controller 2, and so on. in the previous example, n_pcc could have been 4, in which case the ?rst four are routed to companion controller 1 and the last two are routed to companion controller 2. the number in this ?eld must be consistent with n_ports and n_cc. 7 prr port routing rules : this ?eld indicates the method used to map ports to companion controllers. 0 the ?rst n_pcc ports are routed to the lowest numbered function companion host controller, the next n_pcc ports are routed to the next lowest function companion controller, and so on. 1 the port routing is explicitly enumerated by the ?rst n_ports elements of the hcsp-portroute array. 6 to 5 reserved - 4 ppc port power control : this ?eld indicates whether the host controller implementation includes port power control. logic 1 indicates the port has port power switches. logic 0 indicates the port does not have port power switches. the value of this ?eld affects the functionality of the port power ?eld in each port status and control register. 3 to 0 n_ports [3:0] number of ports : this ?eld speci?es the number of physical downstream ports implemented on this host controller. the value in this ?eld determines how many port registers are addressable in the operational register space. logic 0 in this ?eld is unde?ned.
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 63 of 98 nxp semiconductors isp1564 hs usb pci host controller 11.2.4 hcsp-portroute register the hcsp-portroute (companion port route description) register is an optional read-only ?eld that is valid only if prr (bit 7 in the hcsparams register) is logic 1. its address is content of the base address register + 0ch. this ?eld is a 15-element nibble array, each 4 bits is one array element. each array location corresponds one-to-one with a physical port provided by the host controller. for example, portroute[0] corresponds to the ?rst portsc port, portroute[1] to the table 97. hccparams - host controller capability parameters register bit allocation address: content of the base address register + 08h bit 31 30 29 28 27 26 25 24 symbol reserved reset 00000000 access rrrrrrrr bit 23 22 21 20 19 18 17 16 symbol reserved reset 00000000 access rrrrrrrr bit 15 14 13 12 11 10 9 8 symbol reserved reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol ist[3:0] reserved pflf 64ac reset 00010010 access rrrrrrrr table 98. hccparams - host controller capability parameters register bit description address: content of the base address register + 08h bit symbol description 31 to 8 reserved - 7 to 4 ist[3:0] isochronous scheduling threshold : default = implementation dependent. this ?eld indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. when ist[3] is logic 0, the value of the least signi?cant three bits indicates the number of microframes a host controller can hold a set of isochronous data structures, one or more, before ?ushing the state. when ist[3] is logic 1, the host software assumes the host controller may cache an isochronous data structure for an entire frame. 3 to 2 reserved - 1 pflf programmable frame list flag : default = implementation dependent. if this bit is cleared, the system software must use a frame list length of 1024 elements with the host controller. the usbcmd register fls[1:0] (bits 3 and 2) is read-only and must be cleared. if pflf is set, the system software can specify and use a smaller frame list, and con?gure the host through the fls bit. the frame list must always be aligned on a 4 kb page boundary to ensure that the frame list is always physically contiguous. 0 64ac 64-bit addressing capability : this ?eld contains the addressing range capability. 0 data structures using 32-bit address memory pointers. 1 data structures using 64-bit address memory pointers.
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 64 of 98 nxp semiconductors isp1564 hs usb pci host controller second portsc port, and so on. the value of each element indicates to which of the companion host controllers this port is routed. only the ?rst n_ports elements have valid information. a value of zero indicates that the port is routed to the lowest numbered function companion host controller. a value of one indicates that the port is routed to the next lowest numbered function companion host controller, and so on. 11.3 operational registers of enhanced usb host controller 11.3.1 usbcmd register the usb command (usbcmd) register indicates the command to be executed by the serial host controller. writing to this register causes a command to be executed. t ab le 99 shows the bit allocation. [1] the reserved bits must always be written with the reset value. table 99. usbcmd - usb command register bit allocation address: content of the base address register + 20h bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol itc[7:0] reset 00001000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol lhcr iaad ase pse fls[1:0] hc reset rs reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 65 of 98 nxp semiconductors isp1564 hs usb pci host controller table 100. usbcmd - usb command register bit description address: content of the base address register + 20h bit symbol description 31 to 24 reserved - 23 to 16 itc[7:0] interrupt threshold control : default = 08h. this ?eld is used by the system software to select the maximum rate at which the host controller will issue interrupts. if software writes an invalid value to this register, the results are unde?ned. valid values are: 00h reserved 01h 1 microframe 02h 2 microframes 04h 4 microframes 08h 8 microframes (equals 1 ms) 10h 16 microframes (equals 2 ms) 20h 32 microframes (equals 4 ms) 40h 64 microframes (equals 8 ms) software modi?cations to this ?eld while hch (bit 12) in the usbsts register is zero results in unde?ned behavior. 15 to 8 reserved - 7 lhcr light host controller reset : this control bit is not required. it allows the driver software to reset the ehci controller, without affecting the state of the ports or the relationship to the companion host controllers. if not implemented, a read of this ?eld will always return zero. if implemented, on read: 0 indicates that the light host controller reset has completed and it is ready for the host software to re-initialize the host controller. 1 indicates that the light host controller reset has not yet completed. 6 iaad interrupt on asynchronous advance doorbell : this bit is used as a doorbell by software to notify the host controller to issue an interrupt the next time it advances the asynchronous schedule. software must write logic 1 to this bit to ring the doorbell. when the host controller has evicted all appropriate cached schedule states, it sets iaa (bit 5 in the usbsts register). if iaae (bit 5 in the usbintr register) is logic 1, then the host controller will assert an interrupt at the next interrupt threshold. the host controller sets this bit to logic 0 after it sets iaa. software must not set this bit when the asynchronous schedule is inactive because this results in an unde?ned value.
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 66 of 98 nxp semiconductors isp1564 hs usb pci host controller 11.3.2 usbsts register the usb status (usbsts) register indicates pending interrupts and various states of the host controller. the status resulting from a transaction on the serial bus is not indicated in this register. software clears the register bits by writing ones to them. the bit allocation is given in t ab le 101 . 5 ase asynchronous schedule enable : default = 0. this bit controls whether the host controller skips processing the asynchronous schedule. 0 do not process the asynchronous schedule. 1 use the asynclistaddr register to access the asynchronous schedule. 4 pse periodic schedule enable : default = 0. this bit controls whether the host controller skips processing the periodic schedule. 0 do not process the periodic schedule. 1 use the periodiclistbase register to access the periodic schedule. 3 to 2 fls[1:0] frame list size : default = 00b. this ?eld is read and write only if pflf (bit 1) in the hccparams register is set to logic 1. this ?eld speci?es the size of the frame list. the size the frame list controls which bits in the frame index register must be used for the frame list current index. 00b 1024 elements (4096 bytes) 01b 512 elements (2048 bytes) 10b 256 elements (1024 bytes) for small environments 11b reserved 1 hcreset host controller reset : this control bit is used by the software to reset the host controller. the effects of this on root hub registers are similar to a chip hardware reset. setting this bit causes the host controller to reset its internal pipelines, timers, counters, state machines, and so on, to their initial values. any transaction currently in progress on usb is immediately terminated. a usb reset is not driven on downstream ports. this reset does not affect the pci con?guration registers. all operational registers, including port registers and port state machines, are set to their initial values. port ownership reverts to the companion host controller(s). the software must re-initialize the host controller to return it to an operational state. this bit is cleared by the host controller when the reset process is complete. software cannot terminate the reset process early by writing logic 0 to this register. software must check that bit hch is logic 0 before setting this bit. attempting to reset an actively running host controller results in unde?ned behavior. 0rs run/stop : 1 = run. 0 = stop. when set, the host controller executes the schedule. the host controller continues execution as long as this bit is set. when this bit is cleared, the host controller completes the current and active transactions in the usb pipeline, and then halts. bit hch indicates when the host controller has ?nished the transaction and has entered the stopped state. software must check that the hch bit is logic 1, before setting this bit. table 100. usbcmd - usb command register bit description continued address: content of the base address register + 20h bit symbol description table 101. usbsts - usb status register bit allocation address: content of the base address register + 24h bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 67 of 98 nxp semiconductors isp1564 hs usb pci host controller [1] the reserved bits must always be written with the reset value. bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol ass psstat recl hch reserved [1] reset 00010000 access rrrrr/wr/wr/wr/w bit 7 6 5 4 3 2 1 0 symbol reserved [1] iaa hse flr pcd usb errint usbint reset 00000000 access r/w r/w r r/w r/w r/w r/w r/w table 102. usbsts - usb status register bit description address: content of the base address register + 24h bit symbol description 31 to 16 reserved - 15 ass asynchronous schedule status : default = 0. the bit reports the current real status of the asynchronous schedule. if this bit is logic 0, the status of the asynchronous schedule is disabled. if this bit is logic 1, the status of the asynchronous schedule is enabled. the host controller is not required to immediately disable or enable the asynchronous schedule when software changes ase (bit 5 in the usbcmd register). when this bit and the ase bit have the same value, the asynchronous schedule is either enabled (1) or disabled (0). 14 psstat periodic schedule status : default = 0. this bit reports the current status of the periodic schedule. if this bit is logic 0, the status of the periodic schedule is disabled. if this bit is logic 1, the status of the periodic schedule is enabled. the host controller is not required to immediately disable or enable the periodic schedule when software changes pse (bit 4) in the usbcmd register. when this bit and the pse bit have the same value, the periodic schedule is either enabled (1) or disabled (0). 13 recl reclamation : default = 0. this is a read-only status bit that is used to detect an empty asynchronous schedule. 12 hch hc halted : default = 1. this bit is logic 0 when rs (bit 0) in the usbcmd register is logic 1. the host controller sets this bit to logic 1 after it has stopped executing because the rs bit is set to logic 0, either by software or by the host controller hardware. for example, on an internal error. 11 to 6 reserved - 5 iaa interrupt on asynchronous advance : default = 0. the system software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing logic 1 to iaad (bit 6) in the usbcmd register. this status bit indicates the assertion of that interrupt source. 4 hse host system error : the host controller sets this bit when a serious error occurs during a host system access, involving the host controller module. in a pci system, conditions that set this bit include pci parity error, pci master abort and pci target abort. when this error occurs, the host controller clears rs (bit 0 in the usbcmd register) to prevent further execution of the scheduled tds.
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 68 of 98 nxp semiconductors isp1564 hs usb pci host controller 11.3.3 usbintr register the usb interrupt enable (usbintr) register enables and disables reporting of the corresponding interrupt to the software. when a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. interrupt sources that are disabled in this register still appear in usbsts to allow the software to poll for events. the usbsts register bit allocation is given in t ab le 103 . 3 flr frame list rollover : the host controller sets this bit to logic 1 when the frame list index rolls over from its maximum value to zero. the exact value at which the rollover occurs depends on the frame list size. for example, if the frame list size, as programmed in fls (bits 3 to 2) of the usbcmd register, is 1024, the frame index register rolls over every time bit 13 of the frindex register toggles. similarly, if the size is 512, the host controller sets this bit to logic 1 every time bit 12 of the frindex register toggles. 2 pcd port change detect : the host controller sets this bit to logic 1 when any port, where po (bit 13 of portsc) is cleared, changes to logic 1, or fpr (bit 6 of portsc) changes to logic 1 as a result of a j-k transition detected on a suspended port. this bit is allowed to be maintained in the auxiliary power well. alternatively, it is also acceptable that, on a d3-to-d0 transition of the ehci host controller device, this bit is loaded with the logical or of all the portsc change bits, including force port resume, overcurrent change, enable or disable change, and connect status change. 1 usberr int usb error interrupt : the host controller sets this bit when an error condition occurs because of completing a usb transaction. for example, error counter under?ow. if the transfer descriptor (td) on which the error interrupt occurred also had its ioc bit set, both this bit and the usbint bit are set. for details, refer to enhanced host controller interface speci?cation for universal serial bus rev. 1.0 . 0 usbint usb interrupt : the host controller sets this bit on completing a usb transaction, which results in the retirement of a td that had its ioc bit set. the host controller also sets this bit when a short packet is detected, that is, the actual number of bytes received was less than the expected number of bytes. for details, refer to enhanced host controller interface speci?cation for universal serial bus rev. 1.0 . table 102. usbsts - usb status register bit description continued address: content of the base address register + 24h bit symbol description table 103. usbintr - usb interrupt enable register bit allocation address: content of the base address register + 28h bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 69 of 98 nxp semiconductors isp1564 hs usb pci host controller [1] the reserved bits must always be written with the reset value. 11.3.4 frindex register the frame index (frindex) register is used by the host controller to index into the periodic frame list. the register updates every 125 m s, once each microframe. bits n to 3 are used to select a particular entry in the periodic frame list during periodic schedule execution. the number of bits used for the index depends on the size of the frame list as set by the system software in fls[1:0] (bits 3 to 2) of the usbcmd register. this register must be written as a dword. byte writes produce unde?ned results. this register cannot be written unless the host controller is in the halted state, as indicated by hch (bit 12 in the usbsts register). a write to this register while rs (bit 0 in the usbcmd register) is set produces unde?ned results. writes to this register also affect the sof value. the bit allocation is given in t ab le 105 . bit 7 6 5 4 3 2 1 0 symbol reserved [1] iaae hsee flre pcie usberr inte usbinte reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 104. usbintr - usb interrupt enable register bit description address: content of the base address register + 28h bit symbol description 31 to 6 reserved - 5 iaae interrupt on asynchronous advance enable : when this bit and iaa (bit 5 in the usbsts register) are set, the host controller issues an interrupt at the next interrupt threshold. the interrupt is acknowledged by software clearing bit iaa. 4 hsee host system error enable : when this bit and hse (bit 4 in the usbsts register) are set, the host controller issues an interrupt. the interrupt is acknowledged by software clearing bit hse. 3 flre frame list rollover enable : when this bit and flr (bit 3 in the usbsts register) are set, the host controller issues an interrupt. the interrupt is acknowledged by software clearing bit flr. 2 pcie port change interrupt enable : when this bit and pcd (bit 2 in the usbsts register) are set, the host controller issues an interrupt. the interrupt is acknowledged by software clearing bit pcd. 1 usb errinte usb error interrupt enable : when this bit and usberrint (bit 1 in the usbsts register) are set, the host controller issues an interrupt at the next interrupt threshold. the interrupt is acknowledged by software clearing bit usberrint. 0 usbinte usb interrupt enable : when this bit and usbint (bit 0 in the usbsts register) are set, the host controller issues an interrupt at the next interrupt threshold. the interrupt is acknowledged by software clearing bit usbint. table 105. frindex - frame index register bit allocation address: content of the base address register + 2ch bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 70 of 98 nxp semiconductors isp1564 hs usb pci host controller [1] the reserved bits must always be written with the reset value. 11.3.5 periodiclistbase register the periodic frame list base address (periodiclistbase) register contains the beginning address of the periodic frame list in the system memory. if the host controller is in 64-bit mode, as indicated by logic 1 in 64ac (bit 0 of the hccparams register), the most signi?cant 32 bits of every control data structure address comes from the ctrldssegment register. for details on the ctrldssegment register, refer to enhanced host controller interface speci?cation for universal serial bus rev. 1.0 . the system software loads this register before starting the schedule execution by the host controller. the memory structure referenced by this physical memory pointer is assumed as 4 kb aligned. the contents of this register are combined with the frindex register to enable the host controller to step through the periodic frame list in sequence. the bit allocation is given in t ab le 108 . bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] frindex[13:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol frindex[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 106. frindex - frame index register bit description address: content of the base address register + 2ch bit symbol description 31 to 14 reserved - 13 to 0 frindex [13:0] frame index : bits in this register are used for the frame number in the sof packet and as the index into the frame list. the value in this register increments at the end of each time frame. for example, microframe. the bits used for the frame number in the sof token are taken from bits 13 to 3 of this register. bits n to 3 are used for the frame list current index. this means that each location of the frame list is accessed eight times, frames or microframes, before moving to the next index. t ab le 107 illustrates n based on the value of fls[1:0] (bits 3 to 2 in the usbcmd register). table 107. n based value of fls[1:0] fls[1:0] number elements n 00b 1024 12 01b 512 11 10b 256 10 11b reserved -
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 71 of 98 nxp semiconductors isp1564 hs usb pci host controller [1] the reserved bits must always be written with the reset value. 11.3.6 asynclistaddr register this 32-bit register contains the address of the next asynchronous queue head to be executed. if the host controller is in 64-bit mode, as indicated by logic 1 in 64ac (bit 0 of the hccparams register), the most signi?cant 32 bits of every control data structure address comes from the ctrldssegment register. for details on the ctrldssegment register, refer to enhanced host controller interface speci?cation for universal serial bus rev. 1.0 . bits 4 to 0 of this register always return zeros when read. the memory structure referenced by the physical memory pointer is assumed as 32 bytes (cache aligned). for bit allocation, see t ab le 110 . table 108. periodiclistbase - periodic frame list base address register bit allocation address: content of the base address register + 34h bit 31 30 29 28 27 26 25 24 symbol ba[19:12] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol ba[11:4] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol ba[3:0] reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 109. periodiclistbase - periodic frame list base address register bit description address: content of the base address register + 34h bit symbol description 31 to 12 ba[19:0] base address : these bits correspond to memory address signals 31 to 12, respectively. 11 to 0 reserved - table 110. asynclistaddr - current asynchronous list address register bit allocation address: content of the base address register + 38h bit 31 30 29 28 27 26 25 24 symbol lpl[26:19] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 72 of 98 nxp semiconductors isp1564 hs usb pci host controller [1] the reserved bits must always be written with the reset value. 11.3.7 configflag register the bit allocation of the con?gure flag (configflag) register is given in t ab le 112 . [1] the reserved bits must always be written with the reset value. bit 23 22 21 20 19 18 17 16 symbol lpl[18:11] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol lpl[10:3] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol lpl[2:0] reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 111. asynclistaddr - current asynchronous list address register bit description address: content of the base address register + 38h bit symbol description 31 to 5 lpl[26:0] link pointer list : these bits correspond to memory address signals 31 to 12, respectively. this ?eld may only reference a queue head (qh). 4 to 0 reserved - table 112. configflag - con?gure flag register bit allocation address: content of the base address register + 60h bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved [1] cf reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 73 of 98 nxp semiconductors isp1564 hs usb pci host controller 11.3.8 portsc registers 1, 2 the port status and control (portsc) register is in the auxiliary power well. it is only reset by hardware when the auxiliary power is initially applied or in response to a host controller reset. the initial conditions of a port are: ? no device connected ? port disabled if the port has power control, software cannot change the state of the port until it sets port power bits. software must not attempt to change the state of the port until power is stable on the port; maximum delay is 20 ms from the transition. for bit allocation, see t ab le 114 . [1] the reserved bits must always be written with the reset value. table 113. configflag - con?gure flag register bit description address: content of the base address register + 60h bit symbol description 31 to 1 reserved - 0cf con?gure flag : the host software sets this bit as the last action in its process of con?guring the host controller. this bit controls the default port-routing control logic. 0 port routing control logic default-routes each port to an implementation dependent classic host controller. 1 port routing control logic default-routes all ports to this host controller. table 114. portsc 1, 2 - port status and control 1, 2 register bit allocation address: content of the base address register + 64h + (4 port number - 1) where port number is 1, 2 bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved wkoc_e wkds cnnt_e wkcnnt_ e ptc[3:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] po pp ls[1:0] reserved [1] pr reset 00100000 access r/w r/w r/w r/w r/w r/w r/w r bit 7 6 5 4 3 2 1 0 symbol susp fpr occ oca pedc ped ecsc eccs reset 00000000 access r/w r/w r r r/w r/w r/w r
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 74 of 98 nxp semiconductors isp1564 hs usb pci host controller table 115. portsc 1, 2 - port status and control 1, 2 register bit description address: content of the base address register + 64h + (4 port number - 1) where port number is 1, 2 bit symbol description 31 to 23 reserved - 22 wkoc_e wake on overcurrent enable : default = 0. setting this bit enables the port to be sensitive to overcurrent conditions as wake-up events. [1] 21 wkds cnnt_e wake on disconnect enable : default = 0. setting this bit enables the port to be sensitive to device disconnects as wake-up events. [1] 20 wkcnnt_e wake on connect enable : default = 0. setting this bit enables the port to be sensitive to device connects as wake-up events. [1] 19 to 16 ptc[3:0] port test control : default = 0000b. when this ?eld is logic 0, the port is not operating in test mode. a nonzero value indicates that it is operating in test mode and test mode is indicated by the value. the encoding of test mode bits are: 0000b test mode disabled 0001b test j_state 0010b test k_state 0011b test se0_nak 0100b test packet 0101b test force_enable 0110b to 1111b reserved 15 to 14 reserved - 13 po port owner : default = 1. this bit unconditionally goes to logic 0 when cf (bit 0) in the configflag register makes logic 0 to logic 1 transition. this bit unconditionally goes to logic 1 when the cf bit is logic 0. the system software uses this ?eld to release ownership of the port to a selected host controller, if the attached device is not a high-speed device. software writes logic 1 to this bit, if the attached device is not a high-speed device. logic 1 in this bit means that a companion host controller owns and controls the port. 12 pp port power : the function of this bit depends on the value of ppc (bit 4) in the hcsparams register. if ppc = 0 and pp = 1 the host controller does not have port power control switches. always powered. if ppc = 1 and pp = 1 or 0 the host controller has port power control switches. this bit represents the current setting of the switch: logi c 0 = off, logi c 1 = on. when pp is logic 0, the port is nonfunctional and will not report any status. when an overcurrent condition is detected on a powered port and ppc is logic 1, the pp bit in each affected port may be changed by the host controller from logic 1 to logic 0, removing power from the port. 11 to 10 ls[1:0] line status : this ?eld re?ects the current logical levels of the dp (bit 11) and dm (bit 10) signal lines. these bits are used to detect low-speed usb devices before the port reset and enable sequence. this ?eld is valid only when the port enable bit is logic 0, and the current connect status bit is set to logic 1. 00b se0: not a low-speed device, perform ehci reset 01b k-state: low-speed device, release ownership of the port 10b j-state: not a low-speed device, perform ehci reset 11b unde?ned: not a low-speed device, perform ehci reset if the pp bit is logic 0, this ?eld is unde?ned. 9 reserved -
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 75 of 98 nxp semiconductors isp1564 hs usb pci host controller 8pr port reset : logic 1 means the port is in reset. logic 0 means the port is not in reset. default = 0. when software sets this bit from logic 0, the bus reset sequence as de?ned in universal serial bus speci?cation rev. 2.0 is started. software clears this bit to terminate the bus reset sequence. software must hold this bit at logic 1 until the reset sequence, as speci?ed in universal serial bus speci?cation rev. 2.0 , is completed. remark: when software sets this bit, it must also clear the port enable bit. remark: when software clears this bit, there may be a delay before the bit status changes to logic 0 because it will not read logic 0 until the reset is completed. if the port is in high-speed mode after reset is completed, the host controller will automatically enable this port; it can set the port enable bit. a host controller must terminate the reset and stabilize the state of the port within 2 ms of software changing this bit from logic 1 to logic 0. for example, if the port detects that the attached device is high-speed during a reset, then the host controller must enable the port within 2 ms of software clearing this bit. hch (bit 12) in the usbsts register must be logic 0 before software attempts to use this bit. the host controller may hold port reset asserted when the hch bit is set. [1] 7 susp suspend : default = 0. logic 1 means the port is in the suspend state. logic 0 means the port is not suspended. the ped (port enabled) bit and this bit de?ne the port states as follows: ped = 0 and susp = x port is disabled. ped = 1 and susp = 0 port is enabled. ped = 1 and susp = 1 port is suspended. when in the suspend state, downstream propagation of data is blocked on this port, except for the port reset. if a transaction was in progress when this bit was set, blocking occurs at the end of the current transaction. in the suspend state, the port is sensitive to resume detection. the bit status does not change until the port is suspended and there may be a delay in suspending a port, if there is a transaction currently in progress on usb. attempts to clear this bit are ignored by the host controller. the host controller will unconditionally set this bit to logic 0 when: ? software changes the fpr (force port resume) bit to logic 0. ? software changes the pr (port reset) bit to logic 1. if the host software sets this bit when the port enabled bit is logic 0, the results are unde?ned. [1] 6 fpr force port resume : logic 1 means resume detected or driven on the port. logic 0 means no resume (k-state) detected or driven on the port. default = 0. software sets this bit to drive the resume signaling. the host controller sets this bit if a j-to-k transition is detected, while the port is in the suspend state. when this bit changes to logic 1 because a j-to-k transition is detected, pcd (bit 2) in the usbsts register is also set to logic 1. if software sets this bit to logic 1, the host controller must not set the pcd bit. when the ehci controller owns the port, the resume sequence follows the sequence speci?ed in universal serial bus speci?cation rev. 2.0 . the resume signaling (full-speed k) is driven on the port as long as this bit remains set. software must time the resume and clear this bit after the correct amount of time has elapsed. clearing this bit causes the port to return to high-speed mode, forcing the bus below the port into a high-speed idle. this bit will remain at logic 1, until the port has switched to the high-speed idle. the host controller must complete this transition within 2 ms of software clearing this bit. [1] 5 occ overcurrent change : default = 0. this bit is set to logic 1 when there is a change in overcurrent active. software clears this bit by setting it to logic 1. 4 oca overcurrent active : default = 0. if set to logic 1, this port has an overcurrent condition. if set to logic 0, this port does not have an overcurrent condition. this bit will automatically change from logic 1 to logic 0 when the overcurrent condition is removed. table 115. portsc 1, 2 - port status and control 1, 2 register bit description continued address: content of the base address register + 64h + (4 port number - 1) where port number is 1, 2 bit symbol description
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 76 of 98 nxp semiconductors isp1564 hs usb pci host controller [1] these ?elds read logic 0, if the pp bit is logic 0. 11.4 miscellaneous registers the isp1564 employs mechanisms to improve throughput in usb transfers. in certain system in which pci throughput is low, however, these mechanisms may fail. the system tuning register provide a mean to disable these mechanisms using software. for bit allocation of the register, see t ab le 116 . 3 pedc port enable/disable change : logic 1 means the port enabled or disabled status has changed. logic 0 means no change. default = 0. for the root hub, this bit is set only when a port is disabled because of the appropriate conditions existing at the eof2 point. for de?nition of port error, refer to chapter 11 of universal serial bus speci?cation rev. 2.0 . software clears this bit by setting it. [1] 2 ped port enabled/disabled : logic 1 means enable. logic 0 means disable. default = 0. ports can only be enabled by the host controller as a part of the reset and enable sequence. software cannot enable a port by writing logic 1 to this ?eld. the host controller will only set this bit when the reset sequence determines that the attached device is a high-speed device. ports can be disabled by either a fault condition or by host software. the bit status does not change until the port state has changed. there may be a delay in disabling or enabling a port because of other host controller and bus events. when the port is disabled, downstream propagation of data is blocked on this port, except for reset. [1] 1 ecsc connect status change : logic 1 means change in eccs. logic 0 means no change. default = 0. this bit indicates a change has occurred in the eccs of the port. the host controller sets this bit for all changes to the port device connect status, even if the system software has not cleared an existing connect status change. for example, the insertion status changes two times before the system software has cleared the changed condition, hub hardware will be setting an already-set bit, that is, the bit will remain set. software clears this bit by writing logic 1 to it. [1] 0 eccs current connect status : logic 1 indicates a device is present on the port. logic 0 indicates no device is present. default = 0. this value re?ects the current state of the port and may not directly correspond to the event that caused the ecsc bit to be set. [1] table 115. portsc 1, 2 - port status and control 1, 2 register bit description continued address: content of the base address register + 64h + (4 port number - 1) where port number is 1, 2 bit symbol description table 116. system tuning register bit allocation address: content of the base address register + 6ch bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 77 of 98 nxp semiconductors isp1564 hs usb pci host controller [1] the reserved bits must always be written with the reset value. bit 7 6 5 4 3 2 1 0 symbol reserved [1] rbd wmd reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 117. system tuning register bit description address: content of the base address register + 6ch bit symbol description 31 to 2 - reserved 1 rbd ring buffering disable : default = sys_tune pin. to enable the ring buffering, clear the rbd bit to logic 0. to disable the ring buffering, set the rbd bit to logic 1. the isp1564 employs the ring buffering mechanism to improve throughput in usb in transfers. this mechanism allows the start of an in packet transfer immediately after a previous in packet is received. in some systems, with congested pci bus, data overrun conditions may occur when the ring buffering is enabled. software can set this bit to disable the ring buffering. see t ab le 118 . remark: if the sys_tune pin is connected to v cc , the rbd bit will always be logic 1. 0 wmd watermark disable : default = sys_tune pin. to enable the watermark feature, clear the wmd bit to logic 0; to disable the watermark feature, set wmd to logic 1. the isp1564 employs a watermark mechanism to improve throughput in usb out transfers. this mechanism starts usb transfer over the usb bus when data fetched from the host system reaches the watermark level (191 bytes, 255 bytes, 383 bytes, 511 bytes, 639 bytes and 767 bytes) just before the full packet size. for example, the isp1564 will start transferring an out packet of size 1024 bytes over the usb bus when 767 bytes has been fetched from the host system. in some systems, with congested pci bus, data underrun conditions may occur when the watermark is enabled. software can set this bit to disable the watermark feature. see t ab le 119 . remark: if the sys_tune pin is connected to v cc , the wmd bit will always be logic 1. table 118. ring buffering disable sys_tune pin rbd bit ring buffering low 0 enable low 1 disable high x disable table 119. watermark disable sys_tune pin wmd bit watermark low 0 enable low 1 disable high x disable
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 78 of 98 nxp semiconductors isp1564 hs usb pci host controller 12. limiting values [1] equivalent to discharging a 100 pf capacitor through a 1.5 k w resistor (human body model jesd22-a114c). 13. recommended operating conditions table 120. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cc(io) io supply voltage - 0.5 +4.6 v v cc(reg) regulator supply voltage - 0.5 +4.6 v v cc(io)aux auxiliary input/output supply voltage - 0.5 +4.6 v v cc(aux) auxiliary supply voltage - 0.5 +4.6 v v cca(aux) auxiliary analog supply voltage - 0.5 +4.6 v i lu latch-up current v i < 0 v or v i >v cc(io) - 100 ma v esd electrostatic discharge voltage all pins (i li <1 m a) [1] - 2+2 kv t stg storage temperature - 40 +125 c table 121. recommended operating conditions symbol parameter conditions min typ max unit v cc(io) io supply voltage 3.0 3.3 3.6 v v cc(reg) regulator supply voltage 3.0 3.3 3.6 v v cc(io)aux auxiliary input/output supply voltage 3.0 3.3 3.6 v v cc(aux) auxiliary supply voltage 3.0 3.3 3.6 v v cca(aux) auxiliary analog supply voltage 3.0 3.3 3.6 v v i input voltage 0 - v cc(io) v v i(xtal1) input voltage on pin xtal1 0 - 1.95 v t amb ambient temperature - 40 - +85 c
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 79 of 98 nxp semiconductors isp1564 hs usb pci host controller 14. static characteristics table 122. static characteristics: i 2 c-bus interface (sda and scl) v cc(io) = 3.0 v to 3.6 v; t amb = - 40 cto+85 c; unless otherwise speci?ed. typical values are at v cc(io) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v ih high-level input voltage 0.7 v cc(io) -- v v il low-level input voltage - - 0.3 v cc(io) v v hys hysteresis voltage 0.15 - - v v ol low-level output voltage i ol = 3 ma - - 0.4 v i cc(susp) suspend supply current - 1 - m a table 123. static characteristics: digital pins (pwe1_n, oc1_n, pwe2_n and oc2_n) v cc(io) = 3.0 v to 3.6 v; t amb = - 40 cto+85 c; unless otherwise speci?ed. typical values are at v cc(io) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v v hys hysteresis voltage 0.4 - - v v ol low-level output voltage i ol = 3 ma - - 0.4 v v oh high-level output voltage 2.4 - - v table 124. static characteristics: pci interface block v cc(io) = 3.0 v to 3.6 v; t amb = - 40 cto+85 c; unless otherwise speci?ed. typical values are at v cc(io) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v ih high-level input voltage 0.5 v cc(io) -- v v il low-level input voltage - - 0.3 v cc(io) v v ipu input pull-up voltage 2.1 - - v i li input leakage current 0 v < v i isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 80 of 98 nxp semiconductors isp1564 hs usb pci host controller [1] high-speed termination resistor disabled, pull-up resistor connected. only during reset, when both the hub and the device ar e capable of high-speed operation. v hsdi high-speed differential input sensitivity | v dp - v dm | 300 - - mv v hscm high-speed data signaling common mode voltage range (guideline for receiver) - 50 - +500 mv output levels for high-speed v hsoi high-speed idle level voltage - 10 - +10 mv v hsoh high-speed data signaling high-level voltage 360 - 440 mv v hsol high-speed data signaling low-level voltage - 10 - +10 mv v chirpj chirp j level (differential voltage) 700 [1] - 1100 mv v chirpk chirp k level (differential voltage) - 900 [1] - - 500 mv input levels for full-speed and low-speed v ih high-level input voltage drive 2.0 - - v v ihz high-level input voltage (?oating) for low-/full-speed 2.7 - 3.6 v v il low-level input voltage - - 0.8 v v di differential input sensitivity voltage | v dp - v dm | 0.2 - - v v cm differential common mode voltage range 0.8 - 2.5 v output levels for full-speed and low-speed v oh high-level output voltage 2.8 - 3.6 v v ol low-level output voltage 0 - 0.3 v v ose1 se1 output voltage 0.8 - - v v crs output signal crossover voltage 1.3 - 2.0 v leakage current i lz off-state leakage current - 1- +1 m a capacitance c in input capacitance pin to gnd - - 5 pf table 125. static characteristics: usb interface block (pins dm1 to dm2 and dp1 to dp2) continued v cca(aux) = 3.0 v to 3.6 v; t amb = - 40 cto+85 c; unless otherwise speci?ed. typical values are at v cca(aux) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 81 of 98 nxp semiconductors isp1564 hs usb pci host controller [1] when one or two full-speed or low-speed power devices are connected, the current consumption is comparable to the current consumption when no high-speed devices are connected. there is a difference of approximately 1 ma. [1] s1 represents the system state that will determine the b1 and d1 states. for details, refer to pci bus power management interface speci?cation rev. 1.1 . [2] s3 represents the system state that will determine the b3 and d3 states. for details, refer to pci bus power management interface speci?cation rev. 1.1 . table 126. current consumption v cc(io)aux = 3.0 v to 3.6 v; v cc(aux) = 3.0 v to 3.6 v; v cca(aux) = 3.0 v to 3.6 v; v cc(io) = 3.0 v to 3.6 v; v cc(reg) = 3.0 v to 3.6 v; t amb = - 40 cto+85 c; unless otherwise speci?ed. typical values are at v cc(io)aux = 3.3 v; v cc(aux) = 3.3 v; v cca(aux) = 3.3 v; v cc(io) = 3.3 v; v cc(reg) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. cumulative current conditions typ unit total current on pins v cc(io)aux plus v cc(aux) plus v cca(aux) plus v cc(io) plus v cc(reg) no device connected to the isp1564 [1] 27 ma one high-speed device connected to the isp1564 54 ma two high-speed devices connected to the isp1564 75 ma auxiliary current on pins v cc(io)aux plus v cc(aux) plus v cca(aux) no device connected to the isp1564 [1] 19 ma one high-speed device connected to the isp1564 43 ma two high-speed devices connected to the isp1564 63 ma on pins v cc(io) plus v cc(reg) no device connected to the isp1564 [1] 8ma one high-speed device connected to the isp1564 11 ma two high-speed devices connected to the isp1564 12 ma table 127. current consumption: s1 and s3 v cc(io)aux = 3.0 v to 3.6 v; v cc(aux) = 3.0 v to 3.6 v; v cca(aux) = 3.0 v to 3.6 v; v cc(io) = 3.0 v to 3.6 v; v cc(reg) = 3.0 v to 3.6 v; t amb = - 40 cto+85 c; unless otherwise speci?ed. typical values are at v cc(io)aux = 3.3 v; v cc(aux) = 3.3 v; v cca(aux) = 3.3 v; v cc(io) = 3.3 v; v cc(reg) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. current consumption typ unit s1 [1] 2.10 ma s3 [2] 160 m a
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 82 of 98 nxp semiconductors isp1564 hs usb pci host controller 15. dynamic characteristics [1] suggested values for external capacitors are 22 pf to 27 pf. [1] the capacitive load for each bus line (c b ) is speci?ed in pf. to meet the speci?cation for v ol and the maximum rise time (300 ns), use an external pull-up resistor with r up(max) = 850 / c b k w and r up(min) =(v cc(io) - 0.4)/3k w . [1] standard load is 10 pf together with a pull-up and pull-down resistor of 10 k w . table 128. dynamic characteristics: system clock timing v cc(io) = 3.0 v to 3.6 v; t amb = - 40 cto+85 c; unless otherwise speci?ed. typical values are at v cc(io) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit pci clock f clk(pci) pci clock frequency 31 - 33 mhz crystal speci?cation f clk clock frequency [1] - 12 - mhz r s series resistance - - 100 w c l load capacitance - 18 - pf t jit(i)(xtal1)rms rms input jitter on pin xtal1 - - 200 ps d f/f frequency stability on pin xtal1 - - 50 ppm external clock speci?cation f i(xtal1) input frequency on pin xtal1 - 12 - mhz t jit(i)(xtal1)rms rms input jitter on pin xtal1 - - 200 ps d f i(xtal1) input frequency tolerance on pin xtal1 --50ppm d i(xtal1) input duty cycle on pin xtal1 45 50 55 % table 129. dynamic characteristics: i 2 c-bus interface (sda and scl) v cc(io) = 3.0 v to 3.6 v; t amb = - 40 cto+85 c; unless otherwise speci?ed. typical values are at v cc(io) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit t f(o) output fall time v ih to v il ; 10 pf < c b < 400 pf [1] - 0 250 ns table 130. dynamic characteristics: pci interface block v cc(io) = 3.0 v to 3.6 v; t amb = - 40 cto+85 c; unless otherwise speci?ed. typical values are at v cc(io) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit sr slew rate standard load [1] 1 - 4 v/ns table 131. dynamic characteristics: high-speed source electrical characteristics v cca(aux) = 3.0 v to 3.6 v; t amb = - 40 cto+85 c; unless otherwise speci?ed. typical values are at v cca(aux) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit driver characteristics t hsr rise time (10 % to 90 %) 500 - - ps t hsf fall time (10 % to 90 %) 500 - - ps
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 83 of 98 nxp semiconductors isp1564 hs usb pci host controller z hsdrv driver output impedance (which also serves as high-speed termination) includes the r s resistor 40.5 45 49.5 w clock timing t hsdrat high-speed data rate 479.76 - 480.24 mbit/s t hsfram microframe interval 124.9375 - 125.0625 m s t hsrfi consecutive microframe interval difference 1 - four high-speed bit times ns table 131. dynamic characteristics: high-speed source electrical characteristics continued v cca(aux) = 3.0 v to 3.6 v; t amb = - 40 cto+85 c; unless otherwise speci?ed. typical values are at v cca(aux) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit table 132. dynamic characteristics: full-speed source electrical characteristics v cca(aux) = 3.0 v to 3.6 v; t amb = - 40 cto+85 c; unless otherwise speci?ed. typical values are at v cca(aux) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit driver characteristics t fr rise time c l =50pf;10%to90% of | v oh - v ol | 4 - 20 ns t ff fall time c l =50pf;90%to10% of | v oh - v ol | 4 - 20 ns t frfm differential rise and fall time matching 90 - 111.1 % data timing; see figure 8 t fdeop source jitter for differential transition to se0 transition full-speed timing - 2 - +5 ns t feopt source se0 interval of eop 160 - 175 ns t feopr receiver se0 interval of eop 82 - - ns t ldeop upstream facing port source jitter for differential transition to se0 transition low-speed timing - 40 - +100 ns t leopt source se0 interval of eop 1.25 - 1.5 m s t leopr receiver se0 interval of eop 670 - - ns t fst width of se0 interval during differential transition - - 14 ns table 133. dynamic characteristics: low-speed source electrical characteristics v cca(aux) = 3.0 v to 3.6 v; t amb = - 40 cto+85 c; unless otherwise speci?ed. typical values are at v cca(aux) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit driver characteristics t lr transition time: rise time 75 - 300 ns t lf transition time: fall time 75 - 300 ns t lrfm rise and fall time matching 90 - 125 %
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 84 of 98 nxp semiconductors isp1564 hs usb pci host controller 15.1 timing [1] req# and gnt# are point-to-point signals. gnt# has a set up of 10 ns; req# has a set up of 12 ns. all others are bus signals. t period is the bit duration corresponding to the usb data rate. fig 8. usb source differential data-to-eop transition skew and eop width 004aaa929 t period differential data lines crossover point differential data to se0/eop skew n t period + t fdeop n t period + t ldeop source eop width: t feopt , t leopt receiver eop width: t feopr , t leopr crossover point extended +3.3 v 0 v table 134. pci clock and i/o timing v cc(io) = 3.0 v to 3.6 v; t amb = - 40 cto+85 c; unless otherwise speci?ed. typical values are at v cc(io) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit pci clock timing; see figure 9 t cyc clk cycle time 30 - 32 ns t high clk high time 11 - - ns t low clk low time 11 - - ns sr clk clk slew rate 1 - 4 v/ns sr rst# rst# slew rate 50 - - mv/ns pci input timing; see figure 10 t su input set-up time to clk - bused signals 7 - - ns t su(ptp) input set-up time to clk - point-to-point [1] 10--ns t h input hold time from clk 0 - - ns pci output timing; see figure 11 t val clk to signal valid delay time - bused signals 2 - 11 ns t val(ptp) clk to signal valid delay time - point-to-point [1] 2 - 12 ns t dzh ?oat to active high delay time 2 - - ns t dhz active high to ?oat delay time - - 28 ns pci reset timing t rst reset active time after power stable 1 - - ms t rst-clk reset active time after clk stable 100 - - m s
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 85 of 98 nxp semiconductors isp1564 hs usb pci host controller fig 9. pci clock fig 10. pci input timing minimum value 0.4v cc(io) t cyc 004aaa923 t high t low 0.6v cc(io) 0.5v cc(io) 0.4v cc(io) 0.3v cc(io) 0.2v cc(io) 004aaa924 0.6v cc(io) 0.2v cc(io) 0.6v cc(io) 0.2v cc(io) t su ; t su(ptp) t h 0.4v cc(io) 0.4v cc(io) inputs valid clk input delay fig 11. pci output timing 004aaa925 0.6v cc(io) 0.2v cc(io) 0.4v cc(io) 0.615v cc(io) (falling edge) 0.285v cc(io) (rising edge) output output delay clk t dhz t dzh t val ; t val(ptp)
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 86 of 98 nxp semiconductors isp1564 hs usb pci host controller 16. package outline fig 12. package outline sot407-1 (lqfp100) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.25 15.75 1.15 0.85 7 0 o o 0.08 0.08 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot407-1 136e20 ms-026 00-02-01 03-02-20 d (1) (1) (1) 14.1 13.9 h d 16.25 15.75 e z 1.15 0.85 d b p e q e a 1 a l p detail x l (a ) 3 b 25 c d h b p e h a 2 v m b d z d a z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 5 10 mm scale lqfp100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm sot407-1
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 87 of 98 nxp semiconductors isp1564 hs usb pci host controller fig 13. package outline sot926-1 (tfbga100) references outline version european projection issue date iec jedec jeita sot926-1 - - - - - - - - - sot926-1 05-12-09 05-12-22 unit a max mm 1.2 0.4 0.3 0.8 0.65 0.5 0.4 9.1 8.9 9.1 8.9 a 1 dimensions (mm are the original dimensions) tfbga100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm a 2 b d e e 2 7.2 e 0.8 e 1 7.2 v 0.15 w 0.05 y 0.08 y 1 0.1 0 2.5 5 mm scale b e 2 e 1 e e 1/2 e 1/2 e a c b ? v m c ? w m ball a1 index area a b c d e f h k g j 246810 13579 ball a1 index area b a e d c y c y 1 x detail x a a 1 a 2
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 88 of 98 nxp semiconductors isp1564 hs usb pci host controller 17. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 17.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 17.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 17.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 89 of 98 nxp semiconductors isp1564 hs usb pci host controller 17.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 14 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 135 and 136 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 14 . table 135. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 136. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 90 of 98 nxp semiconductors isp1564 hs usb pci host controller for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 18. abbreviations msl: moisture sensitivity level fig 14. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 137. abbreviations acronym description cmos complementary metal-oxide semiconductor did device id dword double word ed endpoint descriptor eeprom electrically erasable programmable read-only memory ehci enhanced host controller interface emi electromagnetic interference eof end-of-frame eop end-of-packet esd electrostatic discharge esr effective series resistance hc host controller hcca host controller communication area hcd host controller driver hci host controller interface hs high-speed ls low-speed msb most signi?cant bit ohci open host controller interface
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 91 of 98 nxp semiconductors isp1564 hs usb pci host controller 19. references [1] universal serial bus speci?cation rev. 2.0 [2] enhanced host controller interface speci?cation for universal serial bus rev. 1.0 [3] open host controller interface speci?cation for usb rev. 1.0a [4] pci local bus speci?cation rev. 2.2 [5] pci bus power management interface speci?cation rev. 1.1 [6] the i 2 c-bus speci?cation version 2.1 20. revision history pci peripheral component interconnect pci-sig pci-special interest group pll phase-locked loop pmc power management capabilities pme power management event por power-on reset post power-on system test qh queue head smi system management interrupt sof start-of-frame stb set-top box td transfer descriptor usb universal serial bus vid vendor id table 137. abbreviations continued acronym description table 138. revision history document id release date data sheet status change notice supersedes isp1564_2 20081113 product data sheet - isp1564_1 modi?cations: ? t ab le 2 pin descr iption : updated description of pin sys_tune. ? updated figure 4 p o w er-on reset . ? section 8.2.1.8 latency timer register : added a remark. ? t ab le 48 usb host controller registers : added t ab le note 2 . ? t ab le 110 asynclist addr - current asynchronous list address register bit allocation and t ab le 111 asynclist addr - current asynchronous list address register bit descr iption : changed lpl[19:0] to lpl[26:0]. ? t ab le 128 dynamic char acter istics: system cloc k timing : removed t w(reset_n) . isp1564_1 20061204 product data sheet - -
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 92 of 98 nxp semiconductors isp1564 hs usb pci host controller 21. legal information 21.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 21.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 21.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 21.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 22. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 93 of 98 continued >> nxp semiconductors isp1564 hs usb pci host controller 23. tables table 1. ordering information . . . . . . . . . . . . . . . . . . . . .2 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 table 3. pci con?guration space registers of ohci and ehci . . . . . . . . . . . . . . . . . . . . . . . .14 table 4. vid - vendor id register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .15 table 5. did - device id register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .15 table 6. command register (address 04h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 7. command register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .16 table 8. status register (address 06h) bit allocation . . .17 table 9. status register (address 06h) bit description . .17 table 10. revid - revision id register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .18 table 11. class code register (address 09h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 12. class code register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .19 table 13. cls - cacheline size register (address 0ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .19 table 14. lt - latency timer register (address 0dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .19 table 15. header type register (address 0eh) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 16. header type register (address 0eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .20 table 17. bar0 - base address register 0 (address 10h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .20 table 18. svid - subsystem vendor id register (address 2ch) bit description . . . . . . . . . . . . . .20 table 19. sid - subsystem id register (address 2eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .21 table 20. cp - capabilities pointer register (address 34h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .21 table 21. il - interrupt line register (address 3ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .21 table 22. ip - interrupt pin register (address 3dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .21 table 23. min_gnt - minimum grant register (address 3eh) bit description . . . . . . . . . . . . . .22 table 24. max_lat - maximum latency register (address 3fh) bit description . . . . . . . . . . . . . .22 table 25. ehci-speci?c pci registers . . . . . . . . . . . . . . .23 table 26. sbrn - serial bus release number register (address 60h) bit description . . . . . . . . . . . . . .23 table 27. fladj - frame length adjustment register (address 61h) bit allocation . . . . . . . . . . . . . . . 23 table 28. fladj - frame length adjustment register (address 61h) bit description . . . . . . . . . . . . . . 23 table 29. fladj value vs. sof cycle time . . . . . . . . . . . 24 table 30. portwakecap - port wake capability register (address 62h) bit description . . . . . . . 24 table 31. power management registers . . . . . . . . . . . . . 24 table 32. cap_id - capability identi?er register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 33. next_item_ptr - next item pointer register bit description . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 34. pmc - power management capabilities register bit allocation . . . . . . . . . . . . . . . . . . . . 25 table 35. pmc - power management capabilities register bit description . . . . . . . . . . . . . . . . . . . 26 table 36. pmcsr - power management control/ status register bit allocation . . . . . . . . . . . . . . 27 table 37. pmcsr - power management control/ status register bit description . . . . . . . . . . . . . 27 table 38. pmcsr_bse - pmcsr pci-to-pci bridge support extensions register bit allocation . . . . 28 table 39. pmcsr_bse - pmcsr pci-to-pci bridge support extensions register bit description . . . 28 table 40. pci bus power and clock control . . . . . . . . . . . 29 table 41. data register bit description . . . . . . . . . . . . . . 29 table 42. vpd speci?c registers . . . . . . . . . . . . . . . . . . . 29 table 43. vpd_cap_id - vital product data capability identi?er register bit description . . . 29 table 44. vpd_next_item_ptr - vital product data next item pointer register bit description . . . . 30 table 45. vpd_addr - vital product data address register bit allocation . . . . . . . . . . . . . . . . . . . . 30 table 46. vpd_addr - vital product data address register bit description . . . . . . . . . . . . . . . . . . . 30 table 47. vpd_data - vital product data data bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 48. usb host controller registers . . . . . . . . . . . . . 34 table 49. hcrevision - host controller revision register bit allocation . . . . . . . . . . . . . . . . . . . . 35 table 50. hcrevision - host controller revision register bit description . . . . . . . . . . . . . . . . . . . 36 table 51. hccontrol - host controller control register bit allocation . . . . . . . . . . . . . . . . . . . . 36 table 52. hccontrol - host controller control register bit description . . . . . . . . . . . . . . . . . . . 37 table 53. hccommandstatus - host controller command status register bit allocation . . . . . 38 table 54. hccommandstatus - host controller
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 94 of 98 continued >> nxp semiconductors isp1564 hs usb pci host controller command status register bit description . . . . .39 table 55. hcinterruptstatus - host controller interrupt status register bit allocation . . . . . . .40 table 56. hcinterruptstatus - host controller interrupt status register bit description . . . . . .40 table 57. hcinterruptenable - host controller interrupt enable register bit allocation . . . . . . .41 table 58. hcinterruptenable - host controller interrupt enable register bit description . . . . . .42 table 59. hcinterruptdisable - host controller interrupt disable register bit allocation . . . . . .43 table 60. hcinterruptdisable - host controller interrupt disable register bit description . . . . .43 table 61. hchcca - host controller communication area register bit allocation . . . . . . . . . . . . . . . .44 table 62. hchcca - host controller communication area register bit description . . . . . . . . . . . . . . .45 table 63. hcperiodcurrented - host controller period current endpoint descriptor register bit allocation . . . . . . . . . . . . . . . . . . . .45 table 64. hcperiodcurrented - host controller period current endpoint descriptor register bit description . . . . . . . . . . . . . . . . . . .45 table 65. hccontrolheaded - host controller control head endpoint descriptor register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 66. hccontrolheaded - host controller control head endpoint descriptor register bit description . . . . . . . . . . . . . . . . . . . . . . . . .46 table 67. hccontrolcurrented - host controller control current endpoint descriptor register bit allocation . . . . . . . . . . . . . . . . . . . .46 table 68. hccontrolcurrented - host controller control current endpoint descriptor register bit description . . . . . . . . . . . . . . . . . . .47 table 69. hcbulkheaded - host controller bulk head endpoint descriptor register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 70. hcbulkheaded - host controller bulk head endpoint descriptor register bit description . . . . . . . . . . . . . . . . . . . . . . . . .47 table 71. hcbulkcurrented - host controller bulk current endpoint descriptor register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 72. hcbulkcurrented - host controller bulk current endpoint descriptor register bit description . . . . . . . . . . . . . . . . . . . . . . . . .48 table 73. hcdonehead - host controller done head register bit allocation . . . . . . . . . . . . . . . . . . . .49 table 74. hcdonehead - host controller done head register bit description . . . . . . . . . . . . . . . . . . .49 table 75. hcfminterval - host controller frame interval register bit allocation . . . . . . . . . . . . . 49 table 76. hcfminterval - host controller frame interval register bit description . . . . . . . . . . . . 50 table 77. hcfmremaining - host controller frame remaining register bit allocation . . . . . . . . . . . 50 table 78. hcfmremaining - host controller frame remaining register bit description . . . . . . . . . . 51 table 79. hcfmnumber - host controller frame number register bit allocation . . . . . . . . . . . . . 51 table 80. hcfmnumber - host controller frame number register bit description . . . . . . . . . . . . 52 table 81. hcperiodicstart - host controller periodic start register bit allocation . . . . . . . . . . . . . . . 52 table 82. hcperiodicstart - host controller periodic start register bit description . . . . . . . . . . . . . . 53 table 83. hclsthreshold - host controller low-speed threshold register bit allocation . . 53 table 84. hclsthreshold - host controller low-speed threshold register bit description . 53 table 85. hcrhdescriptora - host controller root hub descriptor a register bit allocation . . . . . . 54 table 86. hcrhdescriptora - host controller root hub descriptor a register bit description . . . . . 54 table 87. hcrhdescriptorb - host controller root hub descriptor b register bit allocation . . . . . . 55 table 88. hcrhdescriptorb - host controller root hub descriptor b register bit description . . . . . 56 table 89. hcrhstatus - host controller root hub status register bit allocation . . . . . . . . . . . . . . 56 table 90. hcrhstatus - host controller root hub status register bit description . . . . . . . . . . . . . 57 table 91. hcrhportstatus[2:1] - host controller root hub port status[2:1] register bit allocation . . . 58 table 92. hcrhportstatus[2:1] - host controller root hub port status[2:1] register bit description . . 58 table 93. caplength/hciversion - capability length/host controller interface version number register bit allocation . . . . . . . . . . . . . 61 table 94. caplength/hciversion - capability length/host controller interface version number register bit description . . . . . . . . . . . . 61 table 95. hcsparams - host controller structural parameters register bit allocation . . . . . . . . . . 61 table 96. hcsparams - host controller structural parameters register bit description . . . . . . . . . 62 table 97. hccparams - host controller capability parameters register bit allocation . . . . . . . . . . 63 table 98. hccparams - host controller capability parameters register bit description . . . . . . . . . 63 table 99. usbcmd - usb command register
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 95 of 98 nxp semiconductors isp1564 hs usb pci host controller bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .64 table 100.usbcmd - usb command register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 table 101.usbsts - usb status register bit allocation . .66 table 102.usbsts - usb status register bit description 67 table 103.usbintr - usb interrupt enable register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .68 table 104.usbintr - usb interrupt enable register bit description . . . . . . . . . . . . . . . . . . . . . . . . .69 table 105.frindex - frame index register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .69 table 106.frindex - frame index register bit description . . . . . . . . . . . . . . . . . . . . . . . . .70 table 107.n based value of fls[1:0] . . . . . . . . . . . . . . . .70 table 108.periodiclistbase - periodic frame list base address register bit allocation . . . . . . . .71 table 109.periodiclistbase - periodic frame list base address register bit description . . . . . . .71 table 110.asynclistaddr - current asynchronous list address register bit allocation . . . . . . . . . .71 table 111.asynclistaddr - current asynchronous list address register bit description . . . . . . . . .72 table 112.configflag - con?gure flag register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .72 table 113.configflag - con?gure flag register bit description . . . . . . . . . . . . . . . . . . . . . . . . .73 table 114.portsc 1, 2 - port status and control 1, 2 register bit allocation . . . . . . . . . . . . . . . . . . . .73 table 115.portsc 1, 2 - port status and control 1, 2 register bit description . . . . . . . . . . . . . . . . . . .74 table 116.system tuning register bit allocation . . . . . . . .76 table 117.system tuning register bit description . . . . . . .77 table 118.ring buffering disable . . . . . . . . . . . . . . . . . . .77 table 119.watermark disable . . . . . . . . . . . . . . . . . . . . . .77 table 120.limiting values . . . . . . . . . . . . . . . . . . . . . . . . .78 table 121.recommended operating conditions . . . . . . . .78 table 122.static characteristics: i 2 c-bus interface (sda and scl) . . . . . . . . . . . . . . . . . . . . . . . .79 table 123.static characteristics: digital pins (pwe1_n, oc1_n, pwe2_n and oc2_n) . . .79 table 124.static characteristics: pci interface block . . . .79 table 125.static characteristics: usb interface block (pins dm1 to dm2 and dp1 to dp2) . . . . . . . .79 table 126.current consumption . . . . . . . . . . . . . . . . . . . .81 table 127.current consumption: s1 and s3 . . . . . . . . . . .81 table 128.dynamic characteristics: system clock timing .82 table 129.dynamic characteristics: i 2 c-bus interface (sda and scl) . . . . . . . . . . . . . . . . . . . . . . . .82 table 130.dynamic characteristics: pci interface block . .82 table 131.dynamic characteristics: high-speed source electrical characteristics . . . . . . . . . . . . . . . . .82 table 132.dynamic characteristics: full-speed source electrical characteristics . . . . . . . . . . . . . . . . .83 table 133.dynamic characteristics: low-speed source electrical characteristics . . . . . . . . . . . . . . . . .83 table 134.pci clock and i/o timing . . . . . . . . . . . . . . . . .84 table 135.snpb eutectic process (from j-std-020c) . . .89 table 136.lead-free process (from j-std-020c) . . . . . .89 table 137.abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 138.revision history . . . . . . . . . . . . . . . . . . . . . . . . 91
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 96 of 98 nxp semiconductors isp1564 hs usb pci host controller 24. figures fig 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 fig 2. pin con?guration lqfp100 (top view) . . . . . . . . . .4 fig 3. pin con?guration tfbga100 (top view). . . . . . . . .5 fig 4. power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . .11 fig 5. power supply connection . . . . . . . . . . . . . . . . . . .12 fig 6. eeprom connection diagram . . . . . . . . . . . . . . .31 fig 7. information loading from eeprom . . . . . . . . . . .32 fig 8. usb source differential data-to-eop transition skew and eop width . . . . . . . . . . . . . . . . . . . . . .84 fig 9. pci clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 fig 10. pci input timing . . . . . . . . . . . . . . . . . . . . . . . . . .85 fig 11. pci output timing . . . . . . . . . . . . . . . . . . . . . . . . .85 fig 12. package outline sot407-1 (lqfp100) . . . . . . . .86 fig 13. package outline sot926-1 (tfbga100). . . . . . .87 fig 14. temperature pro?les for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
isp1564_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 13 november 2008 97 of 98 continued >> nxp semiconductors isp1564 hs usb pci host controller 25. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . 10 7.1 ohci host controller . . . . . . . . . . . . . . . . . . . . 10 7.2 ehci host controller . . . . . . . . . . . . . . . . . . . . 10 7.3 dynamic port-routing logic . . . . . . . . . . . . . . . 10 7.4 hi-speed usb analog transceivers . . . . . . . . 10 7.5 power management . . . . . . . . . . . . . . . . . . . . 10 7.6 phase-locked loop (pll) . . . . . . . . . . . . . . . 10 7.7 power-on reset (por) . . . . . . . . . . . . . . . . . 11 7.8 power supply . . . . . . . . . . . . . . . . . . . . . . . . . 11 8 pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.1 pci interface . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.1.1 pci con?guration space . . . . . . . . . . . . . . . . . 13 8.1.2 pci initiator and target . . . . . . . . . . . . . . . . . . 13 8.2 pci con?guration registers . . . . . . . . . . . . . . . 13 8.2.1 pci con?guration header registers . . . . . . . . . 14 8.2.1.1 vendor id register. . . . . . . . . . . . . . . . . . . . . . 15 8.2.1.2 device id register . . . . . . . . . . . . . . . . . . . . . . 15 8.2.1.3 command register . . . . . . . . . . . . . . . . . . . . . 15 8.2.1.4 status register. . . . . . . . . . . . . . . . . . . . . . . . . 17 8.2.1.5 revision id register . . . . . . . . . . . . . . . . . . . . 18 8.2.1.6 class code register . . . . . . . . . . . . . . . . . . . . 18 8.2.1.7 cacheline size register . . . . . . . . . . . . . . . . . 19 8.2.1.8 latency timer register . . . . . . . . . . . . . . . . . . 19 8.2.1.9 header type register . . . . . . . . . . . . . . . . . . . 19 8.2.1.10 base address register 0 . . . . . . . . . . . . . . . . . 20 8.2.1.11 subsystem vendor id register . . . . . . . . . . . . 20 8.2.1.12 subsystem id register . . . . . . . . . . . . . . . . . . 20 8.2.1.13 capabilities pointer register . . . . . . . . . . . . . . 21 8.2.1.14 interrupt line register . . . . . . . . . . . . . . . . . . . 21 8.2.1.15 interrupt pin register . . . . . . . . . . . . . . . . . . . . 21 8.2.1.16 min_gnt and max_lat registers . . . . . . . . . . . 22 8.2.1.17 trdy timeout register . . . . . . . . . . . . . . . . . . 22 8.2.1.18 retry timeout register . . . . . . . . . . . . . . . . . . 22 8.2.2 enhanced host controller-speci?c pci registers . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.2.2.1 sbrn register. . . . . . . . . . . . . . . . . . . . . . . . . 23 8.2.2.2 fladj register . . . . . . . . . . . . . . . . . . . . . . . . 23 8.2.2.3 portwakecap register . . . . . . . . . . . . . . . . 24 8.2.3 power management registers. . . . . . . . . . . . . 24 8.2.3.1 cap_id register . . . . . . . . . . . . . . . . . . . . . . . 24 8.2.3.2 next_item_ptr register . . . . . . . . . . . . . . . . . . 25 8.2.3.3 pmc register . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.2.3.4 pmcsr register . . . . . . . . . . . . . . . . . . . . . . . 27 8.2.3.5 pmcsr_bse register . . . . . . . . . . . . . . . . . . 28 8.2.3.6 data register. . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2.4 vpd register. . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2.4.1 vpd_cap_id register. . . . . . . . . . . . . . . . . . . 29 8.2.4.2 vpd_next_item_ptr register . . . . . . . . . . . . . 29 8.2.4.3 vpd_addr register . . . . . . . . . . . . . . . . . . . . . 30 8.2.4.4 vpd_data register . . . . . . . . . . . . . . . . . . . . . 30 9i 2 c-bus interface . . . . . . . . . . . . . . . . . . . . . . . 31 9.1 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.2 hardware connections . . . . . . . . . . . . . . . . . . 31 9.3 information loading from eeprom . . . . . . . . 32 9.4 eeprom programming . . . . . . . . . . . . . . . . . 32 10 power management. . . . . . . . . . . . . . . . . . . . . 32 10.1 pci bus power states . . . . . . . . . . . . . . . . . . . 32 10.2 usb bus states . . . . . . . . . . . . . . . . . . . . . . . 33 11 usb host controller registers. . . . . . . . . . . . . 34 11.1 ohci usb host controller operational registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.1.1 hcrevision register . . . . . . . . . . . . . . . . . . . . 35 11.1.2 hccontrol register . . . . . . . . . . . . . . . . . . . . . 36 11.1.3 hccommandstatus register . . . . . . . . . . . . . . 38 11.1.4 hcinterruptstatus register . . . . . . . . . . . . . . . 40 11.1.5 hcinterruptenable register . . . . . . . . . . . . . . . 41 11.1.6 hcinterruptdisable register . . . . . . . . . . . . . . 42 11.1.7 hchcca register . . . . . . . . . . . . . . . . . . . . . . 44 11.1.8 hcperiodcurrented register. . . . . . . . . . . . . . 45 11.1.9 hccontrolheaded register. . . . . . . . . . . . . . . 45 11.1.10 hccontrolcurrented register . . . . . . . . . . . . . 46 11.1.11 hcbulkheaded register . . . . . . . . . . . . . . . . . 47 11.1.12 hcbulkcurrented register . . . . . . . . . . . . . . . 48 11.1.13 hcdonehead register. . . . . . . . . . . . . . . . . . . 48 11.1.14 hcfminterval register. . . . . . . . . . . . . . . . . . . 49 11.1.15 hcfmremaining register . . . . . . . . . . . . . . . . 50 11.1.16 hcfmnumber register . . . . . . . . . . . . . . . . . . 51 11.1.17 hcperiodicstart register . . . . . . . . . . . . . . . . . 52 11.1.18 hclsthreshold register . . . . . . . . . . . . . . . . . 53 11.1.19 hcrhdescriptora register . . . . . . . . . . . . . . . 53 11.1.20 hcrhdescriptorb register . . . . . . . . . . . . . . . 55 11.1.21 hcrhstatus register . . . . . . . . . . . . . . . . . . . . 56 11.1.22 hcrhportstatus[2:1] register . . . . . . . . . . . . . 57 11.2 ehci controller capability registers . . . . . . . . 60 11.2.1 caplength/hciversion register. . . . . . . 60
nxp semiconductors isp1564 hs usb pci host controller ? nxp b.v. 2008. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 13 november 2008 document identifier: isp1564_2 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 11.2.2 hcsparams register . . . . . . . . . . . . . . . . . . 61 11.2.3 hccparams register . . . . . . . . . . . . . . . . . . 62 11.2.4 hcsp-portroute register . . . . . . . . . . . . . 63 11.3 operational registers of enhanced usb host controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11.3.1 usbcmd register . . . . . . . . . . . . . . . . . . . . . . 64 11.3.2 usbsts register . . . . . . . . . . . . . . . . . . . . . . 66 11.3.3 usbintr register . . . . . . . . . . . . . . . . . . . . . . 68 11.3.4 frindex register . . . . . . . . . . . . . . . . . . . . . . 69 11.3.5 periodiclistbase register . . . . . . . . . . . . 70 11.3.6 asynclistaddr register . . . . . . . . . . . . . . . 71 11.3.7 configflag register . . . . . . . . . . . . . . . . . . 72 11.3.8 portsc registers 1, 2 . . . . . . . . . . . . . . . . . . 73 11.4 miscellaneous registers . . . . . . . . . . . . . . . . . 76 12 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 78 13 recommended operating conditions. . . . . . . 78 14 static characteristics. . . . . . . . . . . . . . . . . . . . 79 15 dynamic characteristics . . . . . . . . . . . . . . . . . 82 15.1 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 16 package outline . . . . . . . . . . . . . . . . . . . . . . . . 86 17 soldering of smd packages . . . . . . . . . . . . . . 88 17.1 introduction to soldering . . . . . . . . . . . . . . . . . 88 17.2 wave and re?ow soldering . . . . . . . . . . . . . . . 88 17.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 88 17.4 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 89 18 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 90 19 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 20 revision history . . . . . . . . . . . . . . . . . . . . . . . . 91 21 legal information. . . . . . . . . . . . . . . . . . . . . . . 92 21.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 92 21.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 21.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 21.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 22 contact information. . . . . . . . . . . . . . . . . . . . . 92 23 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 24 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 25 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

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