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f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 1 of 31 3.3 volt synchronous x18 first-in/first-out queue memory configuration device 262,144 x 18 FQV2105 131,072 x 18 fqv295 65,536 x 18 fqv285 32,768 x 18 fqv275 16,384 x 18 fqv265 8,192 x 18 fqv255 key features industry leading first-in/first-out queues (up to 133mhz) write cycle time of 7.5ns independent of read cycle time read cycle time of 7.5ns independent of write cycle time 3.3v power supply 5v input tolerant on all control and data input pins 5v output tolerant on all flags and data output pins master reset clears all previously programmed configurations including write and read pointers partial reset clears write and read pointers but maintains all previously programmed configurations first word fall through (fwft) and standard timing modes presets for eight different almost full and almost empty offset values parallel/serial programming of praf and prae offset values full, empty, almost full, almost empty, and half full indicators asynchronous output enable tri-state data output drivers data retransmission available package: 64 - pin plastic thin quad flat pack (tqfp), 64 - pin slim thin quad flat pack (stqfp) (0c to 70c) commercial operating temperature available for cycle time of 7.5ns and above (-40c to 85c) industrial operating temperature available for cycle time of 7.5ns and above product description hba?s flexq? ii offers industry leading fifo queuing bandwidth (up to 3.0 gbps), with a wide range of memory configurations (from 8,192 x 18 to 262,144 x 18). system designer has full flexibility of implementing deeper and wider queues using fwft mode and width expansion features. full, empty, and half-full indicators allow easy handshaking between transmitters and receivers. user programmable almost full and almost empty (parallel/serial) indicators allow implementation of virtual queue depths. 5v tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. asynchronous output enable pin configures the tri-state data output drivers. independent write and read controls provide rate-matching capability. master reset clears all previously programmed configurations by providing a low pulse on mrst pin. in addition, write and read pointers to the queue are initialized to zero. partial reset will not alter previously programmed configurations but will initialize write and read pointers to zero. in fwft mode, first data written into the queue appears on output data bus after the specified latency period at the low to hig h transition of rclk. subsequent reads from the queue will require asserting ren . this feature is useful when implementing depth expansion functions. in this mode, drdy and qrdy are used instead of full and empty respectively. in standard mode, always assert ren for read operation. full and empty are used instead of drdy and qrdy respectively. praf , prae , and half are available in either fwft or standard mode.
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 2 of 31 product description (continued) at any time, data previously read from the queue can be retransmitted by asserting ret pin at the low to high transition of rclk for a retransmit operation. retransmit initializes the read pointer to zero. hence, all re-reads will always start from the physical 0 th (read pointer = zero) location of the queue. both zero and normal latency timing modes are available for retransmit operation. these flexq? ii devices have low power consumption, hence minimizing system power requirements. in addition, industry standard 64 - pin plastic tqfp and 64 - pin stqfp are offered to save system board space. these queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test equipment, network switching, etc. FQV2105 fqv295 fqv285 fqv275 fqv265 fqv255 write clock (wclk) write enable ( ) load ( ) x18 data in (d 17 - 0 ) first word fall through/ serial data input (fwft/sdi) read clock (rclk) x18 data out (q 17 - 0 ) programmable almost- empty ( ) half-full flag ( ) partial reset ( ) master reset ( ) block diagram of single synchronous queue 262,144 x 18 / 131,072 x 18 / 65,536 x 18 / 32,768 x 18 / 16,384 x 18 / 8,192 x 18 prst mrst wen load prae half serial data enable ( ) sden retransmit ( ) ret output enable ( ) oe read enable ( ) ren empty flag / output ready ( / ) qrdy empty full flag / input ready ( / ) full drdy programmable almost-full ( ) praf figure 1. single device configuration signal flow diagram
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 3 of 31 offset register write control logic write pointer sram input register output register flag logic output buffer q 17-0 x18 x18 d 17-0 read pointer read control logic reset fwft/sdi load sden wclk fwft/sdi praf / full drdy prae half empty qrdy / oe mrst prst rclk ret ren wen figure 2. device architecture
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 4 of 31 d 6 d 5 d 4 d 3 d 2 d 1 d 0 g n d q 0 q 1 g n d q 2 q 3 v c c q 4 q 5 empty/qrdy wclk prst mrst load fwft/sdi gnd full/drdy praf half vcc prae rclk ren ret oe q17 q16 gnd q15 q14 vcc q13 q12 q11 gnd q10 q9 q8 q7 q6 gnd wen sden dc (1) vcc gnd d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 index tqfp - 64 (drw no: pf-01a; order code: pf) stqfp - 64 (drw no: tf-01a; order code: tf) top view notes: 1. dc = don?t care. must be tied to gnd or vcc, cannot be left open. figure 3. device pin out
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 5 of 31 pin # pin name pin symbol input/output description 62 master reset mrst input master reset is required to initialize write and read pointers to the first position of the queue by setting mrst low. in standard mode, full and praf will go high; empty and prae will go low. in fwft mode, drdy will go low and qrdy will go high. praf and prae will go to the same state as standard mode. in both modes, all data outputs will go low. previous programmed configurations will not be maintained. 63 partial reset prst input partial reset is required to initialize write and read pointers to the first position of the queue by setting prst low. in standard mode, full and praf will go high; empty and prae will go low. in fwft mode, drdy will go low and qrdy will go high. praf and prae will go to the same state as standard mode. in both modes, all data outputs will go low. previous programmed configurations will be maintained. 64 write clock wclk input writes data into queue during low to high transitions of wclk if wen is set to low. 1 write enable wen input controls write operation into queue or offset registers during low to high transition of wclk. 61 load enable load input during master reset, set load low to select parallel programming or one of eight default offset values. set load high to select serial programming or one of eight default offset values. after master reset, load controls write/read, to/from offset registers during low to high transition of wclk/rclk respectively. use in conjunction with wen / ren . 6,7,8,9, 10,11,12,13, 14,15,16,17, 18,19,20,21, 22,23 data inputs d 17 - 0 input 18 - bit wide input data bus. 52 read clock rclk input reads data from queue during low to high transitions of rclk if ren is set to low. 51 read enable ren input controls read operation from queue or offset registers during low to high transition of rclk. 49 output enable oe input setting oe low activates the data output drivers. setting oe high deactivates the data output drivers (high-z). 48,47,45,44, 42,41,40,38, 37,36,35,34, 32,31,29,28, 26,25 data outputs q 17 - 0 output 18 - bit wide output data bus. 60 first word fall through/serial data input fwft/sdi input selects fwft timing or standard timing mode during master reset. after master reset, if serial programming is selected ( load = high), fwft/sdi is used as the serial data input for the offset registers. serial data is written during the low to high transition of wclk. use in conjunction with sden . table 1. pin descriptions
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 6 of 31 table 1. pin descriptions (continued) pin # pin name pin symbol input/output description 2 serial data input enable sden input if serial programming is selected, setting sden low and load low enables serial data input to be written into offset registers during the low to high transition of wclk. 50 retransmit ret input data previously read from the queue can be retransmitted by asserting ret pin at the low to high transition of rclk for a retransmit operation. retransmit initializes the read pointer to zero. hence, all re-reads will always start from the physical 0 th (read pointer = zero) location of the queue. 58 full/data input ready flag full / drdy output queue is full when full goes low during the low to high transition of wclk. this prohibits further writes into the queue. in fwft mode, queue is full when drdy goes high during low to high transition of wclk. this prohibits further writes into the queue. 53 empty/data output ready flag empty / qrdy output queue is empty when empty goes low during the low to high transition of rclk. this prohibits further reads from the queue. in fwft mode, queue is empty when qrdy goes high during the low to high transition of rclk. this prohibits further reads from the queue. 57 almost full praf output queue is almost full when praf goes low during the low to high transition of wclk. default (full-offset) or programmed offset values determine the status of praf . 54 almost empty prae output queue is almost empty when prae goes low during the low to high transition of rclk. default (empty +offset) or programmed offset values determine the status of prae . 56 half full half output queue is more than half full when half goes low. triggered by both wclk and rclk. 3 don?t care dc n/a this pin can be tied high or low, cannot be left open. 4, 30, 43, 55 power vcc n/a 3.3v power supply. 5, 24, 27, 33, 39, 46, 57 ground gnd n/a 0v ground.
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 7 of 31 symbol rating com?l & ind?l unit v term terminal voltage with respect to gnd -0.5 to + 4.6 v t stg storage temperature -55 to +125 c i out dc output current -50 to +50 ma notes: absolute max ratings are for reference only. permanent damage to the device may occur if extended period of operation is outside this range. standard operation should fall within the recommended operating conditions. table 2. absolute maximum ratings fqv 2105, fqv295, fqv285, fqv275, fqv265, fqv255 commercial clock = 7.5ns, 10ns, 15ns, 20ns industrial clock = 7.5ns, 10ns, 15ns, 20ns symbol parameter min. typ. max. min. typ. max. unit recommended operating conditions vcc supply voltage com?l / ind?l 3.0 3.3 3.6 3.0 3.3 3.6 v gnd supply voltage 0 0 0 0 0 0 v v ih input high voltage com?l / ind?l 2.0 - 5.0 2.0 - 5.0 v v il input low voltage com?l / ind?l - - 0.8 - - 0.8 v t a operating temperature commercial 0 - 70 0 - 70 c t a operating temperature industrial -40 - 85 -40 - 85 c dc electrical characteristics i li (1) input leakage current (any input) -10 - 10 -10 - 10 a i lo output leakage current -10 - 10 -10 - 10 a v oh output logic ?1? voltage, i oh =-2ma 2.4 - - 2.4 - - v v ol output logic ?0? voltage, i ol = 8ma - - 0.4 - - 0.4 v power consumption icc1 (2,3) active power supply current - - 60 - - 60 ma icc2 (4) standby current - - 20 - - 20 ma table 3. dc specifications
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 8 of 31 capacitance at 100mhz ambient temperature (25 c) symbol parameter conditions max. unit c in (2) input capacitance v in = 0v 10 pf c out (2,4) output capacitance v out = 0v 10 pf notes: 1. measurement with 0.4<=vin<=vcc 2. with output tri-stated ( oe = high) 3. icc(1,2) is measured with wclk and rclk at 20 mhz 4. design simulated, not tested. table 3. dc specifications (continued)
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 9 of 31 commercial & industrial FQV2105-7.5 fqv295-7.5 fqv285-7.5 fqv275-7.5 fqv265-7.5 fqv255-7.5 FQV2105-10 fqv295-10 fqv285-10 fqv275-10 fqv265-10 fqv255-10 FQV2105-15 fqv295-15 fqv285-15 fqv275-15 fqv265-15 fqv255-15 FQV2105-20 fqv295-20 fqv285-20 fqv275-20 fqv265-20 fqv255-20 symbol parameter min. max. min. max. min. max. min. max. unit f s clock cycle frequency - 133 - 100 - 66 - 50 mhz t a data access time 1 5 2 6.5 2 10 2 12 ns t wclk write clock cycle time 7.5 - 10 - 15 - 20 - ns t wclkh write clock high time 3.5 - 4.5 - 6 - 8 - ns t wclkl write clock low time 3.5 - 4.5 - 6 - 8 - ns t rclk read clock cycle time 7.5 - 10 - 15 - 20 - ns t rclkh read clock high time 3.5 - 4.5 - 6 - 8 - ns t rclkl read clock low time 3.5 - 4.5 - 6 - 8 - ns t ds data set-up time 2.5 - 3 - 4 - 5 - ns t dh data hold time 0.5 - 0.5 - 1 - 1 - ns t ens enable set-up time 2.5 - 3 - 4 - 1 - ns t enh enable hold time 0.5 - 0.5 - 1 - 1 - ns t rst reset pulse width (1) 10 - 10 - 15 - 20 - ns t rsts reset set-up time 10 10 - 15 - 20 - ns t rstr reset recovery time 10 - 10 - 15 - 20 - ns t rstf reset to flag and output time - 10 - 10 - 15 - 20 ns t rets retransmit setup time 2.5 - 3 - 4 - 5 - ns t olz output enable to output in low-z (1) 0 - 0 - 0 - 0 - ns t oe output enable to output valid 2 5 2 6 3 8 3 10 ns t ohz output enable to output in high-z (1) 2 5 2 6 3 8 3 10 ns t full write clock to full flag - 5 - 6.5 - 10 - 12 ns t empty read clock to empty flag - 5 - 6.5 - 10 - 12 ns t prafs write clock to almost-full flag - 5 - 6.5 - 10 - 12 ns t praes read clock to almost-empty flag - 5 - 6.5 - 10 - 12 ns t skew 1 skew time between read clock & write clock for full flag / empty flag 4 - 5 - 6 - 10 - ns t skew 2 skew time between read clock & write clock for praf & prae 7 - 12 - 15 - 20 - ns table 4. ac electrical characteristics
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 10 of 31 commercial & industrial FQV2105-7.5 fqv295-7.5 fqv285-7.5 fqv275-7.5 fqv265-7.5 fqv255-7.5 FQV2105-10 fqv295-10 fqv285-10 fqv275-10 fqv265-10 fqv255-10 FQV2105-15 fqv295-15 fqv285-15 fqv275-15 fqv265-15 fqv255-15 FQV2105-20 fqv295-20 fqv285-20 fqv275-20 fqv265-20 fqv255-20 symbol parameter min. max. min. max. min. max. min. max. unit t loads load setup time 2.5 - 3 - 4 - 5 - ns t loadh load hold time 0.5 - 0.5 - 1 - 1 - ns t rts retransmit setup time 3 - 3 - 4 - 5 - ns t hf clock to half - 14 - 16 - 20 - 22 ns notes: 1. design simulated, not tested. table 4. ac electrical characteristics (continued)
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 11 of 31 input pulse levels gnd to 3.0v input rise/fall times 3ns input timing reference levels 1.5v output reference levels 1.5v output load, clock = 7.5 ns refer to figure 4 output load * , clock = 10ns, 15ns, 20ns refer to figure 5 * include jig and scope capacitances table 5. ac test condition figure 5. output load for clock = 10ns, 15ns, 20ns *includes jig and scope capacitances. figure 4. ac test load for clock = 7.5ns d.u.t. 510 ? 30pf* 330 ? 3.3v vcc/2 50 ? z0 = 50 ? i/o
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 12 of 31 pin functions mrst master reset is required to initialize write and read pointers to the first position of the queue by setting mrst low. in standard mode, full and praf will go high; empty and prae will go low. in fwft mode, drdy will go low and qrdy will go high. praf and prae will go to the same state as standard mode. in both modes, all data outputs will go low. previous programmed configurations will not be maintained. prst partial reset is required to initialize write and read pointers to the first position of the queue by setting prst low. in standard mode, full and praf will go high; empty and prae will go low. in fwft mode, drdy will go low and qrdy will go high. praf and prae will go to the same state as standard mode. in both modes, all data outputs will go low. previous programmed configurations will be maintained. wclk writes data into queue during low to high transitions of wclk if wen is activated. synchronizes full / drdy and praf flags. wclk and rclk are independent of each other. wen controls write operation into queue or offset registers during low to high transition of wclk. load during master reset, set load low to select parallel programming or one of eight default offset values. set load high to select serial programming or one of eight default offset values. after master reset, load controls write/read, to/from offset registers during low to high transition of wclk/rclk respectively for parallel programming. use in conjunction with wen / ren . during programming of offset registers, praf and prae flag status is invalid. for serial programming, load is used to enable serial loading of offset registers together with sden . refer to figure 6 for details. d 17-0 18 - bit wide input data bus. rclk reads data from queue during low to high transitions of rclk if ren is set low. synchronizes the empty / qrdy and prae flags. rclk and wclk are independent of each other. ren reads data from queue during low to high transitions of rclk if ren is set to low. this also advances the read pointer of the queue. oe setting oe low activates the data output drivers. setting oe high deactivates the data output drivers (high-z). oe does not control advancement of read pointer. q 17-0 18 - bit wide output data bus. fwft/sdi selects fwft timing or standard timing mode during master reset. after master reset, if serial programming is selected ( load = high), fwft/sdi is used as the serial data input for the offset registers. serial data is written during the low to high transition of wclk. use in conjunction with sden . in fwft mode, drdy and qrdy is used instead of full and empty . refer to table 10 for all flags status. in standard mode, full and empty are used instead of drdy and qrdy . refer to table 9 for all flags status. sden if serial programming is selected, setting sden and load low enables serial data to be written into offset registers during the low to high transition of wclk. during serial programming, praf and prae flags status is invalid. refer to figure 6 for details. ret data previously read from the queue can be retransmitted by asserting ret pin at the low to high transition of rclk for a retransmit operation. retransmit initializes the read pointer to zero. hence, all re-reads will always start from the physical 0 th (read pointer = zero), location of the queue. refer to diagram 7 & 8 for details.
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 13 of 31 pin functions (continued) full / drdy in standard mode, queue is full when full goes low during the low to high transition of wclk. this prohibits further writes into the queue and prevents advancement of write pointer. in fwft mode, queue is full when drdy goes high during the low to high transition of wclk. this prohibits further writes into the queue and prevents advancement of write pointer. refer to table 8 & 9 for behavior of full / drdy . empty / qrdy in standard mode, queue is empty when empty goes low during the low to high transition of rclk. this prohibits further reads from the queue and prevents advancement of read pointer. in fwft mode, queue is empty when qrdy goes low during the low to high transition of rclk. this prohibits further reads from the queue and prevents advancement of read pointer. refer to table 8 & 9 for behavior of empty / qrdy . praf in synchronous mode, queue is almost full when praf goes low during the low to high transition of wclk. default (full-offset) or programmed offset values determine the status of praf . in asynchronous timing mode, praf is triggered by both wclk and rclk. refer to table 8 & 9 for behavior of praf . prae in synchronous mode, queue is almost empty when prae goes low during the low to high transition of rclk. default (empty+offset) or programmed offset values determine the status of prae . in asynchronous timing mode, praf is triggered by both wclk and rclk. refer to table 8 & 9 for behavior of prae . half queue is more than half full when half goes low during the low to high transition of wclk. half goes high during low to high transition of rclk when queue is less than half full. refer to table 8 & 9 for details.
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 14 of 31 load wen ren sden wclk rclk FQV2105 fqv295 fqv285 fqv275 fqv265 fqv255 selection / sequence 0 0 1 1 x write to offset registers: empty offset full offset parallel write to registers: 1. prae 2. praf 0 1 0 1 x read from offset registers: empty offset full offset parallel read from registers: 1. prae 2. praf 0 1 1 0 x serial shift into registers: 36 bits for the FQV2105 34 bits for the fqv295 32 bits for the fqv285 30 bits for the fqv275 28 bits for the fqv265 26 bits for the fqv255 1 bit for each rising wclk edge starting with empty offset (low byte) ending with full offset (high byte) x 1 1 1 x x no operation 1 0 x x x write memory 1 x 0 x x read memory 1 1 1 x x x no operation figure 6. programmable flag offset programming sequence
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 15 of 31 device praf programming (bits) prae programming (bits) d/q 15 ? 0 low word d/q 15 ? 0 low word FQV2105 d/q 1 - 0 high word d/q 1 - 0 high word d/q 15 - 0 low word d/q 15 - 0 low word fqv295 d/q 0 high word d/q 0 high word fqv285 d/q 15 - 0 d/q 15 - 0 fqv275 d/q 14 - 0 d/q 14 - 0 fqv265 d/q 13 - 0 d/q 13 - 0 fqv255 d/q 12 - 0 d/q 12 - 0 all dv = 7fh, when load = 0 dv = 3ffh, when load = 1 dv = 7fh, when load = 0 dv = 3ffh, when load = 1 table 6. parallel offset register data mapping and default values (dv) table device standard mode fwft FQV2105 262,144 x 18 262,145 x 18 fqv295 131,072 x 18 131,073 x 18 fqv285 65,536 x 18 65,537 x 18 fqv275 32,768 x 18 32,769 x 18 fqv265 16,384 x 18 16,385 x 18 fqv255 8,192 x 18 8,193 x 18 table 7. maximum depth of queue for standard and fwft mode
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 16 of 31 # of bits for offset registers 18 bits for FQV2105 17 bits for fqv295 16 bits for fqv285 15 bits for fqv275 14 bits for fqv265 13 bits for fqv255 note: don?t care applies to all unused bits figure 7. parallel offset write/read cycles diagram data width data width fqv285, fqv275, fqv265, fqv255 parallel offset write/read cycles for x18 width d/q8 d/q6 d/q4 d/q2 d/q0 d/q7 d/q5 d/q3 d/q1 d/q9 d/q10 d/q11 d/q12 d/q13 d/q14 d/q15 d/q16 d/q17 d/q8 d/q6 d/q4 d/q2 d/q0 d/q7 d/q5 d/q3 d/q1 d/q9 d/q10 d/q11 d/q12 d/q13 d/q14 d/q15 d/q16 d/q17 prae praf 1st cycle 2nd cycle prae praf 1st cycle 2nd cycle prae praf 3rd cycle 4th cycle FQV2105, fqv295 parallel offset write/read cycles for x18 width 31 8420 75 6 9 10 11 12 13 14 31 8420 75 6 9 10 11 12 13 14 15 15 31 8420 75 6 9 10 11 12 13 14 9 10 12 14 15 16 17 31 8420 75 6 9 10 11 12 13 14 9 10 12 14 15 16 17
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 17 of 31 FQV2105 full praf half prae empty 0 h h h l l 1 to y (1) h h h l h (y+1) to 131,072 h h h h h 131,073 to [262,144-(x+1)] h h l h h (262,144-x (2) ) to 262,143 h l l h h 262,144 l l l h h fqv295 full praf half prae empty 0 h h h l l 1 to y (1) h h h l h (y+1) to 65,536 h h h h h 65,537 to [131,072-(x+1)] h h l h h (131,072-x (2) ) to 131,071 h l l h h 131,072 l l l h h fqv285 full praf half prae empty 0 h h h l l 1 to y (1) h h h l h (y+1) to 32,768 h h h h h 32,769 to [65,536-(x+1)] h h l h h (65,536-x (2) ) to 65,535 h l l h h 65,536 l l l h h fqv275 full praf half prae empty 0 h h h l l 1 to y (1) h h h l h (y+1) to 16,384 h h h h h 16,385 to [32,768-(x+1)] h h l h h (32,768-x (2) ) to 32,767 h l l h h 32,768 l l l h h fqv265 full praf half prae empty 0 h h h l l 1 to y (1) h h h l h (y+1) to 8,192 h h h h h 8,193 to [16,384-(x+1)] h h l h h (16,384 -x (2) ) to 16,383 h l l h h 16,384 l l l h h fqv255 full praf half prae empty 0 h h h l l 1 to y (1) h h h l h (y+1) to 4,096 h h h h h 4,097 to [8,192-(x+1)] h h l h h (8,192-x (2) ) to 8,191 h l l h h 8,192 l l l h h notes: 1. y = prae offset; default values: y = 127 when parallel offset loading is selected or y =1,023 when serial offset loading is selecte d. 2. x = praf offset; default values: x = 127 when parallel offset loading is selected or x =1,023 when serial offset loading is selecte d. table 8. status flags (standard mode)
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 18 of 31 FQV2105 drdy praf half prae qrdy 0 l h h l h 1 to y (1) +1 l h h l l (y+2) to 131,073 l h h h l 131,074 to [262,145-(x+1)] l h l h l (262,145-x (2) ) to 262,144 l l l h l 262,145 h l l h l fqv295 drdy praf half prae qrdy 0 l h h l h 1 to y (1) +1 l h h l l (y+2) to 65,537 l h h h l 65,538 to [131,073-(x+1)] l h l h l (131,073-x (2) ) to 131,072 l l l h l 131,073 h l l h l fqv285 drdy praf half prae qrdy 0 l h h l h 1 to y (1) +1 l h h l l (y+2) to 32,769 l h h h l 32,770 to [65,537-(x+1)] l h l h l (65,537-x (2) ) to 65,536 l l l h l 65,537 h l l h l fqv275 drdy praf half prae qrdy 0 l h h l h 1 to y (1) +1 l h h l l (y+2) to 16,385 l h h h l 16,386 to [32,769-(x+1)] l h l h l (32,769-x (2) ) to 32,768 l l l h l 32,769 h l l h l fqv265 drdy praf half prae qrdy 0 l h h l h 1 to y (1) +1 l h h l l (y+2) to 8,193 l h h h l 8,194 to [16,385-(x+1)] l h l h l (16,385 -x (2) ) to 16,384 l l l h l 16,385 h l l h l fqv255 drdy praf half prae qrdy 0 l h h l h 1 to y (1) +1 l h h l l (y+2) to 4,097 l h h h l 4,098 to [8,193-(x+1)] l h l h l (8,193-x (2) ) to 8,192 l l l h l 8,193 h l l h l notes: 1. y = prae offset; default values: y = 127 when parallel offset loading is selected or y =1,023 when serial offset loading is selecte d. 2. x = praf offset; default values: x = 127 when parallel offset loading is selected or x =1,023 when serial offset loading is selecte d. table 9. status flags (fwft mode)
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 19 of 31 timing diagrams t rst t rsts t rstr t rsts t rstr t rsts t rsts t rstf t rstf t rstf t rstf t rstf t rsts t rstr fwft/sdi q 17- 0 mrst ren wen load ret sden / empty qrdy prae praf half / / full drdy if fwft = 0, = 1 full if fwft = 1, = 0 drdy if fwft = 1, = 1 qrdy if fwft = 0, = 0 empty = 0 oe = 1 oe t rsts t rstr diagram 1. master reset timing
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 20 of 31 t rst t rstr t rstr t rstf t rstf t rstf t rstf t rstf t rsts t rsts t rsts if fwft = 0, = 1 full if fwft = 1, = 0 drdy if fwft = 1, = 1 qrdy if fwft = 0, = 0 empty = 0 oe = 1 oe q 17 - 0 ret sden / empty qrdy prae praf half / / full drdy wen ren prst t rsts diagram 2. partial reset timing
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 21 of 31 dw i + 1 dw i no write no write no write t wclk t wclkh t wclkl t full t full t full t full t ds t dh t ds t dh t skew1 t ens t enh t ens t enh t a t a next data read data read output register data wclk d 17 - 0 rclk q 17 - 0 full ren wen 12 12 t skew1 notes: 1. if the time between a rising edge of rclk to the rising edge of wclk is greater than or equal to t skew1 , full ___________ will go high (after one wclk cycle plus t full ). if t skew1 is not met, then full __________ will assert 1 or more wclk cycles. 2. load ___________ = high, oe ______ = low. diagram 3. write cycle and full flag timing (standard mode)
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 22 of 31 dw 1 dw 2 dw 1 last word last word dw 2 t rclk t rclkh t rclkl t enh t ens t enh t ens t empty t empty t empty t a t a t oen t ohz t olz t olz t skew1 t ens t enh t ens t enh t enh t ens t ds t dh t ds t dh t a rclk q 17 - 0 wclk d 17 - 0 oe wen empty ren 12 notes: 1. if the time between a rising edge of wclk to the rising edge of rclk is greater than or equal to t s kew11 , empty ______________ will go high (after rclk cycle plus t empty ). if t skew1 is not met, then empty ______________ will assert 1 or more rclk cycles. 2. load ___________ = high. 3. first word latency: t skew1 + t empty + 1 * t rclk . diagram 4. read cycle, empty flag and first data word latency timing (standard mode)
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 23 of 31 dw [y+2] dw d dw [d-1] dw [d-x+3] dw [d-x+2] dw [d-x+1] dw [d-x] dw [d-x-1] dw [(d-1)/2+3] dw [(d-1)/2+2] dw [(d-1)/2+1] dw [y+4] dw [y+3] dw 4 dw 3 dw 2 dw 1 3 12 12 wclk d 17 - 0 rclk q 17 - 0 qrdy prae half praf drdy t ens t dh t ds t ds t ds t ds t enh t skew1 t skew2 t full t half t praes t a t empty 1 output register data dw 1 wen ren 2 t prafs notes: 1. if the time between a rising edge of wclk to the rising edge of rclk is greater than or equal to t skew1, qrdy ____________ will go low (after two rclk cycle plus t empty ). if t skew1 is not met, then qrdy ____________ will assert 1 or more rclk cycles. 2. if the time between a rising edge of wclk to the rising edge of rclk is greater than or equal to t skew2 , prae ___________ will go high (after one rclk cycle plus t praes ). if t skew2 is not met, then prae ___________ will assert 1 or more rclk cycles. 3. load ___________ = high, oe ______ = low. 4. y = prae ___________ offset, x = praf ___________ offset. 5. d = maximum queue depth. please refer to table 7 for depth. 6. first word latency: t skew1 + t empty + 2 * t rclk diagram 5. write timing (fwft mode)
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 24 of 31 dw 1 dw d dw [d-1] dw [d-y+2] dw [d-y+1] dw [d-y-1] dw [(d-1)/2+2] dw x+3 dw x+2 dw x+1 dw 3 dw 2 dw 1 dw [d-y] dw [(d-1)/2+1] dw d t ens t enh t skew1 t skew2 t ds t dh t ens t ohz t oe t a t a t a t a t a t a t ens t empty t half t prafs t full t full wclk wen d 17 - 0 rclk ren oe q 17 - 0 qrdy prae half praf drdy 12 12 2 1 t praes notes: 1. if the time between a rising edge of rclk to the rising edge of wclk is greater than or equal to t skew1, drdy ____________ will go low (after one wclk cycle plus t full ) . if t skew1 is not met, then drdy ____________ will assert 1 or more wclk cycles. 2. if the time between a rising edge of rclk to the rising edge of wclk is greater than or equal to t skew2 , praf ___________ will go high (after one wclk cycle plus t prafs ) if t skew2 is not met, then praf ___________ will assert 1 or more wclk cycles. 3. load ____________ = high 4. y = prae ___________ offset, x = praf ___________ offset. 5. d = maximum queue depth. please refer to table 7 for depth. diagram 6. read timing (fwft mode)
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 25 of 31 dw i dw i+1 dw 1 dw 2 rclk q 17 - 0 wclk t ens t enh t rets t a t a t ens t enh t a t skew2 t rets t ens t enh t empty t half t empty t praes t prafs ren wen ret emp ty prae half praf 12 notes: 1. upon completion of retransmit setup, a read operation can begin only after empty returns high. 2. oe = low. 3. dw i = words written to the queue after mrst . where i = 1,2,3? depth. 4. upon reset completion, there must be more than 2 words written to the queue for a retransmit setup to be valid. diagram 7. retransmit timing (standard mode)
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 26 of 31 dw 2 dw i dw i+1 dw 1 rclk q 17 - 0 wclk t ens t enh t rets t a t skew2 t rets t ens t enh t empty t half t empty t pra es t pr afs t enh 2 pra f hal f prae qrdy ret wen ren 1 2 1 34 t ens dw 3 dw 4 notes: 1. upon completion of retransmit setup, a read operation can begin only after qrdy returns low. 2. oe = low. 3. dw i = words written to the queue after mrst . where i = 1,2,3? depth. 4. upon reset completion, there must be more than 2 words written to the queue for a retransmit setup to be valid. 5. please refer to table 7 for depth. diagram 8. retransmit timing (fwft mode)
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 27 of 31 wclk sdi t enh t ens t loadh t loads t ds offset offset t enh t loadh t dh bit 0 bit msb bit 0 bit msb load sden prae praf * refer to table 10. diagram 9. serial loading of programmable flag registers (standard and fwft mode) FQV2105 fqv295 fqv285 fqv275 fqv265 fqv255 msb 17 16 15 14 13 12 table 10. reference table for diagram 9
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 28 of 31 t loads t ens t loadh t enh t loadh t enh t wclkh t wclkl t wclk wclk d 17 - 0 offset t ds t dh t ds t dh wen load prae offset praf diagram 10. parallel loading of programmable flag registers (standard and fwft mode) t loads t ens t loadh t enh t loadh t enh t rclkh t rclkl t rclk rclk q 17 - 0 data in output register t a t a load ren offset prae offset praf diagram 11. parallel read of programmable flag registers (standard and fwft mode)
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 29 of 31 t wclkh t wclkl t enh t ens t skew2 t ens t enh t prafs t prafs 12 12 d - ( x + 1 ) words in queue d - x words in queue d - ( x + 1 ) words in queue wen praf ren wclk rclk notes: 1. x = praf ___________ offset. 2. d = maximum queue depth. please refer to table 7 for depth. 3. if the time between a rising edge of rclk to the rising edge of wclk is greater than or equal to t skew2, praf ___________ will go high (after on wclk cycle plus t prafs ). if t skew2 is not met, then praf ___________ will assert 1 or more wclk cycles. 4. praf ___________ synchronizes to the rising edge of wclk only. diagram 12. programmable almost-full flag timing (standard and fwft mode) t wclkh t wclkl t wclkl t wclkh t ens t enh y words in queue (2) ; y+1 words in queue (3) y+1 words in queue (2) ; y+2 words in queue (3) y words in queue (2) ; y+1 words in queue (3) t praes t praes t skew2 12 1 2 wen prae wclk rclk ren notes: 1. y = prae ___________ offset. 2. for standard mode. 3. for fwft mode. 4. if the time between a rising edge of wclk to the rising edge of rclk is greater than or equal to t skew2 , prae ___________ will go high (after one rclk cycle plus t praes ). if t skew2 is not met, then prae ___________ will assert 1 or more rclk cycles. 5. prae ___________ synchronizes to the rising edge of rclk only. diagram 13. programmable almost-empty flag timing (standard and fwft mode)
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 30 of 31 d/2 words in queue (1) ; [(d+1)/2] words in queue (2) d/2 + 1 words in queue (1) ; [(d+1)/2 + 1] words in queue (2) d/2 words in queue (1) ; [(d+1)/2] words in queue (2) t wclkh t wclkl t ens t enh t half t half t ens wclk rclk wen half ren notes: 1. for standard mode. 2. for fwft mode. 3. please refer to table 7 for depth. diagram 14. half-full flag timing (standard and fwft mode)
f q v2105 f q v295 f q v285 f q v275 f q v265 f q v255 october 2002 flex q tm i i 3f218c ? 2001 high bandwidth access, inc. all rights reserved. product specifications subject to change without notice. page 31 of 31 order information: hba device family device type power speed (ns) * package** temperature range xx xxxx x xx xx x fq v2105 (262,144 x 18) l ow 7-5 ? 133 mhz pf blank ? commercial (0c to 70c) v295 (131,072 x 18) 10 ? 100 mhz tf i ? industrial (-40 to 85c) v285 (65,536 x 18) 15 ? 66 mhz v275 (32,768 x 18 20 ? 50 mhz v265 (16,384 x 18) v255 (8,192 x 18) *speed ? slower speeds available upon request. **package ? 64 pin plastic thin quad flat pack (tqfp), 64 pin slim thin quad flat pack (stqfp) example: fqv275l7-5pf (32k x 18, 7.5ns, commercial temp) fqv265l10pfi (16k x 18, 10ns, industrial temp) usa taiwan 2107 north first street, suite 415 san jose, ca 95131, usa www.hba.com tel: 408.453.8885 fax: 408.453.8886 no. 81, suite 8f-9, shui-lee rd. hsinchu, taiwan, r.o.c. www.hba.com tel: 886.3.516.9118 fax: 886.3.516.9181

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