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tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 1 post office box 655303 ? dallas, texas 75265 push-pull cmos output drives capacitive loads without pullup resistor, i o = 8 ma very low power . . . 200 w typ at 5 v fast response time ...t plh = 2.7 s typ with 5-mv overdrive single supply operation ...3 v to 16 v tlc3704m ...4 v to 16 v on-chip esd protection description the tlc3704 consists of four independent micropower voltage comparators designed to operate from a single supply and be compatible with modern hcmos logic systems. they are functionally similar to the lm339 but use 1/20th the power for similar response times. the push-pull cmos output stage drives capacitive loads directly without a power-consuming pullup resistor to achieve the stated response time. eliminating the pullup resistor not only reduces power dissipation, but also saves board space and component cost. the output stage is also fully compatible with ttl requirements. texas instruments lincmos ? process offers superior analog performance to standard cmos processes. along with the standard cmos advantages of low power without sacrificing speed, high input impedance, and low bias currents, the lincmos process offers extremely stable input offset voltages with large differential input voltages. this characteristic makes it possible to build reliable cmos comparators. the tlc3704c is characterized for operation over the commercial temperature range of 0 c to 70 c. the tlc3704i is characterized for operation over the extended industrial tempera- ture range of ? 40 c to 85 c. the tlc3704m is characterized for operation over the full military temperature range of ? 55 c to 125 c. the tlc3704q is characterized for operation from ? 40 c to 125 c. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. lincmos is a trademark of texas instruments incorporated. copyright ? 2002, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. 3 2 1 20 19 910111213 4 5 6 7 8 18 17 16 15 14 gnd nc 4in + nc 4in ? v dd nc 2in ? nc 2in + fk package (top view) 2out 1out nc 3in? 3in+ 3out 4out 1in+ nc 1in? d, j, or n package (top view) nc ? no internal connection out symbol (each comparator) in + in ? 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1out 2out v dd 2in ? 2in + 1in ? 1in + 3out 4out gnd 4in + 4in ? 3in + 3in ? 1 2 3 4 5 6 7 14 13 12 11 10 9 8 pw package (top view) 1out 2out v dd 2in ? 2in + 1in ? 1in + 3out 4out gnd 4in + 4in ? 3in + 3in ?
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 2 post office box 655303 ? dallas, texas 75265 available options v io max package t a v io max at 25 c small outline (d) ceramic (fk) ceramic dip (j) plastic dip (n) tssop (pw) 0 c to 70 c 5 mv tlc3704cd ? ? tlc3704cn tlc3704cpw ? 40 c to 85 c 5 mv tlc3704id ? ? tlc3704in tlc3704ipw ? 55 c to 125 c 5 mv ? TLC3704MFK tlc3704mj ? ? ? 40 c to 125 c 5 mv ? ? tlc3704qj ? ? the d and pw packages are available taped and reeled. add r suffix to the device type (e.g., tlc3704cdr). functional block diagram (each comparator) v dd gnd out differential input circuits in+ in ? absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ? supply voltage range, v dd (see note 1) ? 0.3 v to 18 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . differential input voltage, v id (see note 2) 18 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i ? 0.3 to v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o ? 0.3 to v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input current, i i 5 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output current, i o (each output) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . total supply current into v dd 40 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . total current out of gnd 60 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous total power dissipation see dissipation rating table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a : tlc3704c 0 to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tlc3704i ? 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tlc3704m ? 55 c to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tlc3704q ? 40 c to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . case temperature for 60 seconds: fk package 260 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: d or n package 260 c . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: j package 300 c . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. all voltage values, except differential voltages, are with respect to network ground. 2. differential voltages are at in+ with respect to in ? .
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 3 post office box 655303 ? dallas, texas 75265 dissipation rating table package t a 25 c power rating derating factor above t a = 25 c t a = 70 c power rating t a = 85 c power rating t a = 125 c power rating d fk j n pw 950 mw 1375 mw 1375 mw 1150 mw 675 mw 7.6 mw/ c 11.0 mw/ c 11.0 mw/ c 9.2 mw/ c 5.4 mw/ c 608 mw 880 mw 880 mw 736 mw 432 mw 494 mw 715 mw 715 mw 598 mw 351 mw n/a 275 mw 275 mw n/a n/a recommended operating conditions tlc3704c unit min nom max unit supply voltage, v dd 3 5 16 v common-mode input voltage, v ic ? 0.2 v dd ? 1.5 v high-level output current, i oh ? 20 ma low-level output current, i ol 20 ma operating free-air temperature, t a 0 70 c electrical characteristics at specified operating free-air temperature, v dd = 5 v (unless otherwise noted) parameter test conditions ? t a tlc3704c unit parameter test conditions ? t a min typ max unit v io in p ut offset voltage v dd = 5 v to 10 v, 25 c 1.2 5 mv v io input offset voltage v ic = v icr min, see note 3 0 c to 70 c 6.5 mv i io in p ut offset current v ic =25v 25 c 1 pa i io input offset current v ic = 2 . 5 v 70 c 0.3 na i ib in p ut bias current v ic =25v 25 c 5 pa i ib input bias current v ic = 2 . 5 v 70 c 0.6 na v icr common mode in p ut voltage range 25 c 0 to v dd ? 1 v v icr common - mode input voltage range 0 c to 70 c 0 to v dd ? 1.5 v 25 c 84 cmrr common-mode rejection ratio v ic = v icr min 70 c 84 db 0 c 84 25 c 85 k svr supply-voltage rejection ratio v dd = 5 v to 10 v 70 c 85 db 0 c 85 v oh high level out p ut voltage v id =1v i oh = 4ma 25 c 4.5 4.7 v v oh high - level output voltage v id = 1 v , i oh = ? 4 ma 70 c 4.3 v v ol low level out p ut voltage v id = 1v i oh =4ma 25 c 210 300 mv v ol low - level output voltage v id = ? 1 v , i oh = 4 ma 70 c 375 mv i dd su pp ly current (all four com p arators) out p uts low no load 25 c 35 80 a i dd supply current (all four comparators) outputs low , no load 0 c to 70 c 100 a ? all characteristics are measured with zero common-mode voltage unless otherwise noted. note 3: the offset voltage limits given are the maximum values required to drive the output up to 4.5 v or down to 0.3 v.
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 4 post office box 655303 ? dallas, texas 75265 recommended operating conditions tlc3704i unit min nom max unit supply voltage, v dd 3 5 16 v common-mode input voltage, v ic ? 0.2 v dd ? 1.5 v high-level output current, i oh ? 20 ma low-level output current, i ol 20 ma operating free-air temperature, t a ? 40 85 c electrical characteristics at specified operating free-air temperature, v dd = 5 v, v ic = 0 (unless otherwise noted) parameter test conditions t a tlc3704i unit parameter test conditions t a min typ max unit v io in p ut offset voltage v dd = 5 v to 10 v, 25 c 1.2 5 mv v io input offset voltage v ic = v icr min, see note 3 ? 40 c to 85 c 7 mv i io in p ut offset current v ic =25v 25 c 1 pa i io input offset current v ic = 2 . 5 v 85 c 1 na i ib in p ut bias current v ic =25v 25 c 5 pa i ib input bias current v ic = 2 . 5 v 85 c 2 na v icr common mode in p ut voltage range 25 c 0 to v dd ? 1 v v icr common - mode input voltage range ? 40 c to 85 c 0 to v dd ? 1.5 v 25 c 84 cmrr common-mode rejection ratio v ic = v icr min 85 c 84 db ? 40 c 83 25 c 85 k svr supply-voltage rejection ratio v dd = 5 v to 10 v 85 c 85 db ? 40 c 83 v oh high level out p ut voltage v id =1v i oh = 4ma 25 c 4.5 4.7 v v oh high - level output voltage v id = 1 v , i oh = ? 4 ma 85 c 4.3 v v ol low level out p ut voltage v id = 1v i oh =4ma 25 c 210 300 mv v ol low - level output voltage v id = ? 1 v , i oh = 4 ma 85 c 400 mv i dd su pp ly current (all four com p arators) out p uts low no load 25 c 35 80 a i dd supply current (all four comparators) outputs low , no load ? 40 c to 85 c 125 a note 3: the offset voltage limits given are the maximum values required to drive the output up to 4.5 v or down to 0.3 v.
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 5 post office box 655303 ? dallas, texas 75265 recommended operating conditions tlc3704m unit min nom max unit supply voltage, v dd 4 5 16 v common-mode input voltage, v ic 0 v dd ? 1.5 v high-level output current, i oh ? 20 ma low-level output current, i ol 20 ma operating free-air temperature, t a ? 55 125 c electrical characteristics at specified operating free-air temperature, v dd = 5 v, v ic = 0 (unless otherwise noted) parameter test conditions t a tlc3704m unit parameter test conditions t a min typ max unit v io in p ut offset voltage v dd = 5 v to 10 v, 25 c 1.2 5 mv v io input offset voltage v ic = v icr min, see note 3 ? 55 c to 125 c 10 mv i io in p ut offset current v ic =25v 25 c 1 pa i io input offset current v ic = 2 . 5 v 125 c 15 na i ib in p ut bias current v ic =25v 25 c 5 pa i ib input bias current v ic = 2 . 5 v 125 c 30 na v icr common mode in p ut voltage range 25 c 0 to v dd ? 1 v v icr common - mode input voltage range ? 55 c to 125 c 0 to v dd ? 1.5 v 25 c 84 cmrr common-mode rejection ratio v ic = v icr min 125 c 83 db ? 55 c 82 25 c 85 k svr supply-voltage rejection ratio v dd = 5 v to 10 v 125 c 85 db ? 55 c 82 v oh high level out p ut voltage v id =1v i oh = 4ma 25 c 4.5 4.7 v v oh high - level output voltage v id = 1 v , i oh = ? 4 ma 125 c 4.2 v v ol low level out p ut voltage v id = 1v i oh =4ma 25 c 210 300 mv v ol low - level output voltage v id = ? 1 v , i oh = 4 ma 125 c 500 mv i dd su pp ly current (all four com p arators) out p uts low no load 25 c 35 80 a i dd supply current (all four comparators) outputs low , no load ? 55 c to 125 c 175 a note 3: the offset voltage limits given are the maximum values required to drive the output up to 4.5 v or down to 0.3 v.
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 6 post office box 655303 ? dallas, texas 75265 recommended operating conditions tlc3704q unit min nom max unit supply voltage, v dd 3 5 16 v common-mode input voltage, v ic ? 0.2 v dd ? 1.5 v high-level output current, i oh ? 20 ma low-level output current, i ol 20 ma operating free-air temperature, t a ? 40 125 c electrical characteristics at specified operating free-air temperature, v dd = 5 v, v ic = 0 (unless otherwise noted) parameter test conditions t a tlc3704q unit parameter test conditions t a min typ max unit v io in p ut offset voltage v dd = 5 v to 10 v, 25 c 1.2 5 mv v io input offset voltage v ic = v icr min, see note 3 ? 40 c to 125 c 7 mv i io in p ut offset current v ic =25v 25 c 1 pa i io input offset current v ic = 2 . 5 v 125 c 15 na i ib in p ut bias current v ic =25v 25 c 5 pa i ib input bias current v ic = 2 . 5 v 125 c 30 na v icr common-mode input volta g e 25 c 0 to v dd ? 1 v v icr g range ? 40 c to 125 c 0 to v dd ? 1.5 v 25 c 84 cmrr common-mode rejection ratio v ic = v icr min 125 c 83 db ? 40 c 83 25 c 85 k svr supply-voltage rejection ratio v dd = 5 v to 10 v 125 c 85 db ? 40 c 83 v oh high level out p ut voltage v id =1v i oh = 4ma 25 c 4.5 4.7 v v oh high - level output voltage v id = 1 v , i oh = ? 4 ma 125 c 4.2 v v ol low level out p ut voltage v id = 1v i oh =4ma 25 c 210 300 mv v ol low - level output voltage v id = ? 1 v , i oh = 4 ma 125 c 500 mv i dd supply current (all four out p uts low no load 25 c 35 80 a i dd y( comparators) outputs low , no load ? 40 c to 125 c 175 a note 3: the offset voltage limits given are the maximum values required to drive the output up to 4.5 v or down to 0.3 v.
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 7 post office box 655303 ? dallas, texas 75265 switching characteristics, v dd = 5 v, t a = 25 c parameter test conditions tlc3704c, tlc3704i tlc3704m, tlc3704q unit min typ max ? overdrive = 2 mv 4.5 ? f10kh overdrive = 5 mv 2.7 t plh pro p agation delay time low to high level out p ut ? f = 10 khz, c l =50 p f overdrive = 10 mv 1.9 s t plh propagation delay time , low - to - high - level output ? c l = 50 f overdrive = 20 mv 1.4 s overdrive = 40 mv 1.1 v i = 1.4-v step at in + 1.1 ? overdrive = 2 mv 4 ? f10kh overdrive = 5 mv 2.3 t phl pro p agation delay time high to low level out p ut ? f = 10 khz, c l =50 p f overdrive = 10 mv 1.5 s t phl propagation delay time , high - to - low - level output ? c l = 50 f overdrive = 20 mv 0.95 s overdrive = 40 mv 0.65 v i = 1.4-v step at in + 0.15 t f fall time f = 10 khz, c l = 50 pf overdrive = 50 mv 50 ns t r rise time f = 10 khz, c l = 50 pf overdrive = 50 mv 125 ns ? simultaneous switching of inputs causes degradation in output response.
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 8 post office box 655303 ? dallas, texas 75265 principles of operation lincmos process the lincmos process is a linear polysilicon-gate cmos process. primarily designed for single-supply applications, lincmos products facilitate the design of a wide range of high-performance analog functions from operational amplifiers to complex mixed-mode converters. this short guide is intended to answer the most frequently asked questions related to the quality and reliability of lincmos products. direct further questions to the nearest ti field sales office. electrostatic discharge cmos circuits are prone to gate oxide breakdown when exposed to high voltages even if the exposure is only for very short periods of time. electrostatic discharge (esd) is one of the most common causes of damage to cmos devices. it can occur when a device is handled without proper consideration for environmental electrostatic charges, e.g., during board assembly. if a circuit in which one amplifier from a dual op amp is being used and the unused pins are left open, high voltages tends to develop. if there is no provision for esd protection, these voltages may eventually punch through the gate oxide and cause the device to fail. to prevent voltage buildup, each pin is protected by internal circuitry. standard esd-protection circuits safely shunt the esd current by providing a mechanism whereby one or more transistors break down at voltages higher than the normal operating voltages but lower than the breakdown voltage of the input gate. this type of protection scheme is limited by leakage currents which flow through the shunting transistors during normal operation after an esd voltage has occurred. although these currents are small, on the order of tens of nanoamps, cmos amplifiers are often specified to draw input currents as low as tens of picoamps. to overcome this limitation, ti design engineers developed the patented esd-protection circuit shown in figure 1. this circuit can withstand several successive 2-kv esd pulses, while reducing or eliminating leakage currents that may be drawn through the input pins. a more detailed discussion of the operation of the ti esd-protection circuit is presented on the next page. all input and output pins on lincmos and advanced lincmos products have associated esd-protection circuitry that undergoes qualification testing to withstand 2000 v discharged from a 100-pf capacitor through a 1500- ? resistor (human body model) and 200 v from a 100-pf capacitor with no current-limiting resistor (charged device model). these tests simulate both operator and machine handling of devices during normal test and assembly operations. to protected circuit d3 r2 q2 d2 d1 q1 input gnd r1 v dd figure 1. lincmos esd-protection schematic
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 9 post office box 655303 ? dallas, texas 75265 principles of operation input protection circuit operation texas instruments patented protection circuitry allows for both positive- and negative-going esd transients. these transients are characterized by extremely fast rise times and usually low energies, and can occur both when the device has all pins open and when it is installed in a circuit. positive esd transients initial positive charged energy is shunted through q1 to v ss . q1 turns on when the voltage at the input rises above the voltage on the v dd pin by a value equal to the v be of q1. the base current increases through r2 with input current as q1 saturates. the base current through r2 forces the voltage at the drain and gate of q2 to exceed its threshold level (v t 22 to 26 v) and turn q2 on. the shunted input current through q1 to v ss is now shunted through the n-channel enhancement-type mosfet q2 to v ss . if the voltage on the input pin continues to rise, the breakdown voltage of the zener diode d3 is exceeded, and all remaining energy is dissipated in r1 and d3. the breakdown voltage of d3 is designed to be 24 to 27 v, which is well below the gate- oxide voltage of the circuit to be protected. negative esd transients the negative charged esd transients are shunted directly through d1. additional energy is dissipated in r1 and d2 as d2 becomes forward biased. the voltage seen by the protected circuit is ? 0.3 v to ? 1 v (the forward voltage of d1 and d2). circuit-design considerations lincmos products are being used in actual circuit environments that have input voltages that exceed the recommended common-mode input voltage range and activate the input protection circuit. even under normal operation, these conditions occur during circuit power up or power down, and in many cases, when the device is being used for a signal conditioning function. the input voltages can exceed v icr and not damage the device only if the inputs are current limited. the recommended current limit shown on most product data sheets is 5 ma. figures 2 and 3 show typical characteristics for input voltage versus input current. normal operation and correct output state can be expected even when the input voltage exceeds the positive supply voltage. again, the input current should be externally limited even though internal positive current limiting is achieved in the input protection circuit by the action of q1. when q1 is on, it saturates and limits the current to approximately 5-ma collector current by design. when saturated, q1 base current increases with input current. this base current is forced into the v dd pin and into the device i dd or the v dd supply through r2 producing the current limiting effects shown in figure 2. this internal limiting lasts only as long as the input voltage is below the v t of q2. when the input voltage exceeds the negative supply voltage, normal operation is affected and output voltage states may not be correct. also, the isolation between channels of multiple devices (duals and quads) can be severely affected. external current limiting must be used since this current is directly shunted by d1 and d2 and no internal limiting is achieved. if normal output voltage states are required, an external input voltage clamp is required (see figure 4).
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 10 post office box 655303 ? dallas, texas 75265 principles of operation circuit-design considerations (continued) figure 2 ? input current ? ma v dd v dd + 4 v dd + 8 v dd + 12 v i ? input voltage ? v input current vs input voltage t a = 25 c 8 7 6 5 4 3 2 1 0 i i figure 3 v dd ? 0.3 v i ? input voltage ? v input current vs input voltage t a = 25 c v dd ? 0.5 v dd ? 0.7 v dd ? 0.9 10 9 8 7 6 5 4 3 2 1 0 ? input current ? ma i i + ? 1/2 tlc3704 v ref v i v dd see note a r i note a: if the correct input state is required when the negative input exceeds gnd, a schottky clamp is required. negative voltage input current limit : r i v i v dd ( 0.3 v) 5ma r i v i v dd 0.3 v 5ma positive voltage input current limit : figure 4. typical input current-limiting configuration for a lincmos comparator
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 11 post office box 655303 ? dallas, texas 75265 parameter measurement information the tlc3704 contains a digital output stage which, if held in the linear region of the transfer curve, can cause damage to the device. conventional operational amplifier/comparator testing incorporates the use of a servo loop which is designed to force the device output to a level within this linear region. since the servo-loop method of testing cannot be used, we offer the following alternatives for measuring parameters such as input offset voltage, common-mode rejection, etc. to verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown in figure 5(a). with the noninverting input positive with respect to the inverting input, the output should be high. with the input polarity reversed, the output should be low. a similar test can be made to verify the input offset voltage at the common-mode extremes. the supply voltages can be slewed as shown in figure 5(b) for the v icr test, rather than changing the input voltages, to provide greater accuracy. + ? 5 v applied v io limit v o + ? 1 v applied v io limit v o ? 4 v (a) v io with v ic = 0 v (b) v io with v ic = 4 v figure 5. method for verifying that input offset voltage is within specified limits a close approximation of the input offset voltage can be obtained by using a binary search method to vary the differential input voltage while monitoring the output state. when the applied input voltage differential is equal, but opposite in polarity, to the input offset voltage, the output changes states. figure 6 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the comparator in the linear region. the circuit consists of a switching mode servo loop in which ic1a generates a triangular waveform of approximately 20-mv amplitude. ic1b acts as a buffer, with c2 and r4 removing any residual d.c. offset. the signal is then applied to the inverting input of the comparator under test, while the noninverting input is driven by the output of the integrator formed by ic1c through the voltage divider formed by r8 and r9. the loop reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input exactly equals the input offset voltage. voltage divider r8 and r9 provides an increase in the input offset voltage by a factor of 100 to make measurement easier. the values of r5, r7, r8, and r9 can significantly influence the accuracy of the reading; therefore, it is suggested that their tolerance level be one percent or lower. measuring the extremely low values of input current requires isolation from all other sources of leakage current and compensation for the leakage of the test socket and board. with a good picoammeter, the socket and board leakage can be measured with no device in the socket. subsequently, this open socket leakage value can be subtracted from the measurement obtained with a device in the socket to obtain the actual input current of the device.
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 12 post office box 655303 ? dallas, texas 75265 parameter measurement information ? + dut v dd + ? ? + ? + c2 1 f r4 47 k ? r5 1.8 k ? 1% c3 0.68 f ic1c 1/4 tlc274cn ic1a 1/4 tlc274cn ic1b 1/4 tlc274cn r6 1 m ? r7 1.8 k ? 1% r8 10 k ? 1% r1 240 k ? r2 10 k ? c1 0.1 f r3 100 ? c4 0.1 f integrator r9 100 ? 1% buffer triangle generator v io (x100) figure 6. circuit for input offset voltage measurement response time is defined as the interval between the application of an input step function and the instant when the output reaches 50% of its maximum value. response time for the low-to-high-level output is measured from the leading edge of the input pulse, while response time for the high-to-low-level output is measured from the trailing edge of the input pulse. response time measurement at low input signal levels can be greatly affected by the input offset voltage. the offset voltage should be balanced by the adjustment at the inverting input as shown in figure 7, so that the circuit is just at the transition point. a low signal, for example 105-mv or 5-mv overdrive, causes the output to change state.
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 13 post office box 655303 ? dallas, texas 75265 parameter measurement information + ? dut v dd c l (see note a) pulse generator 10 ? 10-turn potentiometer 1 v ? 1 v 1 k ? 50 ? 1 f 0.1 f test circuit 100 mv input overdrive 90% 50% 10% t r t plh 100 mv input overdrive 90% 50% 10% t f t phl low-to-high level output high-to-low level output voltage waveforms note a: c l includes probe and jig capacitance. figure 7. response, rise, and fall times circuit and voltage waveforms
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 14 post office box 655303 ? dallas, texas 75265 typical characteristics table of graphs figure v io input offset voltage distribution 8 i ib input bias current vs free-air temperature 9 cmrr common-mode rejection ratio vs free-air temperature 10 k svr supply-voltage rejection ratio vs free-air temperature 11 v oh high level out p ut current vs free-air temperature 12 v oh high - level output current vs high-level output current 13 v ol low level out p ut voltage vs low-level output current 14 v ol low - level output voltage vs free-air temperature 15 t t output transition time vs load capacitance 16 supply current response to an output voltage transition 17 low-to-high-level output response for various input overdrives 18 high-to-low-level output response for various input overdrives 19 t plh low-to-high-level output response time vs supply voltage 20 t phl high-to-low-level output response time vs supply voltage 21 vs frequenc y 22 i dd supply current qy vs supply voltage 23 dd y vs free-air temperature 24 figure 8 number of units v dd = 5 v v ic = 2.5 v t a = 25 c ? 5 ? 4 ? 3 ? 2 ? 10 1 2 3 4 5 v io ? input offset voltage ? mv distribution of input offset voltage ? 200 180 160 140 120 100 80 60 40 20 0 698 units tested from 4 wafer lots ? ? ? ? ? ? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ? ? ? ? ? ? ? figure 9 i t a ? free-air temperature ? c ib ? input bias current ? na 25 50 75 100 125 10 1 0.1 0.01 0.001 input bias current vs free-air temperature ? v dd = 5 v v ic = 2.5 v ? data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various dev ices.
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 15 post office box 655303 ? dallas, texas 75265 typical characteristics ? figure 10 cmrr ? common-mode rejection ratio ? db t a ? free-air temperature ? c common-mode rejection ratio vs free-air temperature ? 75 ? 50 ? 25 0 25 50 75 100 125 90 88 86 84 82 80 78 76 74 72 70 v dd = 5 v figure 11 ? 75 ? 50 ? 25 0 25 50 75 100 125 k svr ? supply voltage rejection ratio ? db t a ? free-air temperature ? c supply voltage rejection ratio vs free-air temperature v dd = 5 v to 10 v 90 88 86 84 82 80 78 76 74 72 70 figure 12 5 t a ? free-air temperature ? c high-level output voltage vs free-air temperature v oh ? high-level outout voltage ? v v dd = 5 v i oh = ? 4 ma ? 75 ? 50 ? 25 0 25 50 75 100 125 4.9 4.8 4.7 4.6 4.5 4.55 4.65 4.75 4.85 4.95 figure 13 v dd = 16 v i oh ? high-level output current ? ma high-level output voltage vs high-level output current v oh t a = 25 c 3 v 4 v 5 v 10 v 0 ? 2.5 ? 5 ? 7.5 ? 10 ? 12.5 ? 15 ? 17.5 ? 20 ? high-input level output voltage ? v v dd ? 0.25 ? 0.5 ? 0.75 ? 1 ? 1.25 ? 1.5 ? 1.75 ? 2 ? data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various dev ices.
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 16 post office box 655303 ? dallas, texas 75265 typical characteristics ? figure 14 5 v i ol ? low-level output current ? ma 0 2 4 6 8 1012141618 20 v ol ? low-level output voltage ? v low-level output voltage vs low-level output current 3 v 10 v 1.5 1.25 1 0.75 0.5 0.25 0 v dd = 16 v 4 v t a = 25 c figure 15 ? 75 ? 50 ? 25 0 25 50 75 100 125 t a ? free-air temperature ? c low-level output voltage vs free-air temperature v ol ? low-level output voltage ? mv 400 350 300 250 200 150 100 50 0 v dd = 5 v i ol = 4 ma figure 16 0 200 400 600 800 1000 c l ? load capacitance ? pf t t ? transition time ? ns output transition time vs load capacitance 250 225 200 175 150 125 100 75 50 25 0 v dd = 5 v t a = 25 c rise time fall time figure 17 i dd ? supply supply current response to an output voltage transition current ? ma t ? time output voltage ? v 10 5 0 5 0 v dd = 5 v c l = 50 pf f = 10 khz ? data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various dev ices.
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 17 post office box 655303 ? dallas, texas 75265 typical characteristics figure 18 012345 40 mv 20 mv 10 mv 5 mv 2 mv v o ? output voltage ? v input voltage ? mv differential low-to-high-level output response for various input overdrives t plh ? low-to-high-level output response time ? s 5 0 100 0 v dd = 5 v t a = 25 c c l = 50 pf figure 19 40 mv 20 mv 10 mv 5 mv 2 mv high-to-low-level output response for various input overdrives t phl ? high-to-low-level output response time ? s v o ? output voltage ? v input voltage ? mv differential 5 0 100 0 012 345 v dd = 5 v t a = 25 c c l = 50 pf figure 20 low-to-high-level output response time vs supply voltage 6 5 4 3 2 1 0 0 2 4 6 810121416 v dd ? supply voltage ? v t plh ? low-to-high-level output response ? s overdrive = 2 mv c l = 50 pf t a = 25 c 5 mv 10 mv 20 mv 40 mv figure 21 high-to-low-level output response time vs supply voltage 6 5 4 3 2 1 0 0 2 4 6 8 101214 16 v dd ? supply voltage ? v t phl ? high-to-low-level output response ? s c l = 50 pf t a = 25 c 5 mv 10 mv 20 mv 40 mv overdrive = 2 mv
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 18 post office box 655303 ? dallas, texas 75265 typical characteristics ? figure 22 average supply current (per comparator) vs frequency 10000 1000 100 10 v ? average supply current ? dd a 0.01 0.1 1 10 100 f ? frequency ? khz t a = 25 c c l = 50 pf v dd = 16 v 10 v 5 v 4 v 3 v figure 23 supply current vs supply voltage v dd ? supply voltage ? v 80 70 60 50 40 30 20 10 0 0246 810121416 t a = 25 c t a = 125 c v ? supply current ? dd a t a = ? 55 c t a = 85 c t a = ? 40 c outputs low no loads supply current vs free-air temperature 30 25 20 15 10 5 0 ? 75 ? 50 ? 25 0 25 50 75 100 125 t a ? free-air temperature ? c i dd ? supply current ? a v dd = 5 v no load outputs low outputs high figure 24 ? data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various dev ices.
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 19 post office box 655303 ? dallas, texas 75265 application information the inputs should always remain within the supply rails in order to avoid forward biasing the diodes in the electrostatic discharge (esd) protection structure. if either input exceeds this range, the device is not damaged as long as the input is limited to less than 5 ma. to maintain the expected output state, the inputs must remain within the common-mode range. for example, at 25 c with v dd = 5 v, both inputs must remain between ? 0.2 v and 4 v to ensure proper device operation. to ensure reliable operation, the supply should be decoupled with a capacitor (0.1 f) that is positioned as close to the device as possible. output and supply current limitations should be watched carefully since the tlc3704 does not provide current protection. for example, each output can source or sink a maximum of 20 ma; however, the total current to ground can only be an absolute maximum of 60 ma. this prohibits sinking 20 ma from each of the four outputs simultaneously since the total current to ground would be 80 ma. the tlc3704 has internal esd-protection circuits that prevents functional failures at voltages up to 2000 v as tested under mil-std-883c, method 3015.2; however, care should be exercised in handling these devices as exposure to esd may result in the degradation of the device parametric performance. table of applications figure pulse-width-modulated motor speed controller 25 enhanced supply supervisor 26 two-phase nonoverlapping clock generator 27 micropower switching regulator 28
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 20 post office box 655303 ? dallas, texas 75265 application information c1 0.01 f (see note b) 5 v 1/2 tlc3704 motor speed control potentiometer + ? + ? 10 k ? 100 k ? 10 k ? 10 k ? see note a 1/2 tlc3704 10 k ? 5 v dir en sn75603 half-h driver 12 v motor dir en 12 v direction control s1 spdt 5 v 5 v sn75604 half-h driver notes: a. the recommended minimum capacitance is 10 f to eliminate common ground switching noise. b. adjust c1 for change in oscillator frequency figure 25. pulse-width-modulated motor speed controller
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 21 post office box 655303 ? dallas, texas 75265 application information 1/2 tlc3704 to p interrupt early power fail + ? + ? 1 k ? 3.3 k ? c t (see note b) 1/2 tlc3704 10 k ? 5 v 5 v 12-v sense r2 r1 v (unreg) (see note a) 1 f 12 v resin ref c t gnd reset sense v cc to p reset monitors 5 vdc rail monitors 12 vdc rail early power fail warning tl7705a 2.5 v notes: a. v (unreg) 2.5 (r1 +r2) r2 b. the value of c t determines the time delay of reset. figure 26. enhanced supply supervisor
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 22 post office box 655303 ? dallas, texas 75265 application information ? + 22 k ? c1 0.01 f (see note a) 1/2 tlc3704 r1 100 k ? (see note b) 12 v 100 k ? 1/2 tlc3704 out2 ? + ? + 1/2 tlc3704 100 k ? 100 k ? 12 v out1 12 v r2 5 k ? (see note c) r3 100 k ? (see note b) out2 out1 12 v notes: a. adjust c1 for a change in oscillator frequency where: 1/f = 1.85(100 k ? )c1 b. adjust r1 and r3 to change duty cycle c. adjust r2 to change deadtime figure 27. two-phase nonoverlapping clock generator
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 23 post office box 655303 ? dallas, texas 75265 application information + ? 100 k ? c1 180 f (see note a) 1/2 tlc3704 100 k ? r2 100 k ? 100 k ? 100 k ? v i v i ? + 1/2 tlc3704 v i + ? tlc271 (see note b) 270 k ? v i 100 k ? c2 100 pf 100 k ? r = 6 ? l = 1 mh (see note d) r l 470 f v o r1 v i 6 v to 16 v i l 0.01 ma to 0.25 ma v o 2.5 (r1 r2) r2 lm385 2.5 v 47 f tantalum in5818 v i gs sk9504 (see note c) d + notes: a. adjust c1 for a change in oscillator frequency b. tlc271 ? tie pin 8 to pin 7 for low bias operation c. sk9504 ? vds = 40 v ids = 1 a will d. to achieve microampere current drive, the inductance of the circuit must be increased. figure 28. micropower switching regulator
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 24 post office box 655303 ? dallas, texas 75265 mechanical data d (r-pdso-g**) plastic small-outline package 8 pins shown 8 0.197 (5,00) a max a min (4,80) 0.189 0.337 (8,55) (8,75) 0.344 14 0.386 (9,80) (10,00) 0.394 16 dim pins ** 4040047/e 09/01 0.069 (1,75) max seating plane 0.004 (0,10) 0.010 (0,25) 0.010 (0,25) 0.016 (0,40) 0.044 (1,12) 0.244 (6,20) 0.228 (5,80) 0.020 (0,51) 0.014 (0,35) 1 4 8 5 0.150 (3,81) 0.157 (4,00) 0.008 (0,20) nom 0 ? 8 gage plane a 0.004 (0,10) 0.010 (0,25) 0.050 (1,27) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). d. falls within jedec ms-012
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 25 post office box 655303 ? dallas, texas 75265 mechanical data fk (s-cqcc-n**) leadless ceramic chip carrier 4040140 / c 11/95 28 terminals shown b 0.358 (9,09) max (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) a no. of min max 0.358 0.660 0.761 0.458 0.342 (8,69) min (11,23) (16,26) 0.640 0.740 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32) (18,78) ** 20 28 52 44 68 84 0.020 (0,51) terminals 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 12 13 14 15 16 18 17 11 10 8 9 7 5 4 3 2 0.020 (0,51) 0.010 (0,25) 6 1 28 26 27 19 21 b sq a sq 22 23 24 25 20 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package can be hermetically sealed with a metal lid. d. the terminals are gold-plated. e. falls within jedec ms-004
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 26 post office box 655303 ? dallas, texas 75265 mechanical data j (r-gdip-t**) ceramic dual-in-line 1 20 0.290 (7,87) 0.310 0.975 (24,77) (23,62) 0.930 (7,37) 0.245 (6,22) (7,62) 0.300 16 14 pins ** 0.290 (7,87) 0.310 0.785 (19,94) (19,18) 0.755 (7,37) 0.310 (7,87) (7,37) 0.290 0.755 (19,18) (19,94) 0.785 0.245 (6,22) (7,62) 0.300 a 0.300 (7,62) (6,22) 0.245 a min a max b max b min c min c max dim 0 ? 15 seating plane 0.014 (0,36) 0.008 (0,20) 4040083/e 03/99 c 8 7 0.020 (0,51) min b 0.070 (1,78) 0.100 (2,54) 0.065 (1,65) 0.045 (1,14) 14 leads shown 14 0.015 (0,38) 0.023 (0,58) 0.100 (2,54) 0.200 (5,08) max 0.130 (3,30) min notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package is hermetically sealed with a ceramic lid using glass frit. d. index point is provided on cap for terminal identification. e. falls within mil std 1835 gdip1-t14, gdip1-t16, and gdip1-t20
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 27 post office box 655303 ? dallas, texas 75265 mechanical data n (r-pdip-t**) plastic dual-in-line package 0.325 (8,26) 0.300 (7,62) 0.010 (0,25) nom gauge plane 0.015 (0,38) 0.430 (10,92) max 20 0.975 (24,77) 0.940 (23,88) 18 0.920 0.850 14 0.775 0.745 (19,69) (18,92) 16 0.775 (19,69) (18,92) 0.745 a min dim a max pins ** (23,37) (21,59) seating plane 14/18 pin only 4040049/d 02/00 9 8 0.070 (1,78) max a 0.035 (0,89) max 0.020 (0,51) min 16 1 0.015 (0,38) 0.021 (0,53) 0.200 (5,08) max 0.125 (3,18) min 0.240 (6,10) 0.260 (6,60) m 0.010 (0,25) 0.100 (2,54) 16 pins shown notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. falls within jedec ms-001 (20-pin package is shorter than ms-001).
tlc3704, tlc3704q quad micropower lincmos ? voltage comparators slcs117b ? november 1986 ? revised january 2002 28 post office box 655303 ? dallas, texas 75265 mechanical data pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 ? 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) 5962-9096901m2a active lccc fk 20 1 none post-plate level-nc-nc-nc 5962-9096901mca active cdip j 14 1 none a42 snpb level-nc-nc-nc tlc3704cd active soic d 14 50 pb-free (rohs) cu nipdau level-2-260c-1year/ level-1-220c-unlim tlc3704cdr active soic d 14 2500 pb-free (rohs) cu nipdau level-2-260c-1year/ level-1-220c-unlim tlc3704cn active pdip n 14 25 pb-free (rohs) cu nipdau level-nc-nc-nc tlc3704cnsr active so ns 14 2000 pb-free (rohs) cu nipdau level-2-260c-1year/ level-1-220c-unlim tlc3704cpw active tssop pw 14 90 none cu nipdau level-1-220c-unlim tlc3704cpwle obsolete tssop pw 14 none call ti call ti tlc3704cpwr active tssop pw 14 2000 none cu nipdau level-1-220c-unlim tlc3704id active soic d 14 50 pb-free (rohs) cu nipdau level-2-260c-1year/ level-1-220c-unlim tlc3704idr active soic d 14 2500 pb-free (rohs) cu nipdau level-2-260c-1year/ level-1-220c-unlim tlc3704in active pdip n 14 25 pb-free (rohs) cu nipdau level-nc-nc-nc tlc3704ipw active tssop pw 14 90 none cu nipdau level-1-220c-unlim tlc3704ipwr active tssop pw 14 2000 none cu nipdau level-1-220c-unlim tlc3704md active soic d 14 50 none cu nipdau level-1-220c-unlim tlc3704mdr active soic d 14 2500 none cu nipdau level-1-220c-unlim TLC3704MFKb active lccc fk 20 1 none post-plate level-nc-nc-nc tlc3704mj active cdip j 14 1 none a42 snpb level-nc-nc-nc tlc3704mjb active cdip j 14 1 none a42 snpb level-nc-nc-nc (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - may not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. none: not yet available lead (pb-free). pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean "pb-free" and in addition, uses package materials that do not contain halogens, including bromine (br) or antimony (sb) above 0.1% of total product weight. (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedecindustry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on package option addendum www.ti.com 22-feb-2005 addendum-page 1
incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 22-feb-2005 addendum-page 2
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2005, texas instruments incorporated

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