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infineon technologies ag 1 v0.6, 2003-01-07 hys64d128020gbdl-[6/7]-a ddr-sdram so-dimm modules 2.5v 200pin ddr-i sdram small outline modules 1gb module pc1600, pc2100 & pc2700 preliminary data sheet v0.6, 2003-01-07 the hys64d128020gbdl are industry standard 200-pin 8-byte small outline dual in-line memory modules (dimms) organized as 128m x 64 in two memory banks. the memory array is designed with double data rate synchronous drams. a va riety of decoupling capacitors are mounted on the pc board. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. ? 200-pin unbuffered 8-byte dual-in-line ddr-i sdram non-parity small outline modules 128m x 64 organization with two memory banks jedec standard double data rate synchronous drams (ddr-i sdram) single +2.5v ( 0.2v) power supply uses eight 1gbit ddr-i sdram components (2x 64mb x8) made of stacked 512mb dies in p-tfbga package. programmable cas latency, burst length, and wrap sequence (sequential & interleave) auto refresh (cbr) and self refresh all inputs and outputs sstl_2 compatible serial presence detect with e 2 prom jedec standard form factor: 67.60mm 31.75mm 3.80mm gold plated contacts performance -6 -7 unit component speed grade ddr333 ddr266a module speed grade pc2700 pc2100 f ck clock frequency (max.) @ cl = 2.5 166 143 mhz f ck clock frequency (max.) @ cl = 2 133 133 mhz
hys64d128020gbdl-[6/7]-a ddr-sdram so-dimm modules infineon technologies ag 2 v0.6, 2003-01-07 ordering information type compliance code description sdram technology hys64d128020gbdl-6-a pc2700s -2533-0-z 1gb so-dimm w/ 2 banks 512mbit stacked die in a fbga hys64d128020gbdl-7- a pc2100s-2033-0-z note: all part numbers end with a place code, designating the silicon die revision. reference information available on request. example: hys 64d128020gbdl-8-a, indicating rev.a die is used for ddr-sdram components. the compliance code which is printed on the module labels describes the speed sort class (?e.g. pc2100?), the module type (?s?), the latencies (e.g. 2033 means cas latency = 2.0, rcd latency = 3 and row precharge latency = 3), the jedec spd revision (?0?) and the raw card used on this dimm (?z?). pin definitions and functions pin name pin function pin name pin function a0 - a12 address inputs cs0, cs1 chip selects ba0, ba1 bank selects v dd power (+ 2.5 v) dq0 - dq63 data input/output v ss ground ras row address strobe v ddq i/o driver power supply cas column address strobe v ddid vdd indentification flag we read/write input v ref i/o reference supply cke0 - cke1 clock enable v ddspd serial eeprom power supply dqs0 - dqs8 sdram low data strobes scl serial bus clock clk0 - clk1, sdram clock (positive lines) sda serial bus data line clk0 - clk1 sdram clock (negative lines) sa0 - sa2 slave address select dm0 - dm8 data masks nc no connect dqs0 - dqs8 data strobes du dont use, reserved address format density organization memory banks sdrams # of sdrams sdram density # of row/ bank/ column bits refresh period interval 1024 mb 128m 64 2 64m x 8 16 512 mbit 13/2/11 8k 64 ms 7.8 s
hys64d128020gbdl-[6/7]-a ddr-sdram so-dimm modules infineon technologies 3 v0.6, 2003-01-07 pin configuration pin # front side pin # back side pin # front side pin # back side pin # front side pin # back side pin # front side pin # back side 1 vref 2 vref 51 vss 52 vss 101 a9 102 a8 151 dq42 152 dq46 3 vss 4 vss 53 dq19 54 dq23 103 vss 104 vss 153 dq43 154 dq47 5 dq0 6 dq4 55 dq24 56 dq28 105 a7 106 a6 155 vdd 156 vdd 7 dq1 8 dq5 57 vdd 58 vdd 107 a5 108 a4 157 vdd 158 ck1 9 vdd 10 vdd 59 dq25 60 dq29 109 a3 110 a2 159 vss 160 ck1 11 dqs0 12 dm0 61 dqs3 62 dm3 111 a1 112 a0 161 vss 162 vss 13 dq2 14 dq6 63 vss 64 vss 113 vdd 114 vdd 163 dq48 164 dq52 15 vss 16 vss 65 dq26 66 dq30 115 a10/ap 116 ba1 165 dq49 166 dq53 17 dq3 18 dq7 67 dq27 68 dq31 117 ba0 118 ras 167 vdd 168 vdd 19 dq8 20 dq12 69 vdd 70 vdd 119 we 120 cas 169dqs6170 dm6 21 vdd 22 vdd 71 (cb0) 72 (cb4) 121 cs0 122 cs1 171dq50172dq54 23 dq9 24 dq13 73 (cb1) 74 (cb5) 123 du 124 du 173 vss 174 vss 25 dqs1 26 dm1 75 vss 76 vss 125 vss 126 vss 175 dq51 176 dq55 27 vss 28 vss 77 (dqs8) 78 (dm8) 127 dq32 128 dq36 177 dq56 178 dq60 29 dq10 30 dq14 79 (cb2) 80 (cb6) 129 dq33 130 dq37 179 vdd 180 vdd 31 dq11 32 dq15 81 vdd 82 vdd 131 vdd 132 vdd 181 dq57 182 dq61 33 vdd 34 vdd 83 (cb3) 84 (cb7) 133 dqs4 134 dm4 183 dqs7 184 dm7 35 ck0 36 vdd 85 du 86 du 135 dq34 136 dq38 185 vss 186 vss 37 ck0 38 vss 87 vss 88 vss 137 vss 138 vss 187 dq58 188 dq62 39 vss 40 vss 89 (ck2) 90 vss 139 dq35 130 dq39 189 dq59 190 dq63 41 dq16 42 dq20 91 (ck2) 92 vdd 141 dq40 142 dq44 191 vdd 192 vdd 43 dq17 44 dq21 93 vdd 94 vdd 143 vdd 144 vdd 193 sda 194 sa0 45 vdd 46 vdd 95 cke1 96 cke0 145 dq41 146 dq45 195 scl 196 sa1 47 dqs2 48 dm2 97 du 98 du 147 dqs5 148 dm5 197 vddspd 198 sa2 49 dq18 50 dq22 99 a12 100 a11 149 vss 150 vss 199 vddid 200 du note: pins 71, 72, 73, 74, 77, 78, 79, 80, 83, 84, 89 and 91 are reserved for x72 variants of this module and are not used on the x64 versions. pin 86 is reserved for a registered variant of this module and is not used on the unbuffered version pin 1 pin 39 pin 41 pin 199 pin 2 pin 40 pin 42 pin 200 front side back side
hys64d128020gbdl-[6/7]-a ddr-sdram so-dimm modules infineon technologies ag 4 v0.6, 2003-01-07 block diagram: two banks 128m x 64 ddr-sdram so-dimm modules using x8 organized sdrams cs0 dqs dq[7:0] cs0 cs1 dqs0 dq[7:0] a0-a12, ba0, ba1 vdd vss d0 - d7 d0 - d7 d0 - d7, spd d0 - d7 ras , cas , we cke0 d0 cs1 serial spd (256wordx8bit) scl sda sa0 sa1 sa2 1. dq wiring may differ than describes in this drawing, however dq/dm/dqs relationship must be maintained as shown. 8 loads clk0 / clk0 clk1 / clk1 8 loads 2. all resistors are 22 ohm. dm0 dm dqs1 dq[15:8] dm1 dqs2 dq[23:16] dm2 dqs3 dq[31:24] dm3 d0 - d7 cke1 d0 - d7 vddspd spd vref d0 - d7 vddid open d0 - d7, spd scl sda a0 a1 a2 wp 8x cs0 dqs dq[7:0] d1 cs1 dm 8x cs0 dqs dq[7:0] d2 cs1 dm 8x cs0 dqs dq[7:0] d3 cs1 dm 8x cs0 dqs dq[7:0] dqs4 dq[39:32] d4 cs1 dm4 dm dqs5 dq[47:40] dm5 dqs6 dq[55:48] dm6 dqs7 dq[63:56] dm7 8x cs0 dqs dq[7:0] d5 cs1 dm 8x cs0 dqs dq[7:0] d6 cs1 dm 8x cs0 dqs dq[7:0] d7 cs1 dm 8x note
hys64d128020gbdl-[6/7]-a ddr-sdram so-dimm modules infineon technologies 5 v0.6, 2003-01-07 absolute maximum ratings parameter symbol limit values unit min. max. input / output voltage relative to v ss v in, v out -0.5 3.6 v power supply voltage on v dd /v ddq to v ss v dd, v ddq -0.5 3.6 v storage temperature range t stg -55 +150 o c power dissipation (per sdram component) p d ?1w data out current (short circuit) i os ?50ma permanent device damage may occur if ?absolute maximum ratings? are exceeded. functional operation should be restricted to recommended operation conditions. exposure to higher than recommended voltage for extended periods of time affect device reliability supply voltage levels parameter symbol limit values unit notes min. nom. max. device supply voltage v dd 2.3 2.5 2.7 v output supply voltage v ddq 2.3 2.5 2.7 v 1 input reference voltage v ref 0.49 x v ddq 0.5 x v ddq 0.51 x v ddq v2 termination voltage v tt v ref -0.04 v ref v ref +0.04 v 3 eeprom supply voltage v ddspd 2.3 2.5 3.6 v 1 under all conditions, v ddq must be less than or equal to v dd 2 peak to peak ac noise on v ref may not exceed 2% v ref (dc) . v ref is also expected to track noise variations in v ddq . 3 v tt of the transmitting device must track v ref of the receiving device. dc operating conditions (sstl_2 inputs) ( v ddq = 2.5 v, t a=70 c, voltage referenced to v ss) parameter symbol limit values unit notes min. max. dc input logic high v ih (dc) v ref +0.15 v ddq +0.3 v 1 dc input logic low v il (dc) -0.30 v ref -0.15 v input leakage current i il -5 5 a1 output leakage current i ol -5 5 a2 1) the relationship between the v ddq of the driving device and the v ref of the receiving device is what determines noise margins. however, in the case of v ih (max) (input overdrive), it is the v ddq of the receiving device that is referenced. in the case where a device is implemented such that it supports sstl_2 inputs but has no sstl_2 outputs (such as a translator), and therefore no v ddq supply voltage connection, inputs must tolerate input overdrive to 3.0 v (high corner v ddq +300mv). 2) for any pin under test input of 0 v v in v ddq + 0.3 v. values are shown per ddr-sdram component.
hys64d128020gbdl-[6/7]-a ddr-sdram so-dimm modules infineon technologies ag 6 v0.6, 2003-01-07 operating, standby and refresh currents notes 4 idd2p ma 2 idd2f ma 2 idd2q ma 2 idd3p ma 2 idd5 ma 1 1. the module idd values are calculated from the component idd datasheet values as: iddx[component] * m + idd3n[component] * n with m, n number of components of bank 1 and 2; n=0 for 1 bank modules 2. the module idd values are calculated from the component idd datasheet values as: iddx[component] * (m + n) 3. dq i/o (iddq) currents are not included into calculations: module idd values will be measured differently depending on load conditions 4. test condition for typical values : vdd = 2.5v ,ta = 25c, test condition for maximum values: test limit at vdd = 2.7v ,ta = 10c 176 max 1560 1760 160 112 idd7 idd6 operating current : four bank; four bank interleaving with burst length 4; refer to the following page for detailed test conditions. 3440 56 self-refresh current : cke <= 0.2v; external clock on 40 3056 1, 3 ma symbol unit parameter/condition idd4w idd4r idd3n 528 precharge quiet standby current : /cs >= vih min, all banks idle; cke >= vih min; address and other control inputs stable at >= vih min or <= vil max; vin = vref for dq, dqs and dm. 720 auto-refresh current : trc = trfc min, distributed refresh precharge power-down standby current : all banks idle; power-down mode; cke <= vil max 2600 656 320 800 1880 1960 ma active standby current : one bank active; cs >= vih min; cke >= vih min; trc = tras max; dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle operating current : one bank active; burst length 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr200 and ddr266(a), cl=3 for ddr333 and ddr400; iout = 0ma operating current : one bank active; burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr200 and ddr266(a), cl=3 for ddr333 and ddr400 3000 2536 40 56 idd0 operating current : one bank; active/read/precharge; burst length 4; refer to the following page for detailed test conditions. operating current : one bank; active / precharge; trc = trc min; dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles idd1 precharge floating standby current : /cs >= vih min, all banks idle; cke >= vih min; address and other control inputs changing once per clock cycle, vin = vref for dq, dqs and dm. ma 1, 3 ma 2 active power-down standby current : one bank active; power-down mode; cke <= vil max; vin = vref for dq, dqs and dm. 560 ma 1 1, 3 ma 1 ma 1680 448 288 1600 2480 typ 1360 1552 1gb, 2 banks -6 pc2700s-2533 120 576 440 256 688 1680 1600 2328 typ 1208 1416 1gb, 2 banks -7 pc2100s-2033 max 1400 1600 496 384 224 608 1424 1368 2200
hys64d128020gbdl-[6/7]-a ddr-sdram so-dimm modules infineon technologies 7 v0.6, 2003-01-07 electrical characteristics & ac timing for ddr-i components (for reference only) (0 c t a 70 c v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v) symbol parameter ddr333 -6 ddr266a -7 unit notes min. max. min. max. t ac dq output access time from ck/ck - 0.7 + 0.7 0.75 0.75 ns 1-4 t dqsck dqs output access time from ck/ck - 0.6 + 0.6 0.75 0.75 ns 1-4 t ch ck high-level width 0.45 0.55 0.45 0.55 t ck 1-4 t cl ck low-level width 0.45 0.55 0.45 0.55 t ck 1-4 t hp clock half period min (t cl, t ch )min (t cl, t ch )ns1-4 t ck clock cycle time cl = 2.5 6 12 7 12 ns 1-4 t ck cl = 2.0 7.5 12 7.5 12 ns 1-4 t dh dq and dm input hold time 0.45 0.5 ns 1-4 t ds dq and dm input setup time 0.45 0.5 ns 1-4 t ipw control and addr. input pulse width (each input) 2.2 2.2 ns 1, 10 t dipw dq and dm input pulse width (each input) 1.75 1.75 ns 1-4, 11 t hz data-out high-impedence time from ck/ck - 0.7 + 0.7 0.75 0.75 ns 1-4, 5 t lz data-out low-impedence time from ck/ck - 0.7 + 0.7 0.75 0.75 ns 1-4, 5 t dqss write command to 1st dqs latching transition 0.75 1.25 0.75 1.25 t ck 1-4 t dqsq dqs-dq skew (for dqs & associated dq signals) 0.40 0.5 ns 1-4 t qhs data hold skew factor + 0.50 + 0.75 ns 1-4 t qh data output hold time from dqs t hp -t qhs t hp -t qhs ns 1-4 t dqsl,h dqs input low (high) pulse width (write cycle) 0.35 0.35 t ck 1-4 t dss dqs falling edge to ck setup time (write cycle) 0.2 0.2 t ck 1-4 t dsh dqs falling edge hold time from ck (write cycle) 0.2 0.2 t ck 1-4 t mrd mode register set command cycle time 2 2 t ck 1-4 t wpres write preamble setup time 0 0 ns 1-4, 7 t wpst write postamble 0.40 0.60 0.40 0.60 t ck 1-4, 6 t wpre write preamble 0.25 0.25 t ck 1-4 t is address and control input setup time fast slew rate 0.75 0.9 ns 2-4, 10,11 slow slew rate 0.8 1.0 ns t ih address and control input hold time fast slew rate 0.75 0.9 ns slow slew rate 0.8 1.0 ns t rpre read preamble 0.9 1.1 0.9 1.1 t ck 1-4 t rpst read postamble 0.40 0.60 0.40 0.60 t ck 1-4 t ras active to precharge command 42 70,000 45 120,000 ns 1-4 t rc active to active/auto-refresh command period 60 65 ns 1-4 t rfc auto-refresh to active/auto-refresh command period 72 75 ns 1-4 t rcd active to read or write delay 18 20 ns 1-4 t rp precharge command period 18 20 ns 1-4 t rrd active bank a to active bank b command 12 15 ns 1-4 t wr write recovery time 15 15 ns 1-4 t dal auto precharge write recovery + precharge time (twr/tck) + (trp/tck) t ck 1-4,9
hys64d128020gbdl-[6/7]-a ddr-sdram so-dimm modules infineon technologies ag 8 v0.6, 2003-01-07 t wtr internal write to read command delay 1 1 t ck 1-4 t xsnr exit self-refresh to non-read command 75 75 ns 1-4 t xsrd exit self-refresh to read command 200 200 t ck 1-4 t refi average periodic refresh interval 7.8 7.8 s1-4, 8 1. input slew rate >=1v/ns for ddr266 & ddr333 and = 1v/ns for ddr200. 2. the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref. ck/ck slew rate are >= 1.0 v/ns. 3. inputs are not recognized as valid until v ref stabilizes. 4. the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 5. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 6. the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 8. a maximum of eight autorefresh commands can be posted to any given ddr sdram device. 9. for each of the terms, if not already an integer, round to th e next highest integer. tck is equ al to the actual system clock cycle time. 10. these parameters guarantee device timing, but they are not necessarily tested on each device 11. fast slew rate >= 1.0 v/ns , slow slew rate >= 0.5 v/ns and < 1v/ns for command/address and ck & ck slew rate >1.0 v/ ns, measured between voh(ac) and vol(ac) symbol parameter ddr333 -6 ddr266a -7 unit notes min. max. min. max.
hys64d128020gbdl-[6/7]-a ddr-sdram so-dimm modules infineon technologies 9 v0.6, 2003-01-07 spd codes byte# description spd entry value pc2100 pc2700 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type ddr-sdram 07 3 number of row addresses 13 0d 4 number of column addresses 11 0b 5 number of dimm banks 2 02 6 module data width x64 40 7 module data width (cont?d) 0 00 8 module interface levels sstl_2.5 04 9 sdram cycle time at cl = 2.5 7ns, 6ns 70 60 10 sdram access time from clock at cl = 2.5 0.75ns, 0.6ns 75 70 11 dimm config non-ecc 00 12 refresh rate/type self-refresh 7.8 s 82 13 sdram width, primary x8 08 14 error checking sdram data width na 00 15 minimum clock delay for back-to-back random column address t ccd =1clk 01 16 burst length supported 2, 4 & 8 0e 17 number of sdram banks 4 04 18 supported cas latencies cas latency = 2 & 2.5 0c 19 cs latencies cs latency = 0 01 20 we latencies write latency = 1 02 21 sdram dimm module attributes unbuffered 20 22 sdram device attributes: general conc. ap weak driver c1 23 min. clock cycle time at cas latency = 2 7.5ns 75 75 24 max. data access time from clock for cl = 2 0.75ns, 0.7ns 75 70 25 minimum clock cycle time at cl = 1.5 not supported 00 26 maximum data access time from clock at cl = 1.5 not supported 00 27 minimum row precharge time 20ns, 18ns 50 48 28 minimum row active to row active delay t rrd 15ns, 12ns 3c 30 29 minimum ras to cas delay t rcd 20ns, 18ns 50 48 30 minimum ras pulse width t ras 45ns, 42ns 2d 2a 31 module bank density (per bank) 512 mbyte 80 32 addr. and command setup time 0.9 ns, 0.75ns 90 75 33 addr. and command hold time 0.9 ns, 0.75ns 90 75 34 data input setup time 0.5ns, 0.45 ns 50 45 35 data input hold time 0.5ns, 0.45 ns 50 45 36-40 superset information ? 00 41 minimum core cycle time trc 65 ns, 60 ns 41 3c 42 min. auto refresh cmd cycle time trfc 75ns, 72 ns 4b 48 43 maximum clock cycle time tck 12 ns 30 44 max. dqs-dq skew tdqsq 0.5 ns, 0.4 ns 32 28 45 x-factor tqhs 0.75ns, 0.5 ns 75 50 46-61 superset information (may be used in future) 00 62 spd revision revision 0.0 00
hys64d128020gbdl-[6/7]-a ddr-sdram so-dimm modules infineon technologies ag 10 v0.6, 2003-01-07 63 checksum for bytes 0 - 62 ? f5 39 64 manufacturers jedec id ? c1 65-71 manufacturer infineo(n) 72 assembly manufacturing location 73-90 module part number 91-92 module revision code 93-94 module manufacturing date 95-98 module serial number 99-127 superset information 128-255 open for customer use byte# description spd entry value pc2100 pc2700
hys64d128020gbdl-[6/7]-a ddr-sdram so-dimm modules infineon technologies ag 11 v0.6, 2003-01-07 package outlines ddr-sdram so-dimm modules l-dim-200-20 detail of chamfer 0.2 - 0.15 0.2 - 0.15 3.8 ma x. 1 0. 1 67.6 63.6 31.75 2.15 11.4 1 39 41 199 47.4 4.2 11.55 0.15 0.13 2.45 20 2.45 1.8 4 6 240 42 200 1.0 4 2.15 2.55 0.25 0.6 detail of contacts 0.45

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