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november 2010 ? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator fan5365 1a / 0.8a, 6mhz digitally programmable regulator features ? high efficiency (>88%) at 6mhz ? 800ma or 1a output current ? regulation maintained with v in from 2.3v to 5.5v ? 6-bit v out programmable from 0.75 to 1.975v ? 6mhz fixed-frequency operation (pwm mode) ? excellent load and line transient response ? small size, 470nh inductor solution ? 2% dc voltage accuracy in pwm mode ? 25ns minimum on-time ? high-efficiency, low-ripple, light-load pfm ? smooth transition between pwm and pfm ? 40 a operating pfm quiescent current ? i 2 c?-compatible interface up to 3.4mbps ? pin-selectable or i 2 c? programmable output voltage ? 9-bump, 1.27 x 1.29mm, 0.4mm pitch wlcsp package applications ? 3g, wifi ? , wimax?, and wibro ? data cards ? netbooks ? , ultra-mobile pcs ? smartreflex?-compliant power supply ? split supply dsps and p solutions omap?, xscale? ? handset graphic processors (nvidia ? , ati) description the fan5365 is a high-frequency, ultra-fast transient response, synchronous step-down, dc-dc converter optimized for low-power applications using small, low-cost inductors and capacitors. the fan5365 supports up to 800ma or 1a load current. the fan5365 is ideal for mobile phones and similar portable applications powered by a single-cell lithium-ion battery. with an output voltage range adjustable via i 2 c? interface from 0.75v to 1.975v, it supports low-voltage dsps and processors, core power supplies, and memory modules in smart phones, data cards, and hand-held computers. the fan5365 operates at 6mhz (nominal) fixed switching frequency in pwm mode. during light-load conditions, the regulator includes a pfm mode to enhance light-load efficiency. the regulator transitions smoothly between pwm and pfm modes with no glitches on v out . in hardware shutdown, the current consumption is reduced to less than 200na. the serial interface is compatible with fast / standard mode, fast mode plus, and high-speed mode i 2 c specifications, allowing transfers up to 3.4mbps. this interface is used for dynamic voltage scaling with 12.5mv voltage steps, for reprogramming the mode of operation (pfm or forced pwm), or to disable/enable the output voltage. the chip's advanced protection features include short-circuit protection and current and temperature limits. during a sustained over-current event, the ic shuts down and restarts after a delay to reduce average power dissipation into a fault. during startup, the ic controls the output slew rate to minimize input current and output overshoot at the end of soft-start. the ic maintains a consistent soft-start ramp, regardless of output load during startup. the fan5365 is available in a 1.27 x 1.29mm, 9-bump wlcsp package. all trademarks are the property of their respective owners
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 2 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator ordering information part number (1) option slave address lsb output current v out programming power-up defaults package a2 a1 a0 ma min. max. vsel0 vsel1 FAN5365UC00X 00 0 1 0 800 0.7500 1.4375 (3) 1.05 1.20 wlcsp-09 fan5365uc02x 02 1 1 0 800 0.7500 1.4375 (3 ) 0.95 1.10 wlcsp-09 fan5365uc03x (2) 03 0 0 0 1000 0.7500 1.5375 1.00 1.20 wlcsp-09 fan5355uc06x (2) 06 0 0 0 1000 1.1875 1.9750 1.80 1.80 wlcsp-09 notes: 1. the ?x? designator on the part number indicates tape and reel packaging. 2. preliminary; not full production release at this time. contact a fairchild representative for information. 3. v out is limited to the maximum voltage for all vsel codes greater than the maximum v out listed. typical application sw q1 q2 modulator pgnd vin c out vout l vout c in en vsel agnd sda scl vin figure 1. typical application table 1. recommended external components component description vendor parameter min. typ. max. units l (l out ) 470nh nominal murata, tdk, fdk l (4) 390 470 600 nh dcr (series r) 80 m c out (5) 0603 (1.6x0.8x0.8), 10 f x5r various c (6) 2.2 10.0 15.0 f c in 0402 (1x0.5x0.25), 4.7 f x5r taiyo-yuden 1.6 4.7 f notes: 4. minimum l incorporates tolerance, temperature, and parti al saturation effects (l decreases when increasing current). 5. a capacitor similar to c in can be used for c out . with 1.4v of bias, a 4.7 f 0402 capacitor minimum value is 2.5 f. the regulator is stable, but transient response degraded due to large signal effects. 6. minimum c is a function of initial tolerance, maximum temperature, and the effective capacitance being reduced due to frequency, dielectric, and voltage bias effects. c in is biased with a higher voltage which reduces its effective capacitance by a larger amount.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 3 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator pin configuration c1 b1 a1 a2 c3 b3 a3 c2 b2 bumps facing down c1 b1 a1 c3 b3 a3 a2 c2 b2 bumps facing up figure 2. wlcsp-09, 0.4mm pitch pin definitions pin # name description a1 vsel voltage select . when high, v out is set by vsel1. when low, v out is set by vsel0. this behavior can be overridden through i 2 c register settings. this pin should not be left floating. a2 vin input voltage . connect to input power source. the connection from this pin to c in should be as short as possible. a3 sda sda . i 2 c interface serial data. this pin should not be left floating. b1 sw switching node . connect to output inductor. b2 scl scl . i 2 c interface serial clock. this pin should not be left floating. b3 en enable . when this pin is high, the circuit is enabled. when low, part enters shutdown mode and input current is minimized. this pin should not be left floating. c1 vout output voltage monitor . tie this pin to the output voltage at c out . this is a signal input pin to the control circuit and does not carry dc current. c2 pgnd power gnd . power return for gate drive and power transistors. connect to agnd on pcb. the connection from this pin to the bottom of c in should be as short as possible. c3 agnd analog gnd . this is the signal ground reference for the ic. all voltage levels are measured with respect to this pin. agnd should be connected to pgnd at a single point.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 4 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. units v cc vin, sw pins ?0.3 6.5 v v out ?0.3 2.5 other pins ?0.3 v in + 0.3 (7) esd electrostatic discharge protection human body model, jesd22-a114 3 kv charged device model, jesd22-c101 1 t j junction temperature ?40 +150 c t stg storage temperature ?65 +150 c t l lead soldering temperature, 10 seconds +260 c note: 7. lesser of 6.5v or v cc +0.3v. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recomm end exceeding them or designing to absolute maximum ratings. symbol parameter min. max. units v in supply voltage 2.3 5.5 v v ccio sda and scl voltage swing (8) 1.2 2.0 v t a ambient temperature ?40 +85 c t j junction temperature ?40 +125 c note: 8. the i 2 c interface operates with t hd;dat = 0 as long as the pull-up voltage for sda and scl is less than 2.5v. if voltage swings greater than 2.5v are required (for example, if the i 2 c bus is pulled up to v in ), the minimum t hd;dat must be increased to 80ns. most i 2 c masters change sda near the midpoint between the falling and rising edges of scl, which provides ample t hd;dat . dissipation ratings (9) package r ja (10 ) power rating at t a 25c derating factor > t a = 25oc wafer-level chip-scale package (wlcsp) 110oc/w 900mw 9mw/oc notes: 9. maximum power dissipation is a function of t j(max) , ja , and t a . the maximum allowable power dissipation at any allowable ambient temperature is p d = [t j(max) - t a ] / ja . 10. this thermal data is measured with a high-k board (f our-layer board, according to the jesd51-7 jedec standard).
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 5 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator electrical specifications unless otherwise noted, over the recommended operating range for v in and t a , en = vsel = scl = sda = 1.8v, and register vsel0[6] bit = 1. typical values are at v in = 3.6v, t a = 25c. circuit and components according to figure 1. symbol parameter conditions min. typ. max. units power supplies i q quiescent current i o = 0ma, pfm mode, 2.3v<=v in <=4.5v 40 55 a i o = 0ma, pfm mode, 2.3v<=v in <=5.5v 40 65 i o = 0ma, 6mhz pwm mode 6.3 ma i sd shutdown supply current en = gnd 0.1 1.0 a en = v in , en_dcdc bit = 0, sda = scl = 1.8v (software shutdown) n/a n/a v uvlo under-voltage lockout threshold v in rising 2.18 2.25 v v in falling 1.95 2.02 v v uvhyst under-voltage lockout hysteresis 160 mv enable, vsel, sda, scl v ih high-level input voltage 1.05 v v il low-level input voltage 0.4 v i in input bias current input tied to gnd or v in 0.01 1.00 a power switch and protection r ds(on)p p-channel mosfet on resistance v in = 3.6v 300 m ? i lkgp p-channel leakage current v ds = 5.5v 0.2 1.0 a r ds(on)n n-channel mosfet on resistance v in = 3.6v 200 m ? i lkgn n-channel leakage current v ds = 5.5v 0.3 1.0 a i limpk p-mos current limit options 00, 02 1150 1350 1600 ma options 03, 06 1300 1550 1840 t limit thermal shutdown 150 c t hyst thermal shutdown hysteresis 20 c frequency control f sw switching frequency (11) pwm operation 5.4 6.0 6.6 mhz output regulation v out v out accuracy i out(dc) = 0, forced pwm, v out = vsel1 default value ?1.5 1.5 % 2.3v v in 5.5v, v out from minimum to maximum, i out(dc) = 0 to 1a, forced pwm ?2.0 2.0 % 2.3v v in 5.5v, v out from minimum to maximum, i out(dc) = 0 to 1a, auto pwm/pfm ?2.0 3.5 % load out i v load regulation i out(dc) = 0 to 1a, forced pwm ?0.2 %/a in out v v line regulation 2.3v v in 5.5v, i out(dc) = 300ma, forced pwm 0 %/v v ripple output ripple voltage pwm mode, v out = 1.2v 4 mv p-p pfm mode, i out(dc) = 10ma 16 mv p-p continued on the following page?
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 6 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator electrical specifications (continued) unless otherwise noted, over the recommended operating range for v in and t a , en = vsel = scl = sda = 1.8v, and register vsel0[6] bit = 1. typical values are at v in = 3.6v, t a = 25c. circuit and components according to figure 1. symbol parameter conditions min. typ. max. units dac resolution 6 bits differential nonlinearity monotonicity assured by design 0.8 lsb timing i 2 c en en high to i 2 c start 250 s t v(l-h) v out low to high settling transition from 0.75v to 1.438v v out settled to within 2% of setpoint 7 s soft-start t ss regulator enable to regulated v out r load > 5 , to v out = power-up default 140 180 s notes: 11. limited by the effect of t off minimum (see figure 14 in typical performance characteristics) . block diagram ref dac soft start fpwm en_reg clk 6 mhz osc i 2 c interface and logic en vsel sda scl sw q1 q2 pgnd vin c out vout l vout c in agnd modulator vin figure 3 block diagram
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 7 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator i 2 c timing specifications guaranteed by design. symbol parameter conditions min. typ. max. units f scl scl clock frequency standard mode 100 khz fast mode 400 fast mode plus 1000 high-speed mode, c b < 100pf 3400 high-speed mode, c b < 400pf 1700 t buf bus-free time between stop and start conditions standard mode 4.7 s fast mode 1.3 fast mode plus 0.5 t hd;sta start or repeated start hold time standard mode 4 s fast mode 600 ns fast mode plus 260 ns high-speed mode 160 ns t low scl low period standard mode 4.7 s fast mode 1.3 ns fast mode plus 0.5 ns high-speed mode, c b < 100pf 160.0 ns high-speed mode, c b < 400pf 320.0 ns t high scl high period standard mode 4 s fast mode 600 ns fast mode plus 260 ns high-speed mode, c b < 100pf 60 ns high-speed mode, c b < 400pf 120 ns t su;sta repeated start setup time standard mode 4.7 s fast mode 600.0 ns fast mode plus 260.0 ns high-speed mode 160.0 ns t su;dat data setup time standard mode 250 ns fast mode 100 fast mode plus 50 high-speed mode 10 t hd;dat data hold time (8) standard mode 0 3.45 s fast mode 0 900.00 ns fast mode plus 0 450.00 ns high-speed mode, c b < 100pf 0 70.00 ns high-speed mode, c b < 400pf 0 150.00 ns t rcl scl rise time standard mode 20+0.1c b 1000 ns fast mode 20+0.1c b 300 fast mode plus 20+0.1c b 120 high-speed mode, c b < 100pf 10 80 high-speed mode, c b < 400pf 20 160 continued on the following page?
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 8 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator i 2 c timing specifications (continued) guaranteed by design. symbol parameter conditions min. typ. max. units t fcl scl fall time standard mode 20+0.1c b 300 ns fast mode 20+0.1c b 300 fast mode plus 20+0.1c b 120 high-speed mode, c b < 100pf 10 40 high-speed mode, c b < 400pf 20 80 t rcl1 rise time of scl after a repeated start condition and after ack bit high-speed mode, c b < 100pf 10 80 ns high-speed mode, c b < 400pf 20 160 t rda sda rise time standard mode 20+0.1c b 1000 ns fast mode 20+0.1c b 300 fast mode plus 20+0.1c b 120 high-speed mode, c b < 100pf 10 80 high-speed mode, c b < 400pf 20 160 t fda sda fall time standard mode 20+0.1c b 300 ns fast mode 20+0.1c b 300 fast mode plus 20+0.1c b 120 high-speed mode, c b < 100pf 10 80 high-speed mode, c b < 400pf 20 160 t su;sto stop condition setup time standard mode 4 s fast mode 600 ns fast mode plus 120 ns high-speed mode 160 ns c b capacitive load for sda and scl 400 pf
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 9 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator timing diagrams start repeated start scl sda t f t hd;sta t low t r t hd;dat t high t su;dat t su;sta t hd;sto t buf start stop t hd;sta figure 4. i 2 c interface timing for fast plus, fast, and slow modes repeated start sclh sdah t fda t low t rcl1 t hd;dat t high t su;sto repeated start t rda t fcl t su;dat t rcl stop = mcs current source pull-up = r p resistor pull-up note a note a: first rising edge of sclh after repeated start and after each ack bit. t hd;sta t su;sta figure 5. i 2 c interface timing for high-speed mode
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 10 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator typical characteristics unless otherwise specified, auto pwm/pfm, v in = 3.6v, scl = sca = vsel = en = 1.8v, t a = 25c; circuit and components according to figure 1. 10 40% 50% 60% 70% 80% 90% 100% 1 100 1000 2.3v auto pfm/pwm 2.7v auto pfm/pwm 3.6v auto pfm/pwm 4.2v auto pfm/pwm 5.5v auto pfm/pwm 3.6v forced pwm efficiency output current (ma) 40% 50% 60% 70% 80% 90% 100% 1 10 100 1000 2.3v auto pfm/pwm 2.7v auto pfm/pwm 3.6v auto pfm/pwm 4.2v auto pfm/pwm 5.5v auto pfm/pwm 3.6v forced pwm efficiency output current (ma) figure 6. efficiency vs. load and input supply at v out = 1.1v figure 7. efficiency vs. load and input supply at v out = 1.2v 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 1101001000 auto pfm/pwm forced pwm v in =3.6v v out =0.75v efficiency output current (ma) 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 1 10 100 1000 auto pfm/pwm forced pwm v in =3.6v v out =1.4375v efficiency output current (ma) figure 8. efficiency, auto pwm/pfm vs. forced pwm at v out = 0.75v figure 9. efficiency, auto pwm/pfm vs. forced pwm at v out = 1.4375v
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 11 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator typical characteristics unless otherwise specified, auto pwm/pfm, v in = 3.6v, scl = sca = vsel = en = 1.8v, t a = 25c; circuit and components according to figure 1. 1.092 1.094 1.096 1.098 1.100 1.102 1.104 1.106 1.108 1.110 1.112 1 10 100 1000 output current(ma) vout(v) auto pfm/pwm forced pwm 1.192 1.194 1.196 1.198 1.200 1.202 1.204 1.206 1.208 1.210 1.212 1 10 100 1000 output current(ma) vout(v) auto pfm/pwm forced pwm figure 10. load regulation, auto pfm / pwm and forced pwm at v out = 1.1v figure 11. load regulation, auto pfm / pwm and forced pwm at v out = 1.2v 0.746 0.748 0.750 0.752 0.754 0.756 0.758 0.760 1 10 100 1000 output current(ma) vout(v) auto pfm/pwm forced pwm 1.430 1.432 1.434 1.436 1.438 1.440 1.442 1.444 1.446 1.448 1.450 1 10 100 1000 output current(ma) vout(v) auto pfm/pwm forced pwm figure 12. load regulation, auto pfm / pwm and forced pwm at v out = 0.75v figure 13. load regulation, auto pfm / pwm and forced pwm at v out = 1.4375v 1.0 2.0 3.0 4.0 5.0 6.0 7.0 0 200 400 600 800 1000 1200 i out (ma) frequency (mhz) v o =1.4375v v o =1.36v v o =1.3v v o =1.2v figure 14. effect of t off(min) on reducing the pwm switching frequency, v in =2.3v
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 12 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator typical characteristics unless otherwise specified, auto pwm/pfm, v in = 3.6v, scl = sca = vsel = en = 1.8v, t a = 25c; circuit and components according to figure 1. 30 35 40 45 50 55 60 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 -40c 25c 85c quiescent current (a) v in (v) 3 6 9 12 15 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 -40c 25c 85c quiescent current (ma) v in (v) figure 15. quiescent current in pfm mode vs. input voltage and temperature figure 16. quiescent current in pwm mode vs. input voltage and temperature 0.0 0.2 0.4 0.6 0.8 1.0 2.32.73.13.53.94.34.75.15.5 -40c 25c 85c shutdown current (a) v in (v) 0 10 20 30 40 50 60 70 80 0.1 1 10 100 1000 v out =1.2v v out =1.05v rejection ratio (db) frequency (khz) figure 17. shutdown current (en = 0) vs. input voltage and temperature figure 18. v in ripple rejection (psrr) in forced pwm at 200ma
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 13 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator typical characteristics unless otherwise specified, auto pwm/pfm, v in = 3.6v, scl = sca = vsel = en = 1.8v, t a = 25c; circuit and components according to figure 1. figure 19. combined line/load transient 3.0 to 3.6v in combined with 500 to 50ma load transient figure 20. combined line/load transient 3.6 to 3.0v in combined with 50 to 500ma load transient figure 21. combined line/load transient 3.0 to 3.6v in combined with 800 to 200ma load transient figure 22. combined line/load transient 3.6 to 3.0v in combined with 200 to 800ma load transient
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 14 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator typical characteristics unless otherwise specified, auto pwm/pfm, v in = 3.6v, scl = sca = vsel = en = 1.8v, t a = 25c; circuit and components according to figure 1. figure 23. vsel transition, single step (defslew = 7), r load = 24 ? figure 24. vsel transition, single step (defslew = 7), r load = 4 ? figure 25. vsel transition, defslew = 0, r load = 24 ? figure 26. vsel transition, defslew = 0, r load = 4 ?
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 15 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator typical characteristics unless otherwise specified, auto pwm/pfm, v in = 3.6v, scl = sca = vsel = en = 1.8v, t a = 25c; circuit and components according to figure 1. figure 27. vsel transition, vsel 1 to 0, r load = 24 ? figure 28. vsel transition, vsel 1 to 0, r load = 4 ? figure 29. shutdown, output discharge on figure 30. shutdown, output discharge off
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 16 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator typical characteristics unless otherwise specified, auto pwm/pfm, v in = 3.6v, scl = sca = vsel = en = 1.8v, t a = 25c; circuit and components according to figure 1. figure 31. metallic short applied at v out figure 32. over-current fault response, r load = 500m ? figure 33. soft start, no load figure 34. soft start, r load = 1.5 ?
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 17 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator circuit description the fan5365 is a synchronous buck regulator that typically operates at 6mhz with moderate to heavy load currents. at light load currents, the converter operates in power-saving pfm mode. the regulator automatically transitions between fixed-frequency pwm mode and variable-frequency pfm mode to maintain the highest possible efficiency over the full range of load current. the fan5365 uses a very fast, non-linear control architecture to achieve excellent transient response with minimum-sized external components. the fan5365 integrates an i 2 c-compatible interface, allowing transfers up to 3.4mbps. this communication interface can be used to: ? dynamically re-program the output voltage in 12.5mv increments ? reprogram the mode of operation to enable or disable pfm mode ? control voltage transition slew rate ? enable / disable the regulator. for more details, refer to the i 2 c interface and register description sections. output voltage programming v out is programmed according to the following equations: option (12) v out equation 00, 02, 03 mv 5 . 12 n 75 . 0 v vsel out ? + = (1) 06 mv 5 . 12 n 1875 . 1 v vsel out ? + = (2) note: 12. for option 00 and 02, the maximum voltage is 1.4375v. table 2. v sel vs. v out dec (nvsel) binary hex 00, 02 03 06 0 000000 00 0.7500 0.7500 1.1875 1 000001 01 0.7625 0.7625 1.2000 2 000010 02 0.7750 0.7750 1.2125 3 000011 03 0.7875 0.7875 1.2250 4 000100 04 0.8000 0.8000 1.2375 5 000101 05 0.8125 0.8125 1.2500 6 000110 06 0.8250 0.8250 1.2625 7 000111 07 0.8375 0.8375 1.2750 8 001000 08 0.8500 0.8500 1.2875 9 001001 09 0.8625 0.8625 1.3000 10 001010 0a 0.8750 0.8750 1.3125 11 001011 0b 0.8875 0.8875 1.3250 12 001100 0c 0.9000 0.9000 1.3375 13 001101 0d 0.9125 0.9125 1.3500 14 001110 0e 0.9250 0.9250 1.3625 15 001111 0f 0.9375 0.9375 1.3750 16 010000 10 0.9500 0.9500 1.3875 17 010001 11 0.9625 0.9625 1.4000 18 010010 12 0.9750 0.9750 1.4125 19 010011 13 0.9875 0.9875 1.4250 20 010100 14 1.0000 1.0000 1.4375 21 010101 15 1.0125 1.0125 1.4500 22 010110 16 1.0250 1.0250 1.4625 23 010111 17 1.0375 1.0375 1.4750 24 011000 18 1.0500 1.0500 1.4875 25 011001 19 1.0625 1.0625 1.5000 26 011010 1a 1.0750 1.0750 1.5125 27 011011 1b 1.0875 1.0875 1.5250 28 011100 1c 1.1000 1.1000 1.5375 29 011101 1d 1.1125 1.1125 1.5500 30 011110 1e 1.1250 1.1250 1.5625 31 011111 1f 1.1375 1.1375 1.5750 32 100000 20 1.1500 1.1500 1.5875 33 100001 21 1.1625 1.1625 1.6000 34 100010 22 1.1750 1.1750 1.6125 35 100011 23 1.1875 1.1875 1.6250 36 100100 24 1.2000 1.2000 1.6375 37 100101 25 1.2125 1.2125 1.6500 38 100110 26 1.2250 1.2250 1.6625 39 100111 27 1.2375 1.2375 1.6750 40 101000 28 1.2500 1.2500 1.6875 41 101001 29 1.2625 1.2625 1.7000 42 101010 2a 1.2750 1.2750 1.7125 43 101011 2b 1.2875 1.2875 1.7250 44 101100 2c 1.3000 1.3000 1.7375 45 101101 2d 1.3125 1.3125 1.7500 46 101110 2e 1.3250 1.3250 1.7625 47 101111 2f 1.3375 1.3375 1.7750 48 110000 30 1.3500 1.3500 1.7875 49 110001 31 1.3625 1.3625 1.8000 50 110010 32 1.3750 1.3750 1.8125 51 110011 33 1.3875 1.3875 1.8250 52 110100 34 1.4000 1.4000 1.8375 53 110101 35 1.4125 1.4125 1.8500 54 110110 36 1.4250 1.4250 1.8625 55 110111 37 1.4375 1.4375 1.8750 56 111000 38 1.4375 1.4500 1.8875 57 111001 39 1.4375 1.4625 1.9000 58 111010 3a 1.4375 1.4750 1.9125 59 111011 3b 1.4375 1.4875 1.9250 60 111100 3c 1.4375 1.5000 1.9375 61 111101 3d 1.4375 1.5125 1.9500 62 111110 3e 1.4375 1.5250 1.9625 63 111111 3f 1.4375 1.5375 1.9750 vsel value vout
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 18 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator power-up, en, and soft-start all internal circuits remain de-biased and the ic is in a very low quiescent current state until the following are true: ? v in is above its rising uvlo threshold, and ? en is high. at that point, the ic begins a soft-start cycle, its i 2 c interface is enabled, and its registers are loaded with their default values. during the initial soft-start, v out ramps linearly to the setpoint programmed in the vsel register selected by the vsel pin. the soft-start features a fixed output voltage slew rate of 20v/ms and achieves regulation approximately 90 s after en rises. pfm mode is enabled during soft-start until the output is in regulation, regardless of the mode bit settings. this allows the regulator to start into a partially charged output without discharging it; in other words, the regulator does not allow current to flow from the load back to the battery. as soon as the output has reached its setpoint, the control forces pwm mode for about 85 s to allow all internal control circuits to calibrate. table 3. soft-start timing symbol description value ( s) t ssdly time from en to start of soft- start ramp 25 t reg v out ramp start to regulation (vsel?0.1) x 53 t pok pwrok (control2[5]) rising from t reg 11 t cal regulator stays in pwm mode during this time 10 v out 0 en pwrok t reg vsel t pok t ca l (fpwm) t ssd ly figure 35. soft-start timing table 4. en_dcdc behavior en_dcdc bit en pin i 2 c regulator 0 0 off off 1 1 on on 1 0 off off 0 1 on off software enable the en_dcdc bit, vselx[7], can be used to enable the regulator in conjunction with the en pin. setting en_dcdc with en high begins the soft-start sequence described above. light-load (pfm) operation the fan5365 provides a low ripple, single-pulse, pfm mode that ensures: ? smooth transitions between pfm and pwm modes ? single-pulse operation for low ripple ? predictable pfm entry and exit currents. pfm begins after the inductor current has become discontinuous, crossing zero during the pwm cycle for 32 consecutive cycles. pfm exit occurs when discontinuous current mode (dcm) operation cannot supply sufficient current to maintain regulation. during pfm mode, the inductor current ripple is about 40% higher than in pwm mode. the load current required to exit pfm mode is thereby about 20% higher than the load current required to enter pfm mode, providing sufficient hysteresis to prevent ?mode chatter.? while pwm ripple voltage is typically less than 4mv p-p , pfm ripple voltage can be up to 30mv p-p during very light load. to prevent significant undershoot when a load transient occurs, the initial dc setpoint for the regulator in pfm mode is set 10mv higher than in pwm mode. this offset decays to about 5mv after the regulator has been in pfm mode for ~100 s. the maximum instantaneous voltage in pfm is 30mv above the setpoint. pfm mode can be disabled by writing to the mode control bits: control1[3:0] ( see table 5 ) output voltage transitions the ic regulates v out to one of two setpoint voltages, as determined by the vsel pin and the hw_nsw bit. table 5. v out setpoint and mode control mode_ctrl, control1[3:2] = 00 vsel pin hw_nsw bit v out setpoint pfm 0 1 vsel0 allowed 1 1 vsel1 per mode1 x 0 vsel1 per mode1 if hw_nsw = 0, v out transitions are initiated through the following sequence: 1. write the new setpoint in vsel1. 2. write desired transition rate in defslew, control2[2:0], and set the go bit in control2[7]. if hw_nsw = 1, v out transitions are initiated either by changing the state of the vsel pin or by writing to the vsel register selected by the vsel pin.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 19 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator positive transitions when transitioning to a higher v out , the regulator can perform the transition using multi-step or single-step mode. multi-step mode: the internal dac is stepped at a rate defined by defslew, control2[2:0], ranging from 000 to 110. this mode minimizes the current required to charge c out and thereby minimizes the current drain from the battery when transitioning. the pwrok bit, control2[5], remains low until about 1.5 s after the dac completes its ramp. v low v high v sel v out pwrok t pok(l-h) figure 36. multi-step v out transition single-step mode: used if defslew, control2[2:0] = 111. the internal dac is immediately set to the higher voltage and the regulator performs the transition as quickly as its current limit circuit allows, while avoiding excessive overshoot. figure 37 shows single-step transition timing. t v(l-h) is the time it takes the regulator to settle to within 2% of the new setpoint, typically 7 s for a full-range transition. the pwrok bit, control2[5], goes low until the transition is complete and v out settled. this typically occurs ~2 s after t v(l-h) . it is good practice to reduce the load current before making positive v sel transitions. this reduces the time required to make positive load transitions and avoids current?limit- induced overshoot. t v(l-h) v low v high 98 % v high v sel v out pwrok t pok(l-h) figure 37. single-step v out transition all positive v out transitions inhibit pfm until the transition is complete, which occurs at the end of t pok(l-h) . negative transitions when moving from v sel = 1 to v sel = 0, the regulator enters pfm mode, regardless of the condition of the mode bits, and remains in pfm until the transition is complete. reverse current through the inductor is blocked, and the pfm minimum frequency control inhibited, until the new setpoint is reached; at which time, the regulator resumes control using the mode established by mode_ctrl. the transition time from v high to v low is controlled by load current and output capacitance as: load low high out ) l h ( v i v v c t ? ? = ? (3) v high v sel v out pwrok t pok(l-h) t v(l-h) v low figure 38. negative v out transition protection features current limit / auto-restart the regulator includes cycle-by-cycle current limiting, which prevents the instantaneous inductor current from exceeding the ?pmos current limit? threshold. the ic enters ?fault? mode after sustained over-current. if current limit is asserted for more than 32 consecutive cycles (about 20 s), the ic returns to shutdown state and remains in that condition for ~80 s. after that time, the regulator attempts to restart with a normal soft-start cycle. if the fault has not cleared, it shuts down ~20 s later. if the fault is a short circuit, the initial current limit is ~30% of the normal current limit, which produces a very small drain on the system power source. thermal protection when the junction temperature of the ic exceeds 150c, the device turns off all output mosfets and remains in a low quiescent current state until the die cools to 130c before starting a normal soft-start cycle.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 20 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator under-voltage lockout (uvlo) the ic turns off all mosfets and remains in a low quiescent current state until v in rises above the uvlo threshold. i 2 c interface the fan5365?s serial interface is compatible with standard, fast, fast plus, and high-speed mode i 2 c bus specifications. the fan5365?s scl line is an input and its sda line is a bi- directional open-drain output; it can only pull down the bus when active. the sda line only pulls low during data reads and when signaling ack. all data is shifted in msb (bit 7) first. slave address in table 6, a1 and a0 are according to the ordering information table on page 2. table 6. i 2 c slave address 7 6 5 4 3 2 1 0 1 0 0 1 a2 a1 a0 w r/ in hex notation, the slave address assumes a 0 lsb. for example, the hex slave address of option 00 is 94h. register addressing fan5365 has four user-accessible registers: table 7. i 2 c register address address 7 6 5 4 3 2 1 0 vsel0 0 0 0 0 0 0 0 0 vsel1 0 0 0 0 0 0 0 1 control1 0 0 0 0 0 0 1 0 control2 0 0 0 0 0 0 1 1 bus timing as shown in figure 39, data is normally transferred when scl is low. data is clocked in on the rising edge of scl. typically, data transitions shortly at or after the falling edge of scl to allow ample time for the data to set up before the next scl rising edge. scl t su t h sda data change allowed figure 39. data transfer timing each bus transaction begins and ends with sda and scl high. a transaction begins with a ?start? condition, which is defined as sda transitioning from 1 to 0 with scl high, as shown in figure 40. scl t hd;sta sda slave address ms bit figure 40. start bit a transaction ends with a ?stop? condition, which is defined as sda transitioning from 0 to 1 with scl high, shown in figure 41. scl sda slave releases master drives ack(0) or nack(1) t hd;sto figure 41. stop bit during a read from the fan5365 (figure 44), the master issues a ?repeated start? command after sending the register address and before resending the slave address. the ?repeated start? is a 1-to-0 transition on sda while scl is high, as shown in figure 42. scl sda ack(0) or nack(1) slave releases sladdr ms bit t hd;sta t su;sta figure 42. repeated start timing
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 21 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator high-speed (hs) mode the protocols for high-speed (hs), low-speed (ls), and fast-speed (fs) modes are identical, except the bus speed for hs mode is 3.4mhz. hs mode is entered when the bus master sends the hs master code 00001xxx after a start condition. the master code is sent in fast or fast plus mode (less than 1mhz clock) and slaves do not acknowledge (ack) this transmission. the master then generates a repeated start condition (figure 42) that causes all slaves on the bus to switch to hs mode. the master then sends i 2 c packets, as described above, using the hs mode clock rate and timing. the bus remains in hs mode until a stop bit (figure 41) is sent by the master. while in hs mode, packets are separated by repeated start conditions. read and write transactions the following figures outline the sequences for data read and write. bus control is signified by the shading of the packet, defined as master drives bus and slave drives bus . all addresses and data are msb first. table 8. i 2 c bit definitions for figure 43 and figure 44 symbol definition s start, figure 40 . a ack. the slave drives sda to 0 to acknowledge the preceding packet. a nack. the slave sends a 1 to nack the preceding packet. r repeated start, see figure 42. p stop, see figure 41. s slave address a reg addr a a p 0 7 bits 8 bits 8 bits data 000 figure 43. write transaction s slave address a reg addr a 0 7 bits 8 bits r slave address 7 bits 1 a data a 8 bits 00 01 p figure 44. read transaction register descriptions default values each option of the fan5365 (see table 9) has different default values for the some of t he register bits. table 9 defines both the default values and the bi t?s type (as defined in table 10) for each available option. table 9. default values and bit types for v sel and control registers v sel0 option 7 6 5 4 3 2 1 0 v out 00 1 1 0 1 1 0 0 0 1.05 02 1 1 0 1 0 0 0 0 0.95 03 1 1 0 1 0 1 0 0 1.00 06 1 1 1 1 0 0 0 1 1.80 v sel1 option 7 6 5 4 3 2 1 0 v out 00 1 1 1 0 0 1 0 0 1.20 02 1 1 0 1 1 1 0 0 1.10 03 1 1 1 0 0 1 0 0 1.20 06 1 1 1 1 0 0 0 1 1.80 control1 option 7 6 5 4 3 2 1 0 00, 02 1 0 0 1 0 0 0 0 03, 06 1 0 0 1 0 0 0 0 control2 option 7 6 5 4 3 2 1 0 00, 02 0 1 0 0 0 1 1 1 03, 06 0 0 0 0 0 1 1 1 table 10. bit type definitions for table 9 # active bit changing this bit changes the behavior of the converter, as described below. # disabled converter logic ignores changes made to this bit. bit can be written and read-back. # read-only writing to this bit through i 2 c does not change the read-back value, nor does it change converter behavior.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 22 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator bit definitions table 11 defines the operation of each register bit. superscript characters define the default state for each option. superscripts 0,2,3,6 signify the default values for options 00, 02, 03, and 06, respectively. a signifies the default for all options. table 11. bit definitions bit name value description vsel0 register address: 00 7 en_dcdc 0 device in shutdown regardless of the state of the en pin. this bit is mirrored in vsel1. a write to bit 7 in either register establishes the en_dcdc value. 1 a device enabled when en pin is high, disabled when en is low. 6 reserved 1 a 5:0 dac[5:0] table 9 a 6-bit dac value to set v out . vsel1 register address: 01 7 en_dcdc 0 device in shutdown regardless of the state of the en pin. this bit is mirrored in vsel1. a write to bit 7 in either register establishes the en_dcdc value. 1 a device enabled when en pin is high, disabled when en is low. 6 reserved 1 a 5:0 dac[5:0] table 9 a 6-bit dac value to set v out . control1 register address: 02 7:6 reserved 10 a vendor id bits. writing to these bits has no effect on regulator operation. these bits can be used to distinguish between vendors via i 2 c. 5 reserved 1 a 4 hw_nsw 0 v out is controlled by vsel1. voltage transitions occur by writing to the vsel1, then setting the go bit. 1 a v out is programmed by the vsel pin. v out = vsel1 when vsel is high and v out = vsel0 when vsel is low. 3:2 mode_ctrl 00 a operation follows mode0, mode1. 01 pfm with automatic transitions to pwm, regardless of vsel. 10 pfm disabled (forced pwm), regardless of vsel. 11 pfm with automatic transitions to pwm, regardless of vsel. 1 mode1 0 a pfm disabled (forced pwm) when regulator output is controlled by vsel1. 1 pfm with automatic transitions to pwm when regulator output is controlled by vsel1. 0 mode0 0 a pfm with automatic transitions to pwm when vsel is low. changing this bit has no effect on the operation of the regulator. 1 control2 register address: 03 7 go 0 a this bit has no effect when hw_nsw = 1. at the end of a v out transition, this bit is reset to 0. 1 starts a v out transition if hw_nsw = 0. 6 output_ discharge 0 3,6 when the regulator is disabled, v out is not discharged. 1 0,2 when the regulator is disabled, v out discharges through an internal pull-down. 5 pwrok (read only) 0 v out is not in regulation or is in current limit. 1 v out is in regulation. 4:3 reserved 00 a 2:0 defslew 000 v out slews at 0.15mv/ s during positive v out transitions. 001 v out slews at 0.30mv/ s during positive v out transitions. 010 v out slews at 0.60mv/ s during positive v out transitions. 011 v out slews at 1.20mv/ s during positive v out transitions. 100 v out slews at 2.40mv/ s during positive v out transitions. 101 v out slews at 4.80mv/ s during positive v out transitions. 110 v out slews at 9.60mv/ s during positive v out transitions. 111 a positive v out transitions use single-step mode (see figure 37) .
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 23 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator physical dimensions 0.03 c 2x b a 0.03 c 2x 0.2080.021 0.3780.018 d c 0.06 c 0.05 c pin a1 index area notes: a. no jedec registration applies. b. dimensions are in millimeters. c. dimensions and tolerance per asmey14.5m, 1994. d. datum c is defined by the spherical crowns of the balls. e. package nominal height is 586 microns 39 microns (547-625 microns). f. for dimensions d, e, x, and y see product datasheet. g. drawing filname: mkt-uc009abrev2 f f e e d a1 ?0.20 cu pad ?0.30 solder mask 0.40 0.40 side views ?0.2600.020 9x 0.40 0.40 (x)0.018 (y)0.018 a b c 123 bottom view top view 0.625 0.547 seating plane land pattern recommendation (nsmd pad type) figure 45. 9-ball wlcsp, 3x3 array, 0.4mm pitch, 250m ball product-specific dimensions product d e x y fan5365uc 1.290 +/-0.030 1.270 +/-0.030 0.250 0.250 package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner wit hout notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to verify or o btain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan5365 ? rev. 1.0.4 24 fan5365 ? 1a / 0.8a, 6mhz digitally programmable regulator

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