1 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8l21665v february 1999 rev. 0 eco # description the edi8l21665vxxbc is a 3.3v, 2x64kx16 sram constructed with two 64kx16 die mounted on a multi-layer laminate substrate. the device is packaged in a 74 lead, 15mm by 15mm, bga. operating with a 3.3v power supply and with access times as fast as 10ns, the device allows the user to develop a fast external memory for texas instuments? tms320c5x dsp. the device consists of two separate banks of 64kx16 of memory. each bank has a separate chip enable pin and higher order address select pin. bank ?a? is controlled using ce 1 \ and a 15a . bank ?b? is controlled using ce 2 \ and a 15b . the two banks have common i/os (dq 0-15 ) and control lines (we\, e\ and g\). e\ connects to the mstrb\ pin of the c54x dsps and is required for write and read timing control. features n access times of 10, 12 and 15ns n dsp memory solution texas instruments tms320c5x n packaging: 74 pin bga, jedec mo-151 n 3.3v operating supply voltage n single write control and output enable lines n one chip enable line per memory bank n 50% space savings vs. monolithic tsops n upgrade path available in same footprint n multiple v cc and v ss pins n reduced inductance and capacitance block diagram pin configuration a 0 - 14 g w ce 1 a 15a e g ce a 15 ce a 15 ce 2 a 15a 64k x 16 ssram 64k x 16 ssram u1 u2 123 45678910 11 a vss vcc vcc dq 15 dq 14 vcc dq 13 dq 11 dq 9 dq 8 nc a b vss vcc vcc vss vss vcc dq 12 dq 10 dq 4 vcc vcc b c vss vss vcc vss vcc c d vss vss vss vcc d e vss vss vss vcc e f a 15a ce 1 dq 3 dq 7 f g ew dq 5 dq 0 g h vss ce 2 dq 6 dq 1 h i vss a 14 vcc dq 2 nc i j vss a 12 vcc a 10 a 8 vss a 6 a 4 a 2 a 0 g j k a 15b a 13 vcc a 11 a 9 vss a 7 v ss a 5 a 3 a 1 k 123 45678910 11 2x64kx16 sram, dsp memory solution
2 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8l21665v recommended operating conditions description symbol min max unit input high voltage v ih 2.2 vcc+0.5 v input low voltage v il -0.3 0.8 v supply voltage vcc 3.0 3.6 v capacitance (f = 1mhz, v in = v cc or v ss ) voltage on vcc supply relative to vss -0.5v to 4.6v v in -0.5v to vcc+0.5v storage temperature -55 c to +125 c junction temperature +125 c power dissipation 3 watts short circuit output current (per i/o) 50 ma * stress greater than those listed under "absolute maximum ratings" may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect reliability. parameter symbol max unit address lines ca 8 pf data lines cd/q 17 pf control lines cc 15 pf pin descriptions pin symbol type description a 0-14 input addresses a 15a input addresses: a 15 on bank ?a? of memory a 15b input addresses: a 15 on bank ?b? of memory w input write enable: this active low input allows a full 16-bit write to occur. ce 1 input chip enable: this active low input is used to enable the ?a? bank of the device. ce 2 input chip enable: this active low input is used to enable the ?b? bank of the device. g input output enable: this active low asynchronous input enables the data output drivers. various dq 0-15 input/output data inputs/outputs various vcc supply core power supply: +3.3v -5%/+10% various vss ground ground e input enable, this active low input controls write and read timing dc electrical characteristics (f = 1mhz, v in = v cc or vss) parameter symbol conditions min max units device selected; all inputs v il or 3 v ih ; -10ns 380 ma power supply current: operating icc1 cycle time 3 t kc min; -12ns 360 v cc = max; outputs open -15ns 260 device deselected; v cc = max; cmos standby isb2 all inputs v ss +0.2 or 3 v cc -0.2; all inputs static; 60 ma clk frequency = 0 ttl standby isb3 device deselected; all inputs v il or 3 v ih ; 120 ma all inputs static; v cc = max; clk frequency = 0 input leakage current ili 0v v in v cc -5 5 m a output leakage current ilo output(s) disabled, 0v v out v cc -5 5 m a output high voltage voh ioh = -4.0ma 2.4 v output low voltage vol iol = 8.0ma 0.4 v absolute maximum ratings*
3 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8l21665v ac test circuit ac test conditions 50 w vt = 1.5v output z0 = 50 w z0 = 50 w parameter i/o unit input pulse levels v ss to 3.0 v input rise and fall times (max) 1.5 ns input and output timing levels 1.5 v output load see figure, at left ac output load equivalent 1.25v ac electrical characteristics symbol 10ns 12ns 15ns read cycle min max min max min max units read cycle time t avav 10 12 15 ns address access time t avqv 10 12 15 ns chip enable access t elqv 10 12 15 ns output hold from address change t avqx 344ns chip enable to output in low-z t elqx 344ns chip disable to output in high-z t ehqz 56 7ns output enable access time t glqv 56 7ns output enable to output in low-z t glqx 000ns output disable to output in high-z t ghqz 56 7ns write cycle write cycle time t avav 10 12 15 ns chip enable to end of write t elwh 889ns address valid to end of write, with g high t avghwh 889ns address setup time t avwl 000ns address hold from end of write t avwh 8810ns write pulse width t wlwh 10 10 11 ns write pulse width, with g high t wlghwh 889ns data setup time t dvwh 667ns data hold time t whdx 000ns write disable to output in low-z t whqx 345ns write enable to output in high-z t wlqz 56 7ns
4 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8l21665v read cycle timing diagrams a q read cycle 1 (w high; g, e low) t avqx t avqv t avav data 2 address 1 address 2 data 1 a q read cycle 2 (w high) t avqv t elqv t glqv t elqx t glqx t avav t ehqz t ghqz g e write cycle timing diagram a d write cycle 2, e controlled t aveh t eleh t ehax t dveh t ehdx t avav data valid high z w e q t avel notes: all writes are e controlled when connected to the tms320c54x. e is connected to mstrb and w is connected to r/w of the tms320c 54x.
5 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8l21665v edi8l21665v package description: 74 pin bga package no. 428 thermal package performance: q j a = 28 c/watt (natural connection) q j b = 4 c/watt commercial temperature range (0 c to +70 c) part number speed package (ns) no. edi8l21665v10bc 10 428 edi8l21665v12bc 12 428 edi8l21665v15bc 15 428 ordering information 0.591 sq. 0.125 max 0.029 max all dimensions are in inches industrial temperature range (-40 c to +85 c) part number speed package (ns) no. edi8l21665v15bi 15 428
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