AS8SLC512K32 rev. 2.0 3/03 austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 sram sram sram sram sram AS8SLC512K32 austin semiconductor, inc. cs cs cs cs \ general description the austin semiconductor, inc. AS8SLC512K32 is a 3.3v 16 megabit cmos sram module organized as 512kx32 bits. the AS8SLC512K32 achieves very high speed access, low power consumption and high reliability by employing advanced cmos memory technology. this military temperature grade product is ideally suited for commercial, industrial, and military applications when asynchronous high speed switching and low active opening power is mandated. features ? fast access times: 10, 12, 15, 17 and 20ns ? fast oe\ access times: 6ns ? ultra-low operating power < 1w worst case ? single +3.3v 0.3v power supply ? fully static -- no clock or timing strobes necessary ? all inputs and outputs are ttl-compatible ? easy memory expansion with ce\ and oe\ options ? automatic ce\ power down ? high-performance, low-power consumption, cmos options markings ? timing 10ns -10 (consult factory) 12ns -12 15ns -15 17ns -17 20ns -20 ? package ceramic quad flatpack q no. 702 pin grid array p no.904 ? operating temperature ranges military (-55 o c to +125 o c) xt industrial (-40 o c to +85 o c) it ? 2v data retention/low power l pin assignment (top view) 68 lead cqfp (q) 512k x 32 sram sram memory array mcm block diagram 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 gnd i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 gnd i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 nc a0 a1 a2 a3 a4 a5 ce\3 gnd ce\4 we\1 a6 a7 a8 a9 a10 vcc vcc a11 a12 a13 a14 a15 a16 ce\1 oe ce\2 a17 we\2 we\3 we\4 a18 nc nc for more products and information please visit our web site at www.austinsemiconductor.com m1 m2 m3 m4 66 lead pga (p)
AS8SLC512K32 rev. 2.0 3/03 austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 sram sram sram sram sram AS8SLC512K32 austin semiconductor, inc. absolute maximum ratings* voltage of vcc supply relative to vss...........-0.5v to +4.6v storage temperature.....................................-65c to +150c short circuit output current(per i/o)............................20ma voltage on any pin relative to vss............-.5v to vcc+4.6v maximum junction temperature**.............................+150c *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation on the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. **junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. see the ap- plication information section at the end of this datasheet for more information. electrical characteristics and recommended dc operating conditions (-55 o c < t a < 125 o c and -40 o c to +85 o c; vcc = 3.3v 0.3v) description conditions symbol min max units notes input high (logic 1) voltage v ih 2.2 v cc +0.3 v1 input low (logic 1) voltage v il -0.3 0.8 v 1 input leakage current add,oe i li1 -10 10 a input leakage current we,ce i li2 -10 10 a output leakage current i/o output(s) disabled 0vv ih ; v cc = max f = max = 1/ t rc (min) outputs open, oe\=v ih low speed power supply current: operating low speed power supply current: operating cs\ AS8SLC512K32 rev. 2.0 3/03 austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 sram sram sram sram sram AS8SLC512K32 austin semiconductor, inc. ac test conditions note: *this parameter is sampled. capacitance (v in = 0v, f = 1mhz, t a = 25 o c)* symbol parameter max units c add a0 - a18 capacitance 40 pf c oe oe\ capacitance 40 pf c we, c cs we\ and cs\ capacitance 12 pf c io i/o 0- i/o 31 capacitance 15 pf input pulse levels...........................................v ss to 3v input rise and fall times...........................................1ns/v input timing reference levels...............................1.5v output reference levels........................................1.5v output load..........................................see figure 1, 2 test specifications figure 1 q 30 pf r l = 50 ? v l = 1.5v z o = 50 ? 3.3v q 333 ? 5 pf 319 ? figure 2
AS8SLC512K32 rev. 2.0 3/03 austin semiconductor, inc. reserves the right to change products or specifications without notice. 4 sram sram sram sram sram AS8SLC512K32 austin semiconductor, inc. electrical characteristics and recommended ac operating conditions (note 5) (-55 o c AS8SLC512K32 rev. 2.0 3/03 austin semiconductor, inc. reserves the right to change products or specifications without notice. 5 sram sram sram sram sram AS8SLC512K32 austin semiconductor, inc. low v cc data retention waveform low power characteristics (l version only) 123456789012345678 123456789012345678 123456789012345678 123456789012345678 123456789012345678 123456789012345678 123456789012345678 123456789012345678 123456789012345678 12345 1 234 5 1 234 5 1 234 5 1 234 5 1 234 5 1 234 5 1 234 5 12345 12345678 1 234567 8 1 234567 8 1 234567 8 1 234567 8 1 234567 8 12345678 123456789012345678 123456789012345678 123456789012345678 123456789012345678 123456789012345678 123456789012345678 123456789012345678 123456789012345678 123456789012345678 12345 1 234 5 1 234 5 1 234 5 1 234 5 1 234 5 1 234 5 1 234 5 12345 12345678 1 234567 8 1 234567 8 1 234567 8 1 234567 8 1 234567 8 12345678 data retention mode 4.5v 4.5v v dr > 2v v dr t cdr t r v cc cs\ 1-4 description symbol min max units notes v cc for retention data v dr 2v v cc = 2v i ccdr 24 ma v cc = 3v i ccdr 32 ma chip deselect to data retention time t cdr 0ns4 operation recovery time t r 20 ms 4, 11 data retention current all inputs @ vcc + 0.2v or vss + 0.2v, cs\ = vcc + 0.2v conditions 7. at any given temperature and voltage condition, t hzcs , is less than t lzcs , and t hzwe is less than t lzwe . 8. we\ is high for read cycle. 9. device is continuously selected. chip selects and output enable are held in their active state. 10. address valid prior to or coincident with latest occurring chip enable. 11. t rc = read cycle time. 12. chip enable (cs\) and write enable (we\) can initiate and terminate a write cycle. 13. i cc is for full 32 bit mode. notes 1. all voltages referenced to v ss (gnd). 2. worst case address switching. 3. i cc is dependent on output loading and cycle rates. the specified value applies with the outputs 4. this parameter guaranteed but not tested. 5. test conditions as specified with output loading as shown in fig. 1 & 2 unless otherwise noted. 6. t hzcs , t hzoe and t hzwe are specified with c l = 5pf as in fig. 2. transition is measured +/- 200 mv typical from steady state voltage, allowing for actual tester rc time constant. rc(min) unloaded, and f= h z. t 1
AS8SLC512K32 rev. 2.0 3/03 austin semiconductor, inc. reserves the right to change products or specifications without notice. 6 sram sram sram sram sram AS8SLC512K32 austin semiconductor, inc. read cycle no. 1 read cycle no. 2 12345 12345 12345 12345 12345 12345 12345 12345 12345 12345 1234567 1 23456 7 1 23456 7 1 23456 7 1234567 12 12 12 12 12 12 12 12 address data i/o previous data valid new data valid t oh t aa t rc address t rc 123456789 123456789 123456789 123456789 123456789 1234 1 23 4 1 23 4 1 23 4 1234 12345 1 234 5 1 234 5 1 234 5 12345 12345678 12345678 12345678 12345678 12345678 123456 1 2345 6 1 2345 6 1 2345 6 123456 1234567 1 23456 7 1 23456 7 1 23456 7 1234567 1234567890123 1234567890123 1234567890123 1234567890123 1234 1 23 4 1 23 4 1234 12345 1 234 5 1 234 5 12345 12345678901 12345678901 12345678901 12345678901 123456 1 2345 6 1 2345 6 123456 1234567 1 23456 7 1 23456 7 1234567 123456 123456 123456 123456 12345 12345 12345 12345 1234 1 23 4 1 23 4 1234 12 12 12 12 1 1 1 1 high impedance data valid t aa t acs t lzcs t hzcs t hzoe t aoe t lzoe cs\ oe\ data i/o
AS8SLC512K32 rev. 2.0 3/03 austin semiconductor, inc. reserves the right to change products or specifications without notice. 7 sram sram sram sram sram AS8SLC512K32 austin semiconductor, inc. write cycle no. 2 (write enable controlled) write cycle no. 1 (chip select controlled) address t wc 123456789 123456789 123456789 123456789 123456789 1234 1 23 4 1 23 4 1 23 4 1234 12345 1 234 5 1 234 5 1 234 5 12345 1234567890123 1234567890123 1234567890123 1234567890123 1234567890123 123456 1 2345 6 1 2345 6 1 2345 6 123456 1234567 1 23456 7 1 23456 7 1 23456 7 1234567 12345 12345 12345 12345 1234 1234 1234 12345678901234 1 234567890123 4 12345678901234 1 1 1 1 1 1 data valid t aw t cw t as t ah t lzwe t wp1 1 t hzwe cs\ we\ data i/o 1234 1234 1234 123 1 2 3 123 1234 1 23 4 1234 t dh t ds address t wc 123456 123456 123456 123456 123456 2 1 123456789 123456789 123456789 123456789 1234567890123 1234567890123 1234567890123 1234567890123 123456 1 2345 6 1 2345 6 123456 1234567 1 23456 7 1 23456 7 1234567 t ah notes 1. all voltages referenced to v ss (gnd).
AS8SLC512K32 rev. 2.0 3/03 austin semiconductor, inc. reserves the right to change products or specifications without notice. 8 sram sram sram sram sram AS8SLC512K32 austin semiconductor, inc. mechanical definitions* asi case #702 (package designator q) detail a l1 1 o - 7 o r b *all measurements are in inches. 4 x d2 4 x d1 d b e a2 see detail a a a1 e min max a 0.123 0.200 a1 0.118 0.186 a2 0.000 0.020 b b 0.013 0.017 d d1 0.870 0.890 d2 0.980 1.000 e 0.936 0.956 e r 0.005 --- l1 0.035 0.045 symbol 0.800 bsc 0.050 bsc specifications 0.010 ref
AS8SLC512K32 rev. 2.0 3/03 austin semiconductor, inc. reserves the right to change products or specifications without notice. 9 sram sram sram sram sram AS8SLC512K32 austin semiconductor, inc. mechanical definitions* asi case #904 (package designator p) *all measurements are in inches. 4 x d d1 d2 e1 pin 66 e pin 11 pin 1 (identified by 0.060 square pad) pin 56 a a1 l b e b1 min max a 0.144 0.181 a1 0.025 0.035 symbol 1.000 typ smd specifications
AS8SLC512K32 rev. 2.0 3/03 austin semiconductor, inc. reserves the right to change products or specifications without notice. 10 sram sram sram sram sram AS8SLC512K32 austin semiconductor, inc. *available processes xt = industrial temperature range -55 o c to +125 o c it = industrial temperature range -40 o c to +85 o c 883c = military processing -55 o c to +125 o c option definitions l = 2v data retention/low power ordering information device number package t yp e speed ns options process AS8SLC512K32 q -10 l /* AS8SLC512K32 q -12 l /* AS8SLC512K32 q -15 l /* AS8SLC512K32 q -17 l /* AS8SLC512K32 q -20 l /* device number package t yp e speed ns options process AS8SLC512K32 p -10 l /* AS8SLC512K32 p -12 l /* AS8SLC512K32 p -15 l /* AS8SLC512K32 p -17 l /* AS8SLC512K32 p -20 l /* example: AS8SLC512K32q-17l/xt example: AS8SLC512K32p-12/it
|
