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preliminary technical data a +2.5 v to +5.5 v, 500 m m m m m a, quad rail-to-rail, voltage output 8/10/12-bit dacs preliminary technical data ad5304/ad5314/AD5324* general description the ad5304/ad5314/AD5324 are quad 8, 10 and 12-bit buffered voltage output dacs in a 10-lead m soic pack- age which operate from a single +2.5v to +5.5v supply consuming 500 m a at 3v. their on-chip output amplifiers allow rail-to-rail output swing to be achieved with a slew rate of 0.7v/ m s. a 3-wire serial interface is used which op- erates at clock rates up to 30mhz and is compatible with standard spi?, qspi?, microwire? and dsp in- terface standards. the references for the four dacs are derived from one reference pin. the outputs of all dacs may be updated simultaneously using the software ldac function. the parts incorporate a power-on-reset circuit that ensures that the dac outputs power up to zero volts and remain there until a valid write takes place to the device. the parts con- tains a power-down feature which reduces the current con- sumption of the device to 200na @5v (50na @3v). the low power consumption of these parts in normal op- eration make them ideally suited to portable battery-oper- ated equipment. the power consumption is 3mw at 5v reducing to 1w in power-down mode. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 analog devices, inc., 1999 rev. pre 7/99 *protected by u.s. patent no. 5684481; other patents pending spi ?, qspi ? are trademarks of motorola, inc. microwire ? is a trademark of national semiconductor corporation. features ad5304: four buffered 8-bit dacs in one package ad5314: four buffered 10-bit dacs in one package AD5324: four buffered 12-bit dacs in one package 10-lead m m m m m soic package micropower operation: 500 m m m m m a@3v, 600 m m m m m a@5v +2.5v to +5.5v power supply guaranteed monotonic by design over all codes power down to 50na@3v, 200na@5v double-buffered input logic output range: 0-v ref power-on-reset to zero volts simultaneous update of outputs ( ldac function) low-power serial interface with schmitt-triggers on-chip rail-to-rail output buffer amplifiers temperature range -40c to 105c. applications portable battery powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators industrial process control functional block diagram dac register input register string dac a buffer interface logic sclk v dd v out a v out b gnd ref in ad5304/ad5314/AD5324 power-down logic sync pow er- on reset dac register input register string dac b buffer dac register input register string dac c buffer dac register input register string dac d buffer v out c v out d din
preliminary technical data C2C ad5304/ad5314/AD5324Cspecifications parameter 1 b version 2 units conditions/comments min typ max dc performance 3,4 ad5304 resolution 8 bits relative accuracy 0.15 1 lsb differential nonlinearity 0.02 0.25 lsb guaranteed monotonic by design over all codes ad5314 resolution 10 bits relative accuracy 0.5 3 lsb differential nonlinearity 0.05 0.5 lsb guaranteed monotonic by design over all codes AD5324 resolution 12 bits relative accuracy 2 12 lsb differential nonlinearity 0.2 1 lsb guaranteed monotonic by design over all codes offset error 0.4 3 % of fsr see figures 2 and 3 gain error 0.15 1 % of fsr see figures 2 and 3 lower deadband 10 60 m v see figures 2 and 3 offset error drift 5 -12 ppm of fsr/c gain error drift 5 -5 ppm of fsr/c power supply rejection ratio 5 -60 db d v dd =10% dc crosstalk 5 30 v dac reference input 5 v ref input range 0 v dd v v ref input impedance 4 5 k w normal operation >10 m w power-down mode reference feedthrough -90 d b frequency=10khz output characteristics 5 minimum output voltage 6 0.001 v this is a measure of the minimum and maximum drive maximum output voltage 6 v dd -0.001 v capability of the output amplifier dc output impedance 0.5 w short circuit current 50 m a v dd = +5v 20 m a v dd = +3v power up time 2.5 s coming out of power down mode. v dd = +5 v 5 s coming out of power down mode. v dd = +3 v logic inputs 5 input current 1 a v il , input low voltage 0.8 v v dd = +5v10% 0.6 v v dd = +3v10% 0.5 v v dd = +2.5v v ih , input high voltage 2.4 v v dd = +5v10% 2.1 v v dd = +3v10% 2.0 v v dd = +2.5v pin capacitance 3 pf power requirements v dd 2.5 5.5 v i dd spec. is valid for all dac codes. interface inactive. i dd (normal mode) all dacs active. excluding load currents. cmos levels. v dd = +4.5v to +5.5v 0.6 0.9 m a v ih = v dd and v il = gnd v dd = +2.5v to +3.6v 0.5 0.7 m a v ih = v dd and v il = gnd i dd (power down mode) v dd = +4.5v to +5.5v 0.2 1 a v ih =v dd and v il =gnd v dd = +2.5v to +3.6v 0.05 1 a v ih =v dd and v il =gnd notes 1 see terminology 2 temperature ranges are as follows: b version: -40c to +105c. 3 dc specifications tested with the outputs unloaded. 4 linearity is tested using a reduced code range: ad5304 (code 8 to 248); ad5314 (code 28 to 995); AD5324 (code 115 to 3981) 5 guaranteed by design and characterization, not production tested 6 in order for the amplifier output to reach its minimum voltage, offset error must be negative. in order for the amplifier outpu t to reach its maximum voltage, v ref =v dd and "offset plus gain" error must be positive. specifications subject to change without notice. rev. pre (v dd = +2.5v to +5.5 v; v ref =+2v; r l =2k w w w w w to gnd; c l =200pfto gnd; all specifications t min to t max unless otherwise noted.)
2 C3C ad5304/ad5314/AD5324 preliminary technical data rev. pre preliminary technical data parameter 2 b version 3 units conditions/comments min typ max output voltage settling time v ref =v dd =+5v ad5304 6 8 s 1/4 scale to 3/4 scale change (40 hex to c0 hex) ad5314 7 9 s 1/4 scale to 3/4 scale change (100 hex to 300 hex) AD5324 8 10 s 1/4 scale to 3/4 scale change (400 hex to c00 hex) slew rate 0.7 v/s major-code change glitch impulse 12 nv-s 1 lsb change around major carry. digital feedthrough 0.10 nv-s dac-to-dac crosstalk 0.01 nv-s multiplying bandwidth 200 khz v ref =2v0.1vpp total harmonic distortion -70 d b v ref =2.5vvpp. frequency=10khz. timing characteristics 1,2,3 (v dd = +2.5 v to +5.5 v. all specifications t min to t max unless otherwise noted) limit at t min , t max parameter (b version) units conditions/comments t 1 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 13 ns min sclk low time t 4 0 ns min sync to sclk rising edge setup time t 5 5 ns min data setup time t 6 4.5 ns min data hold time t 7 0 ns min sclk falling edge to sync rising edge t 8 33 ns min minimum sync high time notes 1 guaranteed by design and characterization, not production tested. 2 all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 3 see figure 1. ac characteristics 1 (v dd = +2.5v to +5.5 v; r l =2k w w w w w to gnd; c l =200pfto gnd; all specifications t min to t max unless otherwise noted.) notes 1 guaranteed by design and characterization, not production tested 2 see terminology 3 temperature range for b version: -40c to +105c. specifications subject to change without notice. figure 1. serial interface timing diagram sclk sync din db15 db0 t5 t6 t1 t3 t4 t7 t2 t8
C4C ad5304/ad5314/AD5324 preliminary technical data rev. pre preliminary technical data absolute maximum ratings 1,2 (t a = +25c unless otherwise noted) v dd to gnd.............................................-0.3v to +7v digital input voltage to gnd..........-0.3v to v dd + 0.3v reference input voltage to gnd.......-0.3v to v dd +0.3v v out a-d to gnd.........................-0.3 v to v dd + 0.3v operating temperature range industrial (b version)........................-40c to +105c storage temperature range..................-65c to +150c junction temperature (t j max) .........................+150c 10-lead microsoic package power dissipation..........................(t j max - t a ) / q ja q ja thermal impedance . . . . . . . . . . . . . . . . . . . 206c /w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . +215c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . +220c 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100ma will not cause scr latch-up pin function description pin numbers pin no. mnemonic function 1v dd power supply input. these parts can be operated from +2.5v to +5.5v and the supply should be decoupled to gnd. 2v out a buffered analog output voltage from dac a. the output amplifier has rail-to-rail operation. 3v out b buffered analog output voltage from dac b. the output amplifier has rail-to-rail operation. 4v out c buffered analog output voltage from dac c. the output amplifier has rail-to-rail operation. 5v ref reference input pin for all four dacs. it has an input range from 0v to v dd . 6v out d buffered analog output voltage from dac d. the output amplifier has rail-to-rail operation. 7 g n d ground reference point for all circuitry on the part. 8 d i n serial data input. this device has a 16-bit shift register. data is clocked into the register on the fall- ing edge of the serial clock input. the din input buffer is powered-down after each write cycle. 9 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data can be transferred at rates up to 30mhz. the sclk input buffer is powered-down after each write cycle. 10 sync active low control input. this is the frame synchronization signal for the input data. when sync goes low, it enables the input shift register and data is transferred in on the falling edges of the fol lowing 16 clocks. if sync is taken high before the 16th falling edge of sclk, the rising edge of sync acts as an interrupt and the write sequence is ignored by the device. ordering guide temperature package branding model range option* information ad5304brm -40c to +105c rm-10 dbb ad5314brm -40c to +105c rm-10 dcb AD5324brm -40c to +105c rm-10 ddb *rm = microsoic. pin configuration caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad5304/ad5314/AD5324 features proprietary esd protection circuitry, perma- nent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper precautions are recommended to avoid performance degradation or loss of functionality. 1 38 2 top view (not to scale) ad5304/ad5314/ AD5324 m soic 9 10 47 5 6
2 C5C ad5304/ad5314/AD5324 preliminary technical data rev. pre preliminary technical data terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot can be seen in figure x. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1lsb change between any two adjacent codes. a specified differential nonlinearity of 1lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code plot can be seen in figure x. offset error this is a measure of the offset error of the dac and the output amplifier. it is expressed as a percentage of the full-scale range. gain error this is a measure of the span error of the dac. it is the deviation in slope of the actual dac transfer characteristic from the ideal expressed as a percentage of the full-scale range. offset error drift this is a measure of the change in offset error with changes in temperature. it is expressed in (ppm of full- scale range)/c. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/c. power-supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is measured in dbs. v ref is held at +2v and v dd is varied 10%. dc crosstalk this is the dc change in the output level of one dac in response to a change in the output of the other dac. it is measured with a full-scale output change on one dac while monitoring the other dac. it is expressed in mv. reference feedthrough this is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated. it is expressed in dbs. major-code transition glitch energy major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the dac register changes state. it is normally specified as the area of the glitch in nv-secs and is measured when the digital code is changed by 1lsb at the major carry transi- tion (011...11 to 100...00 or 100...00 to 011...11). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital input pins of the device when the dac output is not being up- dated. it is specified in nv-secs and is measured with a worst-case change on the digital input pins, e.g. from all 0s to all 1s and vice versa. dac-to-dac crosstalk this is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s and vice versa) with the ldac bit set low and monitoring the output of another dac. the energy of the glitch is ex- pressed in nv-secs. multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3db below the input. total harmonic distortion this is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac and the thd is a measure of the harmonics present on the dac output. it is mea- sured in dbs.
C6C ad5304/ad5314/AD5324 preliminary technical data rev. pre preliminary technical data output voltage dac code negative offset error gain error + offset error negative offset error deadband actual ideal amplifier footroom (1mv) figure 2. transfer function with negative offset output voltage dac code positive offset gain error + offset error actual ideal figure 3. transfer function with positive offset
2 C7C ad5304/ad5314/AD5324 preliminary technical data rev. pre preliminary technical data functional description the ad5304/ad5314/AD5324 are quad resistor-string dacs fabricated on a cmos process with resolutions of 8, 10 and 12 bits respectively. each contains four output buffer amplifiers and each is written to via a 3-wire serial interface. they operate from single supplies of +2.5v to +5.5v and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7v/ m s. the four dacs share a single reference input pin. the devices have a pro- grammable power-down mode, in which all dacs may be turned off completely with a high-impedance output. digital-to-analog section the architecture of one dac channel consists of a resis- tor-string dac followed by an output buffer amplifier. the voltage at the v ref pin provides the reference voltage for the dac. figure 4 shows a block diagram of the dac architecture. since the input coding to the dac is straight binary, the ideal output voltage is given by: v ref * d v out = ---------- 2 n where d=decimal equivalent of the binary code which is loaded to the dac register; 0-255 for ad5304 (8-bits) 0-1023 for ad5314 (10-bits) 0-4095 for AD5324 (12-bits) n = dac resolution resistor string the resistor string section is shown in figure 5. it is sim- ply a string of resistors, each of value r. the digital code loaded to the dac register determines at what node on the string the voltage is tapped off to be fed into the out- put amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. be- cause it is a string of resistors, it is guaranteed monotonic. dac reference inputs there is a single reference input pin for the four dacs. the reference input is unbuffered. the user can have a reference voltage as low as gnd and as high as v dd since there is no restriction due to headroom and footroom of the reference amplifier. it is recommended to use a buffered reference in the ex- ternal circuit (e.g. ref192). the input impedance is typi- cally 180k w . output amplifier the output buffer amplifier is capable of generating rail- to-rail voltages on its output which gives an output range of 0v to v dd when the reference is v dd . it is capable of driving a load of 2k w to gnd or v dd, in parallel with 500pf to an ac gnd. the source and sink capabilities of the output amplifier can be seen in figure x. the slew rate is 0.7v/ m s with a half-scale settling time to +/-0.5 lsb (at 8 bits) of 6 m s. power-on reset the a5304/ad5314/AD5324 are provided with a power- on reset function, so that they power up in a defined state. the power-on state is: - normal operation - output voltage set to 0v both input and dac registers are filled with zeros and re- main so until a valid write sequence is made to the device. this is particularly useful in applications where it is im- portant to know the state of the dac outputs while the device is powering-up. r r r r r to output am plifier figure 5. resistor string refin input register dac register resistor string output buffer amplifier vouta figure 4. dac channel architecture
C8C ad5304/ad5314/AD5324 preliminary technical data rev. pre preliminary technical data serial interface the ad5304/ad5314/AD5324 are controlled over a versatile, 3-wire serial interface, which operates at clock rates up to 30mhz and is compatible with spi tm , qspi tm , microwire tm and dsp interface standards. input shift register the input shift register is 16-bits wide. data is loaded into the device as a 16-bit word under the control of a serial clock input, sclk. the timing diagram for this operation is shown in figure 1 on page 3. the 16-bit word consists of four control bits followed by 8, 10 or 12 bits of dac data, depending on the device type. the first two bits loaded are the bit 15 (msb) and bit 14. these determine whether the data is for dac a, dac b, dac c or dac d. bit 13 is pd which de- termines whether the part is in normal or power- down mode. bit 12 is ldac which controls when dac registers and outputs are updated. bits 13 and 12 control the operating mode of the dac. table 1. address bits for the ad53x4 a1 a0 dac addressed 0 0 dac a 0 1 dac b 1 0 dac c 1 1 dac d figure 6. ad5304 input shift register contents figure 7. ad5314 input shift register contents msb lsb a1 pd ldac d7 d6 d5 d4 d3 d2 d1 d0 x x x x data bits a0 msb lsb d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x data bits a1 pd ldac a0 address and control bits pd : 0: all four dacs go into power-down mode consuming only 200na @ 5v. the dac out- puts enter a high-impedance state. 1:normal operation. ldac : 0:all four dac registers and hence all dac outputs updated simultaneously on comple- tion of the write sequence. 1: addressed input register only is updated. there is no change in the contents of the dac registers. the AD5324 uses all 12 bits of dac data, the ad5314 uses 10 bits and ignores the two lsbs. the ad5304 uses 8 bits and ignores the last 4 bits. the data format is straight binary, with all zeros corresponding to 0v output and all ones corresponding to full-scale output (v ref - 1lsb). the sync input is a level-triggered input that acts as a frame synchronization signal and chip enable. data can only be transferred into the device whilst sync is low. to start the serial data transfer, sync should be taken low observing the minimum sync to sclk active edge setup time, t 4 . after sync goes low, serial data will be shifted into the device's input shift register on the falling edges of sclk for 16 clock pulses. any data and clock pulses after the 16th falling edge of sclk will be ignored because the sclk and din input buffers are powered down. no further serial data transfer will occur until sync is taken high and low again. figure 8. AD5324 input shift register contents msb lsb d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data bits a1 pd ldac a0
2 C9C ad5304/ad5314/AD5324 preliminary technical data rev. pre preliminary technical data sync may be taken high after the falling edge of the 16th sclk pulse, observing the minimum sclk falling edge to sync rising edge time, t 7 . after the end of serial data transfer, data will automatically be transferred from the input shift register to the input register of the selected dac. if sync is taken high be- fore the 16th falling edge of sclk, the data transfer will be aborted and the dac input registers will not be up- dated. when data has been transferred into three of the dac in- put registers, all dac registers and all dac outputs may be updated simultaneously, by setting ldac low when writing to the remaining dac input register. low-power serial interface to reduce the power consumption of the device even fur- ther, the interface only powers-up fully when the device is being written to. as soon as the 16-bit control word has been written to the part, the sclk and din input buffers are powered-down. they only power-up again following a falling edge of sync . double-buffered interface the ad5304/ad5314/AD5324 dacs all have double- buffered interfaces consisting of two banks of registers - input registers and dac registers. the input register is connected directly to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. the dac register contains the digital code which the resistor string uses. access to the dac register is controlled by the ldac bit. when the ldac bit is set high, the dac register is latched and hence the input register may change state without affecting the contents of the dac register. how- ever, when the ldac bit is set low, all dac registers are updated after a complete write sequence. this is useful if the user requires simultaneous updating of all dac outputs. the user may write to three of the input registers individually and then, by setting the ldac bit low when writing to the remaining dac input register, all outputs will update simultaneously. these parts contain an extra feature whereby the dac register is not updated unless its input register has been updated since the last time that ldac was brought low. normally, when ldac is brought low, the dac registers are filled with the contents of the input registers. in the case of the ad5304/ad5314/AD5324, the part will only update the dac register if the input register has been changed since the last time the dac register was updated thereby removing unnecessary digital crosstalk. power-down mode the ad5304/ad5314/AD5324 have low power consump- tion, dissipating only 1.5mw with a 3v supply and 3mw with a 5v supply. power consumption can further be re- duced when the dacs are not in use by putting them into power-down mode, which is selected by bit 13 ( pd ) of the control word. when the pd bit is set to 1, the relevant dac works nor- mally with its normal power consumption of approx 150 m a at 5v. however, in power-down mode, the supply current falls to 200na at 5v (50na at 3v) when all dacs are powered-down. not only does the supply current drop but the output stage is also internally switched from the output of the amplifier to a resistor network of known val- ues. this has the advantage that the output impedance of the part is known while the part is in power-down mode and provides a defined input condition for whatever is connected to the output of the dac amplifier. the output stage is illustrated in figure x. the bias generator, the output amplifier, the resistor string and all other associated linear circuitry are all shut down when the power-down mode is activated. however, the contents of the registers are unaffected when in power- down. the time to exit power-down is typically 2.5 m s for v dd =5v and 5 m s when v dd =3v. resistor string dac vout resistor network pow er- down circuitry amplifier figure 9. output stage during power-down
C10C ad5304/ad5314/AD5324 preliminary technical data rev. pre preliminary technical data outline dimensions dimensions shown in inches and (mm). 10-lead microsoic (rm-10) 0.0197 (0.50) bsc 0.122 (3.10) 0.114 (2.90) 10 6 5 1 0.199 (5.05) 0.187 (4.75) pin 1 0.122 (3.10) 0.114 (2.90) 0.012 (0.30) 0.006 (0.15) 0.037 (0.94) 0.031 (0.78) seating plane 0.120 (3.05) 0.112 (2.85) 0.043 (1.10) max 0.006 (0.15) 0.002 (0.05) 0.028 (0.70) 0.016 (0.40) 0.009 (0.23) 0.005 (0.13) 6 o 0 0.120 (3.05) 0.112 (2.85) o
2 C11C ad5304/ad5314/AD5324 preliminary technical data rev. pre preliminary technical data part no. resolution no. of dacs dnl interface settling time package pins singles ad5300 8 1 0.25 spi 4 m s sot-23, m soic 6,8 ad5310 10 1 0.5 spi 6 m s sot-23, m soic 6,8 ad5320 12 1 1.0 spi 8 m s sot-23, m soic 6,8 ad5301 8 1 0.25 2-wire 6 m s sot-23, m soic 6,8 ad5311 10 1 0.5 2-wire 7 m s sot-23, m soic 6,8 ad5321 12 1 1.0 2-wire 8 m s sot-23, m soic 6,8 duals ad5302 8 2 0.25 spi 6 m s m soic 8 ad5312 10 2 0.5 spi 7 m s m soic 8 ad5322 12 2 1.0 spi 8 m s m soic 8 ad5303 8 2 0.25 spi 6 m s tssop 16 ad5313 10 2 0.5 spi 7 m s tssop 16 ad5323 12 2 1.0 spi 8 m s tssop 16 quads ad5304 8 4 0.25 spi 6 m s m soic 10 ad5314 10 4 0.5 spi 7 m s m soic 10 AD5324 12 4 1.0 spi 8 m s m soic 10 ad5305 8 4 0.25 2-wire 6 m s m soic 10 ad5315 10 4 0.5 2-wire 7 m s m soic 10 ad5325 12 4 1.0 2-wire 8 m s m soic 10 ad5306 8 4 0.25 2-wire 6 m s tssop 16 ad5316 10 4 0.5 2-wire 7 m s tssop 16 ad5326 12 4 1.0 2-wire 8 m s tssop 16 ad5307 8 4 0.25 spi 6 m s tssop 16 ad5317 10 4 0.5 spi 7 m s tssop 16 ad5327 12 4 1.0 spi 8 m s tssop 16 overview of all ad53xx serial devices

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