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never stop thinking. wired communications data sheet, ds1, june 2002 green 24+2g ethernet switch on chip plb 2224 version 1.3
edition 2002-06-03 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 2002. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com. data sheet revision history: 2002-06-03 ds1 previous version: 01.01 page subjects (major changes since last revision) page 23 page 202 page 141 updated package & ball pin assignment, added ac characteristics, added register definitions page 106 page 218 updated iic interface, package details page 202 page 196 updated timing information, register default values
green plb 2224 table of contents page data sheet 3 2002-06-03 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2.1 ports & network interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2.2 switch engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2.3 management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.2.4 benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.3 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.4 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5 typical configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.1.1 signal list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2 functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2.1 10/100/1000 mbit/s media access control (gmac/mac) . . . . . . . . . . . 31 3.2.1.1 10/100 ethernet ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2.1.2 gigabit ethernet ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2.1.3 mdio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.2.2 receive module (rx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.2.3 port configuration, status and event registers . . . . . . . . . . . . . . . . . . 34 3.3 switch controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.3.1 packet data buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.3.2 address resolution logic (arl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.3.3 address learning and updating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.3.3.1 plb 2224 is not configured for auto learning . . . . . . . . . . . . . . . . . 39 3.3.3.2 global updating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.3.3 address resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.3.4 address aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3.3.5 configuring ma table using cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3.4 port tx and mac tx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3.4.1 packet queuing and port queues . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3.4.2 packet scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3.5 packet & queue manager (pqc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3.6 transmit module (tx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.3.6.1 receiving and sending packets from the cpu port . . . . . . . . . . . . . 43 3.3.6.2 cpu port rx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.3.6.3 cpu port tx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3.7 mdio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3.7.1 auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
green plb 2224 table of contents page data sheet 4 2002-06-03 3.3.8 led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.9 reset and initialisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3.9.1 power strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3.9.2 delay select for smii_rclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.4 features for a managed switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.4.1 flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.4.2 spanning tree protocol support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.4.3 packet monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.4.4 packet prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.5 registers in plb 2224 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4 data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.1 internal memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.1.1 vlan memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.1.2 pbl (packet buffer link list) ? 1 k x 2 bytes . . . . . . . . . . . . . . . . . . . . 58 4.1.3 bcastq (broadcast queue) ? 256 x 2 bytes x 32 = 16 kbytes . . . . 58 4.1.4 ma (mac address) - 64 kbyte for up to 8 k addresses . . . . . . . . . . . . 58 4.2 indirect access to the memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.2.1 access to edram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.2.2 access to mib counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.2.2.1 vlan memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.3 network management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.1 data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.1.1 frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.1.2 ingress filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.1.3 frame forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.1.4 egress filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.1.5 frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.1.6 terminating or originating frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.1.7 cpu transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.2 flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.3 statistics registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.4 packet classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.4.1 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.4.1.1 desired filters and actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.4.1.2 pattern register setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.5 packet monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.6 packet prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.7 trunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.8 address learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.9 mac address table and filtering table . . . . . . . . . . . . . . . . . . . . . . . . . . 88
green plb 2224 table of contents page data sheet 5 2002-06-03 5.9.1 accessing the address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.9.2 mac table entry formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.9.3 storage of the mac tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.9.4 forwarding frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.9.4.1 frame forwarding example with snmp . . . . . . . . . . . . . . . . . . . . . . 89 5.9.4.2 using the cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.10 vlan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.10.1 vlan introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.10.2 vlan configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.10.3 vlan operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.10.3.1 vlan memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.10.4 vlan ingress filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.10.5 vlan tag conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.10.6 vlan security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.10.6.1 vlan membership/port list determination . . . . . . . . . . . . . . . . . . . . 94 5.11 spanning tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.11.1 description of spanning tree support . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.11.1.1 spanning tree topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.11.2 spanning tree protocol support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.12 snmp and rmon mibs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.13 led . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6 interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.1 external interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.1.1 10/100 phys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.1.2 gigabit phys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.1.3 mdio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.1.4 led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.1.5 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.1.6 clock / reset interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.2 cpu and eeprom interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.2.1 cpu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.2.2 i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.2.2.1 the pci local bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.2.2.2 the generic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.2.2.3 pci interface details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.2.2.4 generic interface signals description . . . . . . . . . . . . . . . . . . . . . . . 111 6.2.2.5 iic interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.2.3 i2c bus concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.2.3.1 start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.2.3.2 application note for iic interface of plb 2224 . . . . . . . . . . . . . . . . 115 6.3 pci command definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.4 pci configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
green plb 2224 table of contents page data sheet 6 2002-06-03 7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.1 pci configuration phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.2 switch configuration phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 7.2.1 chip level configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 7.2.2 port level configuration and monitoring . . . . . . . . . . . . . . . . . . . . . . . 124 7.2.3 switch level configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 7.2.4 vlan and bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7.2.5 bpdu transmission and receiving . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 7.3 plb 2224 pci configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . 131 7.3.1 register 0x00, pci configuration space id . . . . . . . . . . . . . . . . . . . . 132 7.3.2 register 0x04, pci configuration space status and command . . . . 133 7.3.3 register 0x08, pci configuration class . . . . . . . . . . . . . . . . . . . . . . . 137 7.3.4 register 0x0c, pci configuration miscellaneous 0 . . . . . . . . . . . . . . . 138 7.3.5 register 0x3c, pci configuration miscellaneous 1 . . . . . . . . . . . . . . . 140 7.4 PLB2224 internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 7.4.1 chip configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 7.4.2 chip type register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 7.4.3 switch configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 7.4.4 switch status and mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 7.4.5 port status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 7.4.6 port event register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 7.4.7 port underrun/overrun register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 7.4.8 port mii register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 7.4.9 port monitor register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 7.4.10 port priority register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 7.4.11 port trunk register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 7.4.12 port bridge state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 7.4.13 portlist_1023 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 7.4.14 port index register_20_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 7.4.15 da index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 7.4.16 memory upper address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 7.4.17 memory access register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 7.4.18 cmac data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 7.4.19 cmac rx register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 7.4.20 cmac tx register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 7.4.21 cmac_tx1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 7.4.22 arl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 7.4.23 freeq register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 7.4.24 freeq_cnt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 7.4.25 cpu_txq26 count register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 7.4.26 cpu_txq27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 7.4.27 cpu water mark register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
green plb 2224 table of contents page data sheet 7 2002-06-03 7.4.28 fe watermark control (tx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 7.4.29 fe watermark control (rx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 7.4.30 gport watermark control (tx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 7.4.31 gport watermark control (rx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 7.4.32 tag priority table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 7.4.33 egress priority table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 7.4.34 port cfi register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 7.4.35 vlan aware/intag control register . . . . . . . . . . . . . . . . . . . . . . . . . . 182 7.4.36 vlan ingress filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 7.4.37 port index register 26_21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 7.4.38 led data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 7.4.39 pattern registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 7.4.40 offset registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 7.4.41 offset group register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 7.4.42 op_table registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 7.4.43 action_table registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 7.4.44 enable filtering register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 7.4.45 gmac registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 7.4.46 g_mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 7.4.47 g_pcs0 register / gport link status register . . . . . . . . . . . . . . . . . . 195 7.4.48 g_pcs_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 7.4.49 g_pcs_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 8 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 8.1 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 8.1.1 mdio interface timing details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 8.1.2 smii interface timing details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 8.1.3 gmii/tbi interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 8.1.4 pci interface / generic interface timing . . . . . . . . . . . . . . . . . . . . . . . 205 8.1.5 timing parameters ( figure 29 to figure 36 ) . . . . . . . . . . . . . . . . . . 213 8.1.6 serial led interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 8.1.7 iic timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 9 package details (p-bga-272) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
green plb 2224 list of figures page data sheet 8 2002-06-03 figure 1 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 2 general system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 3 48 x 10/100 mbit/s port managed solution . . . . . . . . . . . . . . . . . . . . . 17 figure 4 mdu/mtu application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5 pin configuration (bottom view: power & ground pins) . . . . . . . . . . . 20 figure 6 pin configuration ( top view: functional part 1) . . . . . . . . . . . . . . . . . 21 figure 7 pin configuration ( top view: functional part 2) . . . . . . . . . . . . . . . . . 21 figure 8 pin configuration (top view: functional part 3) . . . . . . . . . . . . . . . . . 22 figure 9 pin configuration (top view: functional part 3) . . . . . . . . . . . . . . . . . 22 figure 10 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 11 destination port list creation (vlan?s disabled) . . . . . . . . . . . . . . . . 40 figure 12 matrix mode led connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 13 delay control for smii clock internally . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 14 flow control mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 15 packet classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 16 vlan tag conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 17 address resolution/destination port list creation (vlan enabled) . . 94 figure 18 vlan membership determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 19 start & stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 20 data transfer on the iic bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 21 acknowledge on the i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 22 read protocol for iic bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 23 write protocol for iic interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 24 mdio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 figure 25 smii interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 figure 26 gmii/tbi tx. interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 figure 27 gmii/tbi rx. interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 figure 28 pci / generic interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 figure 29 32-bit generic interface write cycle - separate addr/data / r / w. . 206 figure 30 32-bit generic interface read cycle - separate addr / data / r / w. 207 figure 31 32-bit generic interface write cycle - separate addr / data with strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 figure 32 32-bit generic interface write cycle - separate addr / data with strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 figure 33 32-bit generic interface read - muxed addr / data & separate r/w 210 figure 34 32-bit generic interface write - muxed addr / data & separate r/w 211 figure 35 32-bit generic interface write cycle - muxed addr / data with strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 figure 36 32 bit generic interface read cycle - muxed addr/data with strobe 213 figure 37 serial led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 figure 38 iic interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
green plb 2224 list of tables page data sheet 9 2002-06-03 table 1 typical configurations using plb 2224 . . . . . . . . . . . . . . . . . . . . . . . 19 table 2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 3 pbh header format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 4 packet buffer header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 5 ma entry formats for unicast and multicast addresses . . . . . . . . . . . 37 table 6 ma table entry types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 7 pbh packet length for different crc_gen & pkt_padding bits . . . . . . . 45 table 8 matrix led modes (per port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 9 power strapping table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 10 spanning tree states and actions . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 11 register table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 12 edram details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 13 sram details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 14 internal memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 15 vlan memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 16 pbl format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 17 broadcast queue entry format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 18 packet buffer header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 19 ma format for unicast entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 20 ma format for multicast entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 21 memory upper address register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 22 memory access register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 23 vlan memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 24 rx counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 25 tx counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 26 vlan rx counters (per vlan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 27 vlan tx counters (per vlan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 28 group[3] set to detect ip in ethernet ii format . . . . . . . . . . . . . . . . . . 81 table 29 group[2] set to detect ip in 802.3 snap . . . . . . . . . . . . . . . . . . . . . . 81 table 30 group[1] used for ip packets in ethernet ii format . . . . . . . . . . . . . . 82 table 31 group[0] -used for ip packets in 802.3 snap format . . . . . . . . . . . . 82 table 32 group[3] -op code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 33 action code table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 34 trunk combination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 35 ma entry formats for unicast and multicast addresses . . . . . . . . . . . 88 table 36 vlan table entry format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 37 vlan memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 38 vlan ingress filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 39 qualification of packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 40 spanning tree states and actions . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 41 snmp receiving counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 42 snmp transmitting counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
green plb 2224 list of tables page data sheet 10 2002-06-03 table 43 led configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 44 correspondence between pci/generic and iic interface . . . . . . . . . 108 table 45 pci interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 46 generic interface signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 47 i2c interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 48 definition of iic bus terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 49 pci command definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 50 pci configuration register address space . . . . . . . . . . . . . . . . . . . . 120 table 51 chip level configration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 52 port level configuration and monitoring . . . . . . . . . . . . . . . . . . . . . . 124 table 53 switch level configuration setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 54 vlan and bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 55 filtering configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 56 mac address accessing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 57 bpdu transmission and reception . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 58 pci configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 59 pci configuration space id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 60 register 0x08 pci configuration class . . . . . . . . . . . . . . . . . . . . . . . 137 table 61 register 0x0c pci config miscellaneous0 . . . . . . . . . . . . . . . . . . . . 138 table 62 register 0x10, pci configuration base address . . . . . . . . . . . . . . . . 139 table 63 register 0x3c, pci configuration miscellaneous 1 . . . . . . . . . . . . . . 140 table 64 chip configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 65 chip_type register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 66 switch configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 67 switch status and mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 68 port status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 69 port event register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 70 port underrun/overrun register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 71 port mii register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 72 port monitor register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 73 port priority register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 74 port trunk register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 75 port bridge state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 76 portlist_1023 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 77 port index register_20_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 78 da index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 79 memory upper address register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 80 memory access register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 81 cmac data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 82 cmac rx register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 83 cmac tx register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 84 cmac_tx1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
green plb 2224 list of tables page data sheet 11 2002-06-03 table 85 arl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 86 freeq register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 87 freeq_cnt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 88 cpu txq26 count register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 89 cpu_txq27 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 90 cpu water mark register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 91 fe tx watermark control register . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 92 fe rx watermark control register . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 93 gport tx watermark control register . . . . . . . . . . . . . . . . . . . . . . . . 178 table 94 gport rx watermark control register . . . . . . . . . . . . . . . . . . . . . . . 179 table 95 tag priority table register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 96 egress priority table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 97 port cfi register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 98 vlan aware/intag control register . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 99 vlan ingress filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 100 port index register 26_21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 101 led data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 table 102 pattern registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 103 offset group0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 104 offset group1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 table 105 op_table registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 106 action_table registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 107 enable filtering register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 108 g_rxtx register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 109 g_mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 table 110 g_pcs_0 / gport link status register . . . . . . . . . . . . . . . . . . . . . . . 196 table 111 g_pcs_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 112 g_pcs_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 113 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 table 114 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 table 115 dc characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 116 ac characteristics mdio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 table 117 ac characteristics - smii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 118 ac characteristics gmii tx. interface . . . . . . . . . . . . . . . . . . . . . . . . 204 table 119 ac characteristics gmii rx. interface . . . . . . . . . . . . . . . . . . . . . . . . 205 table 120 ac characteristics pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 table 121 32-bit generic interface timing parameters . . . . . . . . . . . . . . . . . . . 213 table 122 serial led interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 table 123 iic bus timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 table 124 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
green plb 2224 overview data sheet 12 2002-06-03 1overview 1.1 introduction plb 2224 is a single chip multiport ethernet switch, with embedded frame buffer & address table memory. plb 2224 is a single-chip solution for building high-port count workgroups and wiring closet fast ethernet switches. the architecture allows the device to implement standalone and stackable fast ethernet switches, which are low-cost, low part-count and have low power implementations. plb 2224 provides a high level of integration, it provides 24 fast ethernet and 2 gigabit ethernet ports. it is capable of supporting wire-speed, full-duplex packet traffic on all ports under worst-case traffic conditions. plb 2224 provides 32-bit pci or generic cpu interface as well as a 2-wire master/slave serial interface for connecting an external micro-controller for managed switch implementation. the device is based on infineon 0.18 embedded dram process & integrates all the necessary memory required to implement full duplex wire speed switch for 24 fast ethernet ports with 2 gigabit uplink ports. hence the device can be targeted for both high performance ethernet core switches or high density ethernet edge switches. the on chip frame buffer is organized as 2 banks of 256-bit wide embedded dram, operating at 100 mhz, providing up to 16 gbit/s memory bandwidth. plb 2224 can achieve packet forwarding/switching speed of up to 8 million packets per second. it provides 2 priority queues per port to enable time sensitive data have access to the network with minimal delay. smii support on 10/100 mbit/s interfaces & gmii/mii/tbi on gigabit interface is provided. matrix & serial interface for port status leds is provided. embedded packet buffer & address table allows low pin count packaging in a p-bga-272 pin package. this ?system on chip? solution enables system designers to develop cost effective unmanaged/managed/intelligent switches. the core logic operates at 1.8 v & i/os operate at 3.3 v.
data sheet 13 2002-06-03 type package plb 2224 p-bga-272 24+2g ethernet switch on chip green plb 2224 version 1.3 p-bga-272-1 1.2 features 1.2.1 ports & network interfaces high performance gigabit fast ethernet switch controller, wire-speed operation on every port. single chip with twentyfour x 10/100 mbit/s and two x gbit/s ports (10/100/1000 mbit/s ports) smii interface on 10/100 mbit/s ports ? supports auto- negotiation for speed and duplex setting. gmii and pma interface on gigabit ports (full-duplex only) and optional mii interface support on gigabit ports, half duplex is supported in 10/100 mbit/s mode only. full-duplex ieee 802.3x flow control and collision-based congestion control in half- duplex provide packet switching functions between 1000/100/10 mbit/s & fast ethernet ports support 802.3ad based port trunking for high-bandwidth inter-switch links. 2/4/8 10/100 ports or 2 gigabit ports can be combined to form trunks ? multiple trunks per device 1.2.2 switch engine support wire-speed switching with low latency using store-and-forward switching. fast latency time for both unicast and broadcast. best broadcast throughput performance address learning and resolution ? up to 8 k entries, auto-learning and auto-aging. two priority levels per port for cos support ? wfq scheduling. supports both port-based and tagged 802.1q vlan scheme for up to 1 k active vlans port monitoring and forwarding of packets to the cpu port
green plb 2224 overview data sheet 14 2002-06-03 1.2.3 management allow network administrators to create layer 2 mac-address based filters to constrain users to particular destinations, implement basic layer 2 security, and simulate a multicast environment using static filters. support extensive traffic/network management through snmp, four critical groups of rmon (statistics, history, alarms, events) and mibs. supports ieee 802.1d spanning tree for network loop detection and disabling (particularly useful in larger networks) and for fault-tolerant connectivity supports secure mode traffic filtering on a per port basis pci compliant 32-bit, 33 mhz cpu interface. can also be used as a generic interface with multiplexed or separate address/data. glueless interface to many 32-bit processors. 2-wire serial interface for configuration i 2 c e2prom or cpu connection for unmanaged, minimally managed or stackable switches. supports local console and telnet interface for operation, administration, and maintenance. simple to use and troubleshoot, with minimum reconfigurations required. new software releases can be downloaded either locally or over the network glue less led interfaces ? four status leds per port for displaying buffer utilization at each port (optional serial interface for leds for customer specific glue logic) 1.2.4 benefits embedded packet buffer & address table enables low cost system design.support for up to 1 k port/tag based vlan (ieee 802.1q) with up to 3 mibs per vlan, enables application in mdu/mtu markets.
green plb 2224 overview data sheet 15 2002-06-03 1.3 logic symbol the vaious interfaces that are available on plb 2224 is shown in the figure below. figure 1 logic symbol port #2 gmii/tbi port #1 gmii/tbi pci/generic-host interface mdio interface iic master/slave serial/matrix led interface reset sys_clock 100mhz jtag interface PLB2224 port #24 smii port #23 smii port #2 smii port #1 smii mac_clock 125mhz
green plb 2224 overview data sheet 16 2002-06-03 1.4 typical applications figure 2 to figure 4 gives a general overview of system integration of the plb 2224 figure 2 general system integration PLB2224 power & reset controller management cpu (optional) clock generator 4x27 led matrix customer specific led glue logic serial/matrix led interface configuration eeprom/ ucontroller iic pci/ generic- host interface serdes/ copper gigabit phy octal smii phy magnetics/rj45/ optical connector magnetics/ rj45 2 x gmii/tbi 24 x smii
green plb 2224 overview data sheet 17 2002-06-03 figure 3 48 x 10/100 mbit/s port managed solution management cpu 2 x gmii 24/25 PLB2224 leds PLB2224 leds octal smii phy 8 x smii octal smii phy 8 x smii octal smii phy 8 x smii octal smii phy 8 x smii octal smii phy 8 x smii octal smii phy 8 x smii
green plb 2224 overview data sheet 18 2002-06-03 figure 4 mdu/mtu application office building or apartments networked remote buildings basement wiring closet optical cable network t3 line ar2224 da t a/ pow er /g r ou nd 2-w ir e i /f 32-bit i/f s mi i gmi i ssram sdram oc t al smii phy oc t al smii phy pe f 2 2822 pe f 2 2811 pe f 2 2822 pe f 2 2811 pe f 2 2822 pe f 2 2811 pe f 2 2822 pe f 2 2811 s mi i s mi i layer 2 switch telephone wiring to each room cat5 cabling to businessservices application servers cat5 cabling www lsp core switch 100 mbps bandwidth infineon-ardent's layer 2 switch connections gigabit bandwidth within each room computer telephone tv cpe business services 10 mbps bandwidth
green plb 2224 overview data sheet 19 2002-06-03 1.5 typical configurations switches in a variety of different configurations can be designed using plb 2224. the table below shows a few configurations that can be built and the major components that are needed to build them. table 1 typical configurations using plb 2224 plb 2224 10 /100 octal phy gbit phy cpu subsys comments 24 10/100 + 2ge fully managed 1 3 2 32-bit generic or pci 24 10/100 + 2ge minimally managed 1 3 2 8-bit with 2 wire serial interface spanning tree protocol only 24 10/100 + 2 ge soho with wan router 2 3 2 32-bit generic or pci 48 10/100 standalone, managed 2 6 0 32-bit generic or pci 48 10/100 low-cost unmanaged 2 6 0 none uses eeprom for initial configuration 24 x 10/100 stackable managed 1 3 2 32-bit generic with 2-wire serial interface ge ports used to connect stack elements, 2-wire serial interface is used to communicate between stack elements 32x 10/100 stackable, managed 2 6 0 32-bit generic with 2-wire serial interface 8 10/100 ports from each plb 2224 are used to form two trunks that are used for connecting the stack. 2 wire serial interface is used to communicate between stack elements
green plb 2224 pin descriptions data sheet 20 2002-06-03 2 pin descriptions the pin diagram for plb 2224 is shown in figure 5 . the package used is p-bga-272 pin diagram figure 5 pin configuration (bottom view: power & ground pins) p-bga-272 b a c d e h f g j k m l n p r u t v w y 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 b a c d e h f g j k m l n p r u t v w y 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 1 4 3 2 27 mm 27 mm vss (gnd) (35 balls) vddp (3.3v) (12 balls) vdd (1.8v) (12 balls) functional (213 balls)
green plb 2224 pin descriptions data sheet 21 2002-06-03 figure 6 pin configuration ( top view: functional part 1) figure 7 pin configuration ( top view: functional part 2) 1 2 3 4 5678910 a gnd trst bist_enab le frame_n vddp par pci_clk cbe_n0 cbe_n3 ad3 b scl tms eeprom_s peed mdc devsel _n perr_n trdy_n cbe_n1 ad0 ad4 c t_rsv1 tdi reset_n mdio stop_n vdd idsel cbe_n2 ad1 ad5 d led_row _n1 t_rsv2 tck gnd inta_n serr_n irdy_n gnd ad2 vdd e vddp normal_ mode sel_iic t_rsv f led_col 24 led_row _n0 vdd sda g led_col 23 led_col 25 led_row _ n3 tdo h led_col 20 led_col 22 led_col26 gnd j led_col 18 led_col 19 led_col21 led_row _n2 gnd gnd k led_col 15 led_col 17 clk100 vdd gnd gnd 11 12 13 14 15 16 17 18 19 20 ad6 ad7 ad10 ad14 ad18 vddp ad23 ad27 ad31 gnd a vddp ad9 ad13 ad16 ad20 ad22 ad26 ad30 crs0 r_0_1 b ad8 ad11 ad15 ad19 vdd ad25 ad28 test_e nable r_0_0 r_0_5 c ad12 ad17 gnd ad21 ad24 ad29 gnd coll0 r_0_4 r_0_8 d ew rap r_0_3 r_0_6 vddp e r_0_2 vdd rclkn0 rclk0 f r_0_7 r_0_9 t_0_0 t_0_2 g gnd t_0_1 t_0_3 t_0_6 h g nd g nd t_0_4 t_0_5 t_0_7 t_0_8 j g nd g nd vdd t_0_9 m ii_ t x c lk0 gtx_cl k0 k
green plb 2224 pin descriptions data sheet 22 2002-06-03 figure 8 pin configuration (top view: functional part 3) figure 9 pin configuration (top view: functional part 3) l led_col 13 vddp led_col14 led_col 16 gnd gnd m led_col 12 led_col 11 led_col10 led_col 9 gnd gnd n led_col 8 led_col 7 led_col6 gnd p led_col 5 led_col 4 led_col2 sm ii_c lk _7_0 top r led_col 3 led_col 1 v d d s m ii_t x 01 t vddp led_col 0 s m ii_r x 01 sm ii_r x 0 2 u smii_syn c_7_0 smii_rx0 0 smii_tx02 gnd smii_tx 04 s m ii_t x 06 s m ii_r x 08 gnd smii_rs ync_15_ 8 vdd v s m ii_t x 00 smii_rcl k_7_0 s m ii_r x 03 sm ii_r x 0 5 s m ii_r x 07 vdd s m ii_r x 09 smii_tx 10 s m ii_r c lk_15_8 s m ii_r x 13 w s m ii_r sy nc_7_0 s m ii_t x 03 sm ii_t x 05 s m ii_t x 07 sm ii_c l k_15_8 gnd sm ii_tx 09 sm ii_r x 11 smii_rx 12 smii_tx 13 y gnd smii_rx0 4 s m ii_r x 06 smii_syn c_15_8 vddp s m ii_t x 08 s m ii_r x 10 smii_tx 11 s m ii_tx 12 s m ii_r x 14 1 2 3 4 5678910 gnd gnd r_1_4 r_1_0 vddp sdet0 l gnd gnd clk125 r_1_5 r_1_2 r_1_1 m gnd r_1_8 r_1_6 r_1_3 n view t_1_0 vdd r_1_9 r_1_7 p t_1_5 gnd rclk1 rclkn1 r t_1_8 sdet1 m ii_t x c lk1 vddp t smii_sy nc_23_1 6 s m ii_c l k_23_16 gnd smii_tx 19 s m ii_t x 20 s m ii_t x 22 gnd t_1_7 t_1_3 t_1_1 u s m ii_t x 14 s m ii_r x 16 s m ii_r x 18 smii_rs ync_23_ 16 vdd s m ii_t x 21 smii_tx 23 gtx_cl k1 t_1_6 t_1_2 v vddp smii_tx 16 s m ii_t x 17 sm ii_r x 19 gnd smii_rx 20 s m ii_r x 22 crs1 t_1_9 t_1_4 w smii_rx 15 smii_tx 15 s m ii_r x 17 smii_tx 18 smii_rc lk_23_1 6 vddp s m ii_r x 21 smii_rx 23 coll1 gnd y 11 12 13 14 15 16 17 18 19 20
green plb 2224 pin descriptions data sheet 23 2002-06-03 2.1 pin definitions and functions 2.1.1 signal list table 2 pin descriptions symbol type/ (default internal state of the pins) function width system clock, reset & jtag control pins clk100 i system clock, 100 mhz 1 clk125 i clock input for all macs (125 mhz) 1 reset_n i power on reset. must be asserted longer than 2 cycles of clock to cause reset. (being defined in pci spec.) 1 trstn, tck, tms, tdi, i / (pull down) i / (pull up) i / (pull up) i / (pull up) these pins are for test purposes including full-scan, boundary-scan, bist-mode, etc. they function only when ?normal_mode? pin is 1. otherwise, the pins are only for debugging purposes. the functions of the pins in ?normal_mode? mode are as follows: trst: boundary scan?s enable or!reset. tck: boundary scan?s clock. tms: boundary scan?s mode select. tdi: boundary scan?s data in. 5 tdo o this pin is used as boundary scan?s tdo 1 bootstrap pins (must be initialized for proper operation) normal_mode i / (pull up) this bit needs to be 1 for normal operation. it is pulled down only for debugging purposes. 1
green plb 2224 pin descriptions data sheet 24 2002-06-03 sel_iic i pci interface: sel_iic = 0 / sel_pci =1 generic interface: sel_iic = 0 / sel_pci = 0 serial iic: sel_iic = 1 / sel_pci = 0 1 t_rsv (nc) i reserved (= 0) 1 t_rsv1 (sel_pci) i pci interface: sel_pci=1 generic interface: sel_pci = 0 1 t_rsv2 (one_wait_cycle / muxed ad) i pci interface: number of trdy wait cycles generic interface: multiplexed address/ data bus. 1 bist_enable i enable for bist mode of operation: to be tied to gnd for normal operation. 1 test_enable i for scan mode: to be tied to ?0? for normal operation. 1 eprom_speed i 1: data rate 3.3 mhz 0: data rate = 100 khz (this is valid only when led_row_n[2] is pin strapped to 1) 1 smii: fast ethernet interface smii_sync_7_0 o, (15 ma) smii sync output for ports 0 to 7 1 smii_sync_15_8 o, (15 ma) smii sync output for ports 8 to 15 1 smii_sync_23_16 o, (15 ma) smii sync output for ports 16 to 23 1 smii_rsync_7_0 i smii sync input for ports 0 to 7 1 smii_rsync_15_8 i smii sync input for ports 8 to 15 1 smii_rsync_23_16 i smii sync output for ports 16 to 23 1 smii_clk_7_0 o, (15 ma) smii clk output for ports 0 to 7 1 smii_clk_15_8 o, (15 ma) smii clk output for ports 8 to 15 1 smii_clk_23_16 o, (15 ma) smii clk output for ports 16 to 23 1 table 2 pin descriptions (cont?d) symbol type/ (default internal state of the pins) function width
green plb 2224 pin descriptions data sheet 25 2002-06-03 smii_rclk_7_0 i smii clk input for ports 7 to 0 1 smii_rclk_15_8 i smii clk input for ports 15 to 8 1 smii_rclk_23_16 i smii clk input for ports 16 to 23 1 smii_rx [23:0] i (pull down) fast ethernet receive data (if some of the ports are not used they can be left open, pulldown value 15 k) 24 smii_tx [23:0] o, (15 ma) fast ethernet transmit data 24 tbi/gmii: gigabit ethernet interface ewrap o, (15 ma) gb phy to loopback internally if 1. 1 rclk[1:0], rclkn[1:0] i (pull up) gb receive clocks 4 mii_txclk[1:0] i (pull up) mii_tx clock inputs when mii interface is used 2 t_(1-0)_[9:0] o, (15 ma) gb transmit character for the 2 gport 20 gtx_clk[1:0] o, (15 ma) gb phy?s 125 mhz gb?s tx_clk 2 sdet[1:0] i (pull down) gb light detection. internal pulldown value is 15 k 2 r_(1-0)_[9:0] i (pull down) gb receive character. internal pulldown value is 15 k 20 crs[1:0] i carrier sense, used in mii mode for half-duplex operation 2 coll[1:0] i collision detect, used in mii mode for half-duplex operation 2 phy management and led interface mdc o, (15 ma) phy management clock 1 mdio b, (15 ma) phy management data 1 led_row_n[3:0] b, (5 ma) led row output. active low. ( internal pullup of 20 k and a value of 1 k can be used for pulling down this line for pinstrap inputs) 4 table 2 pin descriptions (cont?d) symbol type/ (default internal state of the pins) function width
green plb 2224 pin descriptions data sheet 26 2002-06-03 led_col[26:0] b, (5 ma) led column output. active high ( internal pullup of 20 k and a value of 1 k can be used for pulling down this line for pinstrap inputs) 27 cpu interface pci_clk i pci clk 1 ad<31:0> b, (6 ma) pci interface : address data bus generic interface : ad bus 32 cbe_n<3> b, (6 ma) pci interface : command byte enable generic interface : ale or address strobe 1 cbe_n<2> b, (6 ma) pci interface : command byte enable generic interface : data strobe 1 cbe_n<1> b, (6 ma) pci interface : command byte enable generic interface : data strobe or read 1 cbe_n<0> b, (6 ma) pci interface : command byte enable generic interface : read/write 1 frame_n b, (6 ma) pci interface : framing signal generic interface : chip select serial interface : master mode 1 trdy_n o, (6 ma) pci interface : target ready generic interface : ready 1 idsel i pci interface : initialization device select generic interface : address bit 8 1 irdy_n i pci interface : initiator ready signal generic interface : address bit 2 serial : device id bit 0 1 par b, (6 ma) pci interface : parity check bit generic interface : address bit 3 serial : device id bit 0 1 table 2 pin descriptions (cont?d) symbol type/ (default internal state of the pins) function width
green plb 2224 pin descriptions data sheet 27 2002-06-03 perr_n b, (6 ma) pci interface : parity error signal generic interface : address bit 4 serial : device id bit 2 1 serr_n b, (6 ma) pci interface : system error signal generic interface : address bit 5 serial : device id bit 3 1 devsel_n b, (6 ma) pci interface : device select signal generic interface : address bit 6 serial : device id bit 4 1 stop_n b, (6 ma) pci interface : bus stop signal generic interface : address bit 7 serial : device id bit 5 1 inta_n o, (6 ma) pci interface : interrupt signal generic interface : interrupt signal serial : interrupt signal 1 sda b, (10 ma, iic pad) serial data 1 scl i serial clock 1 power and ground pins vss power ground 35 vdd power core supply (1.8 v) 12 vddp power i/o supply (3.3 v) 12 table 2 pin descriptions (cont?d) symbol type/ (default internal state of the pins) function width
green plb 2224 functional description data sheet 28 2002-06-03 3 functional description the functional block diagram of plb 2224 is shown in figure 10 . figure 10 functional block diagram mac(rx) x 24 gmac(rx) x 2 mem_ arb (6 + 1) mac(tx) x 24 gmac(tx) x 2 tx_mb (txblk) gtx_mb (txblk) address resolution logic packet & queue manager init reg snmp_ctr (pkt_ctr) cpu_if /iic led_if sram_ctl miscellaneous blocks (27=>1)x6 mdio (27=>1) (27=>1)x 6 tx (txfifo) gtx (txfifo) rx_mb (rxblk) grx_mb (rxblk) rx (rxfifo) grx (rxfifo) dram_ctl (2) cmac(rx) cmac(tx) crx (rxfifo) crx_mb (rxblk) ctx (txfifo) ctx_mb (txblk) dram (12 mbit) packet buffer sram (640 kbit) address table smii gmii/tbi pci/iic smii gmii/tbi
green plb 2224 functional description data sheet 29 2002-06-03 3.1 introduction figure 10 shows the functional block diagram of plb 2224. each of the 24 serial media independent interface ports consists of a configurable mac core, which supports back pressure, mii management, programmable backoff & full duplex. each port has 256-byte rx & 224 byte tx fifos & 802.3x flow control. two 10/100/1000 interfaces consists ofa configurable gmac core. the fast ethernet interface with the mac?s are via smii ports only. the 10/100/1000 gigabit port can interface to external transceivers via the gigabit media independent interface (gmii) or ten bit interface (tbi). the gigabit interfaces include a physical coding sublayer (pcs) block, which can be used when interfacing to fiber via tbi. the pcs block can be bypassed when the gmii is used with copper transceivers. the address resolution logic & queue manager support both 802.1p & 802.1q for traffic class prioritization of multimedia or real time applications & also for increased security, simplified moves/changes & fault localization. support for port based & tag based vlan is provided. plb 2224 can support up to 1022 tag/port based vlan, making it ideal for emerging mdu/mtu market. plb 2224 supports two levels of priority per output port. this allows for time sensitive data to have access to the network with minimal latency. the packet & queue manager implements a hardware based flow control. the watermarks for the flow control can be programmed via external cpu. the onchip embedded dram is used entirely for packet buffering. the packet buffer is organized as buckets of 1536 bytes. the packet manager controls the utilization & allocation of the packet buffer in a dynamic fashion. the packet buffer is physically implemented with 2 banks of 256-bit wide dram, running at 100 mhz, giving a raw memory bandwidth of up to 16 gigabit per second. the ieee 802.1q port & vlan based tagging is done via the address resolution logic & the tx blocks. they can handle up to 1024 vlans for broadcast traffic isolation purposes (including the membership corresponding to entries of "0" & "1023"). for network management purposes rmon groups 1,2,3 & 9 are fully supported using 32-bit wide counters. additional debugging features are offered by port mirroring support. port based traffic can be copied to any designate port or cpu. ip multicast is supported via software for sending data streams to multiple nodes. the internet group management protocol (igmp) is supported to further reduce the ip multicast streams, by forwarding packets to only those nodes which are requesting them. spanning tree software is supported for eliminating redundant links as well as loops in the network. ip bootp & dhcp software is supported for automatic assignment of ip addresses in intelligent system configuration
green plb 2224 functional description data sheet 30 2002-06-03 server load balancing & failover mechanisms are supported by allowing flexible link aggregation based on mac da, sa. stack management is through iic interface. with the help of an external cpu, managed & intelligent switch configurations can be implemented with low level software drivers running over industry standard rtos. an integrated system development platform (wind river tornado for managed switches (tms)) is provided to enable network equipment vendor to explore the chip architecture & begin immediate software development.
green plb 2224 functional description data sheet 31 2002-06-03 3.2 functional block description as shown in the functional block diagram in figure 10 , the plb 2224 consists of seven major blocks. 10 / 100 / 1000 mbit/s media access control mac/gmac, receive fifo / rx. control (rx), address resolution logic (arl), packet & queue manager (pqc), tx (transmit fifo), cpu (cpu subsystem), memory block (arbitration and storage). 3.2.1 10/100/1000 mbit/s media access control (gmac/mac) the mac on each port interfaces to the external phy through the gmii/tbi in case of gigabit port & smii in case of 10/100 mbit/s ports. it receives packet data from phy & transmits them to phy based on ieee 802.3 specification. the port stays disabled until auto-negotiation & memory initialisation is done. link, speed & duplex modes are polled via the mdio interface. the mac supports full duplex & half duplex modes in 10/100 mbit/s modes & supports only full duplex mode in gigabit mode. ieee 802.3x based flow control is supported via pause frame generation & back pressure. 3.2.1.1 10/100 ethernet ports the 10/100 ports (fast ethernet) support 10 or 100 mbit/s speed, in either full or half duplex transmission mode. the ports interface to the phy devices through the smii . smii is an industry standard serial interface that operates at 125 mhz. using the mdio interface, each port is capable of carrying out auto-negotiation with the phy device for link speed and duplex mode. the speed and duplex mode of the port can also be set using the cpu. the cpu can alter the speed and duplex settings by overwriting configuration registers in the phy devices using the mdio bus. the plb 2224 provides three sync and three clock signals, allowing easy interface with octal smii phy devices. eight smii ports share a sync signal (smii_sync) and clock signal (smii_clk) and also support source synchronous smii where the interface can also take in a clock (smii_rclk). 3.2.1.2 gigabit ethernet ports there are three possible modes of operation for the two gigabit ports on the plb 2224. connecting to external gigabit phy devices the two gigabit ethernet ports connect to phy devices using either the gmii or tbi . the gmii is used with phy devices that provide the 8b/10b physical sublayer (pcs) encoding ? for example broadcom?s bcm5400 and level one?s lxt1000, while the tbi
green plb 2224 functional description data sheet 32 2002-06-03 is used with the phy devices (called serializer/deserializer or serdes devices) that do not contain the pcs functionality ? for example vitesse?s vsc7123 and hp?s hdmp1636. for each gigabit port, the corresponding configuration bit sel_gb is set to 1 to choose 1 gbit/s speed, and bit tbi / gmii bit is set to 1 for tbi and the gmii bit is set to select between gmii mode of operation or mii mode of operation. see configuration register. the gigabit ports are full duplex only for 1000mbit/s and can be used for half duplex in 10/100 mbit/s mode. connecting to external 100 mbit/s phy devices the gigabit ethernet ports can also connect to 100 mbit/s phy devices supporting the mii . for example, the two gigabit ports can be used for 100fx uplinks. for each gigabit port, the corresponding configuration bit sel1000 bit is set to 0 to choose 100 mbit/s speed with mii in the table 109 "g_mode register" on page 193 . the gigabit ports when used as 100 mbit/s ports can operate in full duplex mode or half duplex. connecting plb 2224s back-to-back the gmii on the plb 2224 can also be used to connect two plb 2224 devices on the same board, effectively acting as a high capacity trunk between them. connecting two plb 2224s back-to-back in this fashion makes it possible to design a fixed configuration or stackable 48-port 10/100 switch that is rack mountable. note that this configuration does not require gigabit phy devices . 3.2.1.3 mdio interface the mdio serial interface defined in the mii specification is used for communicating with the phy device(s). using this interface, plb 2224 can access the internal registers of the phy devices. auto-negotiation plb 2224 supports auto-negotiation on the 10/100 ports. autonegotaiation on the gports is supported when the gmii mode of operation is selected. using the mdio interface the ports can negotiate the link parameters - speed, duplex mode and pause_enable (i.e. full-duplex control) and pause_augment (for gigbit speed only). this allows the switch to neogotiate the status and capabilities of the phy device and configure itself appropriately. for smii, the link information can be obtained by reading the status information continuously coming over the smii or by accessing the phy registers using the mdio interface. see use_mdio_mode bit in ?chip configuration register? on page 141 section. for the gigabit ports, the auto-negotiation is performed using the mdio interface when the gmii or mii option is selected. using the mdio interface, the cpu can access the phy device registers and override the auto-negotiated settings if desired. e_hw_mode bit in ?switch configuration register? on page 145 must be cleared to 0 in order to disable auto-negotiation. for the mdio interface, the ethernet (phy) port addresses are mapped into mdio address space as follows:
green plb 2224 functional description data sheet 33 2002-06-03 mdio addresses #4 and #5 gigabit ethernet ports #0 and #1 mdio addresses #8 through #31 <-> 10/100 ethernet ports #0 through #23 3.2.2 receive module (rx) the rx interfaces to the gmac/mac, handles all signals in both full duplex (fd) and half duplex (hd) modes of operation. it also determines whether packet is snap encapsulated/vlan tagged. if vlan tagged, vlan id and priority is communicated to arl. the rx block also forms packet header (pbh) information. pbh is written to the edram along with the packet data. data is written to the edram in 32-byte bursts. each 1536-byte segment can be referenced using a packet numbers (pbnum), which are obtained from packet & queue manager (pqc). it discards packets less than 64 byte in length. it also consist of mib counters to support rmon ethernet statistics group. interfacing with arl/edram is implemented via synchronous handshaking. it makes decision on dropping frames with errors (crc error/fifo overrun/collision fragment etc.), pause frames and non-tagged frames when so programmed. it also supports port based mirroring. support for up to 1022 vlans /multicast groups (802.1q/ 802.1d) is provided. mac rx and port rx the mac rx block implements the media access functionality for the 10/100 ports as per the ieee 802.3 standard. it strips the preamble of the incoming ethernet packet, deserializes the data, checks for legal packet length and correct crc. any packets longer than the maximum allowed length of 1536 byte are truncated. if a crc error is found, the crc_err bit in the packet buffer header (pbh) is set. several configuration bits control the behavior of the mac rx block. these configuration options are described in the section port configuration, status and event registers. when a port is in full duplex mode with flow control enabled, the mac rx block processes the pause frames it receives and communicates the flow control status to the mac tx block. the mac rx block also requests the mac tx block to send pause frames if necessary. a pause frame received at mac rx is not forwarded to the destination address unless rx_pause_frame bit switch configuration register is set to 1. the port rx block receives packet data from the mac rx and segments it into an 8-byte chunk followed by a number of 32-byte chunks. the 8-byte chunk is stored in the sram while the remaining packet data (i.e., all the 32-byte chunks including the very last chunk, which could be 32-byte or less) is stored in the edram. in addition, the port rx blocks extracts the 6-byte sa and 6-byte da from the packet and sends them to the arl block in the switch controller. the sa is looked up for learning and update. the da is looked up for determining the destination port(s) for the packet. the port rx block creates a packet header (pbh) to record packet related information such as the packet length, crc status, source port id (src_pid) and the sdram number in which the first 32-byte chunk of packet data is stored.
green plb 2224 functional description data sheet 34 2002-06-03 the format of the pbh (packet buffer header), is described below. table 3 pbh header format table 4 packet buffer header the plb 2224 supports the spanning tree protocol. when enabled, the address learning and packet forwarding functions are determined by the bridge state for the port as described in the section spanning tree protocol support. the plb 2224 also implements flow control. depending on the configuration setup, the packet forwarding treatment is modified as described in the section flow control. the port rx blocks for 10/100 ports and gigabit ports are essentially identical. the interface to the packet buffer memory are different to account for the difference in line speed on 10/100 and gigabit ports. 3.2.3 port configuration, status and event registers several registers are used to keep information, either on a global or per port basis, about portconfiguration, priority, monitoring, status and critical events. these registers are summarized below anddescribed in detail in the section ?operational description? on page 71 32 21 20 15 10 filter_match[9:0] src_pid[ 5:0] start_m em[2:0] crc_gen crc_err pkt_len[10:0] bit fields name description 31:22 filter_match[9:0] matching results for user defined filters. 21:16 src_pid port id of the source port. 15:13 start_mem[2:0] edram number used as the starting logical edram location for packet storage. 12 crc_gen indicates that the packet is from the cpu port and mac tx needs to generate and append the crc before transmitting the packet. for packets received from non-cpu ports, this bit should be 0. 11 crc_err indicates that packet was received with a crc error. 10:0 pkt_len[11:0] packet length. maximum allowed length without truncation is 1536 byte.
green plb 2224 functional description data sheet 35 2002-06-03 ?chip configuration register? on page 141 : - global parameters such as flow control and packet dropping when tx queues are full. ?switch status and mask register? on page 152 : switch status and interrupt mask register ? global status parameters such as activation of congestion control. ?port status register? on page 154 : ? active/inactive status and detecting late collisions, crc errors and packet drops. ?port event register? on page 155 ? detecting tx queue full and other critical events such as station moves, oversize packet reception. ?port underrun/overrun register? on page 156 - detecting underrun and overrun condition for internal tx and rx fifos respectively. for internal use only. ?port mii register? on page 157 - speed, flow control, duplex and link configuration parameters. ?port monitor register? on page 158 ? monitoring status to indicate whether packets received and transmitted from this port are to be monitored. ?port priority register? on page 158 ? priority status, for implementing source port based priority. ?port trunk register? on page 159 ? trunk membership and configuration for implementing trunking support. ?port bridge state register? on page 160 - bridging status for implementation of the spanning tree protocol. ?port index register_20_0? on page 161 & ?port index register 26_21? on page 184 ? vlan index for implementation of the port-based vlan functionality.
green plb 2224 functional description data sheet 36 2002-06-03 3.3 switch controller the switch controller performs a variety of functions, including packet data buffering, address learning and resolution, managing packet buffer memory, packet queuing and scheduling for transmission. 3.3.1 packet data buffering the plb 2224 uses a combination of sram and edram for packet storage. every incoming packet requires 12 byte of sram ? 4 byte for pbh and 8 byte for the first chunk of packet data. a total of 12 kbyte of the ssram is reserved for this purpose. the plb 2224 allocates fixed, 1.5 kbyte (1,536 byte) cells for storing packet data in the edram. the plb 2224 architecture supports a maximum of k (1,024) packets. the switch controller uses a link list mechanism to keep track of where the packets are stored in the packet buffer memory. the packet link list buffer (pbll) is maintained on- chip and can store a total of 1k entries. the plb 2224 maintains read and write pointers to manage a total of 57 queues that are on chip. the queues are: 26x2 = 52 variable length, unicast traffic queues for the 26 ethernet ports, each with two priorities ? txhq and txlq. 2x2 = 4 variable length, unicast traffic queues for the two cpu transmit ports, each with two priorities. ctxhq and ctxlq one variable length queue to keep track of all free or unassigned pointers (freeq). in addition, there are 28, 256-entry broadcast tables (bcastt), one per port, to keep track of multiple destination packets (i.e., multicast, broadcast and unknown da packets that are destined for multiple ports). these pointers point to the entries in the pbll. as a packet arrives into the switch the next available free entry (i.e., packet buffer number) in the pbll gets assigned to that packet and the read pointer for the freeq is updated. for single destination packets, the write pointer of either the high or low priority tx queue of the destination port gets updated. as packets are transmitted on to the link (or possibly dropped) from the destination port queue, the corresponding read pointer for the tx queue is updated; and the packet buffer is returned back to the free packet buffer pool, and the write pointer for the freeq is updated. 3.3.2 address resolution logic (arl) the plb 2224 supports auto-learning and auto-aging as configurable options. see bit in_ma_en in ?chip configuration register? on page 141 and ma_freeze and ma_new_freeze bits in ?chip configuration register? on page 141 . the arl block performs these functions.
green plb 2224 functional description data sheet 37 2002-06-03 a mac address table (ma table) is used to manage address learning. an 8-byte entry is created and maintained for each known unicast and multicast mac address. the sram is used for storing the ma table. the plb 2224 uses hashing mechanism for fast address lookup and supports up to a total of 2k hash values. there are four entries per hash value, for total maximum of 8-k entries in the ma table. in addition, the plb 2224 uses a small, 16-entry ma table on chip to store overflow entries in an unlikely event that five or more mac addresses generate the same hash vector. this minimizes the probability of ma table thrashing (i.e., constant swapping of a valid entry with a new entry). the arl searches mac table entry based on destination address of the received packet. it determines vlan tag/priority for all untagged frames. support is provided for port based/tag based vlan and priority assignment. it implements the mac address lookup/learn/aging functions. up to 8192 mac addresses can be resolved via 2048 buckets with 4 entries each. arl supports link aggregation (802.1ad) when deciding on destination port list. it forwards queue headers for each packet to the queue manager (pqc) once packet has been successfully stored in edram. table 5 ma entry formats for unicast and multicast addresses each ma table entry is 8b. entries with the ma_state[3:0] field value between 4?b0000 and 4?b0011 (inclusive) are considered special ? locked entries, and high priority and/or critical entries. these entries cannot be aged or bumped from the ma table to make room for new entries. during chip initialization all ma table entries are set to invalid. ?ma bit fields name description unicast 63 unicast denotes whether the entry is unicast or multicast 62:57 rsv 56:52 port_id[4:0] index to vlan/floodmap for port list lookup 51:48 ma_state[3:0] denotes age; plus criticality, priority and lock attributes 47:0 ma[47:0] mac address multicast 62 multicast denotes whether the entry is unicast or multicast 58:52 flood_ix index to vlan/floodmap for port list lookup (upto 256 multicast entries) 51:48 ma_state[3:0] denotes age; plus criticality, priority and lock attributes 47:0 ma[47:0] mac address
green plb 2224 functional description data sheet 38 2002-06-03 table entry types? on page 38 , below show the different entry types based on the ma_state[3:0] value. table 6 ma table entry types 3.3.3 address learning and updating when a new, valid unicast packet is received at an ethernet port, the source mac address (sa), along with the source port number (src_pid) is pushed on to the source address learning queue (saq). the ma table is searched for the existence of an entry corresponding to the sa and one of the following actions is performed, depending on certain configuration options. if an entry corresponding to the sa is in the table and the actual source port number (src_pid) matches with the value stored in the ma table entry and the entry is not marked as a locked entry, the ma_state[3:0] field value is reset to 4?b0100. if, on the other hand the entry is marked as locked, the ma_state[3:0] field value is left unchanged. this requires the plb 2224 to be configured for auto-learning. if an entry corresponding to the sa is in the table but the actual source port number (src_pid) does not match with the value stored in the ma table entry, and the entry is not marked as a locked entry, the src_pid in the entry is updated to the new source port id and the ma_state[3:0] field value is reset to 4?b0100. if, on the other hand the entry is marked as locked, the ma_state[3:0] field value is left unchanged. this requires the plb 2224 to be configured for auto-learning. if an entry corresponding to the sa is not in the ma table or has become invalid as a result of aging, a new entry is created in the ma table corresponding to the sa and src_pid.the status field is set to 4?b0100. the new entry in the table is created in one ma_state[3:0] locked critical high priority description 0000 yes no no locked entry. cannot be aged or bumped. 0001 yes yes no locked and critical entry. cannot be aged orbumped. 0010 yes no yes locked and (high) priority entry. cannot be aged or bumped. 0011 yes yes yes locked, critical and (high) priority entry. cannot be aged or bumped. 0100-1110 no - - normal entry that can be aged or bumped. 1111 no - - invalid entry.
green plb 2224 functional description data sheet 39 2002-06-03 of the following possible ways, in the specified sequence. note that the creation of a new entry requires the plb 2224 to be configured for auto-learning matching with 1. an invalid entry in the main ma table corresponding to the hash value of the sa is replaced. 2. if entries in the main ma table corresponding to the hash value are valid, then the four entries and all the enties in the 16-entry on-chip ma table are searched and the oldest entry (i.e., entry with the highest ma_state[3:0] value in the range 4?b0100 to 4?b1111) is replaced. 3.3.3.1 plb 2224 is not configured for auto learning if the plb 2224 is not configured for auto learning and either an entry corresponding to the sa does not exist or the src_pid associated with the entry is different from the actual src_pid, this event is considered as intrusion and the appropriate programmed action - either updating the ma table entry if the bit ma_freeze_new is set to 1, or dropping the packet, or sending it to a pre-configured port list . 3.3.3.2 global updating as shown in ?chip configuration register? on page 141 , the plb 2224 also supports two global configurations options that apply to the entire ma table. the ma_freeze bit when set treats all ma table entries as being locked while ma_new_freeze bit treats all ma table entries as locked but allows sa to src_pid associations to be changed. the cpu must explicitly create all multicast entries in the ma table. see the section configuring ma table using cpu, below for details on how the ma table entries are created using the cpu. 3.3.3.3 address resolution the address resolution process involves searching the ma table for an entry corresponding to the destination address (da) of the incoming packet and extracting information regarding the associated (destination) port id (for unicast da), destination port_ix (for multicast da), priority and criticality. this information is used to create appropriate entry(s) in the transmit queue(s) of the egress ports. the address resolution process (i.e. computation of the destination port list for the da) is quite involved and depends on the type of packet (unicast or multicast or broadcast), whether the da is known or unknown, and whether the plb 2224 is configured for vlan support (source port security and/or multicast/broadcast containment). figure 11 , below shows the process in the absence of vlans, and is described below.
green plb 2224 functional description data sheet 40 2002-06-03 figure 11 destination port list creation (vlan?s disabled) known unicast da : b.3 -> b.7 : the ma table da look up directly returns destination port id (dst_pid). known multicast da : b.3 -> b.5 -> b.6 : the ma table lookup returns an index (mcast_ix) which is used to look up the vlan/floodmap table or port_list1023 register if mcast_ix = 10?b1111111111, which returns the destination port list. broadcast da : b.2 -> b.4 -> b.6: the da_index_reg lookup returns an index which (bcast_ix) is used to lookup the vlan/floodmap table or port_list1023 register if mcast_ix = 10?b1111111111, which returns the destination port list. unknown unicast da : b.1 -> b.4 -> b.6: the da_index_reg lookup returns an index (un_ucast_ix) which is used to lookup the vlan/floodmap table or port_list register if mcast_ix = 10?b1111111111, which returns the destination port list. unknown multicast da : b.1 -> b.4 -> b.6: the da_index_reg lookup returns an index (un_mcast_ix) which is used to lookup the vlan/floodmap table or port_list1023 register if mcast_ix = 10'b1111111111, which returns the destination port list. un_da bcast_da known_da ma table mcast_ix port_i d un_ucast_ix un_mcast_ix bcast_ix b. 1 b.2 da_index_reg b.4 en try #0 en try #1 en try #10 22 vlan / fl ood map table port li st_ 102 3 b.5 b.3 b.7 b.6 forwarding port(s) li st
green plb 2224 functional description data sheet 41 2002-06-03 3.3.3.4 address aging the address aging function is used for automatically aging out address entries in the ma table. periodically, all entries in the ma table are examined sequentially and the ma_state[3:0] for the entries that are not locked (i.e., entries with ma_state[3:0] > 4?b0100) value is incremented by one. as described in ?switch configuration register? on page 145 , the timer tick period for the aging function is determined by the field timer_tick_sel[2:0] . when the ma_state[3:0] equals 4?b1111, the entry is considered aged (invalid) and cannot be used for da lookup. the locked entries are unaffected by the aging process. 3.3.3.5 configuring ma table using cpu in a cpu-based system, the cpu can create entries in the ma table by sending special packets over the cpu port. the process involves two steps. in the first step, the arl register described ?arl register? on page 170 , is set as appropriate by writing to it. this is followed by sending a packet whose sa is the address that is to be learnt. the ma table entry is constructed as follows: unicast entry ? ma = sa, src_pid = ma_ports bits 4 through 0, ma_state[3:0] = 4?b0100, assumes ma_pri, ma_critical, ma_locked bits (see ?chip configuration register? on page 141 ) are set to 0. multicast entry ? ma = sa, portlist_ix = ma_ports bits 10 through 0, ma_state[3:0] = 4?b0100, assumes ma_pri, ma_critical, ma_locked bits are set to 0. special unicast entry - ma = sa, src_pid = ma_ports bits 4 through 0, ma_state[3:0] = encoded value of ma_pri, ma_critical, ma_locked bits. special multicast entry - ma = sa, portlist_ix = ma_ports bits 10 through 0, ma_state[3:0] = encoded value of ma_pri, ma_critical, ma_locked bits. the cpu can also delete (invalidate) entries in the ma table by first setting the ma_delete bits in the arl register to ?1?, followed by sending a special packet with sa that matches the mac address in the entry to be deleted. the creation or deletion of ma table entries requires that e_ma_learn bit in ?arl register? on page 170 be set to 1. the ma table is accessible for cpu reads and writes. although not advised, the cpu can also create or invalidate entries by creating ma table entries in the software, calculating the hash value for the mac address and writing to the appropriate location in the ma table. 3.3.4 port tx and mac tx the port transmit function continuously monitors the transmit queues to see if there is a packet that needs to be transmitted from that port. when a packet is available for transmission, it reads the packet data from the packet buffer ? first 8-byte of the packet data are read from the sram while the remaining
green plb 2224 functional description data sheet 42 2002-06-03 bytes from the edram. the information about packet length and starting edram number is obtained from the packet header (pbh). the packet data is assembled and forwarded to the mac tx block for the actual transmission. in full duplex mode, the mac tx block works by altering the transmission behavior based on the reception of any pause frames on mac rx. the mac tx block also sends out pause frames to activate flow control if requested by mac rx. refer to the section on flow control ( page 52 ) for more details. for packets generated by the cpu, port tx calculates the crc before forwarding the data to the mac tx. mac tx block generates the preamble, serializes the data and sends the packet to the phy device. 3.3.4.1 packet queuing and port queues the plb 2224 supports two priorities per port. the priority for the packet is determined either by the ingress port priority or the results of the ma table lookup. see the section on packet prioritization ( page 52 ) for more details. each port maintains two queues for packet transmission ? high and low priority queue. the switch controller modifies the packet buffer link list to append the packet to the appropriate queue of all the destination ports for the packet. the fixed-size, 256 entry broadcast table, (bcastt), allows each port to have a maximum of 256 multiple destination packets in the tx queue at any one time. a new multiple destination packet that is to be transmitted from the port that has reached this limit is dropped. when the priority feature is enabled, the bcastt is split in half, allowing the high and low priority queues to have a maximum of 128 multiple destination packets. the maximum number of total (i.e., unicast and multiple destination) packets in the high and low priority queues is determined by the watermarks, as described in the section on flow control ( page 52 ). 3.3.4.2 packet scheduling the plb 2224 uses weighted fair queuing (wfq) for transmitting packets that are in the port queues. setting the bandwidth_ratio[2:0] bits appropriately configures the relative weights. the txhq to txlq bandwidth ratio can vary from 1:0 (i.e., txlq can send a packet only when the txhq is empty), to 1:1 (i.e., about equal access for the two queues). refer to ?chip configuration register? on page 141 for more details. 3.3.5 packet & queue manager (pqc) the packet manager maintains free packet buffers (pb) it allocates packet buffer to rx for incoming packets. it stores service count(a packet may be forwarded to more than 1 destination ports) in case of broadcasts/multicasts. it de-allocates the packet buffer if it decides to drop the packet. packet drop decisions are based on error,control information from arl& switch configuration registers.it de-allocates packet buffer or decrement
green plb 2224 functional description data sheet 43 2002-06-03 service count after a packet is transmitted by tx. when requested it gives tx the next pbnum of a packet from its corresponding egress queue. based on append requests from arl, it establishes egress queue for each port. it generates service count of a ingress packet. it sends congestion status to all the port mac for flow/congestion control. it schedules one packet from each port?s all available queues to the corresponding port?s tx. 3.3.6 transmit module (tx) the tx block generates requests to pqc when its transmit queue is ready to receive new data. it interfaces to gmac & mac, handling all signals in both full duplex (fd) and half duplex (hd) modes of operation. collisions are handled in 10/100 mbit/s half duplex mode of operation. it is capable of inserting/deleting or modifying the vlan tag/ priority to/from all frames based on packet header information and arl indication in the queue header. it interfaces with pqc to obtain first pbnum/tagging information/packet length/source pid for new frame to be transmitted. it instructs pqc to release frames, which have been transmitted. controller subsystem (cpu): the cpu subsystem consist of a pci v2.1 compliant interface, a master-slave iic interface, a motorola/intel generic host interface (shared with pci), a generic packet filter & configuration registers.the pci port interfaces to the most popular 32-bit processors with minimal or no glue logic. the generic interface supports 32-bit cpus with either multiplexed or de-multiplexed address and data. the 32-bit cpu interface is a slave or target-only interface. in addition, a 2-wire master/ slave serial interface is provided. in the master mode, a serial enhanced expanded programmable read-only memory (eeprom) containing power-on configuration data can be connected to this interface. in the slave mode, a cpu can be connected to provide initialization and management functions. only one interface (out of 32-bit generic, 32-bit pci, 2-wire serial master and 2-wire serial slave) can be active and must be selected at reset via pinstrapping. 3.3.6.1 receiving and sending packets from the cpu port the cpu port on the plb 2224 is a logical port that can be accessed by one of the three physical cpu interfaces ? 32-bit pci, 32-bit generic or 2-wire serial. only one physical interface is allowed in the system. this section describes the operation of the logical interface, while the physical interfaces are described in the section titled cpu interface ( ?cpu interface? on page 106 ). the logical cpu port has one receive and two transmit ports. the receive port is identified as port 26, and the transmit ports are identified as ports 26 and 27. in keeping with the terminology for the user ports, the cpu sends packets to the plb 2224 ethernet
green plb 2224 functional description data sheet 44 2002-06-03 ports over the rx port while the data from the ethernet ports to the cpu is sent from the tx ports. 3.3.6.2 cpu port rx a small block called cmac rx is used to emulate the functionality of the mac rx block on the ethernet ports. this block collects data written by the cpu, computes the length of the packet and presents it to the cport rx block. typically, the packets received from the cpu are special packets and may carry with them other optionssuch as: whether the packet is to be forwarded to an ethernet port without looking up the da in the matable whether the sa is to be learnt and entry needs to be created/modified in the ma table if the sa is to be learnt, then whether the sa is to be associated with a port id other than the ingress port (i.e., the cpu port) when the ma table entry is created whether the sa needs to be associated with special attributes such as locked, critical and high priority in the ma table. the cpu sends packet data using the registers described in table 36: cmac data register and ?cmac rx register? on page 167 . the rx fifo is 16-byte deep, so the data is written 16-byte at a time. the following protocol is used: check the crx_cpu_pkt_rdy bit in the cmac rx register to see if the plb 2224 is ready to accept the packet. check the crx_cpu_fifo_rdy bit in the cmac rx register to see if the rx fifo is available set the crx_sof bit in the cmac rx register to indicate start of packet data. write 16-byte (or less in the case of last chunk) of data, 4-byte at a time, in the cmac data register using any of the four base addresses and then wait for the crx_cpu_fifo_rdy bit to set. if the cpu writes to this register at a rate of 100 mbit/s or less, then the crx_cpu_fifo_rdy bit need not be checked. before writing the very last 4-byte or less of data, set the crx_bytecnt[1:0] , crx_eof , crx_crc_err , crx_crc_gen and e_cpu_pkt_padding in the cmac rx register. write the last 4-byte or less of data. following table lists the consequence of setting crc_gen and e_cpu_pkt_padding bits
green plb 2224 functional description data sheet 45 2002-06-03 table 7 pbh packet length for different crc_gen & pkt_padding bits 3.3.6.3 cpu port tx the cpu reads the packets being transmitted to the cpu ports 26 and 27 using the registers ?cmac data register? on page 167 , ?cmac tx register? on page 169 and ?cmac_tx1 register? on page 170 . the following protocol is used: poll cmac tx0 register, bits ctx_cpu_pkt_rdy[27:26] to see if a packet available in either of the cpu tx ports. poll cmac tx0 register , bits ctx_cpu_fifo_rdy[27:26] to see if data is available in either of the tx fifos. set either the cpu_txq_rd_req[1] or cpu_txq_rd_req[0] bit to 1 in the cmac tx0 register indicating that the cpu wants to read the packet. read the packet header from the appropriate cmac tx register to retrieve information such as packet length, and crc status. read the packet data, 16-byte at a time from the cmac data register using any of the four base addresses and then wait for the ctx_cpu_fifo_rdy bit to be set to 1. if the cpu reads from this register at a rate of 100 mbit/s or less, then the ctx_cpu_fifo_rdy bit need not be checked. cpu can flush the cmac data register for the tx port it is currently reading by setting the ctx_flush bit in the cmac tx0 register. 3.3.7 mdio interface the mdio serial interface is used for communicating with the phy device(s). using this interface, plb 2224 can access the internal registers of the phy devices. 3.3.7.1 auto-negotiation plb 2224 supports auto-negotiation on the 10/100 mbit/s ports. auto-negotiation on the gigabit ports is supported when the gmii is selected. using the mdio interface plb 2224 can negotiate the link parameters ? speed, duplex mode and pause_enable (i.e., full-duplex flow control), and pause_augment (for gigabit speed only) by understanding the status and capabilities of the phy device and configure itself appropriately. crc_gen 0 1 0 1 e_cpu_pkt_padding 0 0 1 1 pbh pkt_len actual packet length actual packet lenght + 4 packet length = 64 & crc_gen set to ?1? internally packet length =64
green plb 2224 functional description data sheet 46 2002-06-03 for smii, the link information can be obtained by reading the status information continuously coming over the smii or by accessing the phy registers using the mdio interface. see use_mdio_mode bit in ?chip configuration register? on page 141 . for the gigabit ports, the auto-negotiation is performed using the mdio interface when the gmii or mii option is selected. using the mdio interface, the cpu can access the phy device registers and override the auto-negotiated settings if desired. e_hw_mode bit in ?switch configuration register? on page 145 must be cleared to 0 in order to disable auto-negotiation. with e_hw_mode = ?0?, plb 2224 will be in software mode of operation and for speed/ duplex mode/pause_enable settings the ?port mii register? on page 157 comes into picture. through this plb 2224 can read the phy registers and set the corresponding parameters speed/duplex mode/pause_enable accordingly. 3.3.8 led interface a flexible led interface is supported. the interface can be either used in the matrix format or serial format. four leds per port can be used to display link, speed, duplex, activity status and warning conditions.
green plb 2224 functional description data sheet 47 2002-06-03 figure 12 matrix mode led connection for each port on plb 2224, there are four led's. led has two display modes. in mode 1, led0 indicates speed of either 10/100 mbit/s, led1 indicates port link status and activities, led2 indicates full/half duplex, and led3 displays the status warning/error. table 8 summarises status of leds in various modes. led logic row_0_ 1 col_25 0 col_.. 0 1 3 2 3 col_5 0 1 2 col_4 0 1 3 2 col_3 0 1 3 2 1 col_2 0 3 col_1 0 1 3 2 col_0 0 1 3 2 port #0 row_1_ row_2_ row_3_ column<27:0> 0 1 3 2 col_26 port #1 ... port #3 port #2 ... port #25 port #5 ... port #26 port #4 ... 2 2 2 3
green plb 2224 functional description data sheet 48 2002-06-03 to display status/activity of 26 ethernet ports plus cpu's port per chip, each chip will need to drive 108 leds. it is ensured by design that, there is only one row active at a given time, i.e. logic 0. each row alternately has 5 ms of active time. led assignment is defined such that port 0 is assigned to column 0, port 1 to column 1, and port 26 is to column 26. each column has four led's from row 0 to 3. led's for port 26 can only be controlled by cpu. leds for port 0 to 25 directly refelct the status of ethernet ports if soft_led is 0, and they are written by cpu if soft_led is 1. if soft_led is 1, led_d[3:0] is matched to port#0, led_d[7:4] is to port 1, and led_d[103:100] is to port 25. cpu led, i.e. led_d[107:104], are always for port 26. at reset, all the led?s are turned on for 0.5 s and then turned off. the status led lights up whenever there is a change in the following a packet received with crc error table 8 matrix led modes (per port) mode led # led activity description mode 0 led #0 on/off 10 mbit/s link ok/not ok flashing 10 mbit/s recieving/transmitting led #1 on/off 100 mbit/s link ok/not ok flashing 100 mbit/s receiving/ transmitting led #2 off half duplex on full duplex & link ok led #3 off normal on port disabled flashing error (crc error | pkt overflow | packet drop mode 1 led #0 on 100 mbit/s & link ok off 10 mbit/s led #1 on/off link without activity/link down falshing port receiving/transmitting led #2 off half duplex on full duplex & link ok led #3 off normal on port disabled flashing same as mode 0
green plb 2224 functional description data sheet 49 2002-06-03 oversize packet a dropped packet ma change collision ( in conjunction with mask_coll_led bit in switch configuration register) late collision serial mode led the above information is serialy shifted out, when the led interface is configured in serial mode led_row_n[0] : led_sync led_row_n[1] : led_load led_row_n[2] : led_data led_row_n[3] : led_clk 3.3.9 reset and initialisation setting reset_n low (for a minimum of 3 clocks or 30 ns) activates the reset and initialization block. when in the reset state, all the internal logic is reset and all configuration registers are set to their default values. when the reset_n line goes from low to high, the logic levels on the strapping pins are registered and stored in the appropriate configuration registers and the plb 2224 enters a secondary reset state. during this state, the plb 2224 initializes the data structures such as ma table, reset sequence for the edram and packet buffer link list (pbll). if the plb 2224 is configured as a non-cpu system, some of the configuration registers are read from the eprom. data integrity check on the eprom data is carried out. if it fails, the status led (i.e., led #3) for port #7 continues to blink indicating an eprom read error. tthe port logic is disabled until the plb 2224 successfully completes power on sequence, is configured correctly and determines that the 10/100 and gigabit links are ok. 3.3.9.1 power strapping the led interface pins led_row_n[3:0] and led_col[26:0] are also used as power strapping pins to set certain operating parameters for the plb 2224. on the rising edge of the reset_n pulse, the logic level of led_row_n[3:0] and led_col[23:0] are sensed and latched into the chip configuration register as shown in ?chip configuration register? on page 141 . all the led signals have internal pullups. the power strapping pins can be pulled-up through ~10 k resistor or pulled-down through a ~1 k ohm resistor to set the required value.
green plb 2224 functional description data sheet 50 2002-06-03 the following table shows the power strapping information table 9 power strapping table 3.3.9.2 delay select for smii_rclk the signals delay_sel in the above table are used to control the delay the smii_rclk internally. this is mainly used in applications where source synchronous smii is not used. the details of the delay selection is shown in the figure below for non-source synchronous application, smii_clk is connected back to smii_rclk ( like smii_clk_7_0 is connected to smii_rclk_7_0) signal power starp pin register bit intelligent led_row_n[3] chip configuration register bit 31 eeprom present led_row_n[2] disable_pause led_row_n[1] chip configuration register bit 28 gmii/serdes_25 led_row_n[0] gport1 gmode register bit 0 gmii/mii_25 led_col[25] gport1 gmode register bit 5 gmii/serdes_24 led_col[26] gport0 gmode register bit 0 gmii/mii_24 led_col[24] gport0 gmode register bit 5 delay_sel5[1:0] led_col[23:22] chip configuration register bits 23/22 delay_sel4[1:0] led_col[21:20] chip configuration register bits 21/20 delay_sel3[1:0] led_col[19:18] chip configuration register bits 19/18 delay_sel2[1:0] led_col[17:16] chip configuration register bits 17/16 delay_sel1[1:0] led_col[15:14] chip configuration register bits 15/14 delay_sel0[1:0] led_col[13:12] chip configuration register bits 13/12 sim_mode[1:0] led_col[11:10] chip configuration register bits 11/10 in_ma_en led_col[9] chip configuration register bit 9 use_mdio_mode led_col[8] chip configuration register bit 8 led parallel-serial mode led_col[7] e_hd_cg_ctl led_col[6] chip configuration register bit 6 mask_coll_led led_col[5] chip configuration register bit 5 en_tx_led led_col[4] chip configuration register bit 4 led_mode led_col[3] chip configuration register bit 3 pcb_config led_col[2:0] chip configuration register bit 2:0
green plb 2224 functional description data sheet 51 2002-06-03 figure 13 delay control for smii clock internally 0.8 ns 1.6 ns 2.4 ns smii_r clk d elay_ sel[1 :0 ] 0 1 2 3 inte rn al sm ii_clk 4 to 1 m u lt ip le x e r (pin strap values from led_c ol pin) (inp u t a t th e pin)
green plb 2224 functional description data sheet 52 2002-06-03 3.4 features for a managed switch 3.4.1 flow control the plb 2224 supports flow control in both half and full duplex modes. flow control in the half duplex mode is implemented by creating collisions on the link. the flow control in full duplex mode uses pause frames as per the 802.3x specification. 3.4.2 spanning tree protocol support the plb 2224 supports the spanning tree protocol as per the 802.1d specification. as specified in ?port bridge state register? on page 160 , each port has two configuration bits that define the bridging state for that port. for the ehthernet (i.e., non-cpu) ports, the following actions are performed, depending on the state of the port. upon reset, each port is in the default forwarding state (2?b11). depending on the state, the non- transmitted packets are automatically purged from the tx queue. table 10 spanning tree states and actions 3.4.3 packet monitoring packets can be monitored based on the ingress port or egress port, if the monitor bit as described in ?port monitor register? on page 158 is set to 1. the id of the monitoring port (i.e., port to which all the monitored packets are sent) is specified in ?switch configuration register? on page 145 . the plb 2224 can also be configured to monitor a) packets with crc errors and b) packets whose source port number does not match with the port id value the ma table entry corresponding to the packet sa. setting the appropriate configuration bits in ?switch configuration register? on page 145 activates packet monitoring. 3.4.4 packet prioritization the plb 2224 architecture supports two priorities ? high and low per port. the priority can be based on the ingress port and/or da. two configuration bits, pri_at_src and pri_at_da , specified in ?switch configuration register? on page 145 are used to determine how packet priority is set. when pri_at_src is set, the configuration register in port state[1:0] receive packets learn sa lookup da transmit packets 00 - diabled no no no no 01 - listening yes no yes only those with the critical packets 10 - learning yes yes yes only those with the critical packets 11 - forwarding yes yes yes all packets
green plb 2224 functional description data sheet 53 2002-06-03 ?port priority register? on page 158 is looked up to set the priority. when pri_at_da bit is set, the ma table is used to set the priority. when both pri_at_src and pri_at_da bits are set, the priority is set to high if either lookup results in high priority (i.e., the result is an or function). the following rules are used in determining da based priority: for broadcast packets, priority is always set to low, for unknown packets, priority is always set to low, when ma table entry corresponding to the da is not a locked entry, the priority is always set to low. 3.5 registers in plb 2224 following table describes the chip registers & their address map table 11 register table byte offset register name access mode description 0x00 chip_config r/w chip configuration register 0x04 chip_type r revision no. & id 0x08 switch_config r/w switchi engine & vlan configuration 0x0c switch_status r address table & interrupt status 0x10-0x1c port_status r depicts status of each port 0x20-0x24 port_event r error & queue status for each port 0x28-0x2c port_run r/w depicts overrun/underrun status of each port 0x30-0x3c port_mii r/w port enable/disable & configuration register 0x40 port_monitor r/w port monitoring control register 0x44 port_priority r/w port based priority allocation register 0x48-0x4c port_trunk r/w port trunking/aggregation grouping register 0x50-0x54 port_bridge_state r/w depicts bidge state (stp) 0x58 portlist_1023 r/w floodmap bypass register 0x60-0x78 port_vid_ix20-0 r/w port index definition register
green plb 2224 functional description data sheet 54 2002-06-03 0x7c da_index r/w index setting for unknown unicast, flood & broadcast 0x80 mem_u_addr r/w upper memory base address 0x84 mem_access r/w indirect memory access register 0x90-0x9c cmac_data r/w data to/from cpu port 0xa0 cmac_rx r/w cpu rx control register 0xa4 ? 0xa8 cmac_tx0/1 r/w cpu tx control register 0xac arl r/w address lookup control register for cpu ports 0xb0 freeq_ptr r read/write pointer of the free queue (only for diagnostic) 0xb4 freeq_cnt r current available packet buffer count in free queue 0xb8-bc cpu_txq26/27 r current tx queue count 0xc0-d0 water_mark_count w water mark register for tx/rx 0xd4 tag_pri r/w tag priority mapping control 0xd8 e_pri r/w egress priority demapping control 0xdc tag r/w tag set control 0xe0 vlan_aware r/w set ingress rule for each port and overall switch vlan awareness 0xec vlan_ingress filtering r/w enable ingress filtering 0xe4 port_index23-21 r/w the index number is defined for each of the ports. the number based on source port will be used to lookup floodmap for the destination port list when a non- unicast packet is received 0xe8 port_index26-24 r/w same as above 0xf0-fc led_data w 32-bits of led display data if cpu has the control of led
green plb 2224 functional description data sheet 55 2002-06-03 0x100-0x11c pattern_mask r/w the register with address offset of 0x100 is for pattern #0, the next one with address offset of 0x104 is for pattern #1, ?and the last one with address offset of 0x11c is for pattern #7. there are eight patterns totally in this chip 0x120-0x124 offset03/47 r/w offset for each half word 0x128-0x12c op_table0/1 r/w opcode table 0x130-0x16c action_table0-15 r/w pattern match action table 0x170 e_filter r/w filter enable control 0x1c0 or 0x1e0 g_rxtx r/w gport control register 0x1cc or 0x1ec g_mode r/w gport mode select 0x1d0-8 or 0x1f0-8 g_pcs0-2 r/w gport autonegotiation & link status control
green plb 2224 data structure data sheet 56 2002-06-03 4 data structure there are three data areas in plb 2224. the first one is edram for packet data only. the second one is ssram for pbh (packet buffer header), the first 8-bytes of packet data, ma table. the third one includes all the fifo's, pbl (pb link list), bcastq (broadcast queue), floodmap (flooded port list) and pkt_ctr. the detailed format of each entry is also described in this section. cpu can only access all the memories indirectly through mem_access register. table 12 edram details table 13 sram details quantity entry unit size (bits) no. of packets total size (bytes) comments 2 banks 256 1 k 1.5 mb 6 mb in each memory bank type entry unit size (bits) no. of entries total size (kbytes) mac address 8 4 x 2 k 64 packet data 8 1 k 8 packet buffer header 4 1 k 4 total 76
green plb 2224 data structure data sheet 57 2002-06-03 4.1 internal memory all memory blocks are separated table 14 internal memories 4.1.1 vlan memories floodmap memory stores the destination port list for each ma?s or vlan membership. for a non-single destination packet the flood_ix[] index from da lookup result will be used to reference floodmap for a destination port list. lower 28-bits of the floodmap stands for the respective port for the destination. in case of a vlan aware switch, floodmap table indicates the ports belonging to a particular vlan. in this case the input description entry unit size (byte) entry # total size (byte) comment rx fifo 192 byte 28 ports 6 kbyte separate ( built using registers ) tx fifo 384 byte 28 ports 12 kbyte dual port memory used here pbl 2 byte 1 kbyte 2 kbyte sram bcastq 2 byte 256 x 32 16 kbyte sram floodmap 4 byte 1024 4096 byte destination port list for each entry. this can be vlan_port_list in case of a vlan aware switch or dst_port list in the case of non-vlan aware switch. table 15 vlan memories description entry size entry # total size comment vlan table 40 1k 40 kbits inputs vid_ix[9:0] outputs {vid[11:0], port_egress_tagged[27:0]} vid_ix table 10 4k 40 kbits inputs: { vid[11:0] } outputs : { vid_ix[9:0] } vlan id index will be referenced to one entry within the vlan table. multiple vlan?s i.e. multiple vid[], may be assigned to one vid_ix[]
green plb 2224 data structure data sheet 58 2002-06-03 lookup is vid_ix. this is used to filter non-member ports at receiving and transmitting side. where vid[11:0] = indicates the global vlan id for the entry. vid[11:0] is the vlan id to the tagged packets. when receiving, each packet will be referenced to one of the vlan table to get the vid_ix[]. port_egress_tagged = list of ports to determine whether the transmitted packet to each destination port should be tagged. for those ports with corresponding bits equal to ?1?, the packet needs to be tagged. 4.1.2 pbl (packet buffer link list) ? 1 k x 2 bytes pbl is to store all the pb?s link list. there are 26 links (txq) for each of 26 forwarding ports and two links for two cpu ports, and there is one free link for all the pb?s which are yet to receive packet data. note: all the entries are assigned to the free link after reset. each ethernet port may occupy two queues instead of one if high priority is enabled. 4.1.3 bcastq (broadcast queue) ? 256 x 2 bytes x 32 = 16 kbytes each port has an independent 256 entries of queue from bcastq to store all the nxt_pbnum[] when the packet is not a single_dst. the nxt_pbnum[] indicates the next pb number to be forwarded right after the current pb number?s transmission. sram all the packet data are stored in edram (packet buffer). for each packet, the first 8-byte data and packet buffer header (pbh) are stored in ssram, the rest of packet data are in eram. the maximum of packet data size is (1536) bytes. pbh stores the packet information such as pkt_len[10:0], crc_err, crc_gen, src_pid[] and filter_match[]. 4.1.4 ma (mac address) - 64 kbyte for up to 8 k addresses there are 8 k different hash values. each of them indexes to 2 entries of ma. entry format for pbl, pbh, ma table, etc. packet buffer link list ( pbl ) table 16 pbl format single_dst = 0 monitor nxt_pbnum[12:0] single_dst = 1 rsv ser_cnt[4:0]
green plb 2224 data structure data sheet 59 2002-06-03 where single_dst = the pb is for single destination if this bit is set, otherwise, it is for multiple destination ports. nxt_pbnum[] = if current pb is not ?flood? and is appended to one of the txq, nxt_pbnum[] indicates the next pb number to be forwarded right after this pb?s transmission. if the current pb belongs to freeq instead of any txq, nxt_pbnum[] points to the next freeq entry. after chip reset, all nxt_pbnum[] entries should be linked. ser_cnt[] = if ?single_dst? is not set, ser_cnt[] indicates how many more ports still need to transmit this packet, and it is initialized when txq is appended and should be in sync with the number of ports to be forwarded. ser_cnt[] decrements for each port?s forwarding until it is zero. this field is valid only when the current pb is for non-single_dst packet. monitor = pb needs to be forwarded to the monitoring port. when ?monitor? is set, pb cannot be released until both monitor equal to 0 and ser_cnt[] equal to 0. broadcast queue (bcastq) table 17 broadcast queue entry format where nxt_pbnum[] = indicates the next pb number to be forwarded right after this pb?s transmission. note: snooping may be needed if the entry is read before nxt_pbnum[] is written for the following packet. packet buffer header (pbh) where filter_match[] = the matching results for all the filtering patterns. rsv nxt_pbnum[12:0] table 18 packet buffer header 31:22 21:16 filter_match[9:0] src_pid[5:0] 15:13 12 11 10:0 start_mem[2:0] crc_gen crc_err pkt_len[10:0]
green plb 2224 data structure data sheet 60 2002-06-03 start_mem[] = indicating which edram bank stores the first burst data of the packet. each packet is divided onto 32 b data cell, and the cell is stored onto, in turn, one of edram?s until eof. ?start_mem[]? indicates which memory is the first edram to store the first data cell. src_pid[] = indicating which port has received this packet from. this information is used to record the number of pb each port has used. the most significant bit of this field is the parity bit for this field. the sum of one?s in this field should be odd number. if parity error is detected, it will set the status bit src_pid_parity_err. src_pid[] is also encoded for crc_gen bit if source port is from cpu, i.e. either from #26 or #27. for most received packets from cpu, crc_gen is asserted. cpu?s src_pid[] can be changed to #28 or #29 to indicate crc_gen not asserted. crc_err = indicating the packet data with crc error. pkt_len[] = packet data length. due to the pb size, it can only go up to 1536. if the received packet data size is more than 1536, mac will hold the fifo write to 1536 and set ?crc_err? for the packet. crc_gen = indicating the packet is from cpu and mac requires to transmit crc bytes after the packet data. for normal packets being received from ports, it should be 0. this bit should be passed to mac to append crc bytes. note: this bit is encoded within the src_pid[]. ma entries (ma) there are 8 k entries of which index, i.e. ma_entry_ix[12:0], is the hashed value of {ma[47:0]]}. table 19 ma format for unicast entry table 20 ma format for multicast entry where unicast/multicast = the ma is for single destination if this bit is 0, otherwise, it is for multiple destination ports. this bit is always 0 for learned sa from any of ethernet ports. it can be 0 or 1 if the entry is set by cpu. bit 63 bits 62:57 bits 56:52 bits 51:48 bits 47:0 unicast reserved port_id ma_state ma bit 63 bits 61:52 bits 51:48 bits 51:48 bits 47:0 multicast flood_ix[9:0] ma_state ma_state ma
green plb 2224 data structure data sheet 61 2002-06-03 ma_state[] = aging state. after initialization, all the ma_state[] fields should be ?f?. when any sa is learned, it is cleared to ?4?. field ma_state[] of each entry will increment once every 28.5 seconds until it becomes ?f?. if it is ?0-3?, ma is locked not to be aged and the associated port_id[] should not be changed. if ?1? or ?3?, ma is locked with ?critical? attribute. if ?0? or ?2?, ma is locked without ?critical?. note: ma such as bpdu should be ?critical?. port_id[] = the ma associated port number if single_dst. flood_ix[] = the index number for a list of destination ports from floodmap if ma is a ?flood? entry. if flood_ix[] is equal to 1023, the port list is from portlist_1023 register without checking floodmap data base. note: floodmap is merged into vlan attribute table which is also used for vlan attributes. both will share the vlan attribute table. ma[] = 48-bits of mac address. the hashed value is created based on these 48 bits.
green plb 2224 data structure data sheet 62 2002-06-03 4.2 indirect access to the memories a brief description on how to access the different memories in plb 2224 is given below. two registers (memory upper address register and memory access register) are defined for the purpose of cpu indirect access of internal memories. these two registers are defined below: memory upper address register name : mem_u_addr offset :0x80 access : read/write description this register is used to store the upper address of the memory. it should be combined with the lower bits in mem_access register to have the complete address offset. the final memory address for each access is concatenated from mem_addr[20:11] from mem_u_addr register and mem_addr[10:1] from mem_access register. table 21 memory upper address register bits field name block (access) initial value description 31:25 rsv 0 reserved 24:21 blk_sel_msb [3:0] mem (r/w) x the value of this filed indicates which memory will be accessed for cpu to read or write mem_access register. the definition of memory access is described below: 0 - 1: edram block #0 to #1 , 2 - 7: reserved . 8: mib counters . 9: arl . 10: pqc . 11:15: reserved . 20:11 mem_addr [20:11] mem_if (r/w) x upper address of memory access. the definition of each access is described in blk_sel_msb[] field above. 10:0 rsv 0 reserved
green plb 2224 data structure data sheet 63 2002-06-03 memory access register name : mem_access offset :0x84 access : read/write description after cpu writes this register, a memory access state machine, either read or write process, will be activated. this register is designed for all the device access including all the internal memories, and external mii?s phy register. each access can only be 16 bits. for 32-bits memory data, it is in little endian format. so, the first two bytes are from bit[15:0] and the second two bytes of data with mem_addr[1] equal to 1 are from bit[31:16]. table 22 memory access register bits field name access initial value description 31 access_rdy (r/w) 0 when this bit is set on a read operation, it indicates that the mem_data[15:0] field is valid. for a write operation this bit gets set when the write operation is complete. this bit should always be written to 0 by cpu, and it is set when the read operation is complete or the data is written to the destination. access_rdy is asserted when the command read or write is completed.. 30 wr (r/w) 0 this bit is set for memory write command. 29 rd (r/w) 0 this bit is set for memory read command. 28:27 mem_sel (r/w) 00 00 to select mii?s phy. 01 ? reserved. 10 ? reserved. 11 for memory access. upper address bits are needed. refer to mem_u_addr register for them. 26 reserved 0 reserved
green plb 2224 data structure data sheet 64 2002-06-03 4.2.1 access to edram this access is for diagnostic purpose only . 256 bit (16 x16 bits) should be read or write per indirect access. unused address bits should be set to 0. for a write, the sequence is as follows: write memory upper address register first. write 16 times memory access register with ?wr? bit set. the address for the first write must be at 256-bit boundary. then every write, address should be incremented by 1 word (2 bytes). then read memory access register to check ?access_bit? bit until ?access_bit? is ?1?. next indirect access can be issued. 25:16 mem_addr [10:1] (r/w) x memory access lower address bits. for each memory write access, it is always 2 bytes that will be temporarily stored in a part of 16-byte register with the offset given by mem_addr[3:1]. the real memory operation won?t start until mem_addr[3:1] stands for the last access, i.e. equal to ?e?. access_rdy won?t be set until receiving memory write ack. for each 16-bytes of memory write, there are eight writes to this register, with bit [3:1] equal to 0 for the very first write. after receiving the eighth write with mem_addr[3:0] equal to ?e?, the memory operation starts. for a 16-bytes of read, plb 2224 issues a command to request for 16-bytes of data from memory after receiving a read command with mem_addr[3:1] equal to 0. cpu then polls this register until access_rdy is asserted, after which mem_data[] is valid. after detecting access_rdy, cpu reads the first two bytes. it continues to issue the write of read command with mem_addr[3:1] issued as a continuous offset, and then polls for mem_data[]. at the second and subsquent polling, access_rdy should be always ready, because all the 16-bytes of data are acquired at the first command with mem_addr[3:1] equal to 0. 15:0 mem_data [15:0] (r/w) x write data for write command, and read data for read command.
green plb 2224 data structure data sheet 65 2002-06-03 for read, the sequence is write memory upper address register first. write memory access register with ?rd? bit set. the address for the write must be at 256-bit boundary. then read memory access register to check ?access_bit? bit until ?access_bit? is ?1?. store the first 16-bytes. then read another 16 times access register with ?rd? bit set. then every read address should be incremented by 1 word (2-bytes). next indirect access can be issued. 4.2.2 access to mib counters 32 bit (2 times 16 bits) should be read or written per indirect access. unused address bits should be set to 0. there are two parts in this area: mib counters for non vlan aware switch and vlan mib for vlan aware switch. the selection is controlled by mem_addr[14]. mem_addr[14]: 0: mib 1: vlan mib for normal mib counter each counter has a unique address defined in mem_addr[12:2]. mem_addr[12:2] consists of {cnt_sel,?0?, port_id[4:0], item_num[3:0]}. cnt_sel = 1 for receiving counter, and 0 for transmitting counter. port_id[] is the logical port number for each ethernet port or cpu port. and item_num[] is defined below under the headingnetwork management. for vlan mib each vlan has a 3 mib counters which are used to represent the number of unicast packets received, number of multicast packets received and the number of packets dropped. incase of tx vlan mibs this represents the number of packets transmitted for each category. each counter has a unique address defined in mem_addr[13:2]. mem_addr[13:2] consists of {cnt_sel, vlan_id[9:0]} . cnt_sel = 00 for ucast packet counter 01 for mcast packet counter 10 for number of packets that are dropped for a write, the sequence is as follows write memory upper address register first.
green plb 2224 data structure data sheet 66 2002-06-03 write 2 times memory access register with ?wr? bit set. the address for the first write must be at 32-bit boundary. then every write, address should be incremented by 1 word (2 bytes). then read memory access register to check ?access_bit? bit until ?access_bit? is ?1?. next indirect acccess can be issued. for read, the sequence is write memory upper address register first. write memory access register with ?rd? bit set. the address for the write must be at 32-bit boundary. then read memory access register to check ?access_bit? bit until ?access_bit? is ?1?. store the first 16 bytes then read another access register with ?rd? bit set. then every read address should be incremented by 1 word (2 bytes). next indirect acccess can be issued. access to arl memory area 128 bit (8 times 16 bits) should be read or write per indirect access. unused address bits should be set to 0. there are four different memories that can be accessed in this area. mem_addr[19:18] is used to select one of the memory 00: to select ssram 20 k x 32 01: to select internal small arl cache the above two areas are for diagnostic purpose only. 10: to select vlan ix table 4 k x 10 11:to select vlan table 1 k x 40 for write, the sequence is as follows write memory upper address register first. write 8 times, the memory access register with ?wr? bit set. the address for the first write must be at 128 boundary. then every write, address should be incremented by 1 word (2 bytes). then read memory access register to check ?access_bit? bit until ?access_bit? is ?1?. next indirect acccess can be issued. for read, the sequence is as follows write memory upper address register first. write memory access register with ?rd? bit set. the address for the write must be at 128 boundary.
green plb 2224 data structure data sheet 67 2002-06-03 then read memory access register to check ?access_bit? bit until ?access_bit? is ?1?. store the first 16 bytes then read another 7 times access register with ?rd? bit set. then every read address should be incremented by 1 word (2 bytes). next indirect acccess can be issued. since internal bus size is 32 bit. when accessing the vlan ix table. lower 10-bits per even number of reads or writes is valid. during odd number of reads or writes, the lower 10-bits are invalid. for vlan table which is 40-bit wide, every even number of read or write is valid andonly lower 8-bits in the case off odd number of read or write is valid. access to pqc memory area 32 bits (16-bits read twice) should be read or written per indirect access. unused address bits should be set to 0. there are seven parts in this area: pbl, floodmap, bcastq0 to bcastq3 mem_addr[17:15] is used to select one of the memory inside pqc. 000: to select pbl memory 001: to select internal floodmap 010 ? 011: reserved 100 ? 111: to select bcastq0 to bcastq3 respectively these areas except floodmap are for diagnostic purpose only. the read and write sequnce is same as access to mib. the internal bus is also 32-bit wide. when access pbl. lower 12-bit per even number of rd or write is valid. odd number read or wrote is invalid. when access floodmap. even number and lower 12-bit of odd number of rd or write is valid. when accessing bcast. lower 10 bit per even number of rd or write is valid. odd number read or wrote is invalid.
green plb 2224 data structure data sheet 68 2002-06-03 4.2.2.1 vlan memories table 23 vlan memories description entry size entry # total size comment floodmap 4 b 1024 4096 b destination port list for each entry. this can be vlan_port_list in case of a vlan aware switch and dst_port list in the case of non-vlan aware switch. vlan table 40 1 k 40 kbits inputs vid_ix[9:0] outputs {vid[11:0], port_egress_tagged[27:0]} vid_ix table 10 4 k 40 kbits inputs: { vid[11:0] } outputs : { vid_ix[9:0] } vlan id index will be referenced to one entry within the vlan table. multiple vlan?s i.e. multiple vid[], may be assigned to one vid_ix[]
green plb 2224 data structure data sheet 69 2002-06-03 4.3 network management there are statistic counters for each port in plb 2224. each counter is 32-bit wide. the on-chip sram to store the counter is also 32-bit wide. and it is reset to zero at each chip reset. the counters being supported in plb 2224 are shown below. the offset of each counter is equal to (4 bytes x item_number). the base address of this register is defined in memory upper address register in the register list. receiving counters 0. receive good packet 1. receive good octet 2. receive good broadcast packet 3. receive good multicast packet 4. receive crcerr packet with 64 bytes or more, including alignment error. 5. receive fragment (less than 512 bits) with good or bad crc. 6. receive oversized packet with good or bad crc (1519 to 1536 bytes). 7. receive jumbo packet greater than 1536 bytes. 8. receive dropped packet due to lack of resource. 9. receive packet with 64-bytes with good or bad crc. 10.receive packet with 65 to 127-bytes with good or bad crc. 11.receive packet with 128 to 255-bytes with good or bad crc. 12.receive packet with 256 to 511-bytes with good or bad crc. 13.receive packet with 512 to 1023-bytes with good or bad crc. 14.receive packet with 1024 to 1536-bytes with good or bad crc. 15.receive good pause packet for the vlan aware switch there are 3 mib counters per vlan, which indicate the number of unicast packets recevied, number of multicast packets received and the number of packets dropped transmitting counters 0. transmit packet 1. transmit octet 2. transmit broadcast packet 3. transmit multicast packet 4. transmit oversized packet (1519 to 1536 bytes) 5. tranmit packet with 64 bytes 6. tranmit packet with 65 to 127 bytes 7. transmit packet with 128 to 255 bytes 8. transmit packet with 256 to 511 bytes 9. transmit packet with 512 to 1023 bytes 10.transmit packet with 1024 to 1536 bytes
green plb 2224 data structure data sheet 70 2002-06-03 11.late collision. 12.collision 13.transmit pause packet 14.filter matched packet counter 15.bridge filter counter: packet received and being filtered without forwarding to any port for vlan aware switch there are 3 transmit mib counters per vlan, which indicate the number of unicast packets received, number of multicast packets received and number of packets dropped.
green plb 2224 operational description data sheet 71 2002-06-03 5 operational description the plb 2224 is a network-on-a-chip switch device. all the functions such as address learning, packet filtering, aging, and port monitoring are done by the plb 2224 chip itself. the cpu in the plb 2224 switch performs the following operation, administration, and maintenance (oam) functions: 1. configure plb 2224 chip and plb 2224 switch through the console, 2. access and manage mac address tables, 3. access mib and rmon registers, 4. provide an snmp interface for nms, 5. provide a console through rs232 or telnet sessions, 6. provide tftp for software download and upgrade, 7. process 802.1d spanning tree protocol bpdus, 8. process other packets delivered to the cpu port.data flowdata flow
green plb 2224 operational description data sheet 72 2002-06-03 5.1 data flow a mac bridge relays individual mac user data frames between the separate mac entities of the bridged lans connected to its ports. the order of frames is preserved. before leaving plb 2224, frames coming into plb 2224 will typical go through: 1. frame reception 2. ingress filtering 3. frame forwarding 4. egress filtering 5. frame transmission a terminating frame will be forwarded to one of the cpu ports at the frame forwarding phase. a frame originated from the plb 2224 will go through all the phases through an emulated mac port (cmac). 5.1.1 frame reception frame reception performs the following functions: 1. discard on receiving a frame in error, 2. discard a frame if the non user_data_frame and request_with_no_response mac_action parameters are met, 3. regenerate user priority, if required. 5.1.2 ingress filtering ingress filtering performs the following functions: 1. screen vlan-tagged frames if necessary, 2. filter frames based on ingress filtering rules. 5.1.3 frame forwarding frame forwarding performs the following functions: 1. enforcing (bridge) topology restrictions and legal frame sizes, 2. filtering frames based on the destination mac address and vlan id in the filtering database, 3. default group filtering for the transmission port, 4. queuing the frame based on traffic class, 5. scheduling frames for transmission based on certain criteria, 6. mapping priorities between user priority and outbound access priority, 7. regenerating fcs in the case of frame payload change. 5.1.4 egress filtering egress filtering filters out frames destined to members of a different vlan.
green plb 2224 operational description data sheet 73 2002-06-03 5.1.5 frame transmission frame transmission transmits frames. 5.1.6 terminating or originating frames a frame typically does not go to the cpu, unless one of the followings happened: 1. receiving bpdus or gvrp pdus (in case of 802.1q), 2. for address learning, 3. for other monitoring purpose. in the case of a frame being forwarded to the cpu, different process will pick up and process the frame. 5.1.7 cpu transmission the cpu will originate frames for the following reasons: 1. generating bpdus or gvrp pdus (in case of 802.1q). 2. programming the mac address table. the packet will follow the same data path as a regular frame through an emulated mac port (cmac).
green plb 2224 operational description data sheet 74 2002-06-03 5.2 flow control the plb 2224 supports flow control in both half and full duplex modes. flow control in the half duplex mode is implemented by creating collisions on the link. the flow control in full duplex mode uses pause frames as per the 802.3x specification. each port maintains three counters. the rx_cnt keeps track of the total received packets on a port that are in the switch (i.e., have still to be transmitted from at least one port). the txhq_cnt and txlq_cnt maintain the count of the number of packets in the high and low priority tx queues for the port. in addition, there are four rx watermarks and two tx watermarks per port. the default values of the watermarks may be changed by the cpu. see ?cpu water mark register? on page 175 through ?gport rx watermark control register? on page 179 for details. figure 14 shows the watermarks. figure 14 flow control mechanism when the rx_cnt equals rx_cnt2, flow control is asserted until the rx_cnt drops to rx_cnt1. if the rx_cnt continues to rise above rx_cnt2 and reaches rx_cnt3, the receiving port starts dropping all non-critical packets until rx_cnt drops below rx_cnt2. for example packets like bpdus are those packets that have critical attribute set (critical packets). refer to ?ma table entry types? on page 38 for details. if the rx_cnt continues to rise beyond rx_cnt3 and reaches rx_cnt4 then all packets, including critical packets at the receiving port are dropped until rx_cnt drops below rx_cnt3. the same discussion holds true for gigabit ports, however, the watermark values used are different. the flow control mechanism is designed to prevent faulty links from hogging packet buffer resources and bringing down the system. flow control is disabled upon reset and then depending on disable_pause bit and e_hd_cg_ctl bits in chip configuration register flow control is controlled. in addition, if the port is configured for full duplex operation, the appropriate pause_e_cpu bit in ?port mii register? on page 157 must also be set to 1. rx _c nt4 rx _c nt3 rx _c nt2 rx _c nt1 rx_cnt tx_cnt3 rx_cnt2 tx_cnt1 txhq_cnt tx_cnt3 tx_cnt2 rx_cnt1 txlq_cnt
green plb 2224 operational description data sheet 75 2002-06-03 on the tx side, identical count values and mechanism is used for the high and low priority queues. when txhq_cnt reaches tx_cnt2 non-critical packets are not appended to the txhq queue of the transmitting port, until the txhq_cnt falls below tx_cnt1. if txhq_cnt continues to rise and reaches tx_cnt3, then no packets are appended to the txhq until txhq_cnt drops below tx_cnt2. the same discussion holds true for gigabit and cpu ports, however, the watermark values used are different. this feature is disabled upon reset and must be enabled by setting the en_txq_drop (see ?chip configuration register? on page 141 , page 60) bit to 1 for the ethernet ports. to enable this feature for the cpu ports, en_cpu_txq_drop ( see ?switch configuration register? on page 145 ) bit must be set to a 1.
green plb 2224 operational description data sheet 76 2002-06-03 5.3 statistics registers there are statistic counters for each port in plb 2224. each counter is 32-bit wide. the on-chip sram to store the counter is also 32-bit wide. and it is reset to zero at each chip reset. each counter is at an 4x relative offset starting at the base address. the cpu can read these registers and all registers are cleared to zero upon reset. receiving counters table 24 rx counters counter # counter description 0 number of good packets received 1 number of good octets received 2 number of good broadcast packets received 3 number of good multicast packets received 4 number of received packets with packet length => 64 bytes with crc or alignment error. 5 number of received fragments (packet size < 64 bytes) with good or bad crc 6 number of received oversized packet (length 1519 bytes to 1536 bytes) with good or bad crc 7 number of received jumbo packets (length > 1536 bytes) 8 number of received packets dropped because of insufficient buffer resources 9 number of packets received, length = 64 bytes, with good or bad crc 10 number of packets received, length > 64 bytes and < 128 bytes, with good or bad crc 11 number of packets received, length => 128 bytes and < 256 bytes, with good or bad crc 12 number of packets received, length => 256 bytes and < 512 bytes, with good or bad crc 13 number of packets received, length => 512 bytes and < 1024 bytes, with good or bad crc 14 number of packets received, length => 1024 bytes and <= 1536 bytes, with good or bad crc 15 number of good pause packets received
green plb 2224 operational description data sheet 77 2002-06-03 transmit counters table 25 tx counters vlan counters table 26 vlan rx counters (per vlan) table 27 vlan tx counters (per vlan) counter # counter description 0 number of packets transmitted 1 number of octets transmitted 2 number of broadcast packets transmitted 3 number of multicast packets transmitted 4 number of oversized (lenght => 1519 bytes and <= 1536 bytes) packets transmitted 5 number of packets transmitted, length = 64 bytes 6 number of packets transmitted, length > 64 bytes and < 128 bytes 7 number of packets transmitted, length => 128 bytes and < 256 bytes 8 number of packets transmitted, length => 256 bytes and < 512 bytes 9 number of packets transmitted, length => 512 bytes and < 1024 bytes 10 number of packets transmitted, length => 1024 bytes and <= 1536 bytes 11 number of late collisions 12 number of collisions 13 number of pause frames transmitted 14 reserved 15 reserved counter # counter description 0 number of unicast packets 1 number of multicast packets 2 number of packets dropped counter # counter description 0 number of unicast packets
green plb 2224 operational description data sheet 78 2002-06-03 5.4 packet classification the packet classification and filtering feature enables the plb 2224 to identify patterns within the first 64 b of packet data and take a specific action if a match is found. packet filtering allows identification of packets such as protocol type (i.e., an ip packet), tos values within a certain range of the ip packet, and igmp control packet. once a packet is classified, one of the following actions can be taken: increment a dedicated counter for management purposes, forward the packet to a port designated for forwarding such packets. typically the forwarding port is a cpu port, but it could also be some other port, discard the packet, i.e., do not forward it to the normal destination port(s), monitor the packet, i.e., forward it to the monitoring port, assign high priority to the packet. the data pattern(s) used for identification and handling actions are configured globally and are shared by all ports on the plb 2224. figure 15 shows how packet filtering is accomplished. several registers are used to implement packet classification and filtering. they are described in chapter 7 . these configuration registers are mapped into the cpu address space and can be loaded using the cpu interface. the packet identification is done with the help of four groups of pattern registers. the groups are identified as group #0 through #3, and pattern sets within a group are identified as pattern #0 through #3. out of the 4 groups, pattern registers in group #0 and #1 are user configurable, while in group #2 and #3 they are hard coded to identify ip protocol packets in 802.3 snap and ethernet ii frame formats respectively. groups #0 and #1 each consist of 4 pattern sets. each set has a 16-bit pattern value, a 16-bit mask, 5-bit offset, and a flag for the type of comparison (le or eq). when a packet is received by a port on the plb 2224, the two bytes with the starting half- word (==2-bytes) address of offset[5:1] within the packet are compared with the data stored in pattern[15:0], and a match signal is generated when the results of the comparison are true. in doing the comparison, the pattern[15:0] is qualified by the corresponding mask[15:0]. a 1 at any position in the mask implies that the corresponding bit in the ethernet packet and the pattern register are not being compared (i.e., they are considered matched). the first pattern set (i.e., pattern set #0) in each group can be programmed to generate a match when the packet data is less than or equal to (le) the pattern data. setting the corresponding comp_le0 bit to a 1 does this. the other three pattern sets can only check if the ethernet packet data is equal to the pattern. thus, groups #0 and #1 generate four match signals each, called match0 through match3 1 number of multicast packets 2 number of packets dropped
green plb 2224 operational description data sheet 79 2002-06-03 the handling of the identified packets, i.e., the action(s) to be performed, is determined by a two-stage lookup process as follows: the four match signals each from group #0 and #1 are used as a 4-bit address to do a lookup into a 16-entry x 2-bit table associated with each group. so groups #0 and #1 generates a 2-bit output, called opcode[1:0] as a result of the first look up. the hard- coded groups #2 and #3 generate 1-bit output called opcode0. the 6 opcode bits consisting of 2-bit output, op_code[1:0] from each of group#0 and #1 and 1-bit output op_code[0] from each of the hard coded groups #2 and #3, are used as an address to do the second lookup into a 64-entry x 5-bit table to generate five action signals. the action bits and the corresponding actions are listed below. the action signal is asserted when the corresponding bit is a 1. bit 4 - inc_filter_cnt: increment rx filter count. statistics register #14 in the tx group is used for this purpose. bit 3 - drop: tag the packet to be dropped, i.e., not sent to the normal intended destination port(s) based on the da lookup. bit 2 - filter_fwd_port: forward the packet to the designated forwarding port for such filtered packets bit 1 - monitor: tag the packet for monitoring bit 0 - priority: tag the packet as high priority the filtering feature can be enabled on a per port basis, by setting the appropriate bit in ?enable filtering register? on page 192 . also, if the filtering is enabled on any of the ports, the forwarding port_id, filter-fwd_port[4:0] in this register must also be specified.
green plb 2224 operational description data sheet 80 2002-06-03 figure 15 packet classification 5.4.1 examples the following example shows how the lookup tables are created to perform a typical filtering function. 5.4.1.1 desired filters and actions detect type of service (tos) on all the tcp/ip packets and assign them to different priority queues based on tos value, count all the tcp/ip packets received at each port, forward all igmp packets to the cpu.
green plb 2224 operational description data sheet 81 2002-06-03 5.4.1.2 pattern register setup group #3 and group #2 pattern_mask and offset registers are hardcoded as follows: table 28 group[3] set to detect ip in ethernet ii format table 29 group[2] set to detect ip in 802.3 snap pattern # pattern[15:0] mask[15:0] offset[5:1] comp_le comment 15 0xffff ignored 14 0xffff ignored 13 0xffff ignored 12 0x0800 0x0000 12 0 ip (v4) protocol in ethernet ii pattern # pattern[15:0] mask[15:0] offset[5:1] comp_le comment 11 0x0800 0x0000 20 0 10 0x03xx 0x00ff 16 0 9 0xaaaa 0x0000 14 0 8 0x1500 0x0000 12 1
green plb 2224 operational description data sheet 82 2002-06-03 cpu sets up group #1 and group #0 pattern_mask and offset registers as follows: table 30 group[1] used for ip packets in ethernet ii format table 31 group[0] -used for ip packets in 802.3 snap format opcode table setup group #3 and group #2 opcodes are hard coded as follows table 32 group[3] -op code pattern # pattern[15:0] mask[15:0] offset[5:1] comp_le comment 11 0xxxxx 0xffff 0 ignored 10 0xxx02 0xff00 22 0 identify igmp control frame 9 0xxx06 0xfff0 22 0 identify tcp protocol 8 0xxxx2 0xfff0 16 1 compare 3 tos bits pattern # pattern[15:0] mask[15:0] offset[5:1] comp_le comment 7 0xxxxx 0xffff 0 ignored 6 0xxx02 0xff00 22 0 identify igmp control frame 5 0xxx06 0xfff0 22 0 identify tcp protocol 4 0xxxx2 0xfff0 16 1 compare 3 tos bits match[3:0] op code[0] comment xxx1 1 ip (v4) protocol all other 0 non-ip frame
green plb 2224 operational description data sheet 83 2002-06-03 group[2] - op code the cpu sets up group #1 and group #0 opcodes as follows: group[1] - op code group[0] - op code action code setup the cpu sets up the action code table as follows: table 33 action code table 1111 1 ip (v4) protocol all other 0 non-ip frame match[3:0] op code[1:0] comment x010 11 tcp/ip packet, tos > 2 x011 10 tcp/ip packet, tos <= 2 x10x 01 igmp control frame all other 00 match[3:0] op code[1:0] comment x010 11 tcp/ip packet, tos > 2 x011 10 tcp/ip packet, tos <= 2 x10x 01 igmp control frame all other 00 match[3:0] action[4:0] action taken 1x11xx 00001 tcp packet; set to high priority x1xx11 00001 tcp packets, tos > 2 1x1xxx 10000 tcp/ip packet, increment filter count x1xx1x 10000 tcp/ip packet, increment filter count 1x01xx 01100 igmp packet, send to cpu instead of normal da x1xx01 01100 igmp packet, send to cpu instead of normal da all other 00000 no special action
green plb 2224 operational description data sheet 84 2002-06-03 finally, the enable filter register is set up to enable filtering on all ports and filter_fwd_port[4:0] is set to port 26, i.e. the cpu port. 5.5 packet monitoring packets can be monitored based on the ingress port or egress port, if the monitor bit as described in register 0 x 40, port monitor is set to 1. the id of the monitoring port (i.e., port to which all the monitored packets are sent) is specified in register 0 x 08, switch configuration. the plb 2224 can also be configured to monitor: 1. packets with crc errors, 2. packets whose source port number does not match with the port id value in the ma table entry corresponding to the packet sa. setting the appropriate configuration bits in register 0 x 08, switch configuration activates packet monitoring. 5.6 packet prioritization the plb 2224 architecture supports two priorities ? high and low per port. the priority can be based on the ingress port and/or da. two configuration bits, pri_at_src and pri_at_da , specified in ?switch configuration register? on page 145 are used to determine how packet priority is set. when pri_at_src is set, the configuration register in ?port priority register? on page 158 is looked up to set the priority. when pri_at_da bit is set, the ma table is used to set the priority. when both pri_at_src and pri_at_da bits are set, the priority is set to high if either lookup results in high priority (i.e., the result is an or function). the following rules are used in determining da based priority: for broadcast packets, priority is always set to low for unknown packets, priority is always set to low when ma table entry corresponding to the da is not a locked entry, the priority is always set to low.
green plb 2224 operational description data sheet 85 2002-06-03 5.7 trunking the plb 2224 supports port trunking among like ports. two, four or eight 10/100 ports can be grouped together to form a trunk. the two gigabit ports can also be grouped to create a trunk. there is no limit on the number of trunks. only consecutively numbered ports can be members of a given trunk. the possible trunk configurations are shown in table 34 . the plb 2224 can be configured to use any combination of 8-port, 4-port and 2-port trunks as long as the same physical port is not a part of two trunks. if any of the port(s) in a trunk group are disabled or have a link failure, the other ports in the group share the traffic. it is the port with the next higher id that would transmit the packets in case of failure of one of the ports in a trunk. but if the port that has failed has the highest port id, then it will be the port with the lowest id in the trunk group that would be transmitting the packets. setting the bits described in ?port trunk register? on page 159 enables trunking. table 34 trunk combination number 8-port trunks 4-port trunks 2-port trunks 0 trunk8a trunk4a trunk2a 1 2 trunk2b 3 4 trunk4b trunk2c 5 6 trunk2d 7 8 trunk8b trunk4c trunk2e 9 10 trunk2f 11 12 trunk4d trunk2g 13 14 trunk2h 15
green plb 2224 operational description data sheet 86 2002-06-03 the two configuration bits, trunk_da_based and trunk_sa_based in the ?switch configuration register? on page 145 along with the number of member ports in the trunk is used to determine the physical port over which the packet is transmitted; the first port (i.e., the port with the lowest port number) is considered port 0. for trunks containing 2, 4 or 8 ports, the least significant 1, 2 or 3 bits respectively, of the sa, or da, or sa xored with da determines the physical port. for proper operation, the port trunk register bits must be set correctly (i.e., they must result in complete, unambiguous and legal trunk definitions). also, at least one of the bits trunk_da_based and trunk_sa_based must be set to a 1. 16 trunk8c trunk4e trunk2i 17 18 trunk2j 19 20 trunk4f trunk2k 21 22 trunk2l 23 24 (gport 0) gtrunk 25 (gport 1) number 8-port trunks 4-port trunks 2-port trunks
green plb 2224 operational description data sheet 87 2002-06-03 5.8 address learning the learning process observes the source mac addresses of frames received on each port and updates the filtering database conditionally on the state of the receiving port. the vlan id associated with the frame is used to ensure that the address information is learned relative to the frame?s vlan. frames are submitted to the learning process by the ingress rules as described in the previous sections. the learning process can deduce the port through which particular end stations in the bridged lan can be reached by inspecting the source mac address field and vlan id of received frames. it records such information in the filtering database. the process creates or updates a dynamic filtering entry associated with the frame?s vlan id, associating the reception port with the source mac address, if the following conditions all apply: 1. the port on which the frame was received is in a state that allows learning and, 2. the source address field of the frame denotes a specific end station, i.e., is not a group mac address and, 3. the resulting number of entries would not exceed the capacity of the filtering database, and 4. the member set for the frame?s vlan id includes at least one port. if the filtering database is already filled up to its capacity, where a new entry would otherwise be made, then an existing entry may be removed to make room for the new entry. since the learning is performed in the plb 2224, this processing in the cpu is redundant. however, the cpu keeps a copy of the mac addresses for console or other management entities. a copy of the mac address table is stored and maintained by the cpu. all the sorting, vlan association, and port association is stored. address aging is performed through the cpu in coordination with the same function performed in the plb 2224.
green plb 2224 operational description data sheet 88 2002-06-03 5.9 mac address table and filtering table the mac address table is used by the address resolution logic to determine the destination ports of the received frame. the mac addresses are either learned from the address learning process or statically configured by the management interface. the addresses are part of the filtering database that is used by the arl (ingress filtering, frame forwarding, and egress filtering). 5.9.1 accessing the address table the mac address table in plb 2224 can be accessed through the console or other management entities via api?s. the following api?s are provided by the mac address: 1. mac address matching, 2. list all mac address sorted by mac address, 3. list mac address by port number in ascending mac address order, 4. list mac address by vlan in ascending mac address order. 5.9.2 mac table entry formats the format of the unicast/multicast mac address table entry is. table 35 ma entry formats for unicast and multicast addresses bit fields name description unicast 62 unicast denotes whether the entry is unicast or multicast 62:57 rsv 56:52 port_id[4:0] index to vlan/floodmap for port list lookup 51:48 ma_state[3:0] denotes age; plus criticality, priority and lock attributes 47:0 ma[47:0] mac address multicast 62 multicast denotes whether the entry is unicast or multicast 61:52 flood_ix index to vlan/floodmap for port list lookup for multicast entries the number of entries supported is 256 (address 0 to adress 255) 51:48 ma_state[3:0] denotes age; plus criticality, priority and lock attributes 47:0 ma[47:0] mac address
green plb 2224 operational description data sheet 89 2002-06-03 5.9.3 storage of the mac tables the mac address table is stored in the sram controlled by plb 2224. the cpu can access the mac address table through indirect addressing by programming the memory access register. once stored, this table is updated for each new address learned or address change. the table stored in the cpu is the primary source for console or other management entities to access. 5.9.4 forwarding frames to forward frames to one of the two cpu ports, specific mac addresses (or filters) have to be programmed into the mac address table (or the filtering database). the cpu can send a frame to plb 2224 (cmac) with the values of specific mac addresses assigned to the source mac address field. before sending it to the plb 2224, the cpu also needs to program the plb 2224 arl to assert the learning option. 5.9.4.1 frame forwarding example with snmp an arp request coming into the port will be broadcast to all ports in the same vlan (including a cpu port). since this embedded snmp is destined for the cpu?s ip stack, an arp response is generated by the arp module, replying to the arp request with the mac address of the switch as the source mac address. the source mac address in the frame will be learned and an entry is created. 5.9.4.2 using the cpu a mac address can be assigned by the cpu for each and every port. then there is no need for a mac entry in the mac address table for this purpose. the filter table is programmed through the configuration of plb 2224 registers. there are four filters in the plb 2224 filter table. these four filters can be used to filter (discard) frames, redirect frames to the cpu or to a specific port. one of the examples is to have ip multicast redirect to the cpu. the filter examines the ip protocol field for frames of the igmp protocol type. the igmp packets will be handled by cpu?s ip multicasting process (if supported). igmp packets originated from the ip multicasting process in the cpu will be delivered to cmac without arl to prevent the packets coming back to the cpu again.
green plb 2224 operational description data sheet 90 2002-06-03 5.10 vlan 5.10.1 vlan introduction the plb 2224 supports the vlan feature. this implementation compliant to 802.1d supports a total of 1024 port-based/tag-based vlans. vlans facilitate the easy administration of logical groups of stations that can communicate as if they were on the same lan. they also facilitate easier administration of members of these groups (moving, adding, and changing). the vlan definitions, i.e., the port list comprising a vlan, are stored in an on-chip table that has 1023 32-bit wide entries. within each entry, the vlan membership is specified by setting the corresponding bit for each of the member ports to a 1. the format of the vlan table entry is shown in table 36 . table 36 vlan table entry format 5.10.2 vlan configuration traffic between vlans is restricted. bridges forward unicast, multicast, and broadcast traffic only on lan segments that serve the vlan to which the traffic belongs. vlans maintain compatibility with existing bridges and end stations. if all bridge ports are configured to transmit and receive untagged frames, bridges will work in plug-and-play iso/iec 15802-3 mode. end stations will be able to communicate throughout the bridged lan. a mac bridge that conforms to this standard: 1. conforms to the requirements of iso/iec 15802-3, as modified by the provisions of this standard, 2. relays and filters frames, 3. on each port, supports at least one of the permissible values for the acceptable frame types parameter, 4. supports the following on each port that supports untagged and priority-tagged frames: a) a port vlan identifier (pvid) value, b) the ability to configure at least one vlan whose untagged set includes that port, c) configuration of the pvid value via management operations, d) configuration of static filtering entries via management operations. 5. supports the ability to insert tag headers into, modify tag headers in, and remove tag headers from relayed frames,
green plb 2224 operational description data sheet 91 2002-06-03 6. supports the ability to perform automatic configuration and management of vlan topology information by means of generic attribute registration protocol (garp) vlan registration protocol (gvrp) on all ports, 7. supports the ability for the filtering database to contain static and dynamic configuration information for at least one vlan, by means of static and dynamic vlan registration entries, 5.10.3 vlan operation 5.10.3.1 vlan memories floodmap memory stores the destination port list for each ma?s or vlan membership. for a non-single destination packet the flood_ix[] index from da lookup result will be used to reference floodmap for a destination port list. lower 28-bits of the floodmap stands for the respective port for the destination. in case of a vlan aware switch, floodmap table indicates the membership ports belonging to a particular vlan. in this case the input lookup is vid_ix. this is used to filter non-member ports at receiving and transmitting. registers that are to be used for vlan operation apart from the above memories tag_pri_table (0 x d4) e_pri_table (0 x d8) port_ix_register (0 x 60 , 0 x 78 ) vlan_aware / admit tagged only (0 x e0) table 37 vlan memories description entry size entry # total size floodmap 4 bytes 1024 4096 bytes destination port list for each entry. this can be vlan_port_list in case of a vlan aware switch r dst_port list in the case of non-vlan aware switch. vlan table 40-bits 1 k 40 kbits inputs vid_ix[9:0] outputs {vid[11:0], port_egress_tagged[27:0]} vid_ix table 10-bits 4 k 40 kbits inputs: { vid[11:0] } outputs : { vid_ix[9:0] } vlan id index will be referenced to one entry within the vlan table. multiple vlan?s i.e. multiple vid[], may be assigned to one vid_ix[]
green plb 2224 operational description data sheet 92 2002-06-03 ingress filter enable (0 x ec) security enable ( e_ucast_secu bit 0 x 08) 5.10.4 vlan ingress filter name :vlan ingress filter offset :0 x ec access :read/write description :enables the ingress filtering parameter on a per port basis. table 38 vlan ingress filter an enable ingress filtering parameter is associated with each port. if the enable ingress filtering parameter for a given port is set, the ingress rules shall discard any frame received on that port whose vlan classification does not include that port in its member set. if the parameter is reset for that port, the ingress rules shall not discard frames received on that port on the basis of their vlan classification.the default value for this parameter is reset, i.e., disable ingress filtering, for all ports. the value of this parameter may be configured by means of the management operations, if management operations are supported by the implementation. plb 2224 supports the ability to enable ingress filtering on any port, and also supports the ability to disable ingress filtering on those ports. bit fields name block (access) initial value description 31:28 rsv 0 27:0 ingress filter [27:0] (r/w) 0 0:disable ingress filtering 1:enable ingress filtering an enable ingress filtering parameter is associated with each port. if the enable ingress filtering parameter for a given port is set, the ingress rules (8.6) as mentioned in 802.1q document, shall discard any frame received on that port whose vlan classification does not include that port in its member set
green plb 2224 operational description data sheet 93 2002-06-03 5.10.5 vlan tag conversion figure 16 vlan tag conversion the received frames are checked for the vlan tag in the rx module. vlan tagging, untagging and qualification based on vlan membership are performed only when vlan aware bit in vlan aware register is set. when the vlan aware bit is set to ?0?, plb 2224 treats all the frames as pure mac frames. if the ingress packet is tagged and its size is between 64 bytes and 67 bytes, vlan padding is performed by tx, before the frame is sent out. for fe port this is done by default. for gport the bit 22 in g_rxtx is set (registers 0 x c0 / 0 x e0). this helps in making sure that the egress packet size is guranteed a minimum size of 64 bytes. (the padded data is between the data field and the crc field and has a value equal to ?0?). vid_ix table and vlan_table is configured by cpu through indirect access, as already explained under the data structures section. 3 5 (tagged) pri[2:0] (tagged) cfi e_tag[27:0] pri[2:0] cfi vid[11:0] tag_pri_table (d4h) 8x1 [7:0] e_pri_table (d8h) 2x3 [2:0] (untagged) - sport priority - da priority (filter match priority is not used for egress ta g) internal use onl y (tagged) vid[11:0] rx 10 vidix table 4k x 10 [9:0] vid_ix vlan table 1k x 40 [39:28] vid, [27: 0] e_tag (untagged) p ort ix [ 9:0 ] arl port_cfi (dch) 1x28 [27:0] (untagged) p ort id [ 4:0 ] tx 12 28 12 12 pri
green plb 2224 operational description data sheet 94 2002-06-03 5.10.6 vlan security bit 7 ( e_ucast_sec ) of switch configuration register (0x08) is the vlan security bit for enabling the security features for unicast packets. the packet is dropped if the destination port is not the same vlan as the one associated with the packet. if this bit is set to ?0? the security check is disabled. 5.10.6.1 vlan membership/port list determination figure 17 address resolution/destination port list creation (vlan enabled) vlan membership is applied to qualify packet forwarding list so that each packet does not cross vlan boundary. first the switch generates candidate forwarding port list [27:0] for each packet. depending on da of received packet, switch refers to da_index reg (0x7c) or ma table, and vlan/floodmap table, and port list [27:0] is prepared. last entry for vlan/floodmap table is 1023, which is not on the memory of this table, instead the portlist1023_reg (0x58) is used. entry #1022 en try # 0 v la n / f loodm ap table po rtl is t_1 02 3 po rt _i x po rt _ in de x r e g u n_u cast_ix un _m cast_ix bcast_i x a.2 b.4 a.1 b.1 b.2 da_index reg ma tab le port_id mc ast _ ix b.5 src_pid un _da bcast_da known_da b. 3 b. 7 candidate port(s) l ist vl an me m b e r s h ip lis t b.6 a.3 . forwardi ng port(s) list c. 1
green plb 2224 operational description data sheet 95 2002-06-03 plb 2224 also generates the vlan membership for each packet [27:0]. depending on whether the ingress packet is tagged, vid >0 and vlan_aware=?1?, the switch refers to vidix table or port_ix reg (0x60, 0x78) and the vlan/floodmap table. then the vlan membership [27:0] is prepared. the floodmap memory is shared by the vlan membership information and the floodmap information. figure 18 vlan membership determination then an and function is performed between the candidate port list [27:0] and the vlan membership [27:0]. the switch also checks if the source port is a member of the vlan. the table below shows the qualification of various packets. the description of the legend a / b / c / d in the table is given below the table. vid[11:0] vidix table 4k x 10 [9:0] vid_ix port_id[4:0] vlan/floodmap table [27:0] #0 #1 ? #1022 #1023 not used vlan me mbe r s hi p [ 27:0 ] portlist1023 port_ix reg [9:0] port_ix 12 5 10 10 28 port_id[4:0] 5 (incoming untagged, or vid=?0? or vlan_aware=?0?) (incoming tagged, vid>0 and vlan_aware=?1?)
green plb 2224 operational description data sheet 96 2002-06-03 table 39 qualification of packets legend a : no qualification b : qualified by destination port (and function) c : qualified by destination port (and function) and source port (membership check). d : packet is dropped. an enable ingress filtering parameter is associated with each port. if the enable ingress filtering parameter for a given port is set, the ingress rules shall discard any frame received on that port whose vlan classification does not include that port in its member set. if the parameter is reset for that port, the ingress rules shall not discard frames received on that port on the basis of their vlan classification.the default value for this parameter is reset, i.e., disable ingress filtering, for all ports. the value of this parameter may be configured by means of the management operations, if management operations are supported by the implementation. plb 2224 supports the ability to enable ingress filtering on any port, and also supports the ability to disable ingress filtering on those ports. if the vlan_identifier parameter carried in a received data indication is equal to the null vlan id and the acceptable frame types parameter for the port through which the frame was received is set tothe value admit only vlan-tagged frames , then the frame shall be discarded. ingress tagged and vid>0 vlan aware admit tagged only per port basis ingress filter enable per port basis unicast security enable known unicast unkown unicast, known mcast, unkown mcast, broadcast 0 00/1 0/1 0ab 1bb 10 0 a b 1bb 10/1dd 1 0 0/1 0ab 1bb 100/1bb 1cc
green plb 2224 operational description data sheet 97 2002-06-03 each frame received by a vlan bridge shall be classified as belonging to exactly one vlan by associating a vid value with the received frame. the classification is achieved as follows: a) if the vlan_identifier parameter carried in a received data indication is the null vlan id, then 1. if the implementation supports further vlan classification rules in addition to port- based classification and if the application of these rules associates a non-null vid value with the frame, then that vid value is used. 2. if the enable ingress filtering parameter for the port through which the frame was received is set, and if the port is not in the member set for the frame?s vlan classification, then the frame is dis-carded. associated with each port of a vlan bridge is an acceptable frame types parameter that controls the reception of vlan-tagged and non vlan-tagged frames on that port. valid values for this parameter are: a) admit only vlan-tagged frames ; b) admit all frames . if this parameter is set to admit only vlan-tagged frames , any frames received on that port that carry no vid (i.e., untagged frames or priority-tagged frames) are discarded by the ingress rules. frames that are not discarded as a result of this parameter value are classified and processed according to the ingress rules that apply to that port.
green plb 2224 operational description data sheet 98 2002-06-03 5.11 spanning tree 5.11.1 description of spanning tree support plb 2224 supports multiple vlans. each vlan operates over a single spanning tree. all bridges within a bridged lan infrastructure participate in a single spanning tree. the primary goals of spanning tree are as follows: 1. 1. elimination of loops in a bridged infrastructure, 2. 2. improved scalability in a large network, 3. 3. provision of redundant paths, which can be activated upon failure. 5.11.1.1 spanning tree topologies a spanning tree formed in a vlan environment need not be identical to the topology of the vlan(s). all vlans are aligned along the spanning tree from which they are formed; a given vlan is defined by a subset of the topology of the spanning tree upon which it operates. the topology of a vlan is dynamic. the structure of the vlan may change due to new devices requesting or releasing the services available via the vlan. the dynamic nature of vlans has the advantages of flexibility and bandwidth conservation, at the cost of network management complexity. plb 2224 supports up to 1k vlans, each maps to a single spanning tree. in addition, plb 2224 supports port-based vlan and active vlan?s. each port can be configured as a separate vlan or multiple plb 2224 ports can be configured as one vlan. the port-based vlan is configured through plb 2224 port register configuration. the state of each port in the vlan is derived from the result of the spanning tree algorithm, with the resulting port state for each port written into plb 2224 port register. each of the ports in a vlan can be in the following state: 1. disabling/blocking 2. listening 3. learning 4. forwarding the addition or removal of tag headers by a vlan-aware bridge is performed only on frames submitted to the relay function of the bridge that are potentially to be forwarded on other ports. bpdus are forwarded to one of the cpu ports in plb 2224. forwarding is configured through plb 2224 port register configuration. garp pdus destined for any garp applications are forwarded or filtered depending upon whether the bridge supports the application concerned.
green plb 2224 operational description data sheet 99 2002-06-03 5.11.2 spanning tree protocol support the plb 2224 supports the spanning tree protocol as per the 802.1d specification. as specified in registers 0x50 - 0x54, ?port bridge state register? on page 160 each port has two configuration bits that define the bridging state for that port. for the ethernet (i.e., non-cpu) ports, the following actions are performed, depending on the state of the port. upon reset, each port is in the default forwarding state (2?b11). depending on the state, the non-transmitted packets are automatically purged from the tx queue. table 40 spanning tree states and actions port state[1:0] receive packets learn sa lookup da transmit packets 00 - disabled no no no no 01 - listening yes no yes only those with critical attributes ( treated as a blocking state with only cpu being able to tranmit packets) 10 - learning yes yes yes only those with critical attributes 11 - forwarding yes yes yes all packets
green plb 2224 operational description data sheet 100 2002-06-03 5.12 snmp and rmon mibs snmpv1 is implemented in the plb 2224 switch as part of the tms software. the plb 2224 mib variables are accessible through the simple network management protocol (snmp), which is an application-layer protocol designed to facilitate the exchange of management information between network devices. the snmp system consists of three parts: snmp manager, snmp agent, and mib. instead of defining a large set of commands, snmp places all operations in a get- request, get-next-request, and set-request format. for example, an snmp manager can get a value from an snmp agent or store a value into that snmp agent. the snmp manager can be part of a network management system (nms), and the snmp agent can reside on a networking device such as a router. the snmp agent can respond to mib- related queries being sent by the nms. plb 2224 maintains a set of mib counters, one for each port in its internal registers.
green plb 2224 operational description data sheet 101 2002-06-03 these counters are classified as transmit & receive counters: table 41 snmp receiving counters table 42 snmp transmitting counters counter no. description of the contents 0 number of good packets received 1 number of good octets received 2 number of good broadcast packets received 3 number of good multicast packets received 4 number of packets (>64 bytes) received with crc error, including the allignment error 5 number of fragments received ( < 512 bits) with good or bad crc 6 number of oversized packets received with good or bad crc (1519 to 1536 bytes) 7 number of packets received with size greater than 1536 bytes 8 number of packets dropped due to lack of resources 9 number of packets received with size of 64 bytes (with good or bad crc) 10 number of packets received with sizes from 65 bytes to 127 bytes (with good or bad crc) 11 number of packets received with sizes from 128 bytes to 255 bytes (with good or bad crc) 12 number of packets received with sizes from 256 bytes to 511 bytes (with good or bad crc) 13 number of packets received with sizes from 512 bytes to 1023 bytes (with good or bad crc) 14 number of packets received with sizes from 1024 bytes to 1536 bytes (with good or bad crc) 15 receive good pause frame packet counter no. description of the contents 0 number of good packets transmitted 1 number of good octets transmitted 2 number of good broadcast packets transmitted 3 number of good multicast packets transmitted
green plb 2224 operational description data sheet 102 2002-06-03 the access to these mib counters is through register access as described in the section ?indirect access to the memories? on page 62 . there are 3 mib counters for vlan aware switch for each of transmit & receive section receive vlan mib : number of unicast packets received, number of multicast packets received and number of packets dropped transmit vlan mib : number of unicast packets transmitted, number of multicast packets transmitted and the number of packets dropped 4 oversized packet (1519 to 1536 bytes) transmitted 5 number of packets of size 64-bytes transmitted 6 number of packets transmitted with sizes from 65 bytes to 127 bytes 7 number of packets transmitted with sizes from 128 bytes to 255 bytes 8 number of packets transmitted with sizes from 256 bytes to 511 bytes 9 number of packets transmitted with sizes from 512 bytes to 1023 bytes 10 number of packets transmitted with sizes from 1024 bytes to 1536 bytes 11 packets experiencing late collision 12 packets experiencing collision 13 number of packets transmitted with pause frame 14 filter matched packet counter 15 reserved counter no. description of the contents
green plb 2224 operational description data sheet 103 2002-06-03 5.13 led there are four led?s for each of the 26 ports in plb 2224. each of the four led?s represents a different meaning based on the led display mode which are classified as mode 0 and mode 1 . the table below explains the led configurations. mode 0 is a speed based display mode. in this mode, 10 mbit/s and 100 mbit/s links use a different led. mode 1 is feature based display mode. in this mode, led0 selects link speed and led1 indicates link activities. the led activities also depend on the chip led configurations. the related led configuration bits in the chip configuration register are: mask_coll_led, en_tx_led, and led_mode. the individual led?s meaning is determined by the led_mode. the interpretation of led?s flashing activities considers whether collision is masked out for led activities (mask_coll_led) or packet transmitting is configured to have led activities (en_tx_led). these two work together to determine the actual interpretation of flashing activities. table 43 led configurations in addition plb 2224 offers serial led interface. this provides the user the flexibility of having an external logic to latch and display the data. the serial led interface or the normal matrix led mode of operation can be selected on power-on through powerstrap of led_col[7] pin. for serial led interface the led_col[7] pin is pulled low. the following pins are used in serial mode of operation led mode 0 (speed based) mode 1 (feature based) led0 on 10 mbit/s 100 mbit/s link flashing 10 mbit/s link activity - off 10 mbit/s link bad 10 mbit/s link led1 on 100 mbit/s no activity flashing 100 mbit/s link activity - off 100 mbit/s link bad 10 mbit/s link led2 on full duplex off half duplex led3 on port diabled flashing crc error, oversize packet, drop received packet, mac address update or late collision off 10 mbit/s link bad 10 mbit/s link
green plb 2224 operational description data sheet 104 2002-06-03 led_row_n[1] : load or data strobe led_row_n[2] : serial data out led_row_n[3] : clock the sequence of data flowing out of the serial data out line is in the following order port0 row0, port0 row1, port0 row2, port0 row3, port1 row0, port1 row2, ..... port27 row0, port27 row1, port27 row2, port27 row3. once the last set of data is out, data strobe signal is issued on led_row_n[1]. all the led?s have an internal pullup (2 k), which is used to prevent open inputs when the chip is reset. during the reset phase the values on the led pins are pinstrapped. if a low value has to be pinstrapped, the value of the pull down resistor is k.
green plb 2224 interface description data sheet 105 2002-06-03 6 interface description 6.1 external interfaces the plb 2224 interfaces with the following external devices. they are briefly described in this section; the detailed description is given later in the document. 6.1.1 10/100 phys the plb 2224 has twenty-four 10/100 ports. the plb 2224 connects to either three octal or six quad phy devices that support the smii interface. 6.1.2 gigabit phys there are two gigabit-ethernet ports on the plb 2224. these ports connect to gigabit phy devices using either the gmii or the tbi interface. 6.1.3 mdio interface the mdio interface is compliant with the mii specification and is used to communicate with the phy devices. all 10/100 ethernet and gigabit ethernet ports share this interface. using mdio interface, the cpu can also access the phy registers. 6.1.4 led interface the plb 2224 provides led interface signals that can be used to indicate port status. this interface provides information on link status; speed, duplex and activity can be displayed using the led signals. only external drivers (i.e., no decode logic) are needed to drive the led. serial led interface is also supported by plb 2224. 6.1.5 jtag interface standard jtag interface is provided for board-level testing 6.1.6 clock / reset interface the plb 2224 requires two clock sources: 100 mhz system clock 125 mhz clock for the smii and gigabit interfaces the plb 2224 internally generates the clocks required for the internal logic and cpu logic. the pci interface uses the pci clock which runs at 33 mhz. a single reset signal (reset_n) is shared by all functions on the plb 2224.
green plb 2224 interface description data sheet 106 2002-06-03 6.2 cpu and eeprom interface 6.2.1 cpu interface the plb 2224 has three options for connecting a cpu subsystem: pci bus - a 32-bit pci bus (v2.1 compliant) operating at up to 33 mhz, generic processor bus - a 32-bit data bus operating at up to 33 mhz. cpus with multiplexed address/data as well as de-multiplexed address/data are supported, 2-wire serial bus - for connecting an i 2 c compatible master mode processor. the bus can operate at up to 3.3 mhz. the use of the cpu port is optional and is typically required for managed systems or systems with uplink (atm, fddi, and dsl) capability. only one of the three interfaces can be used in the system at one time. the cpu port can be used to access internal configuration, rmon registers and memory. in addition monitored port traffic, unknown packets and other special packets (uplink) can be directed to this cpu port for further processing. 6.2.2 i 2 c interface an i 2 c compatible eeprom is required for configuring the plb 2224 when a cpu is not present in the system. the plb 2224 interfaces with the eeprom using the 2-wire serial bus operating in master mode. the key features of these three buses are described in the following paragraphs. 6.2.2.1 the pci local bus interface the pci local bus is a high performance 32-bit fully synchronous bus with multiplexed address and data lines. the bus is intended for use as an interconnect mechanism between highly integrated peripheral components, peripheral add-in boards, and processor/memory systems. some of the performance features include: high-bus bandwidth, 132 mbytes/s burst memory transfer on a 33 mhz bus, pci bus bridges give add-on pci bus masters a high bandwidth path to main memory, cache and exclusive access support, typical pci applications typical pci applications are add-on boards that require high-speed memory access, including lan adapters, graphic adapters, hard drive controllers and scsi cards. using the pci bus allows system designers to implement system critical components on a high bandwidth bus using low cost components so enhancing system price and performance. there are three main types of devices that operate on the pci bus:
green plb 2224 interface description data sheet 107 2002-06-03 pci bus/system bridge: this interfaces the pci bus to the system processor and main memory. this device can act as a pci master and arbitrate for systems that allow multiple bus masters, pci bus add-on masters: add-ons are devices that can operate the bus and may need access to other pci add-ons or main memory on the system, pci bus target-only add-ons: these are add-on devices that can only operate as targets. these devices respond to but do not initiate bus cycles. the current implementation of the cpuif supports only 33 mhz , 32-bit, target-only pci local bus for 3.3 v operations. 6.2.2.2 the generic interface the generic interface is a simple asynchronous bus, similar to those used in systems or processors of conventional motorola and intel products. it supports either multiplexed or separated address and data buses. it also can support separated read and write control lines or combined read/write control line with a data strobe signal. a programmable number of wait cycles can be configured for delaying the activation of the ready signal to the host processor. the i 2 c-bus interface the i 2 c bus is a 2-way, 2-line serial communication bus between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). it was developed philips. on an i 2 c bus, each device is recognized by a unique address and can operate as either a receiver-only device (for example, an lcd driver) or a transmitter with the capability to both receive and send information (such as memory). transmitters and/or receivers can operate in two modes, depending on whether the chip has to initiate a data transfer or is only addressed. these modes are: master mode, slave mode. i 2 c is a multi-master bus, i.e. it can be controlled by more than one ic connected to it. the current implementation of i 2 c interface supports a 7-bit address i 2 c bus with two data transfer rates: 100 kbits/s and 3.3 mbits/s. the operating modes include: the master mode for reading the eeprom data (511 data bytes and one check-sum byte), the slave transmit and receive mode for interacting with an external cpu connected on the i 2 c bus. input filtering on both scl and sda lines are provided to suppress any pulse spikes. correspondence between pci/generic and i 2 c interfaces
green plb 2224 interface description data sheet 108 2002-06-03 the description of the pci interface signals, generic interface signals and the i 2 c interface signals. table 44 correspondence between pci/generic and iic interface pci interface signals generic interface signals iic interface signals pin name signal name signal type signal name signal type signal name signal type pci_clk pci_clk i cycle_sel0 i i reset_n reset_n i reset_n i reset_n i ad[31:0] ad[31:0] b(t/s) ad[31:0] d[31:0] b(t/s) b(t/s) cbe_n[3] cbe_n[3] i ale as_n i i cbe_n[2] cbe_n[2] i useds i cbe_n[1] cbe_n[1] i ds_n rd_n i i i cbe_n[0] cbe_n[0] i rd/wr_n wr_n i i cycle_sel i frame_n frame_n i cs_n i trdy_n trdy_n o(t/s) rdy o(o/d) idsel idsel i a8 i device_id6 i irdy_n irdy_n i a2 i device_id0 i par par b(t/s) a3 i device_id1 i perr_n perr_n o(t/s) a4 i device_id2 i serr_n serr_n o(o/d) a5 i device_id3 i devsel_n devsel_n o(s/t/s) a6 i device_id4 i stop_n stop_n o(s/t/s) a7 i device_id5 inta_n inta_n o(o/d) inta_n o(o/d) inta_n o(o/d) sda sda b(o/d) scl scl b(o/d) t_rsv1 (sel_pci) sel_pci =?1? i sel_pci =?0? t_rsv2 one_wait_ cycle i muxed ad i
green plb 2224 interface description data sheet 109 2002-06-03 the signal definition for the above interfaces is shown in the table below 6.2.2.3 pci interface details the pci interface signals are shown in the table below table 45 pci interface signals pin name signal name signal type signal name signal type signal name signal type sel_iic =?0? i =?0? i =?1? i sel_eeprom sel_eeprom signal type definition i input is a standard cmos input only o output is a standard cmos active driver b bi-directional signal t/s tri-state input / output pin s/t/s sustained tri-state is an active-low tri-state signal owned and driven by one and only one agent at a time. the agent that drives an s/t/s pin low must drive it high for atleast one clock before letting it float a pullup is required to sustain the inactive state until another agent drives it. o/d open drain allows multiple devices to be shared as a wire-or. a pullup is required to sustain the inactive state until another agent drives it and must be provided by a central source signal name signal type signal description pci_clk i pci_clk provides the reference signal for all other pciinterface signals, except reset_n and inta_n. the frequency of pci_clk ranges from dc to 33 mhz. reset_n i reset_n initializes the cpuif? s pci interface circuitry to a stable state. reset_n can be asserted asynchronously to the pci clock edge. when active, the pci output signals are tri- stated, and the open-drain signals float. pci interface signals generic interface signals iic interface signals
green plb 2224 interface description data sheet 110 2002-06-03 ad[31:0] i ad[31..0] is a time-multiplexed address/data bus, with each bus transaction consisting of an address phase followed by one or more data phases. the frame_n signal identifies the start of an address phase. the data phases occur when both irdy_n and trdy_n are asserted. c/be_n[3:0] i command and byte enables are multiplexed on c/be_n[]. the bus command is indicated during the address phase of a transaction. the byte enables are active during the data phases of a transaction and indicate which bytes of the 32-bit data transferred are valid. frame_n i frame_n is driven by the current bus master to indicate the beginning and the duration of a bus operation. when frame_n is first asserted, the address and command signals are present on ad[] and c/be_n[]. frame_n remains asserted during the data operation and is de-asserted to identify the end of a data operation. trdy_n o target ready. trdy_n is output by a target towards the initiator to indicate that the target can complete a data operation. idsel i initialization device select. idsel is a chip select forconfiguration read and write transactions. irdy_n i initiator ready. irdy_n is output by a bus master towards a target to indicate that the bus master can complete a data operation. par b par is the signal of even parity calculated on the linking of events in the ad[] and c/be_n[] fields. it is always calculated by the device providing data and by the bus master during address phases. par must be valid one clock following its corresponding data (or address) on the pci bus. perr_n o perr_n indicates data parity errors on data transactions serr_n o serr_n indicates system errors and address parity errors (or data parity errors during special cycles). devsel_n o target asserts devsel_n as a decode acknowledgment when the address and bus command are valid. stop_n o stop_n is asserted by a target to request that the bus master stops the current transaction. signal name signal type signal description
green plb 2224 interface description data sheet 111 2002-06-03 6.2.2.4 generic interface signals description table 46 generic interface signals inta_n o interrupt a is an active low interrupt to the host. inta_n must be used for any single-function device requiring an interrupt capability. sel_iic i sel_iic = 0 t_rsv1 (sel_pci) i sel_pci = 1 signal name signal type signal description pci_clk i generic mode wait cycle select cycle_sel0 =0: no wait cycle_sel0 =1: wait delay cycle = 3 cycles = 90 ns reset_n i reset input (asynchronous) ad[31:0] b when muxed_ad = 1, ad[] is multiplexed address and databus. when muxed_ad = 0, d[] is bidirectional databus. cbe_n[3] i treated as ale / as_n for generic interface when: muxed_ad = 1, ale is the active-high address latch enable input for latching the multiplexed address on ad[]. muxed_ad = 0, as_n is the active-low address strobe input for latching the address lines on a2 thru a8. cbe_n[2] i treated as useds for generic interface when: useds = 1, the active-low data strobe signal ds_n and the read/write signal rd/wr_n are used for memory i/o control. useds = 0, the active-low read strobe signal rd_n and the active-low write strobe signal wr_n are used for memory i/o control. cbe_n[1] i treated as ds_n for generic interface ds_n is the active-low data strobe signal used when useds = 1. rd_n is the active-low read strobe signal when useds = 0. signal name signal type signal description
green plb 2224 interface description data sheet 112 2002-06-03 6.2.2.5 iic interface signals table 47 i 2 c interface signals cbe_n[0] i treated as rd/wr_n for generic interface when useds =1 rd/wr_n is the read/write mode indicator (read when 1; write when 0) when useds = 0 wr_n is the write strobe line. frame_n i cs_n is the active low chip select input for generic mode. trdy_n o when the interface is ready for data transfer, rdy is driven 1. it should be driven 0 as soon as cs_n is active if the interface is not ready for data transfer yet. irdy_n i address line # 2 when muxed_ad = 0 par i address line # 3 when muxed_ad = 0 perr_n i address line # 4 when muxed_ad = 0 serr_n i address line # 5 when muxed_ad = 0 devsel_n i address line # 6 when muxed_ad = 0 stop_n i address line # 7 when muxed_ad = 0 inta_n o (o/d) interrupt output (active low ) sel_iic i sel_iic = 0 t_rsv1 (sel_pci) i sel_pci = 0 t_rsv2 i multiplexed address and data bus selection input. 1: multiplexed address and data on ad[]. 0: address lines on a2 thru a8 and data on d[]. signal name signal type signal description reset_n i reset input (asynchronous) eeprom_sp eed i 1 : data rate 3.3 mhz 0 : data rate 100 khz irdy_n i device id bit 0 par i device id bit 1 signal name signal type signal description
green plb 2224 interface description data sheet 113 2002-06-03 6.2.3 i 2 c bus concept two wires, serial data (sda) and serial clock (scl), carry information between the devices connected to the bus. each device is recognised by a unique address whether it?s a microcontroller, lcd driver, memory or keyboard interface and can operate as either a transmitter or receiver, depending on the function of the device. table 48 definition of iic bus terminology perr_n i device id bit 2 serr_n i device id bit 3 devsel_n i device id bit 4 stop_n i device id bit 5 idsel i device id bit 6 inta_n o (o/d) interrupt request to external cpu on iic bus sel_iic i sel_iic = 1 t_rsv1 (sel_pci) i sel_pci = 0 scl i/o i 2 c serial clock sda i/o i 2 c serial data terminology description tranmitter the device which sends the data to the bus receiver the device which receives the data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by a master multi-master more than one master can attempt to control the bus at the same time without corrupting the message arbitrator procedure to ensure that, if more than one master simultaneously tries to control the buse, only one is allowed to do so and the message is not corrupted synchronisation procedure to synchronize the clock signals of tow or more devices signal name signal type signal description
green plb 2224 interface description data sheet 114 2002-06-03 6.2.3.1 start and stop conditions a high to low transition on the sda line while scl is high indicates a start condition. a low to high transition on the sda line while scl is high indicates a stop condition . start / stop conditions are always generated by the master. figure 19 start & stop condition every byte transferred on the sda line must be 8-bits long and each byte has to be followed by an acknowledge bit. data transfer with acknowledge is mandatory. the acknowledge-related clock pulse is sda line during the acknowledge clock pulse. the receiver must pull down the sda line figure 20 data transfer on the iic bus
green plb 2224 interface description data sheet 115 2002-06-03 figure 21 acknowledge on the i 2 c bus 6.2.3.2 application note for iic interface of plb 2224 figure 22 read protocol for iic bus s address r a s s from master to slave(green) from slave(green) to master a = ack (sdl low) s = start condition p = stop condition w = write command ('0') r = read command ('1') address = 7 bits green i2c bus device address register = 8 bits green register word address (register byte offset divided by 4) byte0 = regiter bits 7..0 byte1 = regiter bits 15..8 byte2 = regiter bits 23..16 byte3 = regiter bits 31..24 msb lsb bit7 bit0 s address w register a a msb lsb msb lsb byte0 a p 32 bits register data 1100,000 1100,000 0000,0010 0 1 read green swith_config register green i2c address is set to 1100,000 bit15 bit8 byte1 a 23 16 byte2 a 31 24 byte3 a
green plb 2224 interface description data sheet 116 2002-06-03 figure 23 write protocol for iic interface 1. iic interface of plb 2224 support 7-bits device address. it requires eeprom's device address be fixed as 7'b1010000. the device address for plb 2224 itself is decided by 6 pins' value when sel_iic == 1: device_id[6:0] = {idsel, stop_n, devsel_n, serr_n, perr_n, par, irdy_n}, in which idsel is device_id6, irdy_n is device_id0. 2. iic interface of plb 2224's data unit is double word (4 bytes). plb 2224 has 512-bytes register space and each register has 4 bytes, so totally ar 2224 has 128 registers. given register 4 as an example, the serial bits occured sequentially on bus sda is: reg4[7], reg4[6], ..., reg4[0], reg4[15], ..., reg4[8], ..., reg4[23], ..., reg4[16], reg4[31], ..., reg4[24] so, the least significant byte is first in 4-bytes and the most significant bit is first in one byte. 3. master mode, or eeprom mode. set sel_iic = 1 and frame_n = 1. plb 2224 will automatically issue 512-bytes sequential read in which the first 511-bytes are plb 2224 register data, the last byte is checksum. s address w register a byte0 a byte1 a byte2 a a byte3 a s s from master to slave(green) from slave(green) to master a = ack (sdl low) s = start condition p = stop condition w = write command ('0') r = read command ('1') address = 7 bits green i2c bus device address register = 8 bits green register word address (register byte offset divided by 4) byte0 = regiter bits 7..0 byte1 = regiter bits 15..8 byte2 = regiter bits 23..16 byte3 = regiter bits 31..24 msblsb msblsb bit7 bit0 bit8 bit23 bit16 bit31 bit24 bit15 p 1100,000 0000,0010 0 32 bits register data written write green swith_config register green i2c address is set to 1100,000
green plb 2224 interface description data sheet 117 2002-06-03 assuming the register is 7'bxxxxxxx, its data are stored in the corresponding four eeprom bytes locations with address 9'bxxxxxxx00, 9'bxxxxxxx01, 9'bxxxxxxx10 and 9'bxxxxxxx11, where the byte at 9'bxxxxxxx00 corresponds to the least significant byte of that register. 4. checksum calculation: assuming data[i] is byte i in the 512-bytes of eerprom. checksum = data[511] = ~(data[0]+data[1]+...+data[510]) +1 5. slave mode, or system has a iic mirocontroller set sel_iic = 1 and frame_n = 0. set device_id[6:0] as needed. see 1. iic interface of plb 2224 supports random read, sequential read, random write and sequential write. in the following section, the terms can be referenced in atmel's eeprom data sheet. the operation is much simillar as atmel's eerpom. the only difference is that eeprom's address is byte boundary, and plb 2224's address is 4-byte boundary. so only 7-bits address (or 7-bits register id, not the 7 bits device address in 1.) can cover plb 2224's 128 registers. random read operation on sda {start, device_id[6:0], 1'b0 (write), ack}; {reg_id[7:0] (actually the msb always 0 because ar 2224 only has 128 registers), ack}; {start, device_id[6:0], 1'b1(read), ack}; {data[7:0] (data is the content of the register whose id is reg_id[7:0], ack}; {data[15:8], ack}; {data[23:16], ack}; {data[31:24], no ack, stop} sequential read operation on sda {start, device_id[6:0], 1'b1(read), ack}; {data_n[7:0], ack}, {data_n[15:8], ack}; {data_n[23:16], ack}; {data_n[31:24], ack}; {data_n+1[7:0], ack}, {data_n+1[15:8], ack}; {data_n+1[23:16], ack}; {data_n+1[31:24], ack}; ...; {data_n+x[7:0], ack}, {data_n+x[15:8], ack}; {data_n+x[23:16], ack}; {data_n+x[31:24], no ack, stop}
green plb 2224 interface description data sheet 118 2002-06-03 random write operation on sda {start, device_id[6:0], 1'b0 (write), ack}; {reg_id[7:0], ack}; {data[7:0] (data is the content of the register whose id is reg_id[7:0], ack}; {data[15:8], ack}; {data[23:16], ack}; {data[31:24], ack, stop} sequential write operation on sda {start, device_id[6:0], 1'b0 (write), ack}; {n[7:0], ack}; {data_n[7:0], ack}, {data_n[15:8], ack}; {data_n[23:16], ack}; {data_n[31:24], ack}; {data_n+1[7:0], ack}, {data_n+1[15:8], ack}; {data_n+1[23:16], ack}; {data_n+1[31:24], ack}; ...; {data_n+x[7:0], ack}, {data_n+x[15:8], ack}; {data_n+x[23:16], ack}; {data_n+x[31:24], ack, stop}
green plb 2224 interface description data sheet 119 2002-06-03 6.3 pci command definition table 49 pci command definition c_be_n command type support in cpuif 0000 interrupt acknowledge no 0001 special cycle no 0010 i/o read no 0011 i/o write no 0100 reserved no 0101 reserved no 0110 memory read yes 0111 memory write yes 1000 reserved no 1001 reserved no 1010 configuration read yes 1011 configuration write yes 1100 memory read multiple no 1101 dual address cycle no 1110 memory read line no 1111 memory write and invalidate no
green plb 2224 interface description data sheet 120 2002-06-03 6.4 pci configuration registers table 50 pci configuration register address space address byte 3210 00 device id vendor id 04 status register command register 08 class code revision id 0c bist header type latency timer cache line size 10 base address register 0 14 base address register 1 18 base address register 2 1c base address register 3 20 base address register 4 24 base address register 5 28 cardbus cis pointer 2c subsystem id subsystem vendor id 30 expansion rom base address 34 capability pointer 38 reserved 3c max latency minimun grant interrupt pin interrupt line
green plb 2224 register description data sheet 121 2002-06-03 7 register description this chapter describes the plb 2224 registers configuration, dealing with the register map and the details of each register. the pci configuration registers are also covered. in a managed ethernet switch, the plb 2224 pci configuration space needs to be programmed first. this is accomplished through the changing of the configuration address and configuration data registers in qspan pci bridge chip.
green plb 2224 register description data sheet 122 2002-06-03 7.1 pci configuration phase the address of qspan ranges from fa210000 to fa21fffff. when an address in this range is accessed, the cpu uses cs6 to select qspan. the reference design will have the idsel (id select) of the plb 2224 hardwired to one of the upper 16-bits of the address. once the device number is determined, cpu can write to con_add (fa210500) for the plb 2224 chip and one specific pci configuration register. the content of the register is written to con_data (fa210504). the following registers need to be programmed before the plb 2224 internal registers can be accessed: pci configuration space control and status, pci configuration miscellaneous 0, pci configuration base address, pci configuration miscellaneous 1. the pci target channel registers in qspan need to be programmed before the address translation takes place in addressing the plb 2224 internal register.
green plb 2224 register description data sheet 123 2002-06-03 7.2 switch configuration phase after pci configuration phase is completed, the PLB2224 internal registers are exposed to the pci bus. these registers can be programmed according to the specific functions required by the ethernet switch. 7.2.1 chip level configuration table 51 chip level configration function register field comment enable/disable all plb 2224 ports ?chip configuration register? on page 141 intelligent this can be used by 802.1d to control the port disable 802.3x flow control for full duplex ports chip configuration register disable_pause mdio or smii polling result selection chip configuration register use_mdio_mode select speed, pause_e, full_duplex, and link_ok source ?switch configuration register? on page 145 e_hw_mode the e_hw_mode should be 1. congestion control for half duplex ports chip configuration register e_hd_cg_ctl generate collision if encountering congestion. tx queue length control chip configuration register en_txq_drop to make sure wire- speed can be achieved and resources are not exceeded.
green plb 2224 register description data sheet 124 2002-06-03 7.2.2 port level configuration and monitoring table 52 port level configuration and monitoring led control chip configuration register led_mode , en_tx_led, mask_coll_led control the behavior of led. watermark setup watermark registers for cpu, fe, and ge ports for both tx and rx. switch configuration register all watermark_scale setup watermarks for each type of ports for resource management. function register field comment monitor port status ?port status register? on page 154 port_active, rxdq_full_drop, crc_err, late_collision one bit for each port can be read to determine the port status corresponding to the events mentioned in the field column ?port event register? on page 155 txdq_full port_critical_event one bit for each port can be read to determine the port status corresponding to the events mentioned in the field column ?port underrun/ overrun register? on page 156 txfifo_underrun rxfifo_overun one bit for each port can be read to determine the port status corresponding to the underrun/ overrun mentioned in the field column function register field comment
green plb 2224 register description data sheet 125 2002-06-03 mii port control ?port mii register? on page 157 speed_cpu pause_e_cpu full_duplex_cpu link_ok_cpu when autonegotiation is bypassed these values are used to configure the individual ports port priority setup ?port priority register? on page 158 priority set priority of individual ports incase of pri_at_src monitor the packets sent and received on each port ?port monitor register? on page 158 monitored packets are monitored for specific port in both receive and transmit directions. the monitoring port is set based on the setting in switch configuration register ( monitoring_pid ) trunking ?port trunk register? on page 159 trunk_opt associated to form a trunk between two ethernet switches ?switch configuration register? on page 145 trunk_da_based trunk_sa_based function register field comment
green plb 2224 register description data sheet 126 2002-06-03 7.2.3 switch level configuration table 53 switch level configuration setup function register field comment select autonegotiation ?switch configuration register? on page 145 e_hw_mode the cpu does the port configuration or gets the results from auot-negotiation results (through mdio interface or smii interface) cpu co-ordination ?switch configuration register? on page 145 big_endian, soft_rst, dis_err_rst supports cpu endian modes and reset behaviour packet priority selection ?switch configuration register? on page 145 e_pri, pri_at_src, pri_at_da, bandwidth_ratio enable packets priority for forwarding to different queues mac address control ?switch configuration register? on page 145 ma_freeze_new, ma_freeze manage mac additiona and deletions set up monitoring port ?switch configuration register? on page 145 monitoring_port forward packets to the monitoring ports if enabled enable monitoring ?switch configuration register? on page 145 monitor_pkt_err, monitor_pkt_ma_ch ange enable packet monitoring queue appropriation ?switch configuration register? on page 145 watermark_scale, rx_pause_frame, bandwidth_ratio
green plb 2224 register description data sheet 127 2002-06-03 aging time control ?switch configuration register? on page 145 age_tick_sofware, age_tick_sel[2:0] control of the aging timer under different situations monitor switch events ?switch status and mask register? on page 152 all bits events like ma_change, freeq_empty, late_collision etc. function register field comment
green plb 2224 register description data sheet 128 2002-06-03 7.2.4 vlan and bridge configuration table 54 vlan and bridge configuration function register/s field comment 802.1d control port bridge state ?port bridge state register? on page 160 bridge_state for spanning tree control ( each vlan operates over a single spanning tree) vlan aware indicator / admit tagged only ?vlan aware/ intag control register? on page 183 vlan_aware, admit_tagged_only[] switch follows 802.1q with tagging and untagging capability. please refer to ?vlan? on page 90 for more details port vlan membership ?port index register_20_0? on page 161 ?port index register 26_21? on page 184 port_ix each port has a vlan index, which is used to findout the membership from the vlan table vlan ingress filter ?vlan ingress filter? on page 184 ingress_filter enable ingress filtering on a per port basis security enable ?switch configuration register? on page 145 e_ucast_secu vlan security bit for unicast packets priority information for tagged packets ?tag priority table register? on page 181 tag_pri to determine the priority of the packets egress priority table ?egress priority table? on page 182 e_pri_1, e_pri_0 priority of the egress packets for a tagged frame
green plb 2224 register description data sheet 129 2002-06-03 table 55 filtering configuration table 56 mac address accessing vlan table / vid_ix_table / floodmap tables ?memory upper address register? on page 163 all please refer to respective register details and also section on vlan for more information ?memory access register? on page 165 all function register field comment vlan port list ?portlist_1023 register? on page 161 portlist port list 1023 is used when port index is 1023 as a special case. this is typically an all port list. broadcast ?da index register? on page 163 unknown_flood_ix, unknow_ucast_ix, bcast_ix port list index for broadcast and unknown mac addresses. function register field comment read and write mac address table memory all please set blk_sel_msb[3:0] = 4?b1001 to access arl dataspace memory access all function register/s field comment
green plb 2224 register description data sheet 130 2002-06-03 7.2.5 bpdu transmission and receiving table 57 bpdu transmission and reception function register field comment configure mac address for bridge or transmit bpdu packets ?cmac rx register? on page 167 all poll crx_cpu_pktid_rdy before sending a packet. setup crx_sof, crx_eof, crx_bytecnt, crx_crc_err, crx_crc_gen. write data to cmac_data till the last transaction is complete. in between crx_cpu_fifo_rdy is polled. before the last transaction the crx_eof & crx_bytecnt is set.arl register is used to do the da lookup, destination ports etc. please refer to ?cpu port rx? on page 44 for more details ?cmac data register? on page 167 all ?arl register? on page 170 arl all receiving bpdu or other learning packet ?cmac tx register? on page 169 all please refer to section ?cpu port tx? on page 45 for more details ?cmac_tx1 register? on page 170 all ?cmac data register? on page 167 all
green plb 2224 register description data sheet 131 2002-06-03 7.3 plb 2224 pci configuration registers table 58 pci configuration registers offset name access description 0x000 pci_id r pci configuration space id register 0x004 pci_cs r/w pci configuration space control and status register 0x008 pci_class r pci configuration class register 0x00c pci_misc0 r/w pci configuration miscellaneous register 0 0x010 pci_bsm0 r/w pci configuration base address for memory register 0x014 pci_bsm1 r/w pci configuration base address for memory register 0x018 pci_bsm2 r/w pci configuration base address for memory register 0x01c pci_bsm3 r/w pci configuration base address for memory register 0x020 pci_bsm4 r/w pci configuration base address for memory register 0x024 pci_bsm5 r/w pci configuration base address for memory register 0x028 pci_cis r/w pci configuration card bus cis pointer register 0x02c pci_sid r pci configuration subsystem id register 0x030 pci_bsrom r/w pci configuration expansion rom base address register 0x034 pci_rsvd0 reserved 0x038 pci_rsvd1 reserved 0x03c pci_misc1 r/w pci configuration misc 1 register
green plb 2224 register description data sheet 132 2002-06-03 7.3.1 register 0x00, pci configuration space id table 59 pci configuration space id description: pci configuration space id register is used by the pci device to identify itself. it consists of a unique vendor id assigned by pci sig and a device id assigned by the vendor. dev_id : 0x0009 vendor_id : 0x15d1. bit(s) name length block access default 31:16 dev_id 16 pci_if ro 0x0009 15:0 vendor_id 16 pci_if ro 0x15d1
green plb 2224 register description data sheet 133 2002-06-03 7.3.2 register 0x04, pci configuration space status and command description the pci configuration space status and command register has two sub-registers. the status sub-register records status information for pci bus related events. the command sub-register provides coarse control to generate and respond to pci commands. perr the perr bit indicates a detected (address or data) parity error. it is set by cpuif when detected. 0: no parity error, 1: parity error bit(s) name length block access default 31 perr 1 pci_if rr 0 30 serr 1 pci_if rr 0 29 rma 1 pci_if rr 0 28 rfa 1 pci_if rr 0 27 sta 1 pci_if rr 0 26:25 dev_sel 2 pci_if ro 0x01 24 dpd 1 pci_if rr 0 23 tfbbc 1 pci_if ro 0x1 22 rsvd 1 pci_if ro 0 21 dev66 1 pci_if ro 0 20:10 rsvd 11 pci_if ro 0 9 mfbbc 1 pci_if ro 0 8 serr_en 1 pci_if r/w 0 7 wait 1 pci_if ro 0 6 peresp 1 pci_if r/w 0 5 vgsps 1 pci_if ro 0 4 mwi_en 1 pci_if ro 0 3 sc 1 pci_if ro 0 2 bm 1 pci_if ro 0 1 ms 1 pci_if ro 0 0ios1pci_ifro0
green plb 2224 register description data sheet 134 2002-06-03 serr the serr bit signals an address parity error. it is set by cpuif when detected. 0: serr# not asserted 1: serr# asserted. rma the rma bit indicates the receiving of a master abort. this bit is hardwired to 0 since plb 2224 does not detect master abort. rta the rta bit indicates the receiving of a target abort by a pci master. this bit is hardwired to 0 since plb 2224 is not a pci master device. sta this bit is set by cpuif whenever it terminates a transaction with target abort. dev_sel the dev_sel field indicates the slowest time that a device asserts devsel# for any bus command except configuration read and configuration write. it encodes the timing of devsel#. the possible values are 0: fast; 1: medium 2: slow 3: reserved this field is hardwired to 1 for cpuif devsel# timing in plb 2224 is medium. dpd this bit is set when three conditions are met: 1. the bus agent asserted perr# itself (on a read) or observed perr# asserted (on a write), 2. the agent setting the bit acted as the bus master for the operation in which the error occurred, and 3. the parity error response bit (command register) is set. this bit is hardwired to 0 since plb 2224 does not act as a pci master.
green plb 2224 register description data sheet 135 2002-06-03 tfbbc this optional read-only bit indicates whether or not the target is capable of accepting fast back-to-back transactions when the transactions are not to the same agent. 0: plb 2224 does not accept fast back-to-back transactions 1: plb 2224 does accept fast back-to-back transactions. dev66 this optional read-only bit indicates whether or not this device is capable of running at 66 mhz. 0: 33 mhz only 1: 66 mhz capable mfbbc this optional read/write bit controls whether or not a master can do fast back-to-back transactions to different devices. initialization software will set the bit if all targets are fast back-to-back capable. 1. fast back-to-back transactions are only allowed to the same agent. 2. master is allowed to generate fast back-to-back transactions to different agents. this bit is hardwired to 0 as plb 2224 does not work as a pci master. serr_en this bit is enable parity error to be reported on serr# pin. 0: disable the serr# 1: enable the serr# wait this bit controls whether or not a device does address/data stepping. 0: devices that never do stepping. 1: devices that always do. devices that can do either, must make this bit read/write and have it initialize to 1 after reset. this bit is hardwired to 0 in plb 2224 does not support address stepping. peresp this bit enables the device?s response to parity errors. 0: disable parity error reporting 1: enable parity error reporting.
green plb 2224 register description data sheet 136 2002-06-03 devices that check parity must implement this bit. devices are still required to generate parity even if parity checking is disabled. this bit is initialized to 1. vgsps this bit controls how vga compatible and graphics devices handle accesses to vga palette registers. 0: disable palette 1: enable palette snooping is enabled vga compatible devices should implement this bit. this bit is hardwired to 0 since plb 2224 is not a vga device. mwi_en this bit enables memory write and invalidate command. 0: disable memory write and invalidate 1: enable memory write and invalidate this bit is hardwired to 0 since PLB2224 does not support memory write and invalidate command. sc this bit controls a device?s action on special cycle operations. 0: ignore all special cycle operations. 1: monitor special cycle operations. this bit is hardwired to 0 as plb 2224 does not monitor special cycles. bm this bit controls a device?s ability to act as a master on the pci bus. 0: pci target only 1: pci master capable this bit is hardwired to 0 as plb 2224 does not act as a pci master. ms this bit controls a device?s response to memory space accesses. 0: disables memory space access 1: enable memory space accesses. this bit is initialized to 1.
green plb 2224 register description data sheet 137 2002-06-03 ios this bit controls a device?s response to i/o space accesses. 0: disables i/o space access 1: enable i/o space accesses. this bit is initialized to 0 as plb 2224 supports memory space access only. 7.3.3 register 0x08, pci configuration class table 60 register 0x08 pci configuration class description the pci configuration class register is read-only and is used to identify the generic function of the plb 2224 device and, in some cases, a specific register-level programming interface. base_class the base class code classifies the type of function the device performs. this field is hardwired to 0x02 ? network controller. sub_class the sub-class code identifies more specifically the function of the device. this field is hardwired to 0x00 ? ethernet controller. program_if the programming interface identifies a specific register-level (if any) programming interface that device independent software can interact with the device. this field is hardwired to 0x00 ? ethernet controller. revision this register specifies a device specific revision identifier. this is vendor specific. zero is an acceptable value. this field should be viewed as a vendor defined extension to the device id. this field is hardwired to 0x01. bits name length block access default 31:24 base_class 8 pci_if read only 0x02 23:16 sub_class 8 pci_if read only 0x00 15:8 program_if 8 pci_if read only 0x00 7:0 revision 8 pci_if read only 0x01
green plb 2224 register description data sheet 138 2002-06-03 7.3.4 register 0x0c, pci configuration miscellaneous 0 table 61 register 0x0c pci config miscellaneous0 description the pci configuration miscellaneous 0 register is used to identify the device independent features for supporting bist, burst, and multiple functions. bist bist is used for control and status of bist. this field is hardwired to 0x0 since plb 2224 does not support bist. header_type this byte identifies the layout of the second part of the predefined header and also whether or not the device contains multiple functions. bit 7 in this register is used to identify a multi-function device. if the bit is 0, then the device is single function. if the bit is 1, then the device has multiple functions. bits 6 through 0 identify the layout of the second part of the predefined header. the encoding 01 h is defined for pci-to-pci bridges. the encoding 02 h is defined for a cardbus bridge. all other codes are reserved. this field is hardwired to 0x00 to indicate a single function device. ltimer this field specifies the value (in pci clock unit) of the latency timer for a pci bus master. this field is hardwired to 0x0 since plb 2224 does not act as a pci master. cline this read/write field specifies the cache line size in unit of 32-bit words for pci master to use in generating memory write and invalidate commands and to determine whether to bits name length block access default 31:24 bist 8 pci_if ro 0x0 23:16 header_type 8 pci_if ro 0x0 15:8 timer 8 pci_if r/w 0x0 7:0 cline 8 pci_if r/w 0x0
green plb 2224 register description data sheet 139 2002-06-03 use read, read line, or read multiple in accessing memory. this field is hardwired to 0x0 since plb 2224 does not act as a pci master. table 62 register 0x10, pci configuration base address description the pci configuration base address register specifies the pci addresses this plb 2224 recognizes in memory space. base_addr base address is a 24 bit (16 mbytes). the first 8 bits are 0?s. prefetch plb 2224 memory space is not pre-fetchable. this field is hardwired to 0. type pci bus base address type 0: base register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. 1: reserved 2: base register is 64-bits wide and can be mapped anywhere in the 64-bit address space. 3: reserved space pci bus address space bit(s) name length block access default 31:4 base_addr 28 pci_if r/w 0x00 3 prefetch 1 pci_if r 0x00 2:1 type 2 pci_if r 0x00 0 space 1 pci_if r 0x00
green plb 2224 register description data sheet 140 2002-06-03 7.3.5 register 0x3c, pci configuration miscellaneous 1 table 63 register 0x3c, pci configuration miscellaneous 1 description the pci configuration miscellaneous 1 register specifies the pci bus related timing and signals for access, burst, and interrupts. max_lat maximum latency specifies how often the device needs to gain access to the pci bus. this field is hardwired to 0x0 since plb 2224 has no special latency requirements. min_gnt minimum grant specifies how long of a burst period the device needs assuming a clock rate of 33 mhz. this field is hardwired to 0x0 since plb 2224 has no major requirements. int_pin interrupt pin specifies which interrupt pin plb 2224 uses. plb 2224 uses inta# (0x01). int_line interrupt line is used to communicate interrupt line routing information for device driver and operating systems to determine priority and vector information. this field is initialized to 0x0. bits name length block access default 31:24 max_lat 8 pci_if r 0x00 23:16 min_gnt 8 pci_if r 0x00 15:8 int_pin 8 pci_if r 0x01 7:0 int_line 8 pci_if r/w 0x00
green plb 2224 register description data sheet 141 2002-06-03 7.4 PLB2224 internal registers 7.4.1 chip configuration register name : chip_config offset : 0x00 access : read/write description used to store configuration information about the plb 2224 within the system. upon hardware reset, bits [23:0], bits [28:26] and bit[31] will reflect values from the the power strapped led signal pins as indicated in the table. all led signal pins have an internal pullup. table 64 chip configuration register bit fields name access / initial value description in plb 2224 31 intelligent (r/w) x 0 :after reset, plb 2224 is ready to do switching function by enabling all the ports. intended for systems without a cpu. 1 : all the ports stay in disabled mode until cpu enable them. intended for systems used in managed mode of operation. the bit is latched from pin-strapping input pin led_row_n[3] during reset. 30:29 rsv 00
green plb 2224 register description data sheet 142 2002-06-03 28 disable_pause (r/w) x 0 : to enable pause bit in advertisement register during auto-negotiation in full duplex mode of operation. 1 : to disable pause feature for all ports and also not to advertise pause capability during auto-negotiation. the bit is latched from pin-strapping input pin led_row_n[1] during reset. note: for each full duplex ports, 802.3x flow control method will be used depending on pause[1:0] bits from the port?s reg. #4 and #5. for all the half duplex ports, collision method is enabled to control the incoming packet rate depending on whether e_hd_cg_ctl (bit 6 in ?chip configuration register? on page 141 ) is asserted. if disable_pause bit has been set to disable pause in software mode of operation, autonegotiation should be restarted for this to take effect. 27:24 rsv 00 23:22 21:20 19:18 17:16 15:14 13:12 delay_sel5[1:0] delay_sel4[1:0] delay_sel3[1:0] delay_sel2[1:0] delay_sel1[1:0] delay_sel0[1:0] (r/w) x delay_sel[5:0][1:0] is to select the delay for smii_clk input pins, one per 4 smii ports. delay_sel0[1:0] is for port 0 to 3, delay_sel1[1:0] is for port 4 to 7, ?, and delay_sel5[1:0] is for port 20 to 23. each select has two bit to control the delay. the total delay will be the bit value times 0.8 ns at typical case. the bit is latched from power-strapping input pin led_col[23:12] during reset. since plb 2224 has source synchronous smii interface, it is very unlikely that the customer will have to make use of the delay pinstrap to control clock delay please refer to section ?delay select for smii_rclk? on page 50 for more details.
green plb 2224 register description data sheet 143 2002-06-03 11:10 sim_mode[1:0] (r/w) xx should always be set to ?11? for normal operation. note: mode 00, 01, 10 will be used for testing purposes only. the bit is latched from power-strapping input pins led_col[11:10] during reset. 9 in_ma_en (r/w) x to enable the internal ma table. this bit should be strapped to 1. ?0? : disable internal ma table the bit is latched from power-strapping input pin led_col[9] during reset. 8 use_mdio_mode (r/w) x this bit is only valid when e_hw_mode (bit 9 in ?switch configuration register? on page 145 ) bit is 1. 1 : the mdio polling result from each fast ethernet port?s speed capability, pause_e capability, full_duplex capability, and link_ok status is used for operation. 0 : the capabilities of the phy are polled over smii interface and the pause capability in this case cannot be determined, as pause information is not available over smii interface during auto-negotiation. note: this bit has no effect on gb ports. the bit is latched from power-strapping input pin led_col[8] during reset. 7rsv 0 reserved 6 e_hd_cg_ctl (r/w) x 1: enables collision-based flow control for half duplex ports. 0: disables collision-based flow control for half duplex ports. the bit is latched from power-strapping input pin led_col[6] during reset. 5 mask_coll_led (r/w) x 0 : the status led flashes when the corresponding port experiences collision. 1 : disables the flashing of the status led this bit is latched from pin-strapping input pin led_col[5] during reset.
green plb 2224 register description data sheet 144 2002-06-03 7.4.2 chip type register name : chip_type offset : 0x04 access : read only description : used for chip identification. table 65 chip_type register 4 en_tx_led (r/w) x 1 : the link led flashes when the corresponding port has successful transmission. 0 : disable the flashing of the link led this bit is latched from pin-strapping input pin led_col[4] during reset. 3 led_mode (r/w) x to select display mode. this bit is latched from pin-strapping input pin led_col[3] when reset. please refer to section ?led? on page 103 for more details 2:0 pcb_config (r) x plb 2224?s pcb configuration bits which are used to identify how plb 2224 is configured. this is more used for board level identification purposes, where the manufacturer can set these bits to do some specific kind of operation. this bit is latched from pin-strapping input pin led_col[2:0] during reset. bit fields name (access) initial value description 31 mem_test_ done (r) 0 1: indicating memory test is done. 0: indicating memory test is still in progress. 30:12 rsv 0 reserved 11:3 chip_type (r) 9?b000000010 plb 2224 chip type is hardwired internally. 2 is assigned to plb 2224. 2:0 chip_rev (r) 3?b010 plb 2224 chip revision number.
green plb 2224 register description data sheet 145 2002-06-03 7.4.3 switch configuration register name : switch_config offset : 0x08 access : read/write description stores the configuration information for paramaters and are common for all the ports in plb 2224. table 66 switch configuration register bit name (access) initial value description 31 endian_mode (r/w) 1 the endian_mode bit selects the plb 2224 internal operation mode based on cpu?s endian mode. 1 : cpu is running big endian mode and is consistent with plb 2224?s internal packet format. 0 : cpu is running little endian mode. all the packet data to and from cpu requires byte swapping. 30 soft_rst (r/w) 0 1 : to reset all the pointers and state machines, except timer and cpu interface. resets all the cpu registers except chip_config register, and re- initializes all the memories. 0 : to release software reset. the soft_rst bit will not reset itself after set to 1. cpu has to reset it by writing a ?0? to this bit to end the soft reset of plb 2224.
green plb 2224 register description data sheet 146 2002-06-03 29 pri_at_src (r/w) 0 1 : the priority of the received packet is set to high when the corresponding bit of the source port priority register is 1. 0 : the packet?s priority is determined by pri_at_da. when both the pri_at_src and pri_at_da bits are set to ?0?, the packet priority flag is set to low. when both pri_at_src and pri_at_da are ?1? and if either lookup results in high priority, the packet priority is set to high. 28 pri_at_da (r/w) 0 1 : the priority of the received packet is set to high when ?ma_pri? bit of da lookup result is 1.( ma_state[3:0]=4?b001x ) 0 : the packet?s priority is determined by pri_at_src. when both pri_at_src and pri_at_da are set to ?1?, either lookup results in higher priority and the packet priority is set to high when both pri_at_src and pri_at_da bits are ?0?, the packet priority is set to high. if both of them are set, packet?s priority is determined by the or result of both. for auto-learned unicast packets and broadcast packets, priority is always ?0? 27 ma_freeze (r/w) 0 the ma_freeze bit controls the updating of ma entries. 1 : no new ma will be learned and the ma port number won?t be changed. non- critical packets (ma_critical set to 0, new ma, or existing ma with port change) will be discarded. ma ageing function is turned off. 26 ma_freeze_new (r/w) 0 the ma_freeze_new controls the creation of new ma only. if set, only port changes with existing ma entry is allowed. no new ma will be learned. all the non-critical packets (ma_critical set to 0, new ma) will be discarded. ma ageing function is turned off.
green plb 2224 register description data sheet 147 2002-06-03 25:23 aging_tick_sel [2:0] (r/w) 3?b001 aging tick timer is controlled by this field and is defined below. default is to select 3.18 ms per tick to have 300 s tick-time for each entry service. aging_tick_sel tick period entry aging time 000 (always tick) 0 001 tick_time x1 300 s 010 - 20 s 011 tick_time x3 15 minutes 100 tick_time x12 1 hour 101 tick_time x48 4 hours 110 tick_time x288 1 day 111 - no aging 22:20 bandwidth_ratio [2:0] (r/w) 3?b001 this is to select the bandwidth ratio between high and low priority queues. if one of them is idle, the other queue will have the full bandwidth to forward its packets. packet burstness for the same queue is reduced. low queue is served only when there is no high available. bandwidth_ratio[2:0] high_q/low_q ratio 000 16/0 001 15/1 010 14/2 011 13/3 100 12/4 101 11/5 110 10/6 111 8/8 please refer to the section ?packet scheduling? on page 42 for more details on the bandwidth ratio
green plb 2224 register description data sheet 148 2002-06-03 19 e_pkt_pri (r/w) 0 the en_pkt_pri bit enables packet prioritization. there are two tx queues and two broadcast queues for each port. one for high priority and one for low priority. if packet prioritization is enabled, packet?s priority is determined by either pri_by_src or pri_by_da as described above. 0. packet prioritization disabled. 1. packet prioritization is enabled. 18 monitor_pkt_err (r/w) 0 set to monitor all the packets with crc error. default to 0. 17 monitor_pkt_ma _change (r/w) 0 the monitor_pkt_ma_change enables packet monitoring for all the packets with ?intrusion?, ?ma_change?, or ?ma_full?. in an ?intrusion? case, the packet should be forwarded only to monitoring port. in ?ma_change? or ?ma_full? case, the packet is forwarded to destination port and monitoring port. the default is set to 0. 16 fwd_ovsz_pkt (r/w) 1 the fwd_ovsz_pkt controls oversize packet (greater than 1518 bytes) forwarding mechanism. the oversize packet is sent to its destination ports as long as its crc is still good. the default value is set to 1. 15 dis_err_rst (r/w) 0 the dis_err_rst bit controls the error recovery mechanism. 0. enable the fatal error status bits in the switch status register to generate a reset command that will reset the chip. 1. disabled reset when detecting a fatal error. fatal errors happen when src_pid_err exists and their corresponding interrupt_en bit is enabled. the default value is set to 0.
green plb 2224 register description data sheet 149 2002-06-03 14 halt_tx (r/w) 0 the halt_tx bit controls port transmission. when set, all ethernet ports (port 0 to 25) will stop transmitting by ignoring txq?s not_empty status. this bit has no effect on the cpu ports.. default to 0. this is only for chip diagnostic purpose. 13 halt_rx (r/w) 0 the halt_rx bit controls port receiving. when set, all ethernet ports (port 0 to 25) drop the received packets while maintaining the correct counters. this bit has no effect on the cpu ports. default to 0. this is only for chip diagnostic purpose. 12 halt_release (r/w) 0 the halt_release bit controls the releasing of packet buffers after transmission. 0. normal operation. 1. stop releasing or updating ser_cnt after each port?s transmission. default to 0. this is only for chip diagnostic purposes. 11 trunk_on_da (r/w) 0 the trunk_on_da bit controls whether to use da to determine the forwarding trunk port. 0 . da is not used to determine which trunk port to forward packets. 1 . da is used to determine which trunk port to forward packets. if both trunk_on_da and trunk_on_sa are set, both da and sa are used for the trunk port decision. either trunk_da_based or trunk_sa_based should be set. if both are cleared, only one port is used for forwarding in a trunk.
green plb 2224 register description data sheet 150 2002-06-03 10 trunk_on_sa (r/w) 0 the trunk_on_sa bit controls whether to use sa to determine the forwarding trunk port. 0 . sa is not used to determine which trunk port to forward packets. 1. sa is used to determine which trunk port to forward packets. if both trunk_on_da and trunk_on_sa are set, both da and sa are used for the trunk port decision. 9 e_hw_mode 1 the e_hw_mode bit decides whether the autonegotiation results from mdio/smii can be used. 0 : autonegotiation results (speed / pause_e / full_duplex) from either mdio or smii is not used. 1 : enable mdio?s polling result or smii polling results. (ethernet?s speed / pause capability / full_duplex). this bit when set to ?1? is used in conjunction with use_mdio_mode bit in ?chip configuration register? on page 141 . the results are written to port_mii registers described in ?port mii register? on page 157 . 8watermark_ scale r/w 0 0 : watermark scale equal 4, which means the values set in the different watermark registers are multiplied by 4 and used in the application for flow control meachnism 1 : watermark scale equal 1, meaning the register setting is used directly for the flow control
green plb 2224 register description data sheet 151 2002-06-03 7.4.4 switch status and mask register name : switch_status offset : 0x0c access : read/write (in misc/led) description all the bits in this register should be set only one time for each event, and will be cleared after reset or cpu read. bits [31:16] are the interrupt enable bits for the corresponding events indicated in bits [15:0]. the event bits [15:0] in this register are set when the 7 e_ucast_secu 0 the e_ucast_secu bit enables vlan security for unicast packets. 0. disable the security check. 1. enable vlan security vlan security is accomplished by dropping unicast packets if the destination port is not in the same vlan as the one associated with the source port. 6 rx_pause_frame (r/w) 0 the rx_pause_frame bit controls the received pause frames. 0 . discard the received pause frames. 1 . forward the received pause frames like anyother packets. 5 age_tick_softwar e (r/w) 0 set to generate aging tick through software. when cpu sets this bit, aging process is initiated for one hash bucket and the age of the ma table entry in that bucket is incremented. the bit is automatically cleared at this point. typically used in conjunction with the setting the aging_tick_sel[2:0] in ?switch configuration register? on page 145 to 3b?111. 4:0 monitoring_pid[4 :0] r/w 5?b 11111 all the monitored packets will be forwarded to this port corresponding to the value set on monitoring_pid[4:0]
green plb 2224 register description data sheet 152 2002-06-03 corresponding event(s) accur. all the event bits are cleared when the cpu reads the register. the event bits are read only. table 67 switch status and mask register bit fields name (access ) initial value description 31:16 interrupt_en[] all 1?s default to all 1. each interrupt enable bit has a corresponding status bit from bit 15 to 0. all the interrupts are enabled after reset. 15 cpu_txq_avail27 (r) set when cpu?s txq port#27 changes from ?empty? to ?not-empty?, indicating availability of packet for the cpu to read. it is cleared when cpu reads and there is no more entry in txq#27. 14 cpu_txq_avail26 (r) 0 set when cpu?s txq port#26 changes from ?empty? to ?not-empty?, indicating availability of packet for the cpu to read. it is cleared when cpu reads and there is no more entry in txq#26. 13 aged_interrupt (r) 0 occurs whenever there is an aging of an entry in the internal cache or the ma table 12 any_seq_err (r) 0 set when packet sequencing error is detected by tx/pqc. it is cleared when cpu reads the bit. if this bit is set and the corresponding interrupt_en bit set, external interrupt output will be asserted (inta_n). if both bits ( any_seq_err and interrupt_en ) are set and dis_err_rst is 0, the chip reset due to fatal error is activated. 11 src_pid_parity_ err (r) 0 set when src_pid[] from sram is read with parity error by pqc/arl. it is cleared when cpu reads. if this bit is set and the corresponding interrupt_en bit set, external interrupt output will be asserted. if both bits are set and dis_err_rst is 0, the fatal error reset will be activated.
green plb 2224 register description data sheet 153 2002-06-03 10 ma_full 0 set when a new ma cannot find an invalid entry to replace. it is cleared when cpu reads. 9 ma_intrusion 0 set if a received packet meets the following conditions ma_change set, ma_freeze set and the da in the packet is non-critical. it is cleared when cpu reads this bit. for the packet resulting in ma_intrusion condition, should not be forwarded to the destination port. 8 ma_change (r) 0 set when either of the 2 conditions is satisfied 1. a new entry is created in the ma table for a newly learnt sa 2. src_pid associated with the sa has changed. it is cleared when cpu reads this bit. 7 freeq_empty (r) 0 set whenever freeq is empty i,e there are no more buffers available to store an incoming packet. it is cleared when cpu reads this bit and freeq is not empty. 6 any_txdq_full (r) 0 set whn txq for any port including cpu?s becomes full (when the queue hits the largest (final) watermark). it is cleared when cpu reads this bit. 5 any_rxdq_cg_ctl (r) 0 set when a 10/100 ethernet port operating in half duplex mode goes into congestion state. it is cleared when cpu reads this bit. 4 any_rxdq_full_ drop (r) 0 set when an incoming packet is dropped because the rxq on that port is full.( when the queue hits the largest (final) watermark). it is cleared when cpu reads this bit. 3 any_crc_error (r) 0 set when any of ethernet ports receives a new packet with crc error. it is cleared when cpu reads this bit.
green plb 2224 register description data sheet 154 2002-06-03 7.4.5 port status register name : port_status offset : 0x10-1c access : read only (in rtx) description stores the status information for the ethernet ports. each of 26 ports has a corresponding bit. all the status bits will be cleared after reset or after cpu read. in all the registers described below bit0 is for port0, bit1 for port1 etc. table 68 port status register 2 any_fifo_run (r) 0 set when any of the ethernet ports experiences rx fifo overrun or tx fifo underrun. it is cleared when cpu reads this bit. 1 any_late_ collision (r) 0 set when a 10/100 ethernet port operating in half duplex mode experiences a late collision 0 any_link_ok_ change (r) 0 set when link_ok state of a port changes from either 1 => 0 or 0 => 1 bit fields name (access ) initial value description 25:0 0x1c rxdq_full_drop (r) 0 set if a new received packet is dropped because rxq is full. if any bit in this register is being set, the bit any_rxdq_full_drop in the ?switch status and mask register? on page 152 is set. 25:0 0x18 crc_err (r) 0 set if a crc error is detected on a received packet with length >= 64. if any of the bits in this register is set, then if a crc error is detected, any_crc_err bit in the ?switch status and mask register? on page 152 is set.
green plb 2224 register description data sheet 155 2002-06-03 7.4.6 port event register name : port_event offset : 0x20-24 access : read/write description stores information about certain events for the ethernet ports. each of the ethernet ports have a corresponding bit. all the status bits are cleared when the cpu reads the corresponding register. table 69 port event register 7.4.7 port underrun/overrun register name : port_run offset : 0x28-2c access :read 25:0 0x14 late_collision (r) 0 set if late collision is detected. cleared by reset or cpu read. if any bit in this register is being set, then any_late_collision bit in the ?switch status and mask register? on page 152 is set. 25:0 0x10 port_active (r) 0 set when txe or crs of the corresponding port is changing to be active. bit fields name (access) initial value description 25:0 0x24 txdq_full (r) 0 set as long as the port?s txq is full. it is cleared by reset or cpu read if the txq for that port is no longer full. 25:0 0x20 port_critical_ event (r) 0 set when either ma_change , ma_intrusion or ovz_pkt event occurs. ( ovz_pkt event occurs when an oversize packet > 1518 bytes is received) it is cleared when the cpu reads the register
green plb 2224 register description data sheet 156 2002-06-03 description stores the information related to the rx and tx fifo?s for the ethernet ports. each of the ethernet ports have a corresponding bit. all the status bits are cleared when the cpu reads the corresponding register. table 70 port underrun/overrun register 7.4.8 port mii register name : port_mii offset : 0x30-3c access : read/write description the values in these registers determine the link operating parameters when the e_hw_mode bit in ?switch configuration register? on page 145 is ?0?. otherwise the operationg parameters depend on the values read from the phy using the mdio interface ( use_mdio_mode bit in chip configuration register set to ?1?) or using the values obtained from the smii interface ( use_mdio_mode bit in ?chip configuration register? on page 141 is cleared to ?0?). for gigbit ports the use_mdio_bit is ignored and the values are always read from the mdio interface. bit fields name (access) initial value description 25:0 0x2c tx_fifo_underrun (r) 0 set if tx fifo experienced an underrun. if any bit in this register is set, the any_fifo_run bit in the switch status and interrupt mask register is set. this bit is cleared by reset or cpu read. 25:0 0x28 rx_fifo_overrun (r) 0 set if rx fifo experienced overrun. if any bit in this register is set, the any_fifo_run bit in the switch status and interrupt mask register is set. this bit is cleared by reset or cpu read.
green plb 2224 register description data sheet 157 2002-06-03 when these registers are read by the cpu, the values that are read are the ones collected from the phy devices, either from the mdio or smii interface. table 71 port mii register 7.4.9 port monitor register name : port_monitor offset : 0x40 access : read/write bit fields/ address name (access) initial value description 23:0 0x3c speed_cpu[] (r/w) 1 1: fe port is running at 100 mbit/s/ and gbit port at 1 gbit/s. 0: fe port is at 10 mbit/s and gbit port at 100 mbit/s. 23:0 0x38 pause_e_cpu[] (r/w) 0 set to enable full-duplex flow control using pause frames. pause_e_cpu enforces the flow control specified in 802.3x. as this information is not available on the smii interface, this register also governs enabling full duplex flow control when e_hw_mode = 1 and use_mdio_mode = 0 1: pause frame is enabled for pause frame control. 0: pause frame is disabled for pause frame control. 23:0 0x34 full_duplex_cpu[] (r/w) 0 1: 10/100 ports is in full duplex mode. 0: 10/100 ports is in half duplex. 23:0 0x30 link_ok cpu[] (r/w) 1 1: ethernet port has link ok status (operational state). 0: ehternet port?s link failed.
green plb 2224 register description data sheet 158 2002-06-03 description specifies if the packets received at or transmitted from these ports are to be monitored, i.e. forwarded to the monitoring port. any packets from or to the ports with the ? monitored ? bit set, the packet is also forwarded to the monitoring port. table 72 port monitor register 7.4.10 port priority register name : port_priority offset : 0x44 access : read/write description the packet from the port or to the port will be forwarded to high priority queue if the corresponding priority bit ( pri_at_src bit in ?switch configuration register? on page 145 ) is set. please also reference to pri_at_src and pri_at_da in the switch_config register. table 73 port priority register 7.4.11 port trunk register name : port_trunk offset : 0x48-4c bit fields name (access) initial value description 31:27 rsv 0 reserved 26:0 monitored[] (r/w) 0 0 = not monitored. 1 = port needs to be monitored. default value is 0. bit 0 is for port 0, and bit 26 is for cpu port 0. bit fields name (access) initial value description 31:27 rsv 0 reserved 26:0 priority[] (r/w) 0 set to ?1? for high priority set to ?0? for low priority bit 0 is for port 0, and bit 26 is for cpu ports.
green plb 2224 register description data sheet 159 2002-06-03 access : read/write description 2, 4 or 8 ports can be assigned to a trunk group for 10/100 mbit/s ports, and 2-gbit ports can be grouped into a trunk group. only the adjacent ports with higher port_id [] bits equal can be formed for a trunk group. for example, for a 4 port option, only ports 0 to 3, ports 4 to 7, or ports 20 to 23 can be in a trunk group. all the trunk ports should share the traffic as a single logic port. if any of the ports is disabled or link failure, the other ports will assume the traffic. table 74 port trunk register 7.4.12 port bridge state register name : port_bridge_state offset : 0x50-0x54 access : read/write bit fields name (access) initial value description 31:17 rsv 0 reserved 16 0x4c trunk_opt (r/w) 0 if 1, two gbit ports are in a trunk. if 0, there is no trunk for gbit ports. 15:0 0x4c trunk_opt (r/w) 0 each port has two bits for trunk option. bit 1:0 is for port 16, bit 3:2 is for port 17, ? and bit 15:14 is for port 23. the number of total ports in each trunk is same as those in ports 0 to 15. 31:0 0x48 trunk_opt (r/w) 0 each port has two bits for trunk option. bit 1:0 is for port 0, bit 3:2 is for port 1, ? and bit 31:30 is for port 15. the number of total ports in each trunk is defined below. note: all the ports in the same trunk should have identical trunk_opt[]. value membership 00 not a member of any trunk 01 member of a 2-port trunk 10 member of 4 port trunk 11 member of 8 port trunk
green plb 2224 register description data sheet 160 2002-06-03 description the port bridge state register specifies the forwarding state of each port as per the 802.1d specification. table 75 port bridge state register 7.4.13 portlist_1023 register name : port_list1023 bit fields offset name (access) initial value description 31:24 0x54 rsv 0 reserved 23:20 0x54 bridge_state[1:0] for each cpu port. (port 26 and 27) (2-bits per port) (r/w) 0 00 = disable, 01 = listening, 10 = learning, 11 = forwarding. cleared to 00 after reset. cpu port?s bridge_state[] stays at 00 until cpu updates them. 19:0 0x54 bridge_state[1:0] for port 25 to 16 (2-bits per port) (r/w) 0 00 = disable, 01 = listening, 10 = learning, 11 = forwarding. clear to 00 after reset. bit 1 and 0 are for port 16, bit 19 and 18 are for port 25. same definition as port 15 to 0. 31:0 0x50 bridge_state[1:0] for port 15 to 0 (2-bits per port) (r/w) 0 00 = disable, 01 = listening, 10 = learning, 11 = forwarding. clear to 00 after reset. bit 1 and 0 are for port 0, bit 31 and 30 are for port 15. at the end of the initialisation sequqnce, bridge_state[] is set to ?11? (forwarding state) when the intelligent bit in ?chip configuration register? on page 141 is ?0?, otherwise it stays at ?00? and must be configured by the cpu.
green plb 2224 register description data sheet 161 2002-06-03 offset : 0x58 access : read/write description sepcifies the destination port list for the index 10?b1111111111. usually, index is used to find the destination port list from floodmap. however, if index is equal to 1023, it will find out the port list from portlist_1023 register instead of floodmap. table 76 portlist_1023 register 7.4.14 port index register_20_0 name : port_ix offset : 0x60-78 access : read/write description the index number is defined for each of the ports. each index is 10-bits wide and is shown at the respective bit positions for the different ports. the index value is used to lookup the destination ports belonging to the source ports vlan. the number based on source port will be used to lookup floodmap for the destination port list when a non- unicast packet is received. all the data are initialized to all 1?s. for ports 21 to 26, the port index registers can be found in ?port index register 26_21? on page 184 table 77 port index register_20_0 bit fields name (access) initial value description 31:28 rsv 0 reserved 27:26 portlist (r/w) all 0?s cpu ports with the corresponding bit set will be one of the destinations for index 1023. default to all 0?s. 25:0 portlist (r/w) all 1?s ports with the corresponding bit set will be one of the destinations for index 1023. bit fields name initial value offset description 31:30 rsv 00 reserved 29:20 port20_ix[] all 1?s 0x78 index value for port 20
green plb 2224 register description data sheet 162 2002-06-03 7.4.15 da index register name : da_index offset : 0x7c access : read/write 19:10 port19_ix[] all 1?s 0x78 index value for port 19 9:0 port18_ix[] all 1?s 0x78 index value for port 18 31:30 rsv 00 reserved 29:20 port17_ix[] all 1?s 0x74 index value for port 17 19:10 port16_ix[] all 1?s 0x74 index value for port 16 9:0 port15_ix[] all 1?s 0x74 index value for port 15 31:30 rsv 00 reserved 29:20 port14_ix[] all 1?s 0x70 index value for port 14 19:10 port13_ix[] all 1?s 0x70 index value for port 13 9:0 port12_ix[] all 1?s 0x70 index value for port 12 31:30 rsv 00 reserved 29:20 port11_ix[] all 1?s 0x6c index value for port 11 19:10 port10_ix[] all 1?s 0x6c index value for port 10 9:0 port9_ix[] all 1?s 0x6c index value for port 9 31:30 rsv 00 reserved 29:20 port8_ix[] all 1?s 0x68 index value for port 8 19:10 port7_ix[] all 1?s 0x68 index value for port 7 9:0 port6_ix[] all 1?s 0x68 index value for port 6 31:30 rsv 00 reserved 29:20 port5_ix[] all 1?s 0x64 index value for port 5 19:10 port4_ix[] all 1?s 0x64 index value for port 4 9:0 port3_ix[] all 1?s 0x64 index value for port 3 31:30 rsv 00 reserved 29:20 port2_ix[] all 1?s 0x60 index value for port 2 19:10 port1_ix[] all 1?s 0x60 index value for port 1 9:0 port0_ix[] all 1?s 0x60 index value for port 0
green plb 2224 register description data sheet 163 2002-06-03 description used to specify the destination port list for the flooding the packet when the da is either unknown multicast, an unknown unicast or broadcast. each index is 10-bit wide, and it will be used to find the destination port list from floodmap. bit 23, 15, and 7 are reserved bits. table 78 da index register 7.4.16 memory upper address register name : mem_u_addr offset : 0x80 access : read/write description this register is used to store the upper address of the memory. it should be combined with the lower bits in mem_access register to have the complete address offset. the final memory address for each access is concatenated from mem_addr[20:11] from mem_u_addr register and mem_addr[10:1] from mem_access register. table 79 memory upper address register bit fields name (access) initial value description 31:30 rsv 0 reserved 29:20 unknown_flood_ ix (r/w) all 1?s this index is used when the da is a multicast (i.e. bit 40 equal to 1) and is not found in ma table. 19:10 unknown_ucast_ ix (r/w) all 1?s this index is used when the da is an unicast (i.e. bit 40 equal to 0) and is not found in ma table. 9:0 bcast_ix (r/w) all 1?s this index is used when da?s bytes are equal to all 1?s. bits field name initial value description 31:25 rsv 0 reserved
green plb 2224 register description data sheet 164 2002-06-03 the description of the blk_sel_msb[3:0] bits is given below: the value of this filed indicates which memory will be accessed for cpu to read or write mem_access register. 0 - 1: to select edram block #0 to #1 , respectively. this area is for diagnostic purpose only. 2 - 7: reserved . 8: to select the memory for mib counters . mem_addr[20:13] is ignored. each counter has a unique address defined in mem_addr[12:2]. mem_addr[12:2] consists {rx_cnt_sel, ?0?, port_id[4:0], item_num[3:0]} . rx_cnt_sel = 1 for accessing receive mib counter, and rx_cnt_sel = 0 for accessing the mib transmit counters. port_id[] is the logical port number for each ethernet port or cpu port. and item_num[] is defined in network management section, which helps in determining the offset for each counter (offset = 4 * item_num). 9: to select the memory for arl data base . mem_addr[19:18] is used to select one of the memories mem_addr[19:18] = 00 : to select ssram 20 k x 32 (used only for diagnostics purposes) mem_addr[19:18] = 01 : to select internal small arl cache (used only for diagnostics purposes) 24:21 blk_sel_msb [3:0] (r/w) x the value of this field indicates which memory will be accessed for cpu to read or write mem_access register. the definition of memory access is described below: 0 - 1: to select edram block #0 to #1 , respectively. 2 - 7: reserved . 8: to select the memory for mib counters . 9: to select the memory for arl data base . 10: to select the memory for pqc link list or queues . 11:15: reserved . 20:11 mem_addr [20:11] (r/w) x higher order address bits (upper address of memory access). the definition of each access is described in blk_sel_msb[] field above. 10:0 rsv 0 reserved
green plb 2224 register description data sheet 165 2002-06-03 mem_addr[19:18] = 10 : to select vlan ix table 4 k x 10 mem_addr[19:18] = 11 :to select vlan table 1 k x 40 10: to select the memory for pqc link list or queues . mem_addr[17:15] is used to select one of the memory inside pqc. mem_addr[17:15] = 000: to select pbl memory in external ssram mem_addr[17:15] = 001: to select internal floodmap mem_addr[17:15] = 010 ? 011: reserved mem_addr[17:15] = 100 ? 111: to select bcastq0 to bcastq3 respectively these area except floodmap are for diagnostic purpose only. 11:15: reserved . 7.4.17 memory access register name : mem_access offset : 0x84 access : read/write description after cpu writes this register, a memory access state machine, either read or write process, will be activated. this register is used for all the device access including all the memories, and external mii?s phy register. each access can only be 16-bits. for 32-bits memory data, it is in little endian format. so, the first two bytes are from bit?s[15:0] and the second two bytes of data with mem_addr [1] equal to 1 are from bit?s[31:16]. table 80 memory access register bits field name access / initial value description 31 access_rdy (r/w) 0 when reading data, this bit indicates that the data is available for the cpu to read. when writing data, this bit indicates that previous write operation is complete and the cpu can write to this register. cpu should clear this bit by writing to ?0? before initiating a read or write operation 30 wr (r/w) 0 this bit is set by cpu to initiate a write operation. 29 rd (r/w) 0 this bit is set by cpu to initiate a read operation.
green plb 2224 register description data sheet 166 2002-06-03 mem_addr[10:1] memory access lower address bits. for each memory write access, 2-bytes per access will be temporarily stored into a 16- byte register with the offset given by mem_addr[3:1]. the real memory transfer operation won?t start until mem_addr[3:1] stands for the last access, i.e. equal to ?e?. access_rdy bit won?t be set until the receiving memory has acknowledged. for each 16-bytes of memory write, there are eight write?s for this register and the value for bit?s[3:1] for the first write is 0. after receiving the eighth write with mem_addr[3:0] equal to ?e?, the memory operation starts. for a 16-bytes of read, plb 2224 issues a command to request for 16-bytes of data from memory after receiving a read command with mem_addr[3:1] equal to 0. cpu then polls this register for mem_data[] until access_rdy is asserted. after detecting access_rdy , cpu reads the first two bytes. it continues to issue the read command with mem_addr[3:1] as a continuous offset, and then polls for access_rdy after which mem_data[] is valid. during the subsequent polling, access_rdy should be always ready because all the 16-bytes of the data are ready when the command with mem_addr[3:1] equal to 0. for mii?s phy access, each read or write command is to access 2-bytes of data. for each write command, the state machine starts to write mem_data[] onto the external device. for each read command, the state machine starts to get the data onto mem_data[]. access_rdy is asserted when the read or write command is completed. for mii?s phy register access, mem_addr[10:6] is for phy device id and mem_addr[5:1] is for phy?s internal register address. details on indirect memory accesses can be found in ?indirect access to the memories? on page 62 28:27 mem_sel (r/w) 00 00 to select mii?s phy. 01 ? reserved. 10 ? reserved. 11 for memory access. upper address bits are needed. refer to memory upper address register for them. 26 reserved 0 reserved 25:16 mem_addr [10:1] (r/w) x the description of this field is given below the table. 15:0 mem_data [15:0] (r/w) x write data for write command, and read data for read command.
green plb 2224 register description data sheet 167 2002-06-03 7.4.18 cmac data register name : cmac_data offset : 0x90-0x9c access : r/w description when this register is written using any of the four addresses, the data is pushed into cpu rx fifo. when this register is read using any of the four addresses, the data is popped from cpu tx fifo. table 81 cmac data register 7.4.19 cmac rx register name : cmac_rx offset : 0xa0 access : r/w description used by the cpu to send packet parameters to plb 2224 table 82 cmac rx register bit fields name initial value description 31:0 cmac_data x cmac data register. data[31:0] for cpu rx fifo or from cpu tx fifo. bit fields name access/initial value description 31 crx_cpu_pktid_ rdy (r) 0 1: indicates that cmac rx. is ready to accept a new packet from the cpu. this bit should be cleared before cpu writes the last byte of data. 30 crx_cpu_fifo_rdy (r) 0 1: indicating cmac rx is ready for cpu to write at least 16 bytes of data. 29:26 rsv 0 reserved
green plb 2224 register description data sheet 168 2002-06-03 25:16 filter_match26 [9:0] (r) x matching status for filtering patterns for each packet being forwarded to port 26, i.e. cpu port. bit 9 indicates whether all the patterns in group #3 have been matched. similarly, bit 8 is for group #2. bit #7 to #4 are the matching results, respectively, for the four patterns #7 to #4 being defined within group#1. similarly, bit #3 to #0 are for group#0. the field and pbh26[] are valid when cpu_txq_rd_req[26] in cmac_tx0 is cleared. 15:7 rsv 0 reserved 6 e_cpu_pkt_ padding (w/r) 0 1: crx to append the packet to packet length to 64-bytes if less. 0: no padding for small size packet. 5 crx_crc_gen (w/r) 0 indicates whether the packet data excludes crc status. usually, it is 1 for the packets from cpu port, and destination port?s tx will append crc bytes at the end of packet data. 4 crx_crc_err (w/r) 0 indicates the crc error status for the current packet. this is generally 0 for packets received from the cpu port. 3 crx_sof (w/r) 0 indicates that the next data write is the first chunk of the newpacket. this bit is always cleared when packet data is written. 2 crx_eof (w/r) 0 indicates that the next data write is the last chunk of data for the current packet. this bit should be set before the last data is written. 1:0 crx_bytecnt[1:0] (w/r) 00 indicates the number of data bytes to be written. this field should be set correctly before the last data write. 00 = 4-bytes to be written 01 = 3-bytes to be written 10 = 3-bytes to be written 11 = 1-byte to be written
green plb 2224 register description data sheet 169 2002-06-03 7.4.20 cmac tx register name : cmac_tx0 offset : 0xa4 access : r/w description stores the packet buffer header for the current packet available in the tx queue for port 26 (cpu port0), as well as some other flags required for the transmit function for both ports 26 and 27 i.e. cpu port0, cpu port1. table 83 cmac tx register 7.4.21 cmac_tx1 name : cmac_tx1 offset : 0xa8 access : r bit fields name access/initial value description 31:30 ctx_txq_avail [27:26] (r) 0 1: indicates one packet being received from ethernet ports is ready for cpu to process. there are two bits for two cpu logical ports. 29 ctx_cpu_fifo_rdy [27:26] (r) 0 1: ctx has at least 16 bytes or eof bytes ready for cpu to read. 0: ctx has no data available for cpu to read which ctx port was selected depends on cpu_txq_rd_req bit setting 28:24 rsv 23:22 cpu_txq_rd_req [27:26] (r/w) 0 set by cpu to collect the packet data from one of cpu?s ports. it is cleared when pbh[] for the corresponding port is read from sram. 21 ctx_flush (r/w) 0 the current processing packet data in ctx will be flushed when this bit toggles from 0 to 1. 20:0 pbh26[20:0] (r) 0 current pbh[] data for port 26.
green plb 2224 register description data sheet 170 2002-06-03 description stores the packet buffer header for the current packet available in the tx queue for port 27 (cpu port 1) table 84 cmac_tx1 register 7.4.22 arl register name : arl offset : 0xac access : r/w description this register is only for the packets being received from port 26 or cpu port 0. table 85 arl register bit fields name access/initial value description 31:22 filter_match27 [9:0] (r) similar to filter_match26[] above, matching status for filtering patterns for each packet being forwarded to port 27, i.e. cpu port. the field and pbh27[] are valid when cpu_txq_rd_req[27] in cmac_tx0 is cleared. 21 rsv 0 reserved 20:0 pbh27[20:0] (r) 0 current pbh[] data for port 27. bit fields name access/initial value description 31 e_da_lookup (r/w) 0 when set to 1, the arl does normal da lookup from the ma table for destination information. when cleared to 0, arl does not do normal da lookup; instead it uses dst_ports , dst_critical and dst_pri as the result of the lookup.
green plb 2224 register description data sheet 171 2002-06-03 30 e_ma_learn (r/w) 0 when set to 1, the arl creates or updates the ma table entries using the sa contained in the received packet, and the values of the ma_ports , ma_locked, ma_critical, and ma_pri fields in this register. if ma_locked = 0 , the ma_state is set to 3?b100. if ma_delete = 1, the matched ma table is deleted. when e_ma_learn = 0: arl does not perform address learning on packets received from the cpu port. 29 dst_critical (r/w) 0 used as the lookup result if e_da_lookup is not asserted. this bit is ignored if e_da_lookup is 1. 28 dst_pri (r/w) 0 used as the lookup result if e_da_lookup is not asserted. this bit is ignored if e_da_lookup is 1. 27 ma_delete (r/w) 0 when set to 1, the matched entry in the ma table is deleted if e_ma_learn = 1. this bit is ignored if e_ma_learn = 0. 26 ma_locked (r/w) 0 used as the learned ma entry?s attribute ? ma_locked ? if e_ma_learn is asserted. this bit is ignored if e_ma_learn is 0. 25 ma_critical (r/w) 0 used as the learned ma entry?s attribute ? ma_critical? if e_ma_learn is asserted. this bit is ignored if e_ma_learn is 0. 24 ma_pri (r/w) 0 used as the learned ma entry?s attribute ? ma_pri ? if e_ma_learn is asserted. this bit is ignored if e_ma_learn is 0. 23:22 rsv 0 reserved
green plb 2224 register description data sheet 172 2002-06-03 7.4.23 freeq register name : freeq_ptr offset : 0xb0 access : read only description for test purposes only. this is used to access read and write pointers for the free packet buffer pool. table 86 freeq register 21:11 dst_ports [10:0] (r/w) 0 used as the lookup result as the destination port information ( either as port id or index into the vlan table, depending on whether the sa is unicast or multicast address) bit 21 if set to ?0? then dst_ports[9:0] is for port_index and if bit 21 is set to a ?1? then dst_ports[9:0] correspond to flood_ix. this field is ignored if e_da_lookup is 1. 10:0 ma_ports [10:0] (r/w) 0 used as the destination port attribute (either as port_id or index into the vlan table, depending on whether the sa is unicast or multicast address) for creating ma table entry when e_ma_learn = 1. this field is ignored if e_ma_learn is ?0?. bit fields name (access) initial value description 31:29 rsv 0 reserved 28:16 freeq_wptr (r) 0 the current freeq write pointer. (used for test purposes only) 15:13 rsv 0 reserved 12:0 freeq_rptr (r) 0 the current freeq read pointer. (used for test purposes only)
green plb 2224 register description data sheet 173 2002-06-03 7.4.24 freeq_cnt name : freeq_cnt offset : 0xb4 access : read only description for test purposes only. this contains the count of buffers currently available in the free packet buffer pool. table 87 freeq_cnt 7.4.25 cpu_txq26 count register name : cpu_txq26 offset : 0xb8 access : read only description maintains the count for the packets in the high and low priority tx. queues for port 26 i.e. cpu port 0 table 88 cpu txq26 count register bit fields name access/initial value description 31:12 rsv 0 reserved 11:0 freeq_cnt [11:0] (r) 0 the current available pb count in freeq. bit fields name access/initial value description 31:29 rsv 0 reserved 28:16 cpuq_cnt_h26 (r) 0 current txq count for cpu port 26 in high priority 15:13 rsv 0 reserved 12:0 cpuq_cnt_l26 (r) 0 current txq count for cpu port 26 in low priority
green plb 2224 register description data sheet 174 2002-06-03 7.4.26 cpu_txq27 name : cpu_txq27 offset : 0xbc access : read only description maintains the count for the packets in the high and low priority tx. queues for port 27. i.e. cpu port 1 table 89 cpu_txq27 register 7.4.27 cpu water mark register name : cpu_wm_cnt offset : 0xc0 access : r/w (pqc) description water mark registers are to specify the limit on the receiving queue and transmit queue for each ports and helps in the flow control. these count limits are for each port to compare its own resource usage not to exceed the limit. the watermark register values can be multiplied by 4 or 1, depending on the watermark_scale bit setted in switch_config register. by default the value is set to a scaling of 4 for the watermark register value vs. the limit on the receiving queue / transmit queue. bit fields name access/initial value description 31:29 rsv 0 reserved 28:16 cpuq_cnt_h27 (r) 0 current txq count for cpu port 27 in high priority 15:13 rsv 0 reserved 12:0 cpuq_cnt_l27 (r) 0 current txq count for cpu port 27 in low priority
green plb 2224 register description data sheet 175 2002-06-03 table 90 cpu water mark register 7.4.28 fe watermark control (tx) name : fe_wm_cnt0 (fe tx watemark control) offset : 0xc4 access : r/w (pqc) bit fields name (access) initial value description 31:24 rsv 0 reserved 23:16 ctx_cnt_3[7:0] (r/w) 0x28 the ctx_cnt_3 field is the turn-off watermark for the cpu port. the ctx_cnt_3 is the cutoff threshold for the cpu port to not accept any packet if either the low or high priority packet counts rise to the value of ctx_cnt_3. 15:8 ctx_cnt_2[7:0] (r/w) 0x20 the ctx_cnt_2 field is the critical packet watermark for the cpu port. the ctx_cnt_2 is the threshold for dropping non-critical packets when packet count rises. the cpu port accepts only critical packets when either low or high priority packet counts rises to the value of ctx_cnt_2. the ctx_cnt_2 is the threshold for accepting critical packets only when packet count drops. when both low and high priority packet counts drop below ctx_cnt_2 (inclusive), the cpu port starts accepting critical packets. 7:0 ctx_cnt_1[7:0] pqc (r/w) 0x18 the ctx_cnt_1 field is the non-critical packet watermark for the cpu port. the ctx_cnt_1 is the threshold for accepting non-critical packets (in addition to the critical packets) when both low and high priority packet counts drop below ctx_cnt_1 (inclusive) from above.
green plb 2224 register description data sheet 176 2002-06-03 description the watermark registers specify the limit on the receiving queue and transmit queue for each ports. these count limits are for each port to compare its own resource usage not to exceed the limit. while comparing, bits 3 to 0 of each counter are ignored. used for the flow control and can be scaled depending on the watermark_scale bit. table 91 fe tx watermark control register 7.4.29 fe watermark control (rx) name : fe_wm_cnt1 (fe rx watermark control) bit fields name (access) initial value description 31:24 rsv 0 reserved 23:16 tx_cnt_3[7:0] (r/w) 0x28 the tx_cnt_3 field is the turn-off watermark for the fe port. the tx_cnt_3 is the cutoff threshold for the fe port to not accept any packet if either low or high priority packet counts rise to the value of tx_cnt_3. 15:8 tx_cnt_2 [7:0] (r/w) 0x20 the tx_cnt_2 field is the critical packet watermark for the fe port. the tx_cnt_2 is the threshold for dropping non-critical packets when packet count rises. fe port accepts only critical packets when either low or high priority packet counts rises to the value of ctx_cnt_2. the tx_cnt_2 is the threshold for accepting critical packets only when packet count drops. when both low and high priority packet counts drop below tx_cnt_2 (inclusive), fe port starts accepting critical packets. 7:0 tx_cnt_1 [7:0] (r/w) 0x18 the tx_cnt_1 field is the non-critical packet watermark for the fe port. the tx_cnt_1 is the threshold for accepting non-critical packets (in addition to the critical packets) when both low and high priority packet counts drop below tx_cnt_1 (inclusive) from above.
green plb 2224 register description data sheet 177 2002-06-03 offset : 0xc8 access :r/w (pqc) description maintains watermark values for rx queues for the 10/100 ports. used for the flow control and can be scaled depending on the watermark_scale bit. table 92 fe rx watermark control register bit fields name (access) initial value description 31:24 rx_cnt_4 [7:0] (r/w) 0x12 the rx_cnt_4 field is the turn-off watermark for the fe port. the rx_cnt_4 is the cutoff threshold for the fe port to not accept any packet if packet counts rise to the value of rx_cnt_4. 23:16 rx_cnt_3 [7:0] (r/w) 0x10 the rx_cnt_3 field is the critical packet watermark for the fe port. the rx_cnt_3 is the threshold for dropping non-critical packets when packet count rises. the fe port accepts only critical packets when packet counts rises to the value of rx_cnt_3. the rx_cnt_3 is the threshold for accepting critical packets only when packet count drops. when packet counts drop below rx_cnt_3 (inclusive), fe port starts accepting critical packets.
green plb 2224 register description data sheet 178 2002-06-03 7.4.30 gport watermark control (tx) name: ge_wm_cnt0 (gport tx watermark control) offset : 0xcc access : r/w (pqc) description maintains watermark values for tx queues for the gigabit ports. used for the flow control and can be scaled depending on the watermark_scale bit. table 93 gport tx watermark control register 15:8 rx_cnt_2 [7:0] (r/w) 0x0c the rx_cnt_2 field is the flow control on watermark for the fe port. the rx_cnt_2 is the threshold for starting flow control when packet count rises. the fe port sends a pause frame with ?0xffff? when packet counts rises to the value of rx_cnt_2. the rx_cnt_2 is the threshold for accepting non-critical packets when packet counts drops. when packet counts drop below rx_cnt_2 (inclusive), fe port starts accepting non-critical packets. 7:0 rx_cnt_1 [7:0] (r/w) 0x08 the rx_cnt_1 field is the flow control off watermark for the fe port. the rx_cnt_1 is the threshold for end of flow control when both packet counts drop below rx_cnt_1 (inclusive) from above. the fe port sends a pause frame with ?0x0? when packet counts drop below rx_cnt_1. bit fields name (access) initial value description 31:24 rsv 0 reserved 23:16 gtx_cnt_3 [7:0] (r/w) 0x90 the gtx_cnt_3 field is the turn-off watermark for the gigabit port. the gtx_cnt_3 is the cutoff threshold for the gigabit port to not accept any packet if either low or high priority packet counts rise to the value of gtx_cnt_3.
green plb 2224 register description data sheet 179 2002-06-03 7.4.31 gport watermark control (rx) name : ge_wm_cnt1 (gport rx watermark control register) offset : 0xd0 access : r/w (pqc) description maintains watermark values for rx queues for the gigabit ports. used for the flow control and can be scaled depending on the watermark_scale bit. table 94 gport rx watermark control register 15:8 gtx_cnt_2 [7:0] (r/w) 0x80 the gtx_cnt_2 field is the critical packet watermark for the gigabit port. the gtx_cnt_2 is the threshold for dropping non-critical packets when packet count rises. the gigabit port accepts only critical packets when either low or high priority packet counts rises to the value of gtx_cnt_2. the gtx_cnt_2 is the threshold for accepting critical packets only when packet count drops. when both low and high priority packet counts drop below gtx_cnt_2 (inclusive), the gigabit port starts accepting critical packets. 7:0 gtx_cnt_1 [7:0] (r/w) 0x70 the gtx_cnt_1 field is the non-critical packet watermark for the gigabit port. the gtx_cnt_1 is the threshold for accepting non-critical packets (in addition to the critical packets) when both low and high priority packet counts drop below gtx_cnt_1 (inclusive) from above. bit fields name access/initial value description 31:24 grx_cnt_4[7:0] (r/w) 0x8c the grx_cnt_4 field is the turn-off watermark for the gigabit port. the grx_cnt_4 is the cutoff threshold for the fe port to not accept any packet if packet counts rise to grx_cnt_4.
green plb 2224 register description data sheet 180 2002-06-03 7.4.32 tag priority table name : tag_pri_table offset : 0xd4 access : read/write 23:16 grx_cnt_3 [7:0] (r/w) 0x70 the grx_cnt_3 field is the critical packet watermark for the gigabit port. the grx_cnt_3 is the threshold for dropping non-critical packets when packet count rises. the gigabit port accepts only critical packets when packet counts rises to the value of grx_cnt_3. the grx_cnt_3 is the threshold for accepting critical packets only when packet count drops. when packet counts drop below grx_cnt_3 (inclusive), the gigabit port starts accepting critical packets. 15:8 grx_cnt_2 [7:0] (r/w) 0x64 the grx_cnt_2 field is the flow control on watermark for the gigabit port. the grx_cnt_2 is the threshold for starting flow control when packet count rises. the gigabit port sends a pause frame with ?0xffff? when packet counts rises to the value of grx_cnt_2. the grx_cnt_2 is the threshold for accepting non-critical packets when packet counts drops. when packet counts drop below grx_cnt_2 (inclusive), the gigabit port starts accepting non- critical packets. 7:0 grx_cnt_1 [7:0] (r/w) 0x48 the grx_cnt_1 field is the flow control off watermark for the gigabit port. the grx_cnt_1 is the threshold for end of flow control when both packet counts drop below grx_cnt_1 (inclusive) from above. the gigabit port sends a pause frame with ?0x0? when packet counts drop below grx_cnt_1.
green plb 2224 register description data sheet 181 2002-06-03 description tag priority table contains 8 entries with one bit each entry. it converts 8 priority classes of the received tagged frame to 2 priority classes (high priority and low priority). for tagged packets, pri[] field will be used to determine the queue class of the egress packet. table 95 tag priority table register 7.4.33 egress priority table name : e_pri_table offset : 0xd8 access : read/write description egress priority table contains two entries with 3-bits per entry. it converts the two internal priority classes to one of the 8 priority classes of tagged frame. this determines the pri[] field of the tag control field if the output tagging is needed and the ingress packet has no tag. bit fields name block (access) initial value description 31:8 rsv 0 reserved 7 tag_pri_7 (r/w) 1 6 tag_pri_6 (r/w) 1 5 tag_pri_5 (r/w) 1 4 tag_pri_4 (r/w) 1 3 tag_pri_3 (r/w) 0 2 tag_pri_2 (r/w) 0 1 tag_pri_1 (r/w) 0 0 tag_pri_0 (r/w) 0
green plb 2224 register description data sheet 182 2002-06-03 table 96 egress priority table 7.4.34 port cfi register name : port_cfi offset : 0xdc access : read/write description this bit is used as cfi in the tag control field if the output tagging is needed and ingress packet has no tag default set to ?0? table 97 port cfi register 7.4.35 vlan aware/intag control register name : vlan_aware/intag control register offset : 0xe0 access : read/write bit fields name (access) initial value description 31:6 rsv 0 reserved 5:3 e_pri_1 (r/w) 3?b110 a internal high priority queue data is translated to the value set the 3 bits 2:0 e_pri_0 (r/w) 3?b010 a internal low priority queue data is translated to the value set the 3 bits bit fields name (access) initial value description 31:29 rsv 0 27:0 port_cfi[27:0] (r/w) 0
green plb 2224 register description data sheet 183 2002-06-03 description this register is used to indicate the status of the switch?s vlan awareness and also the type of frame that are accepted. table 98 vlan aware/intag control register 7.4.36 vlan ingress filter name : vlan ingress filter offset : 0xec access : read/write description enables the ingress filtering parameter on a per port basis. bit fields name access/initial value description 31:29 rsv 0 28 vlan_aware (r/w) 0 0 : indicates a vlan unaware switch 1 : indicates vlan aware switch, which means that the switch will follow 802.1q with tagging and detagging capability. 27:0 admit_tagged_o nly [27:0] (r/w) 0 0: accept tagged and untagged frame 1: only tagged frame will be passed through, untagged frame will be dropped if this parameter is set to admit only vlan-tagged frames , any frames received on that port that carry no vid (i.e., untagged frames or priority-tagged frames) are discarded by the ingress rules
green plb 2224 register description data sheet 184 2002-06-03 table 99 vlan ingress filter 7.4.37 port index register 26_21 name: port_ix21-23,port_ix24-26 offset : 0xe4 - 0xe8 access : read/write description the index number is defined for each of the ports. the number based on source port will be used to lookup floodmap for the destination port list when a non-unicast packet is received. all the data are initialized to all 1?s. port_vid_ix[9:0] of each port is assigned as the default vlan vid_ix[9:0] for a port based vlan, for the packets being received from the corresponding source port. for ports 20 to 0, the port index register can be found in ?port index register_20_0? on page 161 table 100 port index register 26_21 bit fields name (access) initial value description 31:28 rsv (r/w) 0 27:0 ingress filter [27:0] (r/w) 0 0 :disable ingress filtering 1 :enable ingress filtering an enable ingress filtering parameter is associated with each port. if the enable ingress filtering parameter for a given port is set, as per the ingress rules (8.6) as mentioned in 802.1q document, shall discard any frame received on that port whose vlan classification does not include that port in its member set bit fields name offset description 31:30 rsv 0xe8 reserved 29:20 port26_ix[] 0xe8 index value for port 26
green plb 2224 register description data sheet 185 2002-06-03 7.4.38 led data register name : led_data offset : 0xf0-fc access : writeable description 32-bits of led display data if cpu has the control of led. table 101 led data register 19:10 port25_ix[] 0xe8 index value for port 25 9:0 port24_ix[] 0xe8 index value for port 24 31:30 rsv 0xe4 reserved 29:20 port23_ix[] 0xe4 index value for port 23 19:10 port22_ix[] 0xe4 index value for port 22 9:0 port21_ix[] 0xe4 index value for port 21 bit fields name access/initial value description 31:17 0xfc rsv 0 reserved 16 0xfc soft_led (w) 0 set to let cpu control the display of the led bits for the ethernet ports 15:12 rsv 0 reserved 11:8 0xfc cpu_led[3:0] (w) x 4-bits of led data for the cpu ports. 1 = on, 0=off. unlike the led bits for the ethernet ports, these led bits are always controlled by software 7:0 0xfc led_d[25:24] [3:0] (w) x 4-bits of led data for port 25 (gport1) and port 24 (gport0) 1 = on, 0 = off 31:0 0xf8 led_d[23:16] [3:0] (w) x 4-bits for led data for port 23 through port 16. 1 = on, 0 = off
green plb 2224 register description data sheet 186 2002-06-03 7.4.39 pattern registers name : pattern_mask[7:0] offset : 0x100 ? 0x11c access : r/w description the register with address offset of 0x100 is for pattern and mask #0 in group #0, the next one with address offset of 0x104 is for pattern and mask #1 in group #0, the next register with offset of 0x108 is for pattern and mask #2 in group #0, the register with address offset of 0x10c is for pattern and mask #3 in the group #0, the register with address offset of 0x110 is for pattern and mask #0 in group #1, the register with address offset of 0x114 is for pattern and mask #1 in group #1, the register with offset of 0x118 is for pattern and mask #2 in group #1?and the last one with address offset of 0x11c is for pattern and mask #3 in group #1. there are eight patterns totally in plb 2224, which can be configured by the user. table 102 pattern registers 31:0 0xf4 led_d[15:8] [3:0] (w) x 4-bits for led data for port 15 through port 8. 1 = on, 0 = off 31:0 0xf0 led_d[7:0] [3:0] (w) x 4-bits for led data for port 7 through port 0. 1 = on, 0 = off bit fields name (access) initial value description 31:16 pattern[15:0] (r/w) x pattern[] is used to compare with each incoming packet data. each pattern[] has mask[] as companion. 15:0 mask[15:0] (r/w) x 1 : the corresponding bit in pattern[] is skipped for the pattern comparison, and is considered to be compared successfully. 0 : the corresponding bit in pattern[] needs to be compared for the comparison result. note: if mask[] is equal to all 1?s, the whole pattern is always matched.
green plb 2224 register description data sheet 187 2002-06-03 7.4.40 offset registers name : offset_03 (offset_group0) offset : 0x120 access : r/w description specifies half-word offset within the packet for the 2b packet data that has to be compared with the pattern table 103 offset group0 registers bit fields name (access) initial value description 31:29 rsv 0 reserved 28:24 offset3[5:1] (r/w) x offset3[] specifies the starting half word location within each packet for pattern #3 to compare. 23:21 rsv 0 reserved 20:16 offset2[5:1] (r/w) x offset2[] specifies the starting half word location within each packet for pattern #2 to compare. 15:13 rsv 0 reserved 12:8 offset1[5:1] (r/w) x offset1[] specifies the starting half word location within each packet for pattern #1 to compare. 7comp_le0 (r/w) x 1: use ?less than or equal? as the condition for comparison result for pattern #0. 0: use ?equal? as the condition for comparison result. note: only pattern #0 and pattern #4 have this option bit. 6:5 rsv 0 reserved 4:0 offset0[5:1] (r/w) x offset0[] specifies the starting half word location within each packet for pattern #0 to compare.
green plb 2224 register description data sheet 188 2002-06-03 7.4.41 offset group register name: offset_47 (offset_grp1) offset : 0x124 access : r/w description specifies the half-word offset within the packet for the 2b packet data that is to be compared with pattern[] table 104 offset group1 register bit fields name access/initial value description 31:29 rsv 0 reserved 28:24 offset7[5:1] (r/w) x offset7[] specifies the starting half word location within each packet for pattern #7 to compare. 23:21 rsv 0 reserved 20:16 offset6[5:1] (r/w) x offset6[] specifies the starting half word location within each packet for pattern #6 to compare. 15:13 rsv 0 reserved 12:8 offset5[5:1] (r/w) x offset5[] specifies the starting half word location within each packet for pattern #5 to compare. 7comp_le4 (r/w) x 1: use ?less than or equal? as the condition for comparison result for pattern #4. 0: use ?equal? as the condition for comparison result. note: only pattern #0 and pattern #4 have this option bit. 6:5 rsv 0 reserved 4:0 offset4[5:1] (r/w) x offset4[] specifies the starting half word location within each packet for pattern #4 to compare.
green plb 2224 register description data sheet 189 2002-06-03 7.4.42 op_table registers name : op_table0/1 offset : 0x128- 0x12c access : r/w description the register with offset 0x128 is the group op code table which is used to convert the results of the pattern #3 to pattern #0 into 2-bits. similarly the register with offset 0x12c is for pattern #7 to #4. table 105 op_table registers 7.4.43 action_table registers name : action_table0-15 offset : 0x130- 0x16c access : r/w bit fields name access/initial value description 31:0 0x12c op_table1[31:0] (r/w) x similar to op_table0[]. op_table1[] is for pattern #4 to pattern #7. 31:0 0x128 op_table0[31:0] (r/w) x there are four inputs representing the comparison results from pattern #3 to pattern #0, respectively. the most significant bit is from pattern #3 result. four bit inputs are decoded onto 16 select lines from 0 to 15. there are 16 sets of 2-bit op codes, i.e. 32-bits totally. each 2-bit op code is selected by the value of the four inputs. the first set, bit[1:0], are selected by the select line #0. the second set, bit[3:2], are for line #1. and, the last set, bit[31:30], are for line #15.
green plb 2224 register description data sheet 190 2002-06-03 description these registers are to use the combined group_op_code[5:0] as the inputs to select one set of action bits. there are six inputs which are decoded to 64 select lines from 0 to 63. each select line select one set of action bits starting from the register 0x130. note: the description below only show the select lines from 0 to 3. similarly, for select lines from 4 to 7 are used to select the action4 to action7[] which are stored in the register with offset 0x134. continuing in the same way the last four select lines from 60 to 63 are to select the action60 to action63 in the register with offset 0x16c. table 106 action_table registers bit fields name access/initial value description 31:29 rsv 0 reserved 28:24 0x130 action3[4:0] (r/w) x action3[] are selected as the packet?s action bits, when select line #3 is asserted. 23:21 rsv 0 reserved 20:16 0x130 action2[4:0] (r/w) x action2[] are selected as the packet?s action bits, when select line #2 is asserted. 15:13 rsv 0 reserved 12:8 0x130 action1[4:0] (r/w) x action1[] are selected as the packet?s action bits, when select line #1 is asserted. note: the definition of action bits are identical to those in bit 4:0 field.
green plb 2224 register description data sheet 191 2002-06-03 7.4.44 enable filtering register name : e_filter offset : 0x170 access : r/w 7:5 rsv 0 reserved 4:0 0x130 action0[4:0] (r/w) x action0[] are selected as the packet?s action bit,s when select line #0 is asserted. the action bits now are defined below. bit 4: inc_filter_cnt. if asserted, the port with packet received increments its filter_cnt[]. bit 3: pkt_drop. if asserted, the packet is forced to drop instead of forwarding to any port. bit 2: fwd_cpu. if fwd_cpu and ~(pkt_drop), the packet will be forced to forward to filter_fwd_port[] port instead of the normal destination ports from lookup result. bit 1: monitor. add ?monitor? attribute to the packet so that it will also be forwarded to the monitor port besides the destination ports from lookup result. bit 0: pri. add ?pri? attribute to the packet so that the packet will be forwarded through high priority queue.
green plb 2224 register description data sheet 192 2002-06-03 description specifies the ports that are enabled for packet filtering functionality. also specifies the port_id used for the forwarding the filtered packets. table 107 enable filtering register 7.4.45 gmac registers name : g_rxtx offset : 0x1c0/0x1e0 access : r/w description register with offset 0x1c0 is for gmac port 24, and 0 x 1e0 is for port 25. table 108 g_rxtx register bit fields name access/initial value description 31:27 filter_fwd_port [4:0] (r/w) x if fwd_cpu action bit is asserted, the packet will be forwarded to the port assigned by this register instead of the normal destination ports from lookup result. 26:0 e_filter[] (r/w) 0 1: to enable filtering function by taking the action for the corresponding ports. 0: to ignore the action bit results for the corresponding ports. note: port 26 is the cpu port. bit fields name access/initial value description 31:30 rsv 0 reserved 29:24 ipgt[5:0] (r/w) 6?h0a back-to-back transmit ipg inter frame gap between successive transmission of packets. 23 adpad (r/w) 0 auto detect pad enable automatically detects a vlan tagged frame and pads the necessary data to make it a legal 68 byte frame
green plb 2224 register description data sheet 193 2002-06-03 7.4.46 g_mode register name : g_mode (mode of operation for the g ports) offset : 0x1cc / 0x1ec access : r/w description register with offset 0x1cc is for gmac port 24, and 0x1ec is for port 25. this register is used in conjunction with link_ok bit (bit 1) of ?g_pcs_0 / gport link status register? on page 196 register. table 109 g_mode register 22 paden (r/w) 0 pad enable pads data on to a packet to make it legal frame depending on whether adpad bit is set or vlan pad enable is set. 68-byte padding is enabled when paden = ?1? and (adpad = ?1? or vlpad = ?1?) on a vlan tagged frame 64-byte padding is enabled when paden = ?1? and (adpad = ?0? and vlpad = ?0?) on a non vlan tagged frame 21:19 rsv reserved 18 vlpad (r/w) 0 vlan pad enable when set has the same functionality as adpad except that it does not look for vlan tagged frame and makes all the packets which are of size less than 68- bytes, to a packet size of 68-bytes. this bit is activated only if paden = ?1? 17:0 rsv reserved bit fields name (access) initial value description 31:11 rsv 0 reserved 10 speed1000 (r) 0 gport selected speed 1: gport running in 1000 mbit/s 0: gport running either in 10/100 mbit/s depending on speed (bit 9)
green plb 2224 register description data sheet 194 2002-06-03 9 speed (r) 0 gport selected speed 1 : gport running in 100 mbit/s 0 : gport run in 10 mbit/s 8 full_duplex_cpu (r/w) 0 set to run the gport in full duplex clear to run the gport in half duplex this bit is written by cpu to determine whether the gigabit port in half duplex or full duplex if e_hw_mode in ?switch configuration register? on page 145 is 0. if e_hw_mode is asserted, this bit is ignored. the cpu read data is always from the mode finally used. note: plb 2224 supports half duplex only for 100 mbit/s and 10 mbit/s mode of operation for gports 7 rx_pause_e cpu (r/w) 0 set to enable full duplex flow control using pause frame for reception clear to disable full duplex flow control using pause frame for reception this bit is written by cpu to determine the gport?s rx pause capability if e_hw_mode is 0. if e_hw_mode is asserted, this bit is ignored. the cpu read data is always from the mode finally used. 6 tx_pause_e_ cpu (r/w) 0 set to enable full duplex flow control using pause frame for transmission clear to disable full duplex flow control using pause frame for transmission this bit is written by cpu to determine the port?s tx pause capability if e_hw_mode is 0. if e_hw_mode is asserted, this bit is ignored. the cpu read data is always from the mode finally used.
green plb 2224 register description data sheet 195 2002-06-03 7.4.47 g_pcs0 register / gport link status register name : g_pcs_0 offset : 0x1d0 / 0x1f0 access : r/w 5sel_gmii (r/w) 0 1 : to select gmii instead mii interface. 0 : to select mii interface for 100base phy. this field is valid only when gmac_mode (bit 0) is 1. these bits should be pin strapped to 1 if gmac_mode (bit 0) is 0. the bit is latched from pin-strapping input during the reset. led_col[24] for gport0 & led_col[25] for gport1 4 sw_reset (r/w) 0 software reset 3 l10b (r/w) 0 loopback 10-bit symbols in gmac 2l8b (r/w) 0 loopback 8-bit data in gmac 1ewrap (r/w) 0 enable phy loopback 0 gmac_mode (r/w) 0 0 : to select gb serdes based phy instead gmii or mii interface. 1 : to select gmii or mii interface instead of serdes based phy. used as sel_pma bit. this bit is initialized through the value of power strapped input at reset. led_col[26] for gport0 & led_row_n[0] for gport1
green plb 2224 register description data sheet 196 2002-06-03 description register with offset 0x1d0 is for gport 24, and 0x1f0 is for gport 25. this register has information related to link_ok status for the gigabit ports table 110 g_pcs_0 / gport link status register bit fields name (access) initial value description 31:8 rsv 0 reserved 7 autos (r/w) auto-sense bit 6 anen (r/w) 1 auto-negotiation enable should be written to ?0? through cpu interface or eeprom to get the tbi interface working 5rstan (r/w) 0 restart auto-negotiation 4 rfind (r/w) 0 remote fault indicator 3ancplt (r/w) 0 auto-negotiation completed 2pgrx (r/w) 0 auto-negotiation page received
green plb 2224 register description data sheet 197 2002-06-03 7.4.48 g_pcs_1 register name : g_pcs_1 offset : 0x1d4 / 0x1f4 access : r/w 1 link_ok (r/w) 0 the link_ok bit is to indicate the link status for a gmac port. the link status determines whether the port has good link and is able to transmit and receive normally and to assert external led?s. this bit is equivalent to the link_ok_cpu bit in the fe port. if e_hw_mode is 0, the link state of the gmac port is based on the value written by cpu. if e_hw_mode = ?1? , link_ok bit is ignored. when the cpu reads data, it is always based on the mode latched from mdio or internal pcs (depending on gmac_mode). if e_hw_mode is 0, link_ok takes the value written by the cpu. otherwise, (e_hw_mode is 1), the link_ok bit indicates the result of polling the phy or cpu?s read state. cpu can force the link_ok status to ?1? when e_hw_mode is 0. when reading link_ok bit, link_ok indicates pma_linkok bit if gmac_mode is 0. it indicates mii_linkok bit when gmac_mode is 1. 0syncok (r/w) 0 the syncok bit indicates the sync status from internal pcs when gmac is running in tbi mode. it is ignored otherwise. this bit is the result of receiving a good code group.
green plb 2224 register description data sheet 198 2002-06-03 description register with offset 0x1d4 is for gport 24, and 0x1f4 is for gport 25. table 111 g_pcs_1 register 7.4.49 g_pcs_2 register name : g_pcs_2 offset : 0x1d8 / 0x1f8 access : r/w bit fields name (access) initial value description 31 annp (r/w) 0 auto-negotiation additional next page to follow 30 ack (r/w) 0 auto-negotiation acknowledge 29 anmsg (r/w) 0 auto-negotiation message page in code field 28 anack2 (r/w) 0 auto-negotiation acknowledge 2 27 antog (r/w) 0 auto-negotiation toggle flag 26:16 npcf[10:0] (r/w) 11?h0 next page message/unformatted code field 15 nextp (r/w) 0 next page capable 14 rsv 0 reserved 13:12 anerr [1:0] (r/w) 2?b0 auto-negotiation error {rf2, rf1} 11:9 rsvd reserved 7:8 pause [1:0] (r/w) 2?b0 pause capable {asm_dir, pause} 6hd (r/w) 0 half duplex 5fd (r/w) 0 full duplex 0:4 rsv 0 reserved
green plb 2224 register description data sheet 199 2002-06-03 description register with offset 0x1d8 is for gmac port 24, and 0x1f8 is for port 25. table 112 g_pcs_2 register bit fields name (access) initial value description 31 lpannp (r) 0 link partner auto-negotiation additional next page to follow 30 lpack (r) 0 link partner auto-negotiation acknowledge 29 lpanmsg (r) 0 link partner auto-negotiation message page in code field 28 lpanack2 (r) 0 link partner auto-negotiation acknowledge 2 27 lpantog (r) 0 link partner auto-negotiation toggle flag 26:16 lpnpcf[10:0] (r) 11?h0 link partner next page message/ unformatted code field 15 lpnextp (r) 0 link partner next page capable 14 rsv 0 reserved 13:12 lpanerr[1:0] (r) 2?b0 link partner auto-negotiation error (remote fault) {rf2, rf1} 11:9 rsvd reserved 8:7 lppause[1:0] (r) 2?b0 link partner pause capable {asm_dir, pause} 6 lphd (r) 0 link partner half duplex 5lpfd (r) 0 link partner full duplex 4:0 rsv 0 reserved
green plb 2224 electrical characteristics data sheet 200 2002-06-03 8 electrical characteristics note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: in the operating range, the functions given in the circuit description are fulfilled. table 113 absolute maximum ratings parameter symbol limit values unit min. max. ambient temperature under bias t a 070 c storage temperature t stg -65 125 c ic supply voltage v dd -0.4 1.89 v pad (i/o) supply voltage v ddp -0.5 3.65 v voltage on any pin with respect to ground v s -0.4 v ddp + 0.4 v maximum current on all lines connected to the backplane when the doc is without power supply; at 5.5 v external signal level i max 2.3 ma esd robustness 1) hbm: 1.5 k ? , 100 pf 1) according to mil-std 883d, method 3015.7 and esd ass. standard eos/esd-5.1-1993. the rf pins 20, 21, 26, 29, 32, 33, 34 and 35 are not protected against voltage stress > 300 v (versus v s or gnd). the high frequency performance prohibits the use of adequate protective structures. v esd,hbm 2000 v table 114 operating range parameter symbol limit values unit test condition min. max. ambient temperature t a 070 c supply voltage v dd 1.65 1.89 v pad supply voltage v ddp 3.0 3.6 v ground v ss 00v
green plb 2224 electrical characteristics data sheet 201 2002-06-03 table 115 dc characteristic parameter symbol limit values unit notes min. max. input low voltage v il ? 0.4 0.8 v input high voltage v ih 2.0 v dd + 0.4 v output low voltage v ol 0.45 v i ol =7ma 1) i ol =2ma 2) 1) the listed characteristics are ensured over the operating range of the integrated circuit. 2) the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage. output high voltage v oh 2.4 v i oh =?1.0ma avg. power supply current i cc (av) tbd ma v dd =3.3v, t a =25 c: input leakage current i il 1 a v dd =3.3v, gnd = 0 v; all other pins are floating; v in =0v, v ddp +0.4 output leakage current i oz 1 a v dd =3.3v, gnd = 0 v; v out =0v, v ddp +0.4
green plb 2224 electrical characteristics data sheet 202 2002-06-03 8.1 ac characteristics 8.1.1 mdio interface timing details . figure 24 mdio timing table 116 ac characteristics mdio parameter symbol limit values unit min. max. mdc high pulse width t h 40 - ns mdc low pulse width t i 40 - ns mdio (i) setup with respect to mdc rising edge t setup 20 - ns mdio (o) hold time from mdc rising edge t hold 20 - ns mdio (o) valid from mdc rising edge t valid 0- ns mdio timing t setup mdc mdio(i) mdio(o) t hold t l t h t valid
green plb 2224 electrical characteristics data sheet 203 2002-06-03 8.1.2 smii interface timing details figure 25 smii interface timing table 117 ac characteristics - smii parameter symbol limit values unit min. max. smii clock high period t hi 3- ns smii clock low period t io 3- ns smii clock to output data valid t out 1.5 6 ns rx. data input setup time t su 0.8 - ns rx. data input hold time t h 0.5 - ns smii timing t su t h t out t hi t lo smii_clk sync/tx data rsync/rx data
green plb 2224 electrical characteristics data sheet 204 2002-06-03 8.1.3 gmii/tbi interface timing figure 26 gmii/tbi tx. interface timing figure 27 gmii/tbi rx. interface timing table 118 ac characteristics gmii tx. interface parameter symbol limit values unit min. max. setup from valid tx. data / en / er to the rising edge of the gtx clock t setup 2- ns hold from the rising edge of the gtx clock to the tx. data / en / er t hold 1- ns gmii transmit interface timing t hold t setup gtx_clk tx. data / en / er gmii receive interface timing (1000 mb/s) rx clk rx data t hold
green plb 2224 electrical characteristics data sheet 205 2002-06-03 8.1.4 pci interface / generic interface timing figure 28 pci / generic interface timing table 119 ac characteristics gmii rx. interface parameter symbol limit values unit min. max. setup from the rising edge of rx clock to rx. data / en / er t setup 1.5 - ns hold from the rising edge of rx clock to rx. data / en / er t hold 15.5ns table 120 ac characteristics pci parameter symbol limit values unit min. max. data input setup time t su 6.8 - ns data input hold time t h 0- ns data output valid t pval 3 20.2 ns float to active delay t pon 3- ns active to float delay t poff -15ns pci bus timing (@ 33 mhz) t su t h t pval t poff t pon pci clk pci inputs pci outputs
green plb 2224 electrical characteristics data sheet 206 2002-06-03 figure 29 32-bit generic interface write cycle - separate addr/data / r / w 32-bit generic interface , write cycle - separated address/data & read write t su_dwr t w_cs t off_cs t w_wr t d_rd t h_wr t h_csd t h_csa 1 muxed_ad use_ds as_n cs_n a<8:2> d<31:0> rd_n wr_n rdy 0 0 0
green plb 2224 electrical characteristics data sheet 207 2002-06-03 figure 30 32-bit generic interface read cycle - separate addr / data / r / w read cycle timing - separate address / data and read write rdy t d_rd t w_cs t off_cs t h_csd t h_csa 1 0 0 0 t on_cs t on_rdd muxed_ad use_ds as_n cs_n a<8:2> d<31:0> rd_n wr_n
green plb 2224 electrical characteristics data sheet 208 2002-06-03 figure 31 32-bit generic interface write cycle - separate addr / data with strobe write cycle timing - separate address / data with strobe muxed_ad use_ds as_n cs_n a<8:2> d<31:0> ds_n rd / wr_n rdy t d_rd t w_cs t off_cs t h_csd t h_csa 1 0 1 0 t w_ds t su_dwr
green plb 2224 electrical characteristics data sheet 209 2002-06-03 figure 32 32-bit generic interface write cycle - separate addr / data with strobe write cycle timing - separate address / data with strobe muxed_ad use_ds as_n cs_n a<8:2> d<31:0> ds_n rd / wr_n rdy t d_rd t w_cs t off_cs t h_csd t h_csa 1 0 1 0 t w_ds t su_dwr
green plb 2224 electrical characteristics data sheet 210 2002-06-03 figure 33 32-bit generic interface read - muxed addr / data & separate r/w read cycle timing - multiplexed address / data and separate r/w t w_cs t off_cs 1 1 0 address data t d_rd t on_rdd t off_rdd t off_csd t su_ale t h_alea t w_ale muxed_ad use_ds ale cs_n wr_n ad[31:0] rd_n rdy
green plb 2224 electrical characteristics data sheet 211 2002-06-03 figure 34 32-bit generic interface write - muxed addr / data & separate r/w write cycle timing - multiplexed address / data and separate r/w muxed_ad use_ds ale cs_n wr_n ad[31:0] rd_n rdy t w_cs t off_cs 1 1 0 t d_rd t su_dwr t off_rdd t h_alea t w_ale t d_wres t w_wr address data t off_csd t su_ale
green plb 2224 electrical characteristics data sheet 212 2002-06-03 figure 35 32-bit generic interface write cycle - muxed addr / data with strobe 0 1 t d_rd t w_ds muxed_ad use_ds as_n ds_n rd/wr_n rdy write cycle timing - multiplexed address / data with strobe 0 t w_cs t off_cs cs_n data t h_csd ad[31:0] address t h_alea t su_aale tsu_dds t h_dsd t w_ale
green plb 2224 electrical characteristics data sheet 213 2002-06-03 figure 36 32 bit generic interface read cycle - muxed addr/data with strobe 8.1.5 timing parameters ( figure 29 to figure 36 ) table 121 32-bit generic interface timing parameters parameter symbol limit values unit min. max. cs_n fall to rdy rise delay t d_rd 10 - ns wr_n rise to cs_n rise delay t d_wrcs -0ns ale fall to address invalid hold time t h_alea 0- ns cs_n rise to address invalid hold time t h_csa 0- ns cs_n rise to data invalid hold time t h_csd 0- ns wr_n rise to data invalid hold time t h_wrd 0- ns cs_n off time t off_cs 30 - ns cs_n rise to read data invalid delay t off_csd 4- ns 1 1 t d_rd muxed_ad use_ds as_n ds_n rd/wr_n rdy read cycle timing - multiplexed address / data with strobe 0 t w_cs t off_cs cs_n data t off_csd ad[31:0] address t su_aale t w_ale t on_dsd t off_ds
green plb 2224 electrical characteristics data sheet 214 2002-06-03 8.1.6 serial led interface timing figure 37 serial led interface ds_n rise to read data invalid delay t off_dsd 4- ns rd_n rise to read data invalid delay t off_rdd 4- ns cs_n fall to read data valid delay t on_csd -45ns ds_n fall to read data valid delay t on_dsd -45ns rd_n fall to read data valid delay t on_rdd -45ns address valid to ale fall setup time t su_aale 2.5 - ns data valid to ds_n rise setup time t su_dds 30 - ns data valid to wr_n rise setup time t su_dwr 30 - ns width of ale high time t w_ale 2.5 - ns width of cs_n low time t w_cs 60 - ns width of data write ds_n low time t w_ds 32 - ns width of wr_n low time t w_wr 32 - ns table 121 32-bit generic interface timing parameters (cont?d) parameter symbol limit values unit min. max. load data clock expanded last data shifted out
green plb 2224 electrical characteristics data sheet 215 2002-06-03 8.1.7 iic timings figure 38 iic interface timing table 122 serial led interface timing parameter value unit load 20 ms clk 163.8 s the order of data shifted out is port0/row0, port0/row1, port0/row2, ...... port27/row3 table 123 iic bus timing parameters parameter symbol clock rate unit 100 khz 400 khz 1 mhz 3.3 mhz min. max. min. max. min. max. min. max. scl clock frequency f scl 00.100.40103.3mhz hold time start condition. after this period the first clock pulse is generated t hd;sta 4.0 - 0.6 - 0.2 - 0.06 - s low period of the scl clock t low 4.7 - 1.3 - 0.47 - 0.14 - s high period of the scl clock t high 4.0 - 0.6 - 0.4 - 0.12 - s t buf t sp t hd;sta t su;sto t su;sta t f t hd;dat t hd;dat t low t r t r t high sda scl
green plb 2224 electrical characteristics data sheet 216 2002-06-03 setup time for a repeated start condition t su;sta 4.7 - 0.6 - 0.2 - 0.06 - s data hold time t hd;dat 0 3.45 0 0.9 0 0.3 0 0.09 s data setup time t su;dat 250 - 100 - 40 - 12 - s rise time of both sda & scl signals t r - 1000 - 300 120 - 30 ns fall time of both sda & scl signals t f - 300 - 300 120 - 30 ns bus free time between a stop & start condition t buf 4.7 - 1.3 - 0.47 - 0.14 - s setup time for stop condition t su;sto 4.0 - 0.6 - 0.4 - 0.12 - s pulse width of spikes suppressed t sp 10 to 1000 - 10 to 250 - 10 to 100 - 10 to 33 -ns capacitive load for each bus line c b - 400 - 400 - 200 - 100 pf table 123 iic bus timing parameters (cont?d) parameter symbol clock rate unit 100 khz 400 khz 1 mhz 3.3 mhz min. max. min. max. min. max. min. max.
green plb 2224 electrical characteristics data sheet 217 2002-06-03 table 124 capacitances parameter symbol limit values unit notes min. max. clock input capacitance c xin -5pf f c =1mhz the pins, which are not under test, are connected to gnd input capacitance c in -7pf output capacitance c out -7pf
green plb 2224 package details (p-bga-272) data sheet 218 2002-06-03 9 package details (p-bga-272) ?0.15 272x 19 x 1.27 = 24.13 24 27 16 0.2 1 1 (0.36) (1.17) 0.1 0.6 -0.16 +0.14 ?0.76 ?0.3 19 x 1.27 = 24.13 a20 1.27 2.35 max. index marking (sharp edge) index marking b c 0.2 27 16 24 1 1 m m c a c b 0.2 a y1 a1 gpa09270 p-bga-272 (plastic ball grid array package) you can find all of our packages, sorts of packing and others in our infineon internet page ? products ? : http://www.infineon.com/products. dimensions in mm smd = surface mounted device
http://www.infineon.com published by infineon technologies ag infineon goes for business excellence ?business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction.? dr. ulrich schumacher

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