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stock no. 23211-03 9/21/06 advance information 1 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. N08M1618L1A advance information ami semiconductor, inc. ulp memory solutions 670 north mccarthy blvd. suite 220 milpitas, ca 95035 ph: 408-935-7777, fax: 408-935-7770 8mb ultra-low power asynchronous medical cmos sram 512k 16 bit overview the N08M1618L1A is an integrated memory device intended for non life-support medical applications. this device is a 8 megabit memory organized as 524,288 words by 16 bits. the device is designed and fabricated using ami semiconductor?s advanced cmos technology with reliability inhancements for medical users. the device operates with two chip enable (ce1 and ce2) controls and output enable (oe ) to allow for easy memory expansion. byte controls (ub and lb ) allow the upper and lower bytes to be accessed independently and can also be used to deselect the device. this device is optimal for various applications wher e low-power is critical such as battery backup and hand-held devices. the device can operate over a very wide temperature range of -40 o c to +85 o c and is available in a jedec standard bga package. features ? dual voltage for optimum performance: vccq - 2.3 to 3.6 volts vcc - 1.4 to 2.2 volts ? very low standby current 0.5a at 1.8v and 37 deg c ? very low operating current 1.0ma at 1.8v and 1s (typical) ? very low page mode operating current 0.5ma at 1.8v and 1s (typical) ? simple memory control dual chip enables (ce1 and ce2) byte control for independent byte operation output enable (oe ) for memory expansion ? low voltage data retention vcc = 1.2v ? special processing to reduce soft error rate (ser) ? automatic power down to standby mode pin configuration product family part number package type operating temperature power supply speed standby current (i sb ), max operating current (icc), max N08M1618L1Ab 48 - bga -40 o c to +85 o c 2.3v-3.6v(v ccq ) 1.4v-2.2v(v cc ) 85ns @ 1.7v 150ns @ 1.4v 20 a 2.5 ma @ 1mhz N08M1618L1Aw wafer 123456 a lb oe a 0 a 1 a 2 ce2 b i/o 8 ub a 3 a 4 ce1 i/o 0 c i/o 9 i/o 10 a 5 a 6 i/o 1 i/o 2 d v ss i/o 11 a 17 a 7 i/o 3 v cc e v ccq i/o 12 nc a 16 i/o 4 v ss f i/o 14 i/o 13 a 14 a 15 i/o 5 i/o 6 g i/o 15 nc a 12 a 13 we i/o 7 h a 18 a 8 a 9 a 10 a 11 nc 48 pin bga (top) 8 x 10 mm pin descriptions pin name pin function a 0 -a 18 address inputs we write enable input ce1 , ce2 chip enable input oe output enable input lb lower byte enable input ub upper byte enable input i/o 0 -i/o 15 data inputs/outputs v cc power v ss ground v ccq power i/o pins only nc not connected
stock no. 23211-03 9/21/06 advance information 2 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. N08M1618L1A advance information ami semiconductor, inc. functional block diagram functional description ce1 ce2 we oe ub lb i/o 0 - i/o 15 1 1. when ub and lb are in select mode (low), i/o 0 - i/o 15 are affected as shown. when lb only is in the select mode only i/o 0 - i/o 7 are affected as shown. when ub is in the select mode only i/o 8 - i/o 15 are affected as shown. mode power hxxxxx high z standby 2 2. when the device is in standby mode, control inputs (we , oe , ub , and lb ), address inputs and data input/outputs are internally isolated from any external in fluence and disabled from exerti ng any influence externally. standby xlxxxx high z standby 2 standby xxxxhh high z standby 2 standby lhl x 3 3. when we is invoked, the oe input is internally disabled and has no effect on the circuit. l 1 l 1 data in write 3 active -> standby 4 4. the device will consume active power in this mode whenever addresses are changed. data inputs are internally isolated from any expernal influence. lhhl l 1 l 1 data out read active -> standby 4 lhhh l 1 l 1 high z active standby 4 capacitance 1 1. these parameters are verified in device characterization and are not 100% tested item symbol test condition min max unit input capacitance c in v in = 0v, f = 1 mhz, t a = 25 o c 8pf i/o capacitance c i/o v in = 0v, f = 1 mhz, t a = 25 o c 8pf address inputs a0 - a3 address inputs a4 - a18 word address decode logic 32k page x 16 word x 16 bit ram array word mux input/ output mux and buffers page address decode logic control logic ce1 ce2 we oe ub lb i/o0 - i/o7 i/o8 - i/o15
stock no. 23211-03 9/21/06 advance information 3 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. N08M1618L1A advance information ami semiconductor, inc. absolute maximum ratings 1 1. stresses greater than those listed above may cause permanent dam age to the device. this is a stress rating only and functiona l operation of the device at these or any other conditions above those indicated in the operating section of this specification i s not implied. exposure to absolute maximum rating cond itions for extended periods may affect reliability. item symbol rating unit voltage on any pin relative to v ss v in,out ?0.3 to v cc +0.3 v voltage on v cc supply relative to v ss v cc ?0.3 to 4.5 v power dissipation p d 500 mw storage temperature t stg ?40 to 125 o c operating temperature t a -40 to +85 o c soldering temperature and time t solder 240 o c, 10sec(lead only) o c operating characteristics (ove r specified temperature range) item symbol test conditions min. typ 1 1. typical values are measured at vcc=vcc typ., t a =25c and not 100% tested. max unit core supply voltage v cc 1.4 1.8 2.2 v i/o supply voltage v ccq v ccq > or = v cc 2.3 3.6 v data retention voltage v dr chip disabled 3 1.2 v input high voltage v ih v ccq -0.6 v ccq +0.3 v input low voltage v il ?0.3 0.6 v output high voltage v oh i oh = 0.2ma v ccq ?0.2 v output low voltage v ol i ol = -0.2ma 0.2 v input leakage current i li v in = 0 to v cc 0.1 a output leakage current i lo oe = v ih or chip disabled 0.1 a read/write operating supply current @ 1 s cycle time 2 2. this parameter is specified with the out puts disabled to avoid external loading effect s. the user must add current required t o drive output capacitance expected in the actual system. i cc1 v cc =2.2 v, v in =v ih or v il chip enabled, i out = 0 1.5 2.5 ma read/write operating supply current @ 85 ns cycle time 2 i cc2 v cc =2.2 v, v in =v ih or v il chip enabled, i out = 0 10.0 13.0 ma page mode operating supply current @ 85 ns cycle time 2 (refer to power savings with page mode operation diagram) i cc3 v cc =2.2 v, v in =v ih or v il chip enabled, i out = 0 3.5 ma read/write quiescent operating sup- ply current 3 3. this device assumes a standby m ode if the chip is disabled (ce1 high or ce2 low). in order to achieve low standby current all inputs must be within 0.2 volts of either vcc or vss. i cc4 v cc =2.2 v, v in =v ih or v il chip enabled, i out = 0, f = 0 1 a standby current 3 i sb1 v in = v cc or 0v chip disabled t a = 85 o c, v cc = 2.2 v 0.5 20.0 a data retention current 3 i dr v cc = 1.2v, v in = v cc or 0 chip disabled, t a = 85 o c 0.1 1.0 a
stock no. 23211-03 9/21/06 advance information 4 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. N08M1618L1A advance information ami semiconductor, inc. power savings with page mode operation (we = v ih ) note: page mode operation is a method of addressing the sram to save operating current. the internal organization of the sram is optimized to allow this unique operating mode to be used as a valuable power saving feature. the only thing that needs to be done is to address the sram in a manner that the internal page is left open and 8-bit words of data are read from the open page. by treating addresses a0-a3 as the least significant bits and addressing the 16 words within the open page, power is reduced to the page mode value which is considerably lower than standard operating currents for low power srams. page address (a4 - a18) oe ce1 ce2 word address (a0 - a3) open page word 1 word 2 word 16 ...
stock no. 23211-03 9/21/06 advance information 5 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. N08M1618L1A advance information ami semiconductor, inc. timing test conditions item input pulse level 0.1v cc to 0.9 v cc input rise and fall time 5ns input and output timing reference levels 0.5 v cc output load cl = 30pf operating temperature -40 to +85 o c timing v ccq > or = v cc item symbol v cc = 1.4 - 2.2 v v cc = 1.7 - 2.2 v units min. max. min. max. read cycle time t rc 150 85 ns address access time t aa 150 85 ns address access time (page mode) t aap 30 30 ns chip enable to valid output t co 150 85 ns output enable to valid output t oe 50 40 ns byte select to valid output t lb , t ub 150 85 ns chip enable to low-z output t lz 20 10 ns output enable to low-z output t olz 20 5 ns byte select to low-z output t lbz , t ubz 20 10 ns chip disable to high-z output t hz 030015ns output disable to high-z output t ohz 030015ns byte select disable to high-z output t lbhz , t ubhz 030015ns output hold from address change t oh 20 10 ns write cycle time t wc 150 85 ns chip enable to end of write t cw 75 50 ns address valid to end of write t aw 75 50 ns byte select to end of write t lbw , t ubw 75 50 ns write pulse width t wp 50 40 ns address setup time t as 00ns write recovery time t wr 00ns write to high-z output t whz 30 15 ns data to write time overlap t dw 50 40 ns data hold from write time t dh 00 ns end write to low-z output t ow 10 5 ns
stock no. 23211-03 9/21/06 advance information 6 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. N08M1618L1A advance information ami semiconductor, inc. timing of read cycle (ce1 = oe = v il , we = ce2 = v ih ) timing waveform of read cycle (we =v ih ) address data out t rc t aa t oh data valid previous data valid address lb , ub oe data valid t rc t aa t co t hz(1,2) t ohz(1) t lbhz, t ubhz t olz t oe t lz(2) high-z data out t lb, t ub t lblz, t ublz ce1 ce2
stock no. 23211-03 9/21/06 advance information 7 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. N08M1618L1A advance information ami semiconductor, inc. timing waveform of page mode read cycle (we = v ih ) page address (a4 - a18) lb , ub oe t aa t co t hz t ohz t lbhz, t ubhz t olz t oe high-z data out t lb, t ub t lblz, t ublz ce1 ce2 word address (a0 - a3) t aap t rc
stock no. 23211-03 9/21/06 advance information 8 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. N08M1618L1A advance information ami semiconductor, inc. timing waveform of write cycle (we control) address data in ce1 ce2 lb , ub data valid t wc t aw t cw t wr t whz t dh high-z we data out high-z t ow t as t wp t dw t lbw , t ubw
stock no. 23211-03 9/21/06 advance information 9 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. N08M1618L1A advance information ami semiconductor, inc. timing waveform of write cycle (ce1 control) address we data valid t wc t aw t cw t wr t dh lb , ub data in high-z t as t wp t lz t dw t lbw , t ubw data out t whz ce1 (for ce2 control, use inverted signal)
stock no. 23211-03 9/21/06 advance information 10 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. N08M1618L1A advance information ami semiconductor, inc. ball grid array package dimensions (mm) de e = 0.75 ball matrix type sd se j k 80.10 100.10 0.375 0.375 2.125 2.375 full side view top view bottom view e d a1 ball pad corner (3) 1.100.10 0.200.05 0.15 0.05 z z 1. 0.300.05 dia. 1. dimension is measured at the maximum solder ball diameter. parallel to primary z. 2. primary datum z and seating plane are defined by the spherical crowns of the solder balls. 3. a1 ball pad corner i.d. to be marked by ink. 2. seating plane - z sd se e k typ j typ e a1 ball pad corner
stock no. 23211-03 9/21/06 advance information 11 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.amis.com. N08M1618L1A advance information ami semiconductor, inc. ordering information ? 2006 ami semiconductor, inc. all rights reserved. ami semiconductor, inc. ("amis") reserves the right to change or modify the information contained in this data sheet and the pr oducts described therein, without prior notice. amis does not convey any license under its patent rights nor the rights of others. charts, drawings and schedules contained in this data sheet are provided for illustration pur- poses only and they vary depending upon specific applications. amis makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does amis assume an y liability arising out of t he application or use of any product or circuit described herein. amis does not authorize use of its products as critical components in any application in which the failure of the amis product may be expected to result in significant injury or death, incl uding life support systems and critical medical instruments. revision history revision # date change description 01 11/01/02 initial release 02 3/03/05 general update: updated icc4 typical and isb1 typical value updated block diagram, functional description table. added taap, tlb, tub, tlbz, tubz, tlbhz, tubhz, tlbw, tubw timing parameters. added page mode read timing waveform updated bga 8x10 package drawing updated vccq range on dc parameters table 03 9/21/2006 converted to ami semiconductor N08M1618L1Ax -xx x i = industrial, -40c to 85c 85 = 85ns @ 1.7v b = 48-ball bga d = known good die temperature performance package type

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