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ds04-27202-6e fujitsu semiconductor data sheet copyright?1994-2006 fujitsu limited all rights reserved assp bipolar switching regulator controller mb3769a description the fujitsu mb3769a is a pulse-width-modulation controller which is applied to fixed frequency pulse modulation technique. the mb3769a contains wide band width op-a mp and high speed comparator to construct very high speed switching regulator syst em up to 700 khz. output is suitable for power mos fet drive owing to adoption of totem pole output. the mb3769a provides stand-by mode at low voltage power supp ly when it is applied in primary control system. features ? high frequency oscillator (f = 1 khz to 700 khz) on-chip wide band frequency operation amplifier (bw = 8 mhz typ) on-chip high speed comparator (td = 120 ns typ) internal reference voltage generator prov ides a stable reference supply (5 v 2%) low power dissipation (1.5 ma typ at st andby mode, 8 ma typ at operating mode) output current 100 ma ( 600 ma at peak) high speed switching operation (tr = 60 ns, tf = 30 ns, c l = 1000 pf typ) adjustable dead-time on-chip soft start and quick shut down functions internal circuitry prohibits double pulse at dynamic current limit operation under voltage lock out function (off to on: 10 v typ, on to off: 8 v typ) on-chip output shut down circuit wi th latch function at over voltage on-chip zener diode (15 v) one type of package (sop-16pin : 1 type) applications power supply module industrial equipment ac/dc converter etc.
mb3769a 2 pin assignment 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 +in (op) -in (op) fb dtc c t r t gnd v l +in (c) -in (c) v ref ovp v cc v z v h out (top view) (fpt-16p-m06)
mb3769a 3 block diagram + - + - - + + + + + + - - + s r q s r q tr i a n g l e wa v e oscillator over voltage detector - + reference regulator + - power off 2.5 v 1.5 v to 3.5 v (2.5 v) 15.4 v 30 k ? 5.0 + 0.1 v 8/10 v stb over current detection comparator pwm comp. 1.85 v 1.8 v stb stb v ref v h v l v ref out error amp dtc fb -in (op) ovp c t r t v cc v z gnd fig. 1 - mb3769a block diagram 16 4 3 1 2 13 5 6 12 11 7 14 8 9 10 15 -in (c) +in (c) +in (op)
mb3769a 4 absolute maximum ratings *1 : duty 5% *2 : ta = + 25 c, sop package is mounted on the epoxy board. (4 cm x 4 cm x 0.15 cm) warning: semiconductor devices can be permanently dam aged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit min max power supply voltage v cc ? 20 v output current i out ? 120 (660* 1 )ma operation amp input voltage vin (op) ? v cc + 0.3 ( 20) v power dissipation : sop p d ? 620* 2 mw storage temperature t stg -55 +125 c
mb3769a 5 recommended operating conditions warning: the recommended operating conditions are require d in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol sop package unit min typ max power supply voltage v cc 12 15 18 v output current (dc) i out -100 - +100 ma output current (peak) i out peak -600 - +600 ma operation amp input voltage v inop -0.2 0 to vref vcc-3 v fb sink current i sink --0.3ma fb source current i source --2ma comparator input voltage v inc + -0.3 0 to 3 vcc v v inc - -0.3 0 to 2 2.5 v reference section output current i ref -210ma timing resistor r t 91850k ? timing capacitor c t 100 680 10 6 pf oscillator frequency f osc 1 100 700 khz zener current i z --5ma operating ambient temperature: sop ta -30 +25 +75 c
mb3769a 6 electrical characteristics (continued) (v cc =15v, ta=+25 c) parameter symbol condition value unit min typ max reference section output voltage v ref i ref = 1 ma 4.9 5.0 5.1 v input regulation ? vr in 12 v v cc 18 v - 2 15 mv load regulation ? vr ld 1 ma i ref 10 ma - -1 -15 mv temp. stability ? vr temp -30 c ta +85 c - 200 750 v/ c short circuit output current i sc v ref = 0 v 15 40 - ma oscillator section oscillator frequency f osc r t = 18 k ? c t = 680 pf 90 100 110 khz voltage stability ? f oscin 12 v v cc 18 v - 0.03 - % temp. stability ? f osc / ? t-30 c ta +85 c- 2 - % dead -time control section input bias current i d - -210 a max. duty cycle dmax vd = 1.5 v 75 80 85 % duty cycle set dset vd = 0.5 v ref 45 50 55 % input threshold voltage 0% duty cycle v do --3.53.8v max. duty cycle v dm - 1.55 1.85 - v discharge voltage v dh v cc = 7 v, i dtc = -0.3 ma 4.5 - - v error amplifier section input offset voltage v io (op) v 3 = 2.5 v - 2 10 mv input offset current i io (op) v 3 = 2.5 v - 30 300 na input bias current i ir (op) v 3 = 2.5 v -1 -0.3 - a common-mode input voltage v cm (op) 12 v v cc 18 v -0.2 - v cc -3 v voltage gain av (op) 0.5 v v 3 4 v 70 90 - db band width bw av = 0 db - 8 - mhz slew rate sr r l = 10 k ? , av = 0 db - 6 - v/ s common-mode rejection rate cmr v in = 0 v to 10 v 65 80 - db ?h? level output voltage v oh i 3 = -2 ma 4.0 4.6 - v ?l? level output voltage v ol i 3 = 0.3 ma - 0.1 0.5 v
mb3769a 7 (continued) * : v cc = 8v (v cc =15v, ta=+25 c) parameter symbol condition value unit min typ max current comparator input offset voltage v io (c) v in = 1 v - 515 mv input bias current i ib (c) v in = 1 v -5 -1 - a common-mode input voltage v cm (c) - 0-2.5v voltage gain a v (c) - -200- v/v response time td 50 mv over drive -120250 ns pwm comparator section 0% duty cycle v opo r t = 18 k ? c t = 680 pf -3.53.8 v max duty cycle v opm 1.55 1.85 - v output section ?h? level output voltage v h i out = -100 ma 12.5 13.5 - v ?l? level output voltage v l i out = 100 ma -1.11.3 v rise time tr c l = 1000 pf, r l = - 60 120 ns fall time tf c l = 1000 pf, r l = -3080 ns over voltage detector threshold voltage v ovp - 2.4 2.5 2.6 v input current i iovp v in = 0 v -1.0 -0.2 - a v cc reset v cc rst - 2.0 3.0 4.5 v under voltage out stop off to on v thh - 9.2 10.0 10.8 v on to off v thl - 7.2 8.0 8.8 v supply current standby * i stb r t = 18 k ? 4 pin open -1.52.0ma operating i cc r t = 18 k ? -8.012.0ma zener voltage v z i z = 1 ma -15.4- v zener current i z v 11-7 = 1 v -0.03- ma
mb3769a 8 fig. 2 - mb3769a test circuit 16 15 14 13 12 11 10 9 12345678 +in (c) -in (c) v ref ovp v cc v z v h out +in (op) -in (op) fb dtc c t r t gnd v l v fb v dtc mb3769a comp in 1.0 v 15.0 v output 10 k ? 18 k ? 680 pf test input 1000 pf 90% 10% 50% tf td tr 1.05 v 1.0 v 3.5 v typ 1.5 v typ voltage at c t comp in output 0.95 v tr of comp-in should be within 20 ns.
mb3769a 9 soft start operation quick shutdown operation 3.5 v 1.5 v 1.85v (15 v) 10 v (typ) 2.5 v (1 v) 3 v 8 v (typ) standby mode over voltage detector latch off standby mode over current detector over voltage detector 0 v dead-time input voltage triangle wave form error amp output pwm comparator output output wave form comp. current -in wave form comp. current +in wave form comp. current latch output voltage at ovp ovp latch power supply voltage fig. 3 - mb3769a operating timing
mb3769a 10 functions 1. error amplifier the error amplifier detect s the output voltage of the switching regulator. the error amplifier uses a high-sp eed operational amplifier with an 8 mhz bandwidth (typical) and 6 v/ s slew rate (typical). for ease of use, the common mode in put voltage ranges from -0.2 v to v cc -3 v. figure 4 shows the equivalent circuit. 2. overcurrent detection comparator there are two methods for protection of the output transistor of this device from ov ercurrents; one restricts the transistor?s on- time if an overcurrent that flows through the output transistor is detected from an average output current, and the other detec ts an overcurrent in the external tr ansistor (fet) and shuts the ou tput down instantaneously. usin g average output currents, the peak current of the external transistor (fet ) cannot be detected, so an output transist or with a large safe operation area (soa ) margin is required. for the method of detecting overcurrents in the external transistor (fet), the output transistor can be protected against a sho rted filter capacitor or power-on surge current. the mb3769a uses dynamic current limiting to detect overcurr ents in the output transistor (fet). a high-speed comparator and flip-flop are built-in. to detect overcurrents, compare the voltage at +in (c) of current detection resistor connecte d the source of the output transistor (fet), with the reference voltage (connected to -in (c) ) using a comparator. to prevent output oscillation during overcurrent, flip- flop circuit protects against doub le pulses occurring within a cycle. the output of overcurrent detector is ored with ot her signals at the pwm comp arator. see the example ? application example? for details on use. figure 5 shows the equivale nt circuit of the over-current detection comparator. fig. 4 - mb3769a equivalent circuit differential amp v cc gnd -in (op) +in (op) 150 ? 700 a v ref to p w m comp. protection element
mb3769a 11 3. dtc: dead time control (soft-start and quick shutdown) the dead time control te rminal and the error ampl ifier output are connecte d to the pwm comparator. the maximum duty cycle for v dtc (voltage applied to pin 4) is obtained from the following formula (approximate value at low frequency): duty cycle = (3.5 - v dtc ) x 50 (%) [0% duty cycle d max (80%)] the dead time control terminal is used to provide soft start. in figure 6, the dtc termin al is connected to the v ref terminal through r and c. because capacitor c does not charge instantaneously when the power is turned on, the output transistor is kept turned off. the dtc input voltage and the output pul se width increase gradually according to the rc time co nstant so that the control system operates safely. the quick shutdown function prevents soft start malfunction when the power is turned off and on quickly. after the power is shu t down, soft start is disabled because the dtc terminal has low el ectric potential from the beginning if the power is turned on again before the capacitor is discharged. th e mb3769a prevents this by turning on th e discharge transistor to quickly discharge the capacitor in the stand-by mode. fig. 5 - mb3769a equivalent circuit over current detection comparator protection element +in (c) v ref to p w m comp. -in (c) fig. 6 - mb3769a soft start function v ref dtc c r soft start v ref dtc cr 1 soft start + dtc r 2
mb3769a 12 4. triangular wave oscillator the oscillation frequency is expr essed by the following formula: for master/slave synchronized operation of several mb3769as, the c t and r t terminals of the master mb3769a are connected in the usual way and the c t terminals of the master and slave device (s ) are connected together. the slave mb3769a?s r t terminal is connected to it?s v ref terminal to disable the slave?s o scillator. in this case, set 50/n k ? (n is the number of master and slave ics) to the upper limit of r t so that internal bias currents do not stop the master oscillation. 5. overvoltage detector the overvoltage detection circuit shuts the system power down if the switching regulator?s output voltage is abnormal or if abnormal voltage is appeared. the reference voltage is 2.5 v (v ref /2). the system power is shut down if the voltage at pin 13 rises above 2.5 v. the output is kept shut down by the latchi ng circuit until the power supply is turned off (see figure 3). 6. stand-by mode and under-voltage lockout (uvlo) generally, v gs > 6 to 8 v is required to use po wer mosfet for switching. uvlo is set so that output is on at v cc 10 v (standard) when the power is turned on and is off at v cc 8 v (standard) when th e power is turned off. in the stand-by mode, the power supply current is limited to 2 ma or less when the output is inhi bited by the uvlo circuit. whe n the mb3769a is operated from the 100 vac li ne, the power supply current is supplied th rough resistor r (fig ure 8). that is, the ic power supply current is supplied by the ac line through resistor r until operation starts. current is then supplied from the transformer tertiary winding, eliminatin g the need for a second power supply. two volts (typical) of hysteresis are provided for return from op eration mode to stand-by mode not to return to stand-by mode until output power is turned on or to avoid malfunction due to noise. [khz] f osc ~ : f 0.8 x c t x r t + 0.0002 ms :k ? 1 c t r t fig. 7 - mb3769a synchronized operation master r t c t slave v ref r t c t
mb3769a 13 7. output section because the out terminal (pin 9) carries a large current, the collector and emitter of the output transistor are brought out to the v h and v l terminals. in principle, v h is connected to v cc and v l is connected to gnd, but v h can be supplied from another power supply (4 v to 18 v). note that v l and gnd should be co nnected as close to the ic package as possible. a capacitor of 0.1 f or more is inserted between v h and v l (see figure 9). fig. 8 - mb3769a primary control mb3769a c r fig. 9 - mb3769a typical connection circuit of output 10 9 0.1 f 12 78
mb3769a 14 application example overcurrent protection circuit the waveform at the output fet sour ce terminal is shown in figure 11. the rc time constant must be chosen so that the voltage glitch in the waveform does not cause errone ous overcurrent detection. this time constant is should be from 5 ns to 100 ns. a detection current value depends on r or c because a waveform is weakened. to keep this glitch as small as possible, the rectifiers on the transformer secondary winding must be the fast-recovery type. fig. 10 - mb3769a dc - dc convertor mb3769a +in (c) 16 in (c) 15 v ref 14 ovp 13 v cc 12 v z 11 v h 10 out 9 0.1 f 20 k ? 10 k ? r c 100 k ? 330 pf 3.3 k ? 220 pf 51 k ? 18 k ? 10 k ? 5.1 k ? 1 ? s 5 v 1 a 3.6 k ? 2.4 k ? 12 to 18 v 1+in (op) 2-in (op) 3fb 4dtc 5c t 6r t 7gnd 8v l fig. 11 - mb3769a output fet source point glitch point s waveform
mb3769a 15 100 vac r 22 k ? 4.7 f 22 k ? 680 pf 18 k ? 10 k ? 15 k ? 22 ? * 47 k ? +in (op) -in (op) fb dtc c t r t gnd v l +in (c) -in (c) v ref ovp v cc v z v h out 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 *: the resistance (22 ? ) as an output current limiter at pin 9 is required when driving the fet which is more than 1000 pf (cgs). - + fig. 12 -primary control - + 43 k ? 51 k ? 680 pf 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 +in (op) -in (op) fb dtc c t r t gnd v l +in (c) -in (c) v ref ovp v cc v z v h out secondly power supply 15 v 0 v 10 k ? 18 k ? 5.1 k ? 39 k ? 27 k ? 10 k ? 12 v 1000 pf fig. 13 -secondly control
mb3769a 16 short protection circuit the system power can be shut down to protect the outp ut against intermittent short-circuits or continuous overloads. this protection circuit can be configur ed using the ovp input as shown in figure 14. mb3769a 9 14 13 7 1 f pc1 100 k ? 10 k ? 20 k ? pc2 8 5 3 4 16 v 0 (5v output) pc2 pc1 out-b 500 ? hys-a 500 ? mb3761 15 k ? in-b 8.2 k ? in-a 6.8 k ? fig. 14 -case i. (over protection input) primary mode mb3769a 14 13 ovp v ref mb3761 8 5 3 6 12 in-a in-b 15 k ? 8.2 k ? 6.8 k ? out-b hys-a 200 k ? 1 f 20 k ? v 0 (5v output) fig. 15 -case ii. (over protection input) secondly mode
mb3769a 17 how to synchronize with outside clock the mb3769a oscillator circui t is shown in figure 16. c t charge and discharge currents are expressed by the following formula: this circuit shows that if the voltage at the c t terminal is set to 1.5 v or less, one osci llation cycle ends and the next cycle starts. an example of an external synchronous clock circuit is shown in figure 17. 5 v r t i ct = 2 x i 1 = v ref 2.5 v r t - + + - - + s r q 3.5 v 1.5 v 2 x i 1 2 x i 1 1 k ? 500 ? 500 ? 300 ? 150 ? i 1 i ct c t (4 x i 1 ) 6 5 fig. 16 -oscillator circuit 5 6 mb3769a r t c t r(5.1 k ? ) v p ex. mb74hc04 clamp circuit (v l ) v p t p t cycle t cycle = 2.5 s (f ext = 400 khz) t p = 0.5 s r t = 11 k ? fig. 17 -typical connection of synchronized outside clock circuit t p ? v l v ct 1.85 v 3.5 v v th ( 2.5 v) . . fig. 18 -voltage waveform at c t the figure 18 shows the c t terminal waveform. v th may be near 2.5 v. in this case, the maximum duty cycle is restricted as shown in the formula below if t p ? = 0. d max = 59% (v l = 0 v: no clamp circuit) (3.5 - 1.85) + (3.5 - v th ) (3.5 - v l ) + (3.5 - v th ) when v th = 2.5 v, c t can be provided by followings. t cycle - t p =x (3.5 - v l ) + (3.5 - v th ) f osc (3.5 - 1.5) x 2 f osc 1
mb3769a 18 make v l high for a large duty cycle for the clamp circuit. the circ uits below can be used because the clamp voltage must be much lower than 1.5 v. in circuit a, r 1 and r 2 must be determined considering the effects of t p , r, or r t . the transistor saturation voltage must be very small (<0.15 v) for any clamp circ uit, so a transistor with a very small v ce (sat) should be used. c t ~ x(t cycle - t p ) [pf] (r t : k ? , t cycle , t p : ns) 14 0.8 x r t 4.5 - v l f osc ~ 1 0.8 x c t x r t 0.1 f r 2 (1.2 k ? ) (1.2 v) r 1 (4.7 k ? ) v ref a (1.2 v) 0.1 f 820 ? v ref 8 5 3 4 mb3761 b fig. 19 -clamp circuit
mb3769a 19 synchronized outside clock circuit 5 pin c t 150 pf 5.1 k ? v p mb74hc04 1.no clamp circuit (connect with gnd) c t = 150 pf + prove capacitor (~ 15 pf) r t = 11 k ? 2.clamp circuit a (dividing resistor) c t = 220 pf + prove capacitor (~ 15 pf) r t = 11 k ? 5 pin c t 220 pf 5.1 k ? mb74hc04 v p 4.7 k ? 1.2 k ? 0.1 f 3.clamp circuit b (apply mb3761) c t = 220 pf + prove capacitor (~ 15 pf) r t = 11 k ? 5 pin c t 220 pf 5.1 k ? v p mb74hc04 0.1 f v ref 820 ? 8 5 4 3 v ref mb3761 v p (5 v/div) c t (1 v/div) out (10 v/div) gnd level (c t ) v p (5 v/div) c t (1 v/div) gnd level (c t ) out (10 v/div) v p (5 v/div) c t (1 v/div) gnd level (c t ) out (10 v/div) fig. 20 fig. 21 fig. 22 10 v 1 v 500 ns 5 v 1 v 500 ns 10 v 5 v 1 v 500 ns 10 v 5 v 1 v 500 ns 10 v 5 v
mb3769a 20 1 2.4 k ? 11 k ? mb3769a 2.5 v out 2.4 k ? 15 v (v cc ) 2 3 4 5 6 14 15 16 9 7813 12 10 fig. 23 -test circuit
mb3769a 21 typical performance characteristics (continued) 10.0 8.0 6.0 4.0 2.0 0.0 0.0 4.0 8.0 12.0 16.0 20.0 fig. 24 -power supply voltage vs. power supply current (low voltage stop of v cc ) 2 1 0 -30 + 0 + 25 + 50 + 85 fig. 25 -standby current vs. operating ambient temperature ovp operating v 13 = 5 v normal operating v 13 = 0 v v cc = 8 v power supply voltage v cc (v) operating ambient temperature ta ( c) fig. 26 -reference voltage fig. 27 -?l? level output voltage vs. ?l? level output current v cc = 15 v ta = +25 c 3 2 1 00.20.40.60.8 ?l? level output current i ol (ma) v cc = 15 v i ref = 1 ma 5.1 5.0 4.9 0 -30 0 + 25 + 50 + 85 operating ambient temperature ta ( c) 5 4 3 2 1 0 24 6 8 10 ?h? level output current i oh (ma) fig. 28 -?h? level output voltage vs. ?h? level output current power supply current i cc (ma) reference voltage v ref (v) ?h? level output voltage v oh (v) standby current i stb (ma) ?l? level output voltage v ol (v) ovp operating 750 v/c v cc = 15 v ta = +25 c
mb3769a 22 (continued) 700 500 400 300 200 100 50 20 710 2030405070 fig. 29 -oscillator frequency vs. r t , c t fig. 30 -?h?, ?l? level output voltage vs. oscillator frequency c t = 100 pf c t = 220 pf c t = 680 pf c t = 1000 pf c t = 2200 pf 4 3 2 1 0 20 k 50 k 100 k 200 k 500 k 1 m v h v l fig. 31 -duty cycle vs. dead time control voltage fig. 32 -oscillator frequency vs. operating ambient temperature fig. 33 -dead time control voltage vs. current(standby mode) -4 -2 0 2 4 v cc = 15 v 100 khz 300 khz 500 khz f osc = 200 khz f osc = 500 khz 5.0 4.0 3.0 2.0 v cc = 7 v ta = +25 c 1.0 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 100 80 60 40 20 0 01 234 5 r t (k ? ), c t (pf) frequency f osc (hz) operating ambient temperature ta ( c) -30 0 + 25 + 50 + 85 dead time control voltage v dtc (v) dead time control current i dtc (ma) oscillator frequency f osc (khz) dead time control voltage v dtc (v) ?h?, ?l? level output voltage v h , v l (v) oscillator frequency f osc (%) duty cycle (%) 40 30 60 80 90 70 60 89 v h v l v cc = 15 v ta = +25 c v cc = 15 v c t = 1000 pf ta = +25 c target f osc = 100 khz 2 % typ
mb3769a 23 (continued) fig. 34 -gain/phase vs. frequency (set gv = 60 db) gain phase 60 40 20 0 10 k 100 k 1 m 10 m -180 -240 -300 -360 f osc = 500 khz f osc = 200 khz v cc = 15 v c l = 1000 pf v dtc = 2.5 v fig. 35 -duty vs. operating ambient temperature 55 50 45 0 -30 0 + 25 + 50 + 85 fig. 36 -?l? level output voltage vs. ?l? level output current v cc = 15 v ta = +25 c fig. 38 -tr/tf of output and td of comparator vs. operating ambient temperature 160 140 120 100 80 60 40 20 0 -30 0 + 25 + 50 + 85 td tr tf fig. 37 -?h? level output voltage vs. ?h? level output current 1.5 1.0 0.5 0 0 100 200 300 400 500 600 14.0 13.5 13.0 12.5 0 0 100 200 300 400 500 600 frequency f (hz) operating ambient temperature ta ( c) ?l? level output current i ol (ma) ?h? level output current i oh (ma) v cc = 15 v ta = + 2 5 c operating ambient temperature ta ( c) gain (db) ?l? level output voltage v ol (v) ?h? level output voltage v oh (v) phase (deg) duty (%) tr/tf/td (ns) v cc = 15 v ta = +25 c v cc = 15 v c l = 1000 pf
mb3769a 24 (continued) 0 + 20 + 40 + 60 + 100 + 80 6 5 4 3 2 -40 -20 0 + 20 + 40 + 60 + 80 + 100 fig. 39 -ovp latch standby power supply current vs. operating ambient temperature v cc = 8 v 4 pin open 13 pin = 3 v operating ambient temperature ta ( c) fig. 40 -ovp supply voltage reset vs. operating ambient temperature -40 -20 operating ambient temperature ta ( c) 5 4 3 2 1 0 standby power supply current (ma) ovp supply voltage reset (v) 0
mb3769a 25 notes on use take account of common impedance when designing the earth line on a printed wiring board. take measures against static electricity. - for semiconductors, use antista tic or conductive containers. - when storing or carrying a printed circuit board after ch ip mounting, put it in a co nductive bag or container. - the work table, tools and meas uring instruments must be grounded. - the worker must put on a gro unding device containing 250 k ? to 1 m ? resistors in series. do not apply a negative voltage - applying a negative voltage of ? 0.3 v or less to an lsi may generate a parasitic transistor, resulting in malfunction. ordering information rohs compliance information of lead (pb) free version the lsi products of fujitsu with ?e1? are compliant with rohs directive , and has observed the standard of lead, cadmium, mercury, hexavalent chromium, polyb rominated biphenyls (pbb) , and polybrominated diphenyl ethers (pbde) . the product that conforms to this standard is added ?e1? at the end of the part number. marking format (lead free version) part number package remarks mb3769apf- ??? 16-pin plastic sop (fpt-16p-m06) conventional version mb3769apf- ??? e1 16-pin plastic sop (fpt-16p-m06) lead free version index mb3769a xxxx xxx e1 lead free version sop-16
mb3769a 26 labeling sample (lead free version) 2006/03/01 assembled in japan g qc pass (3n) 1mb123456p-789-ge1 1000 (3n)2 1561190005 107210 1,000 pcs 0605 - z01a 1000 1/1 1561190005 mb123456p - 789 - ge1 mb123456p - 789 - ge1 mb123456p - 789 - ge1 pb lead free version lead free mark jeita logo jedec logo
mb3769a 27 mb3769apf- ??? e1 recommended conditions of moisture sensitivity level [temperature profile for fj standard ir reflow] (1) ir (infrared reflow) (2) manual soldering (partial heating method) conditions : temperature 400 c max times : 5 s max/pin item condition mounting method ir (infrared reflow) , m anual soldering (partial heating method) mounting times 2 times storage period before opening please use it within two years after manufacture. from opening to the 2nd reflow less than 8 days when the storage period after opening was exceeded please processes within 8 days after baking (125 c, 24h) storage conditions 5 c to 30 c, 70 % rh or less (the lowest possible humidity) 260 c (e) (d') (d) 255 c 170 c 190 c rt (b) (a) (c) to note : temperature : the top of the package body (a) temperature increase gradient : average 1 c/s to 4 c/s (b) preliminary heating : temperature 170 c to 190 c, 60s to 180s (c) temperature increase gradient : average 1 c/s to 4 c/s (d) actual heating : temperature 260 c max; 255 c or more, 10s or less (d?) : temperature 230 c or more, 40s or less or temperature 225 c or more, 60s or less or temperature 220 c or more, 80s or less (e) cooling : natural cooling or forced cooling h rank : 260 c max
mb3769a 28 package dimension 16-pin pl as tic s op le a d pitch 1.27 mm p a ck a ge width p a ck a ge length 5. 3 10.15 mm le a d s h a pe gullwing s e a ling method pl as tic mold mounting height 2.25 mm max weight 0.20 g code (reference) p- s op16-5. 3 10.15-1.27 16-pin pl as tic s op (fpt-16p-m06) (fpt-16p-m06) c 2002 fujit s u limited f16015 s -c-4-7 0.1 3 (.005) m det a il s of "a" p a rt 7. 8 00.40 5. 3 00. 3 0 (.209.012) (. 3 07.016) ?.00 8 +.010 ?0.20 +0.25 10.15 index 1.27(.050) 0.10(.004) 1 8 9 16 0.470.0 8 (.019.00 3 ) ?0.04 +0.0 3 0.17 .007 +.001 ?.002 "a" 0.25(.010) ( s t a nd off) 0~ 8 ? (mounting height) 2.00 +0.25 ?0.15 .079 +.010 ?.006 0.500.20 (.020.00 8 ) 0.600.15 (.024.006) 0.10 +0.10 ?0.05 ?.002 +.004 .004 .400 * 1 * 2 0.10(.004) dimen s ion s in mm (inche s ). note: the v a lue s in p a renthe s e s a re reference v a lue s . note 1) * 1 : the s e dimen s ion s include re s in protru s ion. note 2) * 2 : the s e dimen s ion s do not include re s in protru s ion. note 3 )pin s width a nd pin s thickne ss include pl a ting thickne ss . note 4) pin s width do not include tie ba r cutting rem a inder.
mb3769a f0605 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. edited business promotion dept.

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