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december 1994 order number: 271327-001 special environment 80960CA-25, -16 32-bit high-performance embedded processor # two instructions/clock sustained execution # four 59 mbytes/s dma channels with data chaining # demultiplexed 32-bit burst bus with pipelining y 32-bit parallel architecture e two instructions/clock execution e load/store architecture e sixteen 32-bit global registers e sixteen 32-bit local registers e manipulates 64-bit bit fields e 11 addressing modes e full parallel fault model e supervisor protection model y fast procedure call/return model e full procedure call in 4 clocks y on-chip register cache e caches registers on call/ret e minimum of 6 frames provided e up to 15 programmable frames y on-chip instruction cache e 1 kbyte two-way set associative e 128-bit path to instruction sequencer e cache-lock modes e cache-off mode y high bandwidth on-chip data ram e 1 kbyte on-chip data ram e sustains 128 bits per clock access y four on-chip dma channels e 59 mbytes/s fly-by transfers e 32 mbytes/s two-cycle transfers e data chaining e data packing/unpacking e programmable priority method y 32-bit demultiplexed burst bus e 128-bit internal data paths to and from registers e burst bus for dram interfacing e address pipelining option e fully programmable wait states e supports 8-, 16- or 32-bit bus widths e supports unaligned accesses e supervisor protection pin y selectable big or little endian byte ordering y high-speed interrupt controller e up to 248 external interrupts e 32 fully programmable priorities e multi-mode 8-bit interrupt port e four internal dma interrupts e separate, non-maskable interrupt pin e context switch in 750 ns typical y product grades available e se3: b 40 cto a 110 c
special environment 80960CA-25, -16 32-bit high-performance embedded processor contents page 1.0 purpose 5 2.0 80960ca overview 5 2.1 the c-series core 6 2.2 pipelined, burst bus 6 2.3 flexible dma controller 6 2.4 priority interrupt controller 6 2.5 instruction set summary 7 3.0 package information 8 3.1 package introduction 8 3.2 pin descriptions 8 3.3 80960ca mechanical data 15 3.3.1 80960ca pga pinout 15 3.4 package thermal specifications 19 3.5 stepping register information 21 3.6 suggested sources for 80960ca accessories 21 4.0 electrical specifications 22 4.1 absolute maximum ratings 22 4.2 operating conditions 22 4.3 recommended connections 22 4.4 dc specifications 23 4.5 ac specifications 24 4.5.1 ac test conditions 28 4.5.2 ac timing waveforms 28 4.5.3 derating curves 32 5.0 reset, backoff and hold acknowledge 34 6.0 bus waveforms 35 7.0 revision history 62 2
contents page list of figures figure 1 80960ca block diagram 5 figure 2 80960ca pga pinouteview from top (pins facing down) 17 figure 3 80960ca pga pinouteview from bottom (pins facing up) 18 figure 4 measuring 80960ca pga case temperature 19 figure 5 register g0 21 figure 6 ac test load 28 figure 7 input and output clocks waveform 28 figure 8 clkin waveform 28 figure 9 output delay and float waveform 29 figure 10 input setup and hold waveform 29 figure 11 nmi , xint7:0 input setup and hold waveform 30 figure 12 hold acknowledge timings 30 figure 13 bus backoff (boff ) timings 31 figure 14 relative timings waveforms 32 figure 15 output delay or hold vs load capacitance 32 figure 16 rise and fall time derating at highest operating temperature and minimum v cc 33 figure 17 i cc vs frequency and temperature 33 figure 18 cold reset waveform 35 figure 19 warm reset waveform 36 figure 20 entering the once state 37 figure 21 clock synchronization in the 2-x clock mode 38 figure 22 clock synchronization in the 1-x clock mode 38 figure 23 non-burst, non-pipelined requests without wait states 39 figure 24 non-burst, non-pipelined read request with wait states 40 figure 25 non-burst, non-pipelined write request with wait states 41 figure 26 burst, non-pipelined read request without wait states, 32-bit bus 42 figure 27 burst, non-pipelined read request with wait states, 32-bit bus 43 figure 28 burst, non-pipelined write request without wait states, 32-bit bus 44 figure 29 burst, non-pipelined write request with wait states, 32-bit bus 45 figure 30 burst, non-pipelined read request with wait states, 16-bit bus 46 figure 31 burst, non-pipelined read request with wait states, 8-bit bus 47 figure 32 non-burst, pipelined read request without wait states, 32-bit bus 48 figure 33 non-burst, pipelined read request with wait states, 32-bit bus 49 figure 34 burst, pipelined read request without wait states, 32-bit bus 50 figure 35 burst, pipelined read request with wait states, 32-bit bus 51 figure 36 burst, pipelined read request with wait states, 16-bit bus 52 figure 37 burst, pipelined read request with wait states, 8-bit bus 53 3
contents page list of figures (continued) figure 38 using external ready 54 figure 39 terminating a burst with bterm 55 figure 40 boff functional timing 56 figure 41 hold functional timing 57 figure 42 dreq and dack functional timing 58 figure 43 eop functional timing 58 figure 44 terminal count functional timing 59 figure 45 fail functional timing 59 figure 46 a summary of aligned and unaligned transfers for little endian regions 60 figure 47 a summary of aligned and unaligned transfers for little endian regions (continued) 61 figure 48 idle bus operation 62 list of tables table 1 80960ca instruction set 7 table 2 pin description nomenclature 8 table 3 80960ca pin descriptioneexternal bus signals 9 table 4 80960ca pin descriptioneprocessor control signals 12 table 5 80960ca pin descriptionedma and interrupt unit control signals 14 table 6 80960ca pga pinoutein signal order 15 table 7 80960ca pga pinoutein pin order 16 table 8 maximum t a at various airflows in c 19 table 9 80960ca pga package thermal characteristics 20 table 10 die stepping cross reference 21 table 11 operating conditions (80960CA-25, -16) 22 table 12 dc characteristics 23 table 13 80960ca ac characteristics (25 mhz) 24 table 14 80960ca ac characteristics (16 mhz) 26 table 15 reset conditions 34 table 16 hold acknowledge and backoff conditions 34 4
special environment 80960CA-25, -16 1.0 purpose this document provides electrical characteristics for the 25 and 16 mhz versions of the 80960ca. for a detailed description of any 80960ca functional topiceother than parametric performanceeconsult the 80960ca product overview (order no. 270669) or the i960 ca microprocessor user's manual (or- der no. 270710). to obtain data sheet updates and errata, please call intel's faxback data-on-de- mand system (1-800-628-2283 or 916-356-3105). other information can be obtained from intel's tech- nical bbs (916-356-3600). 2.0 80960ca overview the 80960ca is the second-generation member of the 80960 family of embedded processors. the 80960ca is object code compatible with the 32-bit 80960 core architecture while including special function register extensions to control on-chip pe- ripherals and instruction set extensions to shift 64-bit operands and configure on-chip hardware. multiple 128-bit internal buses, on-chip instruction caching and a sophisticated instruction scheduler al- low the processor to sustain execution of two in- structions every clock and peak at execution of three instructions per clock. a 32-bit demultiplexed and pipelined burst bus pro- vides a 132 mbyte/s bandwidth to a system's high- speed external memory sub-system. in addition, the 80960ca's on-chip caching of instructions, proce- dure context and critical program data substantially decouple system performance from the wait states associated with accesses to the system's slower, cost sensitive, main memory subsystem. the 80960ca bus controller integrates full wait state and bus width control for highest system perform- ance with minimal system design complexity. un- aligned access and big endian byte order support reduces the cost of porting existing applications to the 80960ca. the processor also integrates four complete data- chaining dma channels and a high-speed interrupt controller on-chip. dma channels perform: single- cycle or two-cycle transfers, data packing and un- packing and data chaining. block transfersein addi- tion to source or destination synchronized trans- ferseare provided. the interrupt controller provides full programmability of 248 interrupt sources into 32 priority levels with a typical interrupt task switch (``latency'') time of 750 ns. 271327 1 figure 1. 80960ca block diagram 5
special environment 80960CA-25, -16 2.1 the c-series core the c-series core is a very high performance micro- architectural implementation of the 80960 core ar- chitecture. the c-series core can sustain execution of two instructions per clock (50 mips at 25 mhz). to achieve this level of performance, intel has incor- porated state-of-the-art silicon technology and inno- vative microarchitectural constructs into the imple- mentation of the c-series core. factors that contrib- ute to the core's performance include: # parallel instruction decoding allows issuance of up to three instructions per clock # single-clock execution of most instructions # parallel instruction decode allows sustained, simultaneous execution of two single-clock in- structions every clock cycle # efficient instruction pipeline minimizes pipeline break losses # register and resource scoreboarding allow simul- taneous multi-clock instruction execution # branch look-ahead and prediction allows many branches to execute with no pipeline break # local register cache integrated on-chip caches call/return context # two-way set associative, 1 kbyte integrated in- struction cache # 1 kbyte integrated data ram sustains a four- word (128-bit) access every clock cycle 2.2 pipelined, burst bus a 32-bit high performance bus controller interfaces the 80960ca to external memory and peripherals. the bus control unit features a maximum transfer rate of 100 mbytes per second (at 25 mhz). internal- ly programmable wait states and 16 separately con- figurable memory regions allow the processor to in- terface with a variety of memory subsystems with a minimum of system complexity and a maximum of performance. the bus controller's main features in- clude: # demultiplexed, burst bus to exploit most efficient dram access modes # address pipelining to reduce memory cost while maintaining performance # 32-, 16- and 8-bit modes for i/o interfacing ease # full internal wait state generation to reduce sys- tem cost # little and big endian support to ease application development # unaligned access support for code portability # three-deep request queue to decouple the bus from the core 2.3 flexible dma controller a four-channel dma controller provides high speed dma control for data transfers involving peripherals and memory. the dma provides advanced features such as data chaining, byte assembly and disassem- bly and a high performance fly-by mode capable of transfer speeds of up to 45 mbytes per second at 25 mhz. the dma controller features a performance and flexibility which is only possible by integrating the dma controller and the 80960ca core. 2.4 priority interrupt controller a programmable-priority interrupt controller man- ages up to 248 external sources through the 8-bit external interrupt port. the interrupt unit also han- dles the four internal sources from the dma control- ler and a single non-maskable interrupt input. the 8-bit interrupt port can also be configured to provide individual interrupt sources that are level or edge triggered. interrupts in the 80960ca are prioritized and sig- naled within 270 ns of the request. if the interrupt is of higher priority than the processor priority, the con- text switch to the interrupt routine typically is com- plete in another 480 ns. the interrupt unit provides the mechanism for the low latency and high through- put interrupt service which is essential for embedded applications. 6
special environment 80960CA-25, -16 2.5 instruction set summary table 1 summarizes the 80960ca instruction set by logical groupings. see the i960 ca microprocessor user's manual for a complete description of the instruction set. table 1. 80960ca instruction set data arithmetic logical bit and bit field movement and byte load add and set bit store subtract not and clear bit move multiply and not not bit load address divide or alter bit remainder exclusive or scan for bit modulo not or span over bit shift or not extract * extended shift nor modify extended multiply exclusive nor scan byte for equal extended divide not add with carry nand subtract with carry rotate comparison branch call/return fault compare unconditional branch call conditional fault conditional compare conditional branch call extended synchronize faults compare and increment compare and branch call system compare and decrement return test condition code branch and link check bit debug processor atomic management modify trace controls flush local registers atomic add mark modify arithmetic controls atomic modify force mark modify process controls * system control * dma control notes: instructions marked by ( * ) are 80960ca extensions to the 80960 instruction set 7
special environment 80960CA-25, -16 3.0 package information 3.1 package introduction this section describes the pins, pinouts and thermal characteristics for the 80960ca in the 168-pin ce- ramic pin grid array (pga) package. for complete package specifications and information, see the packaging handbook (order no. 240800). 3.2 pin descriptions the 80960ca pins are described in this section. ta- ble 2 presents the legend for interpreting the pin de- scriptions in the following tables. pins associated with the 32-bit demultiplexed processor bus are de- scribed in table 3. pins associated with basic proc- essor configuration and control are described in ta- ble 4. pins associated with the 80960ca dma con- troller and interrupt unit are described in table 5. all pins float while the processor is in the once mode. table 2. pin description nomenclature symbol description i input only pin o output only pin i/o pin can be either an input or output e pins ``must be'' connected as described s(...) synchronous. inputs must meet setup and hold times relative to pclk2:1 for proper operation. all outputs are synchronous to pclk2:1. s(e) edge sensitive input s(l) level sensitive input a(...) asynchronous. inputs may be asynchronous to pclk2:1. a(e) edge sensitive input a(l) level sensitive input h(...) while the processor's bus is in the hold acknowledge or bus backoff state, the pin: h(1) is driven to v cc h(0) is driven to v ss h(z) floats h(q) continues to be a valid input r(...) while the processor's reset pin is low, the pin: r(1) is driven to v cc r(0) is driven to v ss r(z) floats r(q) continues to be a valid output 8
special environment 80960CA-25, -16 table 3. 80960ca pin descriptioneexternal bus signals name type description a31:2 o address bus carries the physical address' upper 30 bits. a31 is the most significant address bit; a2 is the least significant. during a bus access, a31:2 s identify all external addresses to word (4-byte) boundaries. the byte enable signals h(z) indicate the selected byte in each word. during burst accesses, a3:2 increment to r(z) indicate successive data cycles. d31:0 i/o data bus carries 32-, 16- or 8-bit data quantities depending on bus width configuration. the least significant bit of the data is carried on d0 and the most s(l) significant on d31. when the bus is configured for 8-bit data, the lower 8 data lines, h(z) d7:0 are used. for 16-bit data bus widths, d15:0 are used. for 32 bit bus widths the r(z) full data bus is used. be3:0 o byte enables select which of the four bytes addressed by a31:2 are active during an access to a memory region configured for a 32-bit data-bus width. be3 s applies to d31:24; be2 applies to d23:16; be1 applies to d15:8; be0 applies to h(z) d7:0. r(1) 32-bit bus: be3 ebyte enable 3 eenable d31:24 be2 ebyte enable 2 eenable d23:16 be1 ebyte enable 1 eenable d15:8 be0 ebyte enable 0 eenable d7:0 for accesses to a memory region configured for a 16-bit data-bus width, the processor uses the be3 , be1 and be0 pins as bhe , a1 and ble respectively. 16-bit bus: be3 ebyte high enable (bhe ) eenable d15:8 be2 enot used (driven high or low) be1 eaddress bit 1 (a1) be0 ebyte low enable (ble ) eenable d7:0 for accesses to a memory region configured for an 8-bit data-bus width, the processor uses the be1 and be0 pins as a1 and a0 respectively. 8-bit bus: be3 enot used (driven high or low) be2 enot used (driven high or low) be1 eaddress bit 1 (a1) be0 eaddress bit 0 (a0) w/r o write/read is asserted for read requests and deasserted for write requests. the w/r signal changes in the same clock cycle as ads . it remains valid for the entire s access in non-pipelined regions. in pipelined regions, w/r is not guaranteed to be h(z) valid in the last cycle of a read access. r(0) ads o address strobe indicates a valid address and the start of a new bus access. ads is asserted for the first clock of a bus access. s h(z) r(1) 9
special environment 80960CA-25, -16 table 3. 80960ca pin descriptioneexternal bus signals (continued) name type description ready i ready is an input which signals the termination of a data transfer. ready is used to indicate that read data on the bus is valid or that a write-data transfer s(l) has completed. the ready signal works in conjunction with the internally h(z) programmed wait-state generator. if ready is enabled in a region, the pin is r(z) sampled after the programmed number of wait-states has expired. if the ready pin is deasserted, wait states continue to be inserted until ready becomes asserted. this is true for the n rad ,n rdd ,n wad and n wdd wait states. the n xda wait states cannot be extended. bterm i burst terminate is an input which breaks up a burst access and causes another address cycle to occur. the bterm signal works in conjunction with s(l) the internally programmed wait-state generator. if ready and bterm are h(z) enabled in a region, the bterm pin is sampled after the programmed number r(z) of wait states has expired. when bterm is asserted, a new ads signal is generated and the access is completed. the ready input is ignored when bterm is asserted. bterm must be externally synchronized to satisfy bterm setup and hold times. wait o wait indicates internal wait state generator status. wait is asserted when wait states are being caused by the internal wait state generator and not by s the ready or bterm inputs. wait can be used to derive a write-data h(z) strobe. wait can also be thought of as a ready output that the processor r(1) provides when it is inserting wait states. blast o burst last indicates the last transfer in a bus access. blast is asserted in the last data transfer of burst and non-burst accesses after the wait state s counter reaches zero. blast remains asserted until the clock following the h(z) last cycle of the last data transfer of a bus access. if the ready or bterm r(0) input is used to extend wait states, the blast signal remains asserted until ready or bterm terminates the access. dt/r o data transmit/receive indicates direction for data transceivers. dt/r is used in conjunction with den to provide control for data transceivers s attached to the external bus. when dt/r is asserted, the signal indicates that h(z) the processor receives data. conversely, when deasserted, the processor r(0) sends data. dt/r changes only while den is high. den o data enable indicates data cycles in a bus request. den is asserted at the start of the bus request first data cycle and is deasserted at the end of the last s data cycle. den is used in conjunction with dt/r to provide control for data h(z) transceivers attached to the external bus. den remains asserted for r(1) sequential reads from pipelined memory regions. den is deasserted when dt/r changes. lock o bus lock indicates that an atomic read-modify-write operation is in progress. lock may be used to prevent external agents from accessing s memory which is currently involved in an atomic operation. lock is asserted h(z) in the first clock of an atomic operation and deasserted in the clock cycle r(1) following the last bus access for the atomic operation. to allow the most flexibility for memory system enforcement of locked accesses, the processor acknowledges a bus hold request when lock is asserted. the processor performs dma transfers while lock is active. hold i hold request signals that an external agent requests access to the external bus. the processor asserts holda after completing the current bus s(l) request. hold, holda and breq are used together to arbitrate access to h(z) the processor's external bus by external bus agents. r(z) 10
special environment 80960CA-25, -16 table 3. 80960ca pin descriptioneexternal bus signals (continued) name type description boff i bus backoff , when asserted, suspends the current access and causes the bus pins to float. when boff is deasserted, the ads signal is asserted s(l) on the next clock cycle and the access is resumed. h(z) r(z) holda o hold acknowledge indicates to a bus requestor that the processor has relinquished control of the external bus. when holda is asserted, the s external address bus, data bus and bus control signals are floated. hold, h(1) boff , holda and breq are used together to arbitrate access to the r(q) processor's external bus by external bus agents. since the processor grants hold requests and enters the hold acknowledge state even while reset is asserted, the state of the holda pin is independent of the reset pin. breq o bus request is asserted when the bus controller has a request pending. breq can be used by external bus arbitration logic in conjunction with hold s and holda to determine when to return mastership of the external bus to the h(q) processor. r(0) d/c o data or code is asserted for a data request and deasserted for instruction requests. d/c has the same timing as w/r . s h(z) r(z) dma o dma access indicates whether the bus request was initiated by the dma controller. dma is asserted for any dma request. dma is deasserted for all s other requests. h(z) r(z) sup o supervisor access indicates whether the bus request is issued while in supervisor mode. sup is asserted when the request has supervisor privileges s and is deasserted otherwise. sup can be used to isolate supervisor code and h(z) data structures from non-supervisor requests. r(z) 11
special environment 80960CA-25, -16 table 4. 80960ca pin descriptioneprocessor control signals name type description reset i reset causes the chip to reset. when reset is asserted, all external signals return to the reset state. when reset is deasserted, initialization begins. when the 2-x clock a(l) mode is selected, reset must remain asserted for 32 clkin cycles before being h(z) deasserted to guarantee correct processor initialization. when the 1-x clock mode is r(z) selected, reset must remain asserted for 10,000 clkin cycles before being deasserted to guarantee correct processor initialization. the clkmode pin selects 1-x or 2-x input clock division of the clkin pin. the processor's hold acknowledge bus state functions while the chip is reset. if the processor's bus is in the hold acknowledge state when reset is asserted, the processor will internally reset, but maintains the hold acknowledge state on external pins until the hold request is removed. if a hold request is made while the processor is in the reset state, the processor bus will grant holda and enter the hold acknowledge state. fail o fail indicates failure of the processor's self-test performed at initialization. when reset is deasserted and the processor begins initialization, the fail pin is asserted. an internal s self-test is performed as part of the initialization process. if this self-test passes, the fail h(q) pin is deasserted; otherwise it remains asserted. the fail pin is reasserted while the r(0) processor performs an external bus self-confidence test. if this self-test passes, the processor deasserts the fail pin and branches to the user's initialization routine; otherwise the fail pin remains asserted. internal self-test and the use of the fail pin can be disabled with the stest pin. stest i self test causes the processor's internal self-test feature to be enabled or disabled at initialization. stest is read on the rising edge of reset . when asserted, the processor's s(l) internal self-test and external bus confidence tests are performed during processor h(z) initialization. when deasserted, only the bus confidence tests are performed during r(z) initialization. once i on circuit emulation , when asserted, causes all outputs to be floated. once is continuously sampled while reset is low and is latched on the rising edge of reset .to a(l) place the processor in the once state: h(z) (1) assert reset and once (order does not matter) r(z) (2) wait for at least 16 clkin periods in 2-x modeeor 10,000 clkin periods in 1-x modeeafter v cc and clkin are within operating specifications (3) deassert reset (4) wait at least 32 clkin periods (the processor will now be latched in the once state as long as reset is high.) to exit the once state. bring v cc and clkin to operating conditions, then assert reset and bring once high prior to deasserting reset . clkin must operate within the specified operating conditions of the processor until step 4 above has been completed. clkin may then be changed to dc to achieve the lowest possible once mode leakage current. once can be used by emulator products or for board testers to effectively make an installed processor transparent in the board. 12
special environment 80960CA-25, -16 table 4. 80960ca pin descriptioneprocessor control signals (continued) name type description clkin i clock input is an input for the external clock needed to run the processor. the external clock is internally divided as prescribed by the clkmode pin to produce a(e) pclk2:1. h(z) r(z) clkmode i clock mode selects the division factor applied to the external clock input (clkin). when clkmode is high, clkin is divided by one to create pclk2:1 and the a(l) processor's internal clock. when clkmode is low, clkin is divided by two to create h(z) pclk2:1 and the processor's internal clock. clkmode should be tied high or low in a r(z) system as the clock mode is not latched by the processor. if left unconnected, the processor will internally pull the clkmode pin low, enabling the 2-x clock mode. pclk2:1 o processor output clocks provide a timing reference for all processor inputs and outputs. all input and output timings are specified in relation to pclk2 and s pclk1. pclk2 and pclk1 are identical signals. two output pins are provided to allow h(q) flexibility in the system's allocation of capacitive loading on the clock. pclk2:1 may r(q) also be connected at the processor to form a single clock signal. v ss e ground connections must be connected externally to a v ss board plane. v cc e power connections must be connected externally to a v cc board pane. v ccpll e v ccpll is a separate v cc supply pin for the phase lock loop used in 1-x clock mode. connecting a simple lowpass filter to v ccpll may help reduce clock jitter (t cp )in noisy environments. otherwise, v ccpll should be connected to v cc . this pin is implemented starting with the d-stepping. see table 13 for die stepping information. nc e no connect pins must not be connected in a system. 13
special environment 80960CA-25, -16 table 5. 80960ca pin descriptionedma and interrupt unit control signals name type description dreq3:0 i dma request causes a dma transfer to be requested. each of the four signals requests a transfer on a single channel. dreq0 requests channel 0, a(l) dreq1 requests channel 1, etc. when two or more channels are requested h(z) simultaneously, the channel with the highest priority is serviced first. the r(z) channel priority mode is programmable. dack3:0 o dma acknowledge indicates that a dma transfer is being executed. each of the four signals acknowledges a transfer for a single channel. dack0 s acknowledges channel 0, dack1 acknowledges channel 1, etc. dack3:0 are h(1) asserted when the requesting device of a dma is accessed. r(1) eop /tc3:0 i/o end of process/terminal count can be programmed as either an input (eop3:0 ) or as an output (tc3:0 ), but not both. each pin is individually a(l) programmable. when programmed as an input, eopx causes the termination h(z/q) of a current dma transfer for the channel corresponding to the eopx pin. r(z) eop0 corresponds to channel 0, eop1 corresponds to channel 1, etc. when a channel is configured for source and destination chaining, the eop pin for that channel causes termination of only the current buffer transferred and causes the next buffer to be transferred. eop3:0 are asynchronous inputs. when programmed as an output, the channel's tcx pin indicates that the channel byte count has reached 0 and a dma has terminated. tcx is driven with the same timing as dackx during the last dma transfer for a buffer. if the last bus request is executed as multiple bus accesses, tcx will stay asserted for the entire bus request. xint7:0 i external interrupt pins cause interrupts to be requested. these pins can be configured in three modes: a(e/l) dedicated mode: each pin is a dedicated external interrupt source. h(z) dedicated inputs can be individually programmed to r(z) be level (low) or edge (falling) activated. expanded mode: the eight pins act together as an 8-bit vectored interrupt source. the interrupt pins in this mode are level activated. since the interrupt pins are active low, the vector number requested is the one's complement of the positive logic value place on the port. this eliminates glue logic to interface to combinational priority encoders which output negative logic. mixed mode: xint7:5 are dedicated sources and xint4:0 act as the five most significant bits of an expanded mode vector. the least significant bits are set to 010 internally. nmi i non-maskable interrupt causes a non-maskable interrupt event to occur. nmi is the highest priority interrupt recognized. nmi is an edge (falling) a(e) activated source. h(z) r(z) 14
special environment 80960CA-25, -16 3.3 80960ca mechanical data 3.3.1 80960ca pga pinout tables 6 and 7 list the 80960ca pin names with package location. figure 2 depicts the complete 80960ca pga pinout as viewed from the top side of the component (i.e., pins facing down). figure 3 shows the complete 80960ca pga pinout as viewed from the pin-side of the package (i.e., pins facing up). see section 4.0, electrical speci- fications for specifications and recommended connections. table 6. 80960ca pga pinoutein signal order address bus data bus bus control processor control i/o signal pin signal pin signal pin signal pin signal pin a31 s15 d31 r3 be3 s5 reset a16 dreq3 a7 a30 q13 d30 q5 be2 s6 dreq2 b6 a29 r14 d29 s2 be1 s7 fail a2 dreq1 a6 a28 q14 d28 q4 be0 r9 dreq0 b5 a27 s16 d27 r2 stest b2 a26 r15 d26 q3 w/r s10 dack3 a10 a25 s17 d25 s1 once c3 dack2 a9 a24 q15 d24 r1 ads r6 dack1 a8 a23 r16 d23 q2 clkin c13 dack0 b8 a22 r17 d22 p3 ready s3 clkmode c14 a21 q16 d21 q1 bterm r4 plck1 b14 eop /tc3 a14 a20 p15 d20 p2 plck2 b13 eop /tc2 a13 a19 p16 d19 p1 wait s12 eop /tc1 a12 a18 q17 d18 n2 blast s8 v ss eop /tc0 a11 a17 p17 d17 n1 location a16 n16 d16 m1 dt/r s11 q8, q9, q10, q11 l15, m3, m15, q7, j15, k3, k15, l3, g15, h3, h15, j3, c11, c12, f15, g3, c7, c8, c9, c10, xint7 c17 a15 n17 d15 l1 den s9 xint6 c16 a14 m17 d14 l2 xint5 b17 a13 l16 d13 k1 lock s14 xint4 c15 a12 l17 d12 j1 xint3 b16 a11 k17 d11 h1 v cc xint2 a17 a10 j17 d10 h2 hold r5 location xint1 a15 a9 h17 d9 g1 holda s4 r8, r10, r11 n3, n15, q6, r7, k2, k16, m2, m16, g2, h16, j2, j16, c6, e15, f3, f16, b7, b9, b11, b12, xint0 b15 a8 g17 d8 f1 breq r13 a7 g16 d7 e1 nmi d15 a6 f17 d6 f2 d/c s13 a5 e17 d5 d1 dma r12 a4 e16 d4 e2 sup q12 v ccpll b10 a3 d17 d3 c1 no connect a2 d16 d2 d2 boff b1 location d1 c2 b4, c4, c5, d3 a1, a3, a4, a5, b3, d0 e3 15
special environment 80960CA-25, -16 table 7. 80960ca pga pinoutein pin order pin signal pin signal pin signal pin signal pin signal a1 nc c1 d3 g1 d9 m1 d16 r1 d24 a2 fail c2 d1 g2 v cc m2 v cc r2 d27 a3 nc c3 once g3 v ss m3 v ss r3 d31 a4 nc c4 nc g15 v ss m15 v ss r4 bterm a5 nc c5 nc g16 a7 m16 v cc r5 hold a6 dreq1 c6 v cc g17 a8 m17 a14 r6 ads a7 dreq3 c7 v ss r7 v cc a8 dack1 c8 v ss h1 d11 n1 d17 r8 v cc a9 dack2 c9 v ss h2 d10 n2 d18 r9 be0 a10 dack3 c10 v ss h3 v ss n3 v cc r10 v cc a11 eop /tc0 c11 v ss h15 v ss n15 v cc r11 v cc a12 eop /tc1 c12 v ss h16 v cc n16 a16 r12 dma a13 eop /tc2 c13 clkin h17 a9 n17 a15 r13 breq a14 eop /tc3 c14 clkmode r14 a29 a15 xint1 c15 xint4 j1 d12 p1 d19 r15 a26 a16 reset c16 xint6 j2 v cc p2 d20 r16 a23 a17 xint2 c17 xint7 j3 v ss p3 d22 r17 a22 j15 v ss p15 a20 b1 boff d1 d5 j16 v cc p16 a19 s1 d25 b2 stest d2 d2 j17 a10 p17 a17 s2 d29 b3 nc d3 nc s3 ready b4 nc d15 nmi k1 d13 q1 d21 s4 holda b5 dreq0 d16 a2 k2 v cc q2 d23 s5 be3 b6 dreq2 d17 a3 k3 v ss q3 d26 56 be2 b7 v cc k15 v ss q4 q28 s7 be1 b8 dack0 e1 d7 k16 v cc q5 d30 s8 blast b9 v cc e2 d4 k17 a11 q6 v cc s9 den b10 v ccpll e3 d0 q7 v ss s10 w/r b11 v cc e15 v cc l1 d15 q8 v ss s11 dt/r b12 v cc e16 a4 l2 d14 q9 v ss s12 wait b13 pclk2 e17 a5 l3 v ss q10 v ss s13 d/c b14 pclk1 l15 v ss q11 v ss s14 lock b15 xint0 f1 d8 l16 a13 q12 sup s15 a31 b16 xint3 f2 d6 l17 a12 q13 a30 s16 a27 b17 xint5 f3 v cc q14 a28 s17 a25 f15 v ss q15 a24 f16 v cc q16 a21 f17 a6 q17 a18 16
special environment 80960CA-25, -16 271327 2 figure 2. 80960ca pga pinouteview from top (pins facing down) 17
special environment 80960CA-25, -16 271327 3 figure 3. 80960ca pga pinouteview from bottom (pins facing up) 18
special environment 80960CA-25, -16 3.4 package thermal specifications the 80960ca is specified for operation when t c (case temperature) is within the range of b 40 c a 110 c. t c may be measured in any environment to determine whether the 80960ca is within speci- fied operating range. case temperature should be measured at the center of the top surface, opposite the pins. refer to figure 4. t a (ambient temperature) can be calculated from i ca (thermal resistance from case to ambient) using the following equation: t a e t c b p * i ca table 8 shows the maximum t a allowable (without exceeding t c ) at various airflows and operating fre- quencies (f pclk ). note that t a is greatly improved by attaching fins or a heatsink to the package. p (maximum power con- sumption) is calculated by using the typical i cc as tabulated in section 4.4, dc specifications and v cc of 5v. 271327 4 figure 4. measuring 80960ca pga case temperature table 8. maximum t a at various airflows in c airflow-ft/min (m/sec) f pclk 0 200 400 600 800 1000 (mhz) (0) (1.01) (2.03) (3.04) (4.06) (5.07) t a with 33 51 66 79 81 85 87 heatsink * 25 61 73 83 85 88 89 16 74 82 89 90 92 93 t a without 33 36 47 59 66 73 75 heatsink * 25 49 58 67 73 78 80 16 66 72 78 82 86 87 notes: 0.285 high undirectional heatsink (al alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). 19
special environment 80960CA-25, -16 table 9. 80960ca pga package thermal characteristics thermal resistancee c/watt parameter airfloweft/min (m/sec) 0 200 400 600 800 1000 (0) (1.01) (2.03) (3.07) (4.06) (5.07) i junction-to-case (case measured as 1.5 1.5 1.5 1.5 1.5 1.5 shown in figure 4) i case-to-ambient 17 14 11 9 7.1 6.6 (no heatsink) i case-to-ambient 13 9 5.5 5 3.9 3.4 (with heatsink) * notes: 1. this table applies to 80960ca pga plugged into socket or soldered directly to board. 2. i ja e i jc a i ca . * 0.285 high unidirectional heatsink (al alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). 20
special environment 80960CA-25, -16 3.5 stepping register information upon reset, register g0 contains die stepping infor- mation. figure 5 shows how g0 is configured. the most significant byte contains an ascii 0. the upper middle byte contains an ascii c. the lower middle byte contains an ascii a. the least significant byte contains the stepping number in ascii. g0 retains this information until it is overwritten by the user pro- gram. ascii 00 43 41 stepping number decimal 0 c a stepping number msb lsb figure 5. register g0 table 10 contains a cross reference of the number in the least significant byte of register g0 to the die stepping number. table 10. die stepping cross reference g0 least significant die stepping byte 01 b 02 c-1 03 c-2,c-3 04 d 3.6 suggested sources for 80960ca accessories the following is a list of suggested sources for 80960ca accessories. this is not an endorsement of any kind, nor is it a warranty of the performance of any of the listed products and/or companies. sockets 1. 3m textool test and interconnection products department p.o. box 2963 austin, tx 78769-2963 2. augat, inc. interconnection products group 33 perry avenue p.o. box 779 attleboro, ma 02703 (508) 699-7646 3. concept manufacturing, inc. (decoupling sockets) 41484 christy street fremont, ca 94538 (415) 651-3804 heatsinks/fins 1. thermalloy, inc. 2021 west valley view lane dallas, tx 75234-8993 (214) 243-4321 fax: (214) 241-4656 2. e g & g division 60 audubon road wakefield, ma 01880 (617) 245-5900 21
special environment 80960CA-25, -16 4.0 electrical specifications 4.1 absolute maximum ratings storage temperature b 65 cto a 150 c case temperature under bias b 40 cto a 110 c supply voltage with respect to v ss b 0.5v to a 6.5v voltage on other pins with respect to v ss b 0.5v to v cc a 0.5v notice: this is a production data sheet. the specifi- cations are subject to change without notice. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. 4.2 operating conditions table 11. operating conditons (80960CA-25, -16) symbol parameter min max units notes v cc supply voltage 80960CA-25 4.50 5.50 v 80960ca-16 4.50 5.50 v f clk2x input clock frequency (2-x mode) 80960CA-25 0 50 mhz 80960ca-16 0 32 mhz f clk1x input clock frequency (1-x mode) 80960CA-25 8 25 mhz (note 1) 80960ca-16 8 16 mhz t c case temperature under bias pga package b 40 a 110 c 80960CA-25, -16 notes: 1. when in the 1-x input clock mode, clkin is an input to an internal phase-locked loop and must maintain a minimum frequency of 8 mhz for proper processor operation. however, in the 1-x mode, clkin may still be stopped when the processor either is in a reset condition or is reset. if clkin is stopped, the specified reset low time must be provided once clkin restarts and has stabilized. 2. case temperatures are ``instant on''. 4.3 recommended connections power and ground connections must be made to multiple v cc and v ss (gnd) pins. every 80960ca- based circuit board should include power (v cc ) and ground (v ss ) planes for power distribution. every v cc pin must be connected to the power plane, and every v ss pin must be connected to the ground plane. pins identified as ``nc'' must not be connect- ed in the system. liberal decoupling capacitance should be placed near the 80960ca. the processor can cause tran- sient power surges when its numerous output buff- ers transition, particularly when connected to large capacitive loads. low inductance capacitors and interconnects are recommended for best high frequency electrical per- formance. inductance can be reduced by shortening the board traces between the processor and decou- pling capacitors as much as possible. capacitors specifically designed for pga packages will offer the lowest possible inductance. for reliable operation, always connect unused in- puts to an appropriate signal level. in particular, any unused interrupt (xint , nmi ) or dma (dreq ) input should be connected to v cc through a pull-up resis- tor, as should bterm if not used. pull-up resistors should be in the in the range of 20 k x for each pin tied high. if ready or hold are not used, the un- used input should be connected to ground. n.c. pins must always remain unconnected. refer to the i960 ca microprocessor user's manual (order number 270710) for more information. 22
special environment 80960CA-25, -16 4.4 dc specifications table 12. dc characteristics (80960CA-25, -16 under the conditions described in section 4.2, operating conditions .) symbol parameter min max units notes v il input low voltage for all pins except reset b 0.3 a 0.8 v v ih input high voltage for all pins except reset 2.0 v cc a 0.3 v v ol output low voltage 0.45 v i ol e 5ma v oh output high voltage i oh eb 1 ma 2.4 v i oh eb 200 m av cc b 0.5 v v ilr input low voltage for reset b 0.3 1.5 v v ihr input high voltage for reset 3.5 v cc a 0.3 v i li1 input leakage current for each pin except : bterm , once , dreq3:0 , stest, eop3:0 /tc3:0 , nmi , xint7:0 , boff , ready , hold, clkmode g 15 m a0 s v in s v cc (1) i li2 input leakage current for: bterm , once , dreq3:0 , stest, eop3:0 /tc3:0 , nmi , xint7:0 , boff 0 b 325 m av in e 0.45v (2) i li3 input leakage current for: ready , hold, clkmode 0 500 m av in e 2.4v (3,7) i lo output leakage current g 15 m a 0.45 s v out s v cc i cc supply current (80960CA-25): i cc max 750 ma (note 4) i cc typ 600 ma (note 5) i cc supply current (80960ca-16): i cc max 550 ma (note 4) i cc typ 400 ma (note 5) i once once-mode supply current 100 ma c in input capacitance for: clkin, reset , once , ready , hold, dreq3:0 , boff , xint7:0 , nmi , bterm , clkmode 0 12 pf f c e 1 mhz c out output capacitance of each output pin 12 pf f c e 1 mhz (6) c i/o i/o pin capacitance 12 pf f c e 1 mhz notes: 1. no pullup or pulldown. 2. these pins have internal pullup resistors. 3. these pins have internal pulldown resistors. 4. measured at worst case frequency, v cc and temperature, with device operating and outputs loaded to the test conditions described in section 4.5.1, ac test conditions . 5. i cc typical is not tested. 6. output capacitance is the capacitive load of a floating output. 7. clkmode pin has a pulldown resistor only when once pin is deasserted. 23
special environment 80960CA-25, -16 4.5 ac specifications table 13. 80960ca ac characteristics (25 mhz) (80960CA-25 only, under conditions described in section 4.2, operating conditions and section 4.5.1, ac test conditions .) symbol parameter min max units notes input clock (1, 9) t f clkin frequency 0 50 mhz t c clkin period in 1-x mode (f clk1x ) 40 125 ns (11) in 2-x mode (f clk2x )20 % ns t cs clkin period stability in 1-x mode (f clk1x ) g 0.1% d (12) t ch clkin high time in 1-x mode (f clk1x ) 8 62.5 ns (11) in 2-x mode (f clk2x )8 % ns t cl clkin low time in 1-x mode (f clk1x ) 8 62.5 ns (11) in 2-x mode (f clk2x )8 % ns t cr clkin rise time 0 6 ns t cf clkin fall time 0 6 ns output clocks (1, 8) t cp clkin to pclk2:1 delay in 1-x mode (f clk1x ) b 2 2 ns (3, 12) in 2-x mode (f clk2x ) 2 25 ns (3) t pclk2:1 period in 1-x mode (f clk1x )t c ns (12) in 2-x mode (f clk2x )2t c ns (3) t ph pclk2:1 high time (t/2) b 3 t/2 ns (12) t pl pclk2:1 low time (t/2) b 3 t/2 ns (12) t pr pclk2:1 rise time 1 4 ns (3) t pf pclk2:1 fall time 1 4 ns (3) synchronous outputs (8) t oh output valid delay, output hold (6, 10) t ov t oh1 ,t ov1 a31:2 3 16 ns t oh2 ,t ov2 be3:0 318ns t oh3 ,t ov3 ads 620ns t oh4 ,t ov4 w/r 320ns t oh5 ,t ov5 d/c , sup , dma 418ns t oh6 ,t ov6 blast , wait 518ns t oh7 ,t ov7 den 318ns t oh8 ,t ov8 holda, breq 4 18 ns t oh9 ,t ov9 lock 418ns t oh10 ,t ov10 dack3:0 420ns t oh11 ,t ov11 d31:0 3 18 ns t oh12 ,t ov12 dt/r t/2 a 3 t/2 a 16 ns t oh13 ,t ov13 fail 216ns t oh14 ,t ov14 eop3:0 /tc3:0 3 20 ns (6, 10) t of output float for all ouputs 3 22 ns (6) synchronous inputs (1, 9, 10) t is input setup t is1 d31:0 5 ns t is2 boff 19 ns t is3 bterm /ready 9ns t is4 hold 9 ns t ih input hold t ih1 d31:0 5 ns t ih2 boff 7ns t ih3 bterm /ready 2ns t ih4 hold 5 ns 24
special environment 80960CA-25, -16 table 13. 80960ca ac characteristics (25 mhz) (continued) (80960CA-25 only, under conditions described in section 4.2, operating conditions and section 4.5.1, ac test conditions .) symbol parameter min max units notes relative output timings (1, 2, 3, 8) t avsh1 a31:2 valid to ads rising t b 4t a 4ns t avsh2 be3:0 , w/r , sup , d/c , dma , dack3:0 valid to ads rising t b 6t a 6ns t avel1 a31:2 valid to den falling t b 4t a 4ns t avel2 be3:0 , w/r , sup , inst , dma , dack3:0 valid to den falling t b 6t a 6ns t nlqv wait falling to output data valid g 4ns t dvnh output data valid to wait rising n * t b 4n * t a 4 ns (4) t nlnh wait falling to wait rising n * t g 4 ns (4) t nhqx output data hold after wait rising (n a 1) * t b 8(n a 1) * t a 6 ns (5) t ehtv dt/r hold after den high t/2 b 7 % ns (6) t tvel dt/r valid to den falling t/2 b 4ns relative input timings (1, 2, 3) t is5 reset input setup (2-x clock mode) 8 ns (13) t ih5 reset input hold (2-x clock mode) 7 ns (13) t is6 dreq3:0 input setup 14 ns (7) t ih6 dreq3:0 input hold 9 ns (7) t is7 xint7:0 , nmi input setup 10 ns (15) t ih7 xint7:0 , nmi input hold 10 ns (15) t is8 reset input setup (1-x clock mode) 3 ns (14) t ih8 reset input hold (1-x clock mode) t/4 a 1 ns (14) notes: 1. see section 4.5.2, ac timing waveforms for waveforms and definitions. 2. see figure 16 for capacitive derating information for output delays and hold times. 3. see figure 17 for capacitive derating information for rise and fall times. 4. where n is the number of n rad ,n rdd ,n wad or n wdd wait states that are programmed in the bus controller region table. wait never goes active when there are no wait states in an access. 5. n e number of wait states inserted with ready . 6. output data and/or dt/r may be driven indefinitely following a cycle if there is no subsequent bus activity. 7. since asynchronous inputs are synchronized internally by the 80960ca, they have no required setup or hold times to be recognized and for proper operation. however, to guarantee recognition of the input at a particular edge of pclk2:1, the setup times shown must be met. asynchronous inputs must be active for at least two consecutive pclk2:1 rising edges to be seen by the processor. 8. these specifications are guaranteed by the processor. 9. these specifications must be met by the system for proper operation of the processor. 10. this timing is dependent upon the loading of pclk2:1. use the derating curves of section 4.5.3, derating curves to adjust the timing for pclk2:1 loading. 11. in the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. when the processor is in reset, the input clock may stop even in 1-x mode. 12. when in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than g 0.1% between adjacent cycles. 13. in 2-x clock mode, reset is an asynchronous input which has no required setup and hold time for proper operation. however, to guarantee the device exits reset synchronized to a particular clock edge, the reset pin must meet setup and hold times to the falling edge of the clkin. (see figure 21). 14. in 1-x clock mode, reset is an asynchronous input which has no required setup and hold time for proper operation. however, to guarantee the device exits reset synchronized to a particular clock edge, the reset pin must meet setup and hold times to the rising edge of the clkin. (see figure 22.) 15. the interrupt pins are synchronized internally by the 80960ca. they have no required setup or hold times for proper operation. these pins are sampled by the interrupt controller every other clock and must be active for at least three consecutive pclk2:1 rising edges when asserting them asynchronously. to guarantee recognition at a particular clock edge, the setup and hold times shown must be met for two consecutive pclk2:1 rising edges. 25
special environment 80960CA-25, -16 table 14. 80960ca ac characteristics (16 mhz) (80960ca-16 only, under conditions described in section 4.2, operating conditions and section 4.5.1, ac test conditions .) symbol parameter min max units notes input clock (1, 9) t f clkin frequency 0 32 mhz t c clkin period in 1-x mode (f clk1x ) 62.5 125 ns (11) in 2-x mode (f clk2x ) 31.25 % ns t cs clkin period stability in 1-x mode (f clk1x ) g 0.1% d (12) t ch clkin high time in 1-x mode (f clk1x ) 10 62.5 ns (11) in 2-x mode (f clk2x )10 % ns t cl clkin low time in 1-x mode (f clk1x ) 10 62.5 ns (11) in 2-x mode (f clk2x )10 % ns t cr clkin rise time 0 6 ns t cf clkin fall time 0 6 ns output clocks (1, 8) t cp clkin to pclk2:1 delay in 1-x mode (f clk1x ) b 2 2 ns (3, 12) in 2-x mode (f clk2x ) 2 25 ns (3) t pclk2:1 period in 1-x mode (f clk1x )t c ns (12) in 2-x mode (f clk2x )2t c ns (3) t ph pclk2:1 high time (t/2) b 4 t/2 ns (12) t pl pclk2:1 low time (t/2) b 4 t/2 ns (12) t pr pclk2:1 rise time 1 4 ns (3) t pf pclk2:1 fall time 1 4 ns (3) synchronous outputs (8) t oh output valid delay, output hold (6, 10) t ov t oh1 ,t ov1 a31:2 3 18 ns t oh2 ,t ov2 be3:0 320ns t oh3 ,t ov3 ads 622ns t oh4 ,t ov4 w/r 322ns t oh5 ,t ov5 d/c , sup , dma 420ns t oh6 ,t ov6 blast , wait 520ns t oh7 ,t ov7 den 320ns t oh8 ,t ov8 holda, breq 4 20 ns t oh9 ,t ov9 lock 420ns t oh10 ,t ov10 dack3:0 422ns t oh11 ,t ov11 d31:0 3 20 ns t oh12 ,t ov12 dt/r t/2 a 3 t/2 a 18 ns t oh13 ,t ov13 fail 218ns t oh14 ,t ov14 eop3:0 /tc3:0 3 22 ns (6, 10) t of output float for all ouputs 3 22 ns (6) synchronous inputs (1, 9, 10) t is input setup t is1 d31:0 5 ns t is2 boff 21 ns t is3 bterm /ready 9ns t is4 hold 9 ns t ih input hold t ih1 d31:0 5 ns t ih2 boff 7ns t ih3 bterm /ready 2ns t ih4 hold 5 ns 26
special environment 80960CA-25, -16 table 14. 80960ca ac characteristics (16 mhz) (continued) (80960ca-16 only, under conditions described in section 4.2, operating conditions and section 4.5.1, ac test conditions .) symbol parameter min max units notes relative output timings (1, 2, 3, 8) t avsh1 a31:2 valid to ads rising t b 4t a 4ns t avsh2 be3:0 , w/r , sup , d/c , dma , dack3:0 valid to ads rising t b 6t a 6ns t avel1 a31:2 valid to den falling t b 6t a 6ns t avel2 be3:0 , w/r , sup , inst , dma , dack3:0 valid to den falling t b 6t a 6ns t nlqv wait falling to output data valid g 4ns t dvnh output data valid to wait rising n * t b 4n * t a 4 ns (4) t nlnh wait falling to wait rising n * t g 4 ns (4) t nhqx output data hold after wait rising (n a 1) * t b 8(n a 1) * t a 4 ns (5) t ehtv dt/r hold after den high t/2 b 7 % ns (6) t tvel dt/r valid to den falling t/2 b 4ns relative input timings (1, 2, 3) t is5 reset input setup (2-x clock mode) 10 ns (13) t ih5 reset input hold (2-x clock mode) 9 ns (13) t is6 dreq3:0 input setup 16 ns (7) t ih6 dreq3:0 input hold 11 ns (7) t is7 xint7:0 nmi input setup 10 ns (15) t ih7 xint7:0 nmi input hold 10 ns (15) t is8 reset input setup (1-x clock mode) 3 ns (14) t ih8 reset input hold (1-x clock mode) t/4 a 1 ns (14) notes: 1. see section 4.5.2, ac timing waveforms for waveforms and definitions. 2. see figure 16 for capacitive derating information for output delays and hold times. 3. see figure 17 for capacitive derating information for rise and fall times. 4. where n is the number of n rad ,n rdd ,n wad or n wdd wait states that are programmed in the bus controller region table. wait never goes active when there are no wait states in an access. 5. n e number of wait states inserted with ready . 6. output data and/or dt/r may be driven indefinitely following a cycle if there is no subsequent bus activity. 7. since asynchronous inputs are synchronized internally by the 80960ca, they have no required setup or hold times to be recognized and for proper operation. however, to guarantee recognition of the input at a particular edge of pclk2:1, the setup times shown must be met. asynchronous inputs must be active for at least two consecutive pclk2:1 rising edges to be seen by the processor. 8. these specifications are guaranteed by the processor. 9. these specifications must be met by the system for proper operation of the processor. 10. this timing is dependent upon the loading of pclk2:1. use the derating curves of section 4.5.3, derating curves to adjust the timing for pclk2:1 loading. 11. in the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. when the processor is in reset, the input clock may stop even in 1-x mode. 12. when in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than g 0.1% between adjacent cycles. 13. in 2-x clock mode, reset is an asynchronous input which has no required setup and hold time for proper operation. however, to guarantee the device exits reset synchronized to a particular clock edge, the reset pin must meet setup and hold times to the falling edge of the clkin. (see figure 21). 14. in 1-x clock mode, reset is an asynchronous input which has no required setup and hold time for proper operation. however, to guarantee the device exits reset synchronized to a particular clock edge, the reset pin must meet setup and hold times to the rising edge of the clkin. (see figure 22.) 15. the interrupt pins are synchronized internally by the 80960ca. they have no required setup or hold times for proper operation. these pins are sampled by the interrupt controller every other clock and must be active for at least three consecutive pclk2:1 rising edges when asserting them asynchronously. to guarantee recognition at a particular clock edge, the setup and hold times shown must be met for two consecutive pclk2:1 rising edges. 27
special environment 80960CA-25, -16 4.5.1 ac test conditions the ac specifications in section 4.5 are tested with the 50 pf load shown in figure 6. figure 15 shows how timings vary with load capacitance. specifications are measured at the 1.5v crossing point, unless otherwise indicated. input waveforms are assumed to have a rise and fall time of s 2ns from 0.8v to 2.0v. see section 4.5.2, ac timing waveforms for ac spec definitions, test points and illustrations. 271327 6 c l e 50 pf for all signals. figure 6. ac test load 4.5.2 ac timing waveforms 271327 7 figure 7. input and output clock waveforms 271327 8 figure 8. clkin waveform 28
special environment 80960CA-25, -16 271327 9 figure 9. output delay and float waveform 271327 10 figure 10. input setup and hold waveform t ov t oh output delayethe maximum output delay is referred to as the output valid delay (t ov ). the minimum output delay is referred to as the output hold (t oh ). t of output float delayethe output float condition occurs when the maximum output current becomes less than i lo in magnitude. t is t ih input setup and holdethe input setup and hold requirements specify the sampling window during which synchronous inputs must be stable for correct processor operation. 29
special environment 80960CA-25, -16 271327 11 figure 11. nmi , xint7:0 input setup and hold waveform 271327 12 figure 12. hold acknowledge timings t ov t oh output delayethe maximum output delay is referred to as the output valid delay (t ov ). the minimum output delay is referred to as the output hold (t oh ). t of output float delayethe output float condition occurs when the maximum output current becomes less than i lo in magnitude. t is t ih input setup and holdethe input setup and hold requirements specify the sampling window during which synchronous inputs must be stable for correct processor operation. 30
special environment 80960CA-25, -16 271327 13 figure 13. bus backoff boff timings 31
special environment 80960CA-25, -16 271327 14 figure 14. relative timings waveforms 4.5.3 derating curves 271327 15 note: pclk load e 50 pf figure 15. output delay or hold vs load capacitance 32
special environment 80960CA-25, -16 271327 16 a) all outputs except: lock , dma , sup , holda, breq, dack3:0 , eop3:0 /tc3:0 , fail b) lock , dma , sup , holda, breq, dack3:0 , eop3:0 /tc3:0 , fail figure 16. rise and fall time derating at highest operating temperature and minimum v cc 271327 17 i cc i cc under test conditions figure 17. i cc vs frequency and temperature 33
special environment 80960CA-25, -16 5.0 reset, backoff and hold acknowledge table 15 lists the condition of each processor output pin while reset is asserted (low). table 15. reset conditions pins state during reset (holda inactive) 1 a31:2 floating d31:0 floating be3:0 driven high (inactive) w/r driven low (read) ads driven high (inactive) wait driven high (inactive) blast driven low (active) dt/r driven low (receive) den driven high (inactive) lock driven high (inactive) breq driven low (inactive) d/c floating dma floating sup floating fail driven low (active) dack3:0 driven high (inactive) eop3:0 /tc3:0 floating (set to input mode) notes: 1. with regard to bus output pin state only, the hold ac- knowledge state takes precedence over the reset state. although asserting the reset pin will internally reset the processor, the processor's bus output pins will not enter the reset state if it has granted hold acknowledge to a previous hold request (holda is active). further- more, the processor will grant new hold requests and enter the hold acknowledge state even while in reset. for example, if holda is inactive and the processor is in the reset state, then hold is asserted, the process- sor's bus pins enter the hold acknowledge state and holda is granted. the processor will not be able to perform memory accesses until the hold request is re- moved, even if the reset pin is brought high. this op- eration is provided to simplify boot-up synchronization among multiple processors sharing the same bus. table 16 lists the condition of each processor output pin while holda is asserted (low). table 16. hold acknowledge and backoff conditions pins state during holda a31:2 floating d31:0 floating be3:0 floating w/r floating ads floating wait floating blast floating dt/r floating den floating lock floating breq driven (high or low) d/c floating dma floating sup floating fail driven high (inactive) dack3:0 driven high (inactive) eop3:0 /tc3:0 driven (if output) 34
special environment 80960CA-25, -16 6.0 bus waveforms 271327 18 figure 18. cold reset waveform 35
special environment 80960CA-25, -16 271327 19 figure 19. warm reset waveform 36
special environment 80960CA-25, -16 271327 20 figure 20. entering the once state 37
special environment 80960CA-25, -16 271327 21 note: case 1 and case 2 show two possible polarities of pclk2:1 figure 21. clock synchronization in the 2-x clock mode 271327 22 note: in 1x clock mode, the reset pin is actually sampled on the falling edge of 2xclk. 2xclk is an internal signal generated by the pll and is not available on an external pin. therefore, reset is specified relative to the rising edge of clkin. the reset pin is sampled when pclk is high. figure 22. clock synchronization in the 1-x clock mode 38
special environment 80960CA-25, -16 271327 23 figure 23. non-burst, non-pipelined requests without wait states 39
special environment 80960CA-25, -16 271327 24 figure 24. non-burst, non-pipelined read request with wait states 40
special environment 80960CA-25, -16 271327 25 figure 25. non-burst, non-pipelined write request with wait states 41
special environment 80960CA-25, -16 271327 26 figure 26. burst, non-pipelined read request without wait states, 32-bit bus 42
special environment 80960CA-25, -16 271327 27 figure 27. burst, non-pipelined read request with wait states, 32-bit bus 43
special environment 80960CA-25, -16 271327 28 figure 28. burst, non-pipelined write request without wait states, 32-bit bus 44
special environment 80960CA-25, -16 271327 29 figure 29. burst, non-pipelined write request with wait states, 32-bit bus 45
special environment 80960CA-25, -16 271327 30 figure 30. burst, non-pipelined read request with wait states, 16-bit bus 46
special environment 80960CA-25, -16 271327 31 figure 31. burst, non-pipelined read request with wait states, 8-bit bus 47
special environment 80960CA-25, -16 271327 32 figure 32. non-burst, pipelined read request without wait states, 32-bit bus 48
special environment 80960CA-25, -16 271327 33 figure 33. non-burst, pipelined read request with wait states, 32-bit bus 49
special environment 80960CA-25, -16 271327 34 figure 34. burst, pipelined read request without wait states, 32-bit bus 50
special environment 80960CA-25, -16 271327 35 figure 35. burst, pipelined read request with wait states, 32-bit bus 51
special environment 80960CA-25, -16 271327 36 figure 36. burst, pipelined read request with wait states, 16-bit bus 52
special environment 80960CA-25, -16 271327 37 figure 37. burst, pipelined read request with wait states, 8-bit bus 53
special environment 80960CA-25, -16 271327 38 figure 38. using external ready 54
special environment 80960CA-25, -16 271327 39 note: ready adds memory access time to data transfers, whether or not the bus access is a burst access. bterm interrupts a bus access, whether or not the bus access has more data transfers pending. either the ready signal or the bterm signal will terminate a bus access if the signal is asserted during the last (or only) data transfer of the bus access. figure 39. terminating a burst with bterm 55
special environment 80960CA-25, -16 271327 40 note: ready /bterm must be enabled: n rad ,n rdd ,n wad ,n wdd e 0 figure 40. boff functional timing 56
special environment 80960CA-25, -16 271327 41 figure 41. hold functional timing 57
special environment 80960CA-25, -16 271327 42 notes: 1. case 1: dreq must deassert before dack deasserts. applications are fly-by and some packing and unpacking modes in which loads are followed by loads or stores are followed by stores. 2. case 2: dreq must be deasserted by the second clock (rising edge) after dack is driven high. applications are non fly-by transfers and adjacent load-stores or store-loads. 3. dackx is asserted for the duration of a dma bus request. the request may consist of multiple bus accesses (defined by ads and blast . refer to i960 ca microprocessor user's manual for ``access'', ``request'' definitions. figure 42. dreq and dack functional timing 271327 43 note: eop has the same ac timing requirements as dreq to prevent unwanted dma requests. eop is not edge triggered. eop must be held for a minimum of 2 clock cycles then deasserted within 15 clock cycles. figure 43. eop functional timing 58
special environment 80960CA-25, -16 271327 44 notes: terminal count becomes active during the last bus request of a buffer if the last load/store bus request is executed as multiple bus accesses, the tc will be active for the entire bus request. refer to the i960 ca microprocessor user's manual for further information. figure 44. terminal count functional timing 271327 45 figure 45. fail functional timing 59
special environment 80960CA-25, -16 271327 46 figure 46. a summary of aligned and unaligned transfers for little endian regions 60
special environment 80960CA-25, -16 271327 47 figure 47. a summary of aligned and unaligned transfers for little endian regions (continued) 61
special environment 80960CA-25, -16 271327 48 figure 48. idle bus operation 7.0 revision history new. 62

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