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semiconductor technical data 1 rev 4 ? motorola, inc. 1997 1/97
the mc88915 clock driver utilizes phaselocked loop technology to lock its low skew outputs' frequency and phase onto an input reference clock. it is designed to provide clock distribution for high performance pc's and workstations. the pll allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple components on a board. the pll also allows the mc88915 to multiply a low frequency input clock and distribute it locally at a higher (2x) system frequency. multiple 88915's can lock onto a single reference clock, which is ideal for applications when a central system clock must be distributed synchronously to multiple boards (see figure 7). five aqo outputs (qoq4) are provided with less than 500 ps skew between their rising edges. the q5 output is inverted (180 phase shift) from the aqo outputs. the 2x_q output runs at twice the aqo output frequency, while the q/2 runs at 1/2 the aqo frequency. the vco is designed to run optimally between 20 mhz and the 2x_q fmax specification. the wiring diagrams in figure 5 detail the different feedback configurations which create specific input/output frequency relationships. possible frequency ratios of the aqo outputs to the sync input are 2:1, 1:1, and 1:2. the freq_sel pin provides one bit programmable divideby in the feedback path of the pll. it selects between divideby1 and divideby2 of the vco before its signal reaches the internal clock distribution section of the chip (see the block diagram on page 2). in most applications freq_sel should be held high ( 1). if a low frequency reference clock input is used, holding freq_sel low ( 2) will allow the vco to run in its optimal range (>20 mhz). in normal phaselocked operation the pll_en pin is held high. pulling the pll_en pin low disables the vco and puts the 88915 in a static atest modeo. in this mode there is no frequency limitation on the input clock, which is necessary for a low frequency board test environment. the second sync input can be used as a test clock input to further simplify boardlevel testing (see detailed description on page 11). a lock indicator output (lock) will go high when the loop is in steadystate phase and frequency lock. the lock output will go low if phaselock is lost or when the pll_en pin is low. under certain conditions the lock output may remain low, even though the part is phaselocked. therefore the lock output signal should not be used to drive any active circuitry; it should be used for passive monitoring or evaluation purposes only. yield surface modeling and ysm are trademarks of motorola, inc. features ? five outputs (qoq4) with outputoutput skew < 500 ps each being phase and frequency locked to the sync input ? the phase variation from parttopart between the sync and feedback inputs is less than 550 ps (derived from the t pd specification, which defines the parttopart skew) ? input/output phaselocked frequency ratios of 1:2, 1:1, and 2:1 are available ? input frequency range from 5mhz 2x_q fmax spec ? additional outputs available at 2x and +2 the system aqo frequency. also a q (180 phase shift) output available ? all outputs have 36 ma drive (equal high and low) at cmos levels, and can drive either cmos or ttl inputs. all inputs are ttllevel compatible ? test mode pin (pll_en) provided for low frequency testing. two selectable clock inputs for test or redundancy purposes
pll_en gnd q1 v cc q0 gnd freq_sel lock gnd q2 v cc q3 gnd q/2 rc1 gnd(an) v cc (an) sync[1] sync[0] ref_sel feedback 2x_q rst v cc v cc q4 q5 gnd 25 24 23 22 21 20 19 11 10 9 8 7 6 5 18 17 16 12 13 14 15 26 27 28 4321 28lead pinout (top view) ordering information mc88915fn55 plcc mc88915fn70 plcc fn suffix plastic plcc case 77602
mc88915 motorola timing solutions br1333 e rev 6 2 mc88915 block diagram m u x 0 1 m u x 0 1 mux 1 0 pll_en r r r r r r r rst feedback q/2 q cp d lock q5 q4 q cp d q cp d external rec network (rc1 pin) ref_sel sync (1) sync (0) charge pump/loop filter divide by two q3 q cp d q2 q1 q0 2x_q q cp d q cp d q q cp d ( 1) ( 2) freq_sel oscillator voltage controlled phase/freq. detector reference clock input reference clock input chooses reference between sync[0] & sync[1] selects q output frequency feedback input to phase detector input for external rc network clock output (locked to sync) inverse of clock output 2 x clock output (q) frequency (synchronous) clock output(q) frequency 2 (synchronous) indicates phase lock has been achieved (high when locked) asynchronous reset (active low) disables phaselock for low freq. testing power and ground pins (note pins 8, 10 are aquieto supply pins for internal logic only) input input input input input input output output output output output input input 1 1 1 1 1 1 5 1 1 1 1 1 1 11 pin summary sync[0] sync[1] ref_sel freq_sel feedback rc1 q(04) q5 2x_q q/2 lock rst pll_en v cc ,gnd pin name num i/o function
mc88915 timing solutions br1333 e rev 6 3 motorola dc electrical characteristics (voltages referenced to gnd; t a =0 c to + 70 c, v cc = 5.0v 5%) symbol parameter test conditions v cc v guaranteed limit unit v ih minimum highlevel input voltage v out = 0.1 v or v cc 0.1 v 4.75 5.25 2.0 2.0 v v il maximum lowlevel input voltage v out = 0.1 v or v cc 0.1 v 4.75 5.25 0.8 0.8 v v oh minimum highlevel output voltage v in = v ih or v il i oh = 36 ma 1 4.75 5.25 4.01 4.51 v v ol maximum lowlevel output voltage v in = v ih or v il i ol = 36 ma 1 4.75 5.25 0.44 0.44 v i in maximum input leakage current v i = v cc or gnd 5.25 1.0 m a i cct maximum i cc /input v i = v cc 2.1 v 5.25 1.5 2 ma i old minimum dynamic output current 3 v old = 1.0v max 5.25 88 ma i ohd v ohd = 3.85 v max 5.25 88 ma i cc maximum quiescent supply current (per package) v i = v cc or gnd 5.25 1.0 ma 1. i ol and i oh are 12ma and 12ma respectively for the lock output. 2. the pll_en input pin is not guaranteed to meet this specification. 3. maximum test duration is 2.0ms, one output loaded at a time. capacitance and power specifications symbol parameter typical values unit conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 40 pf v cc = 5.0 v pd 1 power dissipation @ 33mhz with 50 w thevenin termination 15 mw/output 120 mw/device mw v cc = 5.0 v t = 25 c pd 2 power dissipation @ 33mhz with 50 w parallel termination to gnd 37.5 mw/output 300 mw/device mw v cc = 5.0 v t = 25 c sync input timing requirements symbol parameter min max unit t rise , t fall maximum rise and fall times, (sync inputs: from 0.8v 2.0v) 3.0 ns t cycle input clock period (sync inputs) fn55 fn70 200 1 ns t cycle i npu t cl oc k p er i o d (sync i npu t s ) 36 28.5 200 1 ns duty cycle input duty cycle (sync inputs) 50% 25% 1. information in fig. 5 and in the ageneral ac specification noteso, note #3 describes this specification and its actual limits depending on the application. frequency specifications (t a =0 c to + 70 c, v cc = 5.0v 5%, c l = 50pf) guaranteed minimum symbol parameter mc88915fn55 mc88915fn70 unit f max 1 maximum operating frequency (2x_q output) 55 70 mhz maximum operating frequency (q0q4,q5 output) 27.5 35 mhz 1. maximum operating frequency is guaranteed with the part in a phaselocked condition, and all outputs loaded at 50 pf.
mc88915 motorola timing solutions br1333 e rev 6 4 ac electrical characteristics (t a =0 c to +70 c, v cc = 5.0v 5%, c l = 50pf) symbol parameter min max unit t rise , t fall (outputs) rise and fall times, all outputs into a 50 pf, 500 w load (between 0.2v cc and 0.8v cc ) 1.0 2.5 ns t rise , t fall 3 (2x_q output) rise and fall time, 2x_q output into a 20 pf load with termina- tion specified in note 2 (between 0.8 v and 2.0 v) 0.5 1.6 ns t pulse width 3 output pulse width (q0, q1, q3, q4, q5 , q/2 @v cc /2) 0.5t cycle 0.5 0.5t cycle + 0.5 (q0,q1,q3,q4, q5 ,q/2) t cycle = 1/freq. at which the aqo outputs are running ns t pulse width 3 (q2 only) output pulse width (q2 output @ v cc /2) 0.5t cycle 0.6 0.5t cycle + 0.6 t pulse width 3 (2x_q output) output pulse width (2x_q output @ 1.5 v) (see ac note 2) 0.5t cycle 0.5 0.5t cycle + 0.5 ns t pulse width 3 (2x_q output) output pulse width (2x_q output @ v cc /2) 0.5t cycle 1.0 0.5t cycle + 1.0 ns t pd 3 (470k w from rc1 to an.v cc ) (syncfeedback) sync input to feedback delay 1.05 0.50 (meas. @ sync0 or 1 and feedback input pins) (470k w from rc1 to an.gnd) ns (see general ac specification note 4 and fig. 2 for explanation) +1.25 +3.25 t skewr 1,3 (rising) outputtooutput skew between outputs q0 q4, q/2 (rising edges only) 500 ps t skewf 1,3 (falling) outputtooutput skew between outputs q0 q4 (falling edges only) 750 ps t skewall 1,3 outputtooutput skew between outputs 2x_q, q/2, q0 q4 rising, q5 falling 750 ps t lock time required to acquire 2 phaselock from time sync input sig- nal is received. 1 10 ms t phl (reset q) propagation delay, rst to any output (highlow) 1.5 13.5 ns 1. under equally loaded conditions, c l 50pf ( 2pf), and at a fixed temperature and voltage. 2. with v cc fully poweredon and an output properly connected to the feedback pin. t lock max. is with c1 = 0.1 m f, t lock min is with c1 = 0.01 m f. 3. these specifications are not tested, they are guaranteed by statistical characterization. see general ac specification note 1. reset timing requirements 1 symbol parameter minimum unit t rec , rst to sync reset recovery time rising rst edge to falling sync edge 9.0 ns t w , rst low minimum pulse width, rst input low 5.0 ns 1. these reset specs are valid only when pll_en is low and the part is in test mode (not in phaselock)
mc88915 timing solutions br1333 e rev 6 5 motorola general ac specification notes 1. several specifications can only be measured when the mc88915 is in phaselocked operation. it is not possible to have the part in phaselock on ate (automated test equipment). statistical characterization techniques were used to guarantee those specifications which cannot be measured on the ate. mc88915 units were fabricated with key transistor properties intentionally varied to create a 14 cell designed experimental matrix. ic performance was characterized over a range of transistor properties (represented by the 14 cells) in excess of the expected process variation of the wafer fabrication area. response surface modeling (rsm) techniques were used to relate ic performance to the cmos transistor properties over operation voltage and temperature. ic performance to each specification and fab variation were used in conjunction with yield surface modeling ? (ysm ? ) methodology to set performance limits of ate testable specifications within those which are to be guaranteed by statistical characterization. in this way all units passing the ate test will meet or exceed the nontested specifications limits. 2. these two specs (t rlse/fall and t pulse width 2x_q output) guarantee that the mc88915 meets the 25 mhz 68040 pclock input specification (at 50 mhz). for these two specs to be guaranteed by motorola, the termination scheme shown below in figure 1 must be used. 3. the wiring diagrams and written explanations in figure 5 demonstrate the input and output frequency relationships for three possible feedback configurations. the allowable sync input range for each case is also indicated. there are two allowable sync frequency ranges, depending whether freq_sel is high or low. although not shown, it is possible to feed back the q5 output, thus creating a 180 phase shift between the sync input and the aqo outputs. table 1 below summarizes the allowable sync frequency range for each possible configuration. 88915 2x_q output r s z o (clock trace) 68040 pclock input r s = z o 7 w figure 1. mc68040 pclock input termination scheme r p = 1.5 z o r p freq_sel level feedback output allowable sync input frequency range (mhz) corresponding vco frequency range phase relationships of the aqo outputs to rising sync edge high q/2 5 to (2x_q fmax spec)/4 20 to (2x_q fmax spec) 0 high any aqo (q0q4) 10 to (2x_q fmax spec)/2 20 to (2x_q fmax spec) 0 high q5 10 to (2x_q fmax spec)/2 20 to (2x_q fmax spec) 180 high 2x_q 20 to (2x_q fmax spec) 20 to (2x_q fmax spec) 0 low q/2 2.5 to (2x_q fmax spec)/8 20 to (2x_q fmax spec) 0 low any aqo (q0q4) 5 to (2x_q fmax spec)/4 20 to (2x_q fmax spec) 0 low q5 5 to (2x_q fmax spec)/4 20 to (2x_q fmaxspec) 180 low 2x_q 10 to (2x_q fmax spec)/2 20 to (2x_q fmaxspec) 0 table 1. allowable sync input frequency ranges for different feedback configurations. 4. a 1 m w resistor tied to either analog v cc or analog gnd as shown in figure 2 is required to ensure no jitter is present on the mc88915 outputs. this technique causes a phase offset between the sync input and the output connected to the feedback input, measured at the input pins. the t pd spec describes how this offset varies with process, temperature, and voltage. the specs were arrived at by measuring the phase relationship for the 14 lots described in note 1 while the part was in phaselocked operation. the actual measurements were made with a 10 mhz sync input (1.0 ns edge rate from 0.8 v 2.0 v) with the q/2 output fed back. the phase measurements were made at 1.5 v. the q/2 output was terminated at the feedback input with 100 w to v cc and 100 w to ground.
mc88915 motorola timing solutions br1333 e rev 6 6 2.25ns offset with the 470k w resistor tied in this fashion, the t pd specification measured at the input pins is: 330 w r2 330 w r2 feedback output sync input feedback output sync input 5.0v 3.0v 5.0v analog vcc analog gnd rc1 470k w reference resistor 0.1 m f c1 with the 470k w resistor tied in this fashion, the t pd specification measured at the input pins is: external loop filter analog gnd rc1 470k w reference resistor 0.1 m f c1 figure 2. depiction of the fixed sync to feedback offset (tpd) which is present when a 470k w resistor is tied to vcc or ground 3.0v t pd = 2.25ns 1.0ns t pd = 0.775ns 0.275ns 0.775ns offset 5. the t skewr specification guarantees that the rising edges of outputs q/2, q0, q1, q2, q3, and q4 will always fall within a 500ps window within one part. however, if the relative position of each output within this window is not specified, the 500 ps window must be added to each side of the tpd specification limits to calculate the total parttopart skew. for this reason the absolute distribution of these outputs are provided in table 2. when taking the skew data, q0 was used as a reference, so all measurements are relative to this output. the information in table 2 is derived from measurements taken from the 14 process lots described in note 1, over the temperature and voltage range. output (ps) + (ps) q0 0 0 q1 72 40 q2 44 276 q3 40 255 q4 274 34 q/2 16 250 2x_q 633 35 table 2. relative positions of outputs q/2, q0q4, 2x_q, within the 500ps t skewr spec window
mc88915 timing solutions br1333 e rev 6 7 motorola 6. calculation of total outputtoskew between multiple parts (parttopart skew) by combining the t pd specification and the information in note 5, the worst case outputtooutput skew between multiple 88915's connected in parallel can be calculated. this calculation assumes that all parts have a common sync input clock with equal delay of that input signal to each part. this skew value is valid at the 88915 output pins only (equally loaded), it does not include pcb trace delays due to varying loads. with a 1m w resistor tied to analog v cc as shown in note 4, the t pd spec. limits between sync and the q/2 output (connected to the feedback pin) are 1.05ns and 0.5ns. to calculate the skew of any given output between two or more parts, the absolute value of the distribution of that output given in table 2 must be subtracted and added to the lower and upper t pd spec limits respectively. for output q2, [276 (44)] = 320ps is the absolute value of the distribution. therefore [1.05ns 0.32ns] = 1.37ns is the lower t pd limit, and [0.5ns + 0.32ns] = 0.18ns is the upper limit. therefore the worst case skew of output q2 between any number of parts is |(1.37) (0.18)| = 1.19ns. q2 has the worst case skew distribution of any output, so 1.2ns is the absolute worst case outputtooutput skew between multiple parts. 7. note 4 explains that the t pd specification was measured and is guaranteed for the configuration of the q/2 output connected to the feedback pin and the sync input running at 10mhz. the fixed offset (t pd ) as described above has some dependence on the input frequency and at what frequency the vco is running. the graphs of figure 3 demonstrate this dependence. the data presented in figure 3 is from devices representing process extremes, and the measurements were also taken at the voltage extremes (v cc = 5.25v and 4.75v). therefore the data in figure 3 is a realistic representation of the variation of t pd . sync input frequency (mhz) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 5 10 15 20 25 3.5 3.0 2.5 2.0 1.5 1.0 0.5 2.5 5.0 7.5 10.0 12.5 15.0 17.5 2.5 5.0 7.5 10.0 12.5 15.0 17.5 0.5 1.0 1.5 2.0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 tpd sync to feedback (ns) sync input frequency (mhz) figure 3a. t pd versus frequency variation for q/2 output fed back, including process and voltage variation @ 25 c (with 1m w resistor tied to analog v cc ) 0.50 0.75 1.00 1.25 1.50 tpd sync to feedback (ns) tpd sync to feedback (ns) tpd sync to feedback (ns) figure 3b. t pd versus frequency variation for q4 output fed back, including process and voltage variation @ 25 c (with 1m w resistor tied to analog v cc ) figure 3c. t pd versus frequency variation for q/2 output fed back, including process and voltage variation @ 25 c (with 1m w resistor tied to analog gnd) figure 3d. t pd versus frequency variation for q4 output fed back, including process and voltage variation @ 25 c (with 1m w resistor tied to analog gnd) sync input frequency (mhz) sync input frequency (mhz)
mc88915 motorola timing solutions br1333 e rev 6 8 q/2 output t cycle sync input ? the mc88915 aligns rising edges of the feedback input and sync input, therefore the sync input does not require a 50% duty cycle. ? all skew specs are measured between the v cc /2 crossing point of the appropriate output edges.all skews are specified as `windows', not as a deviation around a center point. ? if a aqo output is connected to the feedback input (this situation is not shown), the aqo output frequency would match the sync input frequency, the 2x_q output would run at twice the sync frequency, and the q/2 output would run at half the sync frequency. timing notes: (these waveforms represent the hookup configuration of figure 5a on page 9) feedback input sync input (sync[1] or sync[0]) figure 4. output / input switching waveforms and timing diagrams t cycle aqo outputs 2x_q output q5 output t skewf t skewf t skewr t skewr t skewall q0 q4 outputs pd t
mc88915 timing solutions br1333 e rev 6 9 motorola figure 5c. wiring diagram and frequency relationships with 2x_q output feed back figure 5b. wiring diagram and frequency relationships with q4 output feed back figure 5a. wiring diagram and frequency relationships with q/2 output feed back q4 q4 q5 allowable input frequency range: 20mhz to (2x_q fmax spec) (for freq_sel high) 10mhz to (2x_q fmax spec)/2 (for freq_sel low) allowable input frequency range: 10mhz to (2x_q fmax spec)/2 (for freq_sel high) 5mhz to (2x_q fmax spec)/4 (for freq_sel low) in this application, the 2x_q output is connected to the feedback input. the internal pll will line up the positive edges of 2x_q and sync, thus the 2x_q frequency will equal the sync frequency. the q/2 output will always run at 1/4 the 2x_q fre- quency, and the aqo outputs will run at 1/2 the 2x_q frequency. 2:1 input to aqo output frequency relationship in this application, the q4 output is connected to the feedback input. the internal pll will line up the positive edges of q4 and sync, thus the q4 frequency (and the rest of the aqo outputs) will equal the sync frequency. the q/2 output will al- ways run at 1/2 the aqo frequency, and the 2x_q output will run at 2x the aqo frequency. 1:1 input to aqo output frequency relationship allowable input frequency range: 5mhz to (2x_q fmax spec)/4 (for freq_sel high) 2.5mhz to (2x_q fmax spec)/8 (for freq_sel low) in this application, the q/2 output is connected to the feedback input. the internal pll will line up the positive edges of q/2 and sync, thus the q/2 frequency will equal the sync frequency. the aqo outputs (q0q4, q5 ) will always run at 2x the q/2 frequency, and the 2x_q output will run at 4x the q/2 frequency. 1:2 input to aqo output frequency relationship 25 mhz feedback signal 12.5 mhz feedback signal 12.5 mhz signal 12.5 mhz signal 50 mhz feedback signal 2x_q analog v cc crystal oscillator 50 mhz input high low high high pll_en fq_sel q0 q1 q2 q3 q/2 rst feedback ref_sel sync[0] analog gnd rc1 mc88915 external loop filter 50 mhz signal 2x_q analog v cc crystal oscillator 25 mhz input high low high high pll_en fq_sel q0 q1 q2 q3 q/2 rst feedback ref_sel sync[0] analog gnd rc1 mc88915 external loop filter 50 mhz signal 2x_q analog v cc 25mhz aqo clock outputs crystal oscillator 12.5 mhz input high low high high pll_en fq_sel q0 q1 q2 q3 q/2 q4 rst feedback ref_sel sync[0] analog gnd rc1 mc88915 q5 q5 external loop filter 25mhz aqo clock outputs 25mhz aqo clock outputs
mc88915 motorola timing solutions br1333 e rev 6 10 figure 6. recommended loop filter and analog isolation scheme for the mc88915 47 w board v cc 0.1 m f (loop filter cap) 330 w 470k w 0.1 m f high freq bypass 10 m f low freq bypass 47 w board gnd 8 9 10 analog v cc rc1 analog gnd analog loop filter/vco section of the mc88915 28pin plcc package (not drawn to scale) a separate analog power supply is not necessary and should not be used. following these prescribed guidelines is all that is necessary to use the mc88915 in a normal digital environment. notes concerning loop filter and board layout issues 1. figure 6 shows a loop filter and analog isolation scheme which will be effective in most applications. the following guidelines should be followed to ensure stable and jitterfree operation: 1a.all loop filter and analog isolation components should be tied as close to the package as possible. stray current passing through the parasitics of long traces can cause undesirable voltage transients at the rc1 pin. 1b.the 47 w resistors, the 10 m f low frequency bypass capacitor, and the 0.1 m f high frequency bypass capacitor form a wide bandwidth filter that will minimize the 88915's sensitivity to voltage transients from the system digital v cc supply and ground planes. this filter will typically ensure that a 100mv step deviation on the digital v cc supply will cause no more than a 100ps phase deviation on the 88915 outputs. a 250mv step deviation on v cc using the recommended filter values should cause no more than a 250ps phase deviation; if a 25 m f bypass capacitor is used (instead of 10 m f) a 250mv v cc step should cause no more than a 100ps phase deviation. if good bypass techniques are used on a board design near components which may cause digital v cc and ground noise, the above described v cc step deviations should not occur at the 88915's digital v cc supply. the purpose of the bypass filtering scheme shown in figure 6 is to give the 88915 additional protection from the power supply and ground plane transients that can occur in a high frequency, high speed digital system. 1c.there are no special requirements set forth for the loop filter resistors (470k and 330 w ). the loop filter capacitor (0.1 m f) can be a ceramic chip capacitior, the same as a standard bypass capacitor. 1d.the 470k reference resistor injects current into the internal charge pump of the pll, causing a fixed offset between the outputs and the sync input. this also prevents excessive jitter caused by inherent pll deadband. if the vco (2x_q output) is running above 40mhz, the 470k resistor provides the correct amount of current injection into the charge pump (23 m a). if the vco is running below 40mhz, a 1m w reference resistor should be used (instead of 470k). 2. in addition to the bypass capacitors used in the analog filter of figure 6, there should be a 0.1 m f bypass capacitor between each of the other (digital) four v cc pins and the board ground plane. this will reduce output switching noise caused by the 88915 outputs, in addition to reducing potential for noise in the `analog' section of the chip. these bypass capacitors should also be tied as close to the 88915 package as possible.
mc88915 timing solutions br1333 e rev 6 11 motorola mc88915 system level testing functionality when the pll_en pin is low, the vco is disabled and the 88915 is in low frequency atest modeo. in test mode (with freq_sel high), the 2x_q output is inverted from the selected sync input, and the aqo outputs are divideby2 (negative edge triggered) of the sync input, and the q/2 output is divideby4. with freq_sel low the 2x_q output is divideby2 of the sync, the aqo outputs divideby4, and the q/2 output divideby8. these relationships can be seen on the block diagram. a recommended test configuration would be to use sync0 as the test clock input, and tie pll_en and ref_sel together and connect them to the test select logic. when these inputs are low, the 88915 is in test mode and the sync0 input is selected. this functionality is needed since most boardlevel testers run at 1 mhz or below, and the 88915 cannot lock onto that low of an input frequency. in the test mode described above, any frequency test signal can be used. figure 7. representation of a potential multiprocessing application utilizing the mc88915 for frequency multiplication and low boardtoboard skew mc88915 pll 2f 2f mc88915 pll system clock source cpu card cpu card memory cards cmmu cmmu cmmu cmmu cmmu cpu clock @ f cmmu cmmu cmmu cmmu cmmu cpu 2f pll memory control clock @ 2f at point of use clock @ 2f at point of use distribute clock @ f
mc88915 motorola timing solutions br1333 e rev 6 12 outline dimensions fn suffix plastic package case 77602 issue d notes: 1. datums l, m, and n determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum t, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). n m l v w d d y brk 28 1 view s s lm s 0.010 (0.250) n s t s lm m 0.007 (0.180) n s t 0.004 (0.100) g1 g j c z r e a seating plane s lm m 0.007 (0.180) n s t t b s lm s 0.010 (0.250) n s t s lm m 0.007 (0.180) n s t u s lm m 0.007 (0.180) n s t z g1 x view dd s lm m 0.007 (0.180) n s t k1 view s h k f s lm m 0.007 (0.180) n s t dim min max min max millimeters inches a 0.485 0.495 12.32 12.57 b 0.485 0.495 12.32 12.57 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 0.51 k 0.025 0.64 r 0.450 0.456 11.43 11.58 u 0.450 0.456 11.43 11.58 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y 0.020 0.50 z 2 10 2 10 g1 0.410 0.430 10.42 10.92 k1 0.040 1.02
mc88915 timing solutions br1333 e rev 6 13 motorola motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, 6f seibubutsuryucenter, p.o. box 5405; denver, colorado 80217. 3036752140 or 18004412447 3142 tatsumi kotoku, tokyo 135, japan. 81335218315 mfax ? : rmfax0@email.sps.mot.com touchtone 6 022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok r oad, tai po, n.t., hong kong. 85226629298 mc88915/d ?

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