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AMD-750 chipset overview publication # 23016 rev: a issue date: august 1999 tm
trademarks amd, the amd logo, amd athlon, and combinations thereof, AMD-750, amd-751, and amd-756 are trademarks of advanced micro devices, inc. microsoft and windows are registered trademarks of microsoft corporation. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ? 1999 advanced micro devices, inc. all rights reserved. the contents of this document are provided in connection with advanced micro devices, inc. (amd) products. amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in amds standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. amds products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other applica- tion in which the failure of amds product could create a situation where per- sonal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice.
AMD-750? chipset 1 23016aaugust 1999 AMD-750? chipset overview AMD-750? chipset the amd athlon? processor powers the next generation of computing platforms, delivering the ultimate performance for cutting-edge applications and an unprecedented computing experience. the AMD-750? chipset is a highly integrated system logic solution that delivers enhanced performance for the amd athlon processor and other amd athlon frontside bus-compatible processors. the AMD-750 chipset consists of the amd-751? system controller in a 492-pin plastic ball-grid array (pbga) package and the amd-756? peripheral bus controller. the amd-751 system controller features the amd athlon frontside bus, system memory controller, accelerated graphics port (agp) controller, and peripheral component interconnect (pci) bus controller. the amd-756 peripheral bus controller features three primary blocks (pci-to-isa bridge, usb controller interface, eide udma-33 and -66 controller), each with independent access to the pci bus, a complete set of pci interface signals and state machines, and capable of working independently with separate devices. figure 1 on page 2 shows the block diagram of the AMD-750 chipset system.
2 AMD-750? chipset AMD-750? chipset overview 23016aaugust 1999 figure 1. AMD-750? chipset system block diagram ethernet southbridge agp dram pci bus eide bus system management, reset, initialize, lan scsi 64-bit 64-bit agp bus 32-bit sdram memory bus system controller isa bus 16-bit bios amd athlon? processor amd-751? system controller amd-756? peripheral bus controller interrupts smbus usbus serr# preq# pgnt# wsc# 72-bit frontside bus
amd-751? system controller 3 23016aaugust 1999 AMD-750? chipset overview amd-751? system controller key features of the amd-751 system controller are provided in this section. for more information, see the amd-751? system controller data sheet , order# 21910. the amd-751 system controller is designed with the following features: n the amd athlon frontside bus supports three 200-mhz high-speed channels n the 33-mhz 32-bit pci 2.2-compliant bus interface supports up to six masters n the 66-mhz agp 2.0-compliant interface supports 2x data transfer mode n high-speed memorythe amd-751 system controller is designed to support 100-mhz pc-100 revision 1.0 sdram dimms amd athlon? system bus the amd athlon frontside bus has the following features: n high-performance point-to-point system bus topology n source synchronous clocking for high-speed transfers n hstl-like low-voltage swing transceiver logic signal levels n three 200-mhz independent high-speed channels: ? 13-pin processor request channel ? 13-pin system probe channel ? 72-pin data transfer channel (8-bit ecc) n 1.6 gbytes per second peak-data-transfer rates at 200 mhz n large 64-byte (cache line) data burst transfers n data buffers: ? memory write fifo (mwf) ? memory read fifo (mrf) ? pci/apci (agp-pci) write buffer ? pci/apci read buffer
4 amd-751? system controller AMD-750? chipset overview 23016aaugust 1999 n transaction queues: ? command queue (cq) ? memory write queue (mwq) ? memory read queue (mrq) ? probe (snoop) queue (pq) integrated memory controller the integrated memory controller has the following features: n memory request organizer (mro) serves as a data crossbar, determines request dependencies, and optimizes scheduling of memory requests n the amd-751 system controller supports the following concurrences: ? processor-to-main-memory with pci-to-main-memory ? processor-to-main-memory with agp-to-main-memory ? processor-to-pci with pci-to-main-memory or agp-to-main-memory n memory error correcting code (ecc) support n supports the following dram: ? up to three non-buffered pc-100 revision 1.0 sdram dimms using 16-mbit, 64-mbit, and 128-mbit technology ? 64-bit data width, plus 8-bit ecc paths ? flexible row and column addressing n supports up to 768 mbytes of memory n four open pages within one cs (device selected by chip select) for one quadword n default two-page leapfrog policy for eight quadword requests n bios-configurable memory-timing parameters and configuration parameters n 3.3-v memory interface operation with no external buffers n four cache lines (32 quadwords) of processor-to-dram posted write buffers with full read-around capability n concurrent dram writeback and read-around-write n burst read and write transactions
amd-751? system controller 5 23016aaugust 1999 AMD-750? chipset overview n decoupled and burst dram refresh with staggered cs timing n provides the following refresh options: ? programmable refresh rate ? cas-before-ras ? populated banks only ? chipset powerdown via sdram automatic refresh command ? automatic refresh of idle slotsimproves bus availability for memory access by the processor or system pci bus controller the pci bus controller has the following features: n compliance with pci local bus specification, revision 2.2 n supports six pci masters n 32-bit interface, compatible with 3.3-v and 5-v pci i/o n synchronous pci bus operation up to 33 mhz n pci-initiator peer concurrence n automatic processor-to-pci burst cycle detection n four-entry, 64-bit pci master (processor or agp) write fifo n extensive utilization of fifos n zero wait-state pci initiator and target burst transfers n pci-to-dram data streaming up to 132 mbytes per second n enhanced pci command optimization, such as memory read line (mrl), memory read multiple (mrm), and memory-write-and-invalidate (mwi) n timer-enforced fair arbitration between pci initiators n supports advanced concurrency n supports retry disconnect for improved bus utilization n pci read buffer keeps track of each master n pci target request queue
6 amd-751? system controller AMD-750? chipset overview 23016aaugust 1999 agp features the agp features include the following: n bus features ? compliance with agp 1.0 specification ? synchronous 66-mhz 1x and 2x data-transfer modes ? multiplexed and demultiplexed transfers ? up to four pipelined grants ? support of sideband address (sba) bus n request queue features ? separate read-request and write-request queues ? reordering of high-priority requests over low-priority requests in queue ? concurrent issuing of requests from both the write queue and read queue ? selects next request to optimize bus utilization n transaction queues ? memory-to-agp and processor-to-agp transaction queues n fifo features ? 16-entry (64-bit) agp-to-memory write fifo ? 64-entry (64-bit) memory-to-agp read fifo n secondary pci bus features ? pipelined burst reads and writes ? extensive utilization of fifos n gart (graphics address remapping table) features ? conventional (two-level) gart scheme ? eight-entry, fully-associative gart table cache (gtc) ? three fully-associative gart directory caches (gdc) ? one 4-entry for pci ? one 8-entry for the processor ? one 16-entry for agp
amd-751? system controller 7 23016aaugust 1999 AMD-750? chipset overview power management the power management features include the following: n support for both acpi and microsoft ? pc 98 power management n amd-751 system controller supports the following power states: ? processor halt/stop-grant/sleep states ? power-on-suspend
8 amd-756? peripheral bus controller AMD-750? chipset overview 23016aaugust 1999 amd-756? peripheral bus controller key features of the amd-756 controller are listed in this section. for more information, see the amd-756? peripheral bus controller data sheet , order# 22548. the amd-756 contains the following functional units: n integrated isa bus controller n enhanced master-mode pci ide controller with ultra dma-33/66 support n usb controller n keyboard/mouse controller n real-time clock pci-to-isa bridge the amd-756 controller includes a pc97-compliant pci-to-isa bridge with the following features: n pci 2.2-compliant interface n eight-level doubleword buffer between pci and isa buses n dual cascaded at-8259-compatible interrupt controllers n dual at-8237-compatible dma controllers n type f dma transfer support n support for isa legacy distributed dma across the pci bus n at-8254-compatible programmable interval timer n integrated real-time clock w/extended 256-byte cmos ram n programmable isa bus clock n fast reset and gate a20 operation n edge-triggered or level-sensitive interrupts n flash, 2-mbyte eprom, bios support n integrated keyboard controller with ps/2 mouse support
amd-756? peripheral bus controller 9 23016aaugust 1999 AMD-750? chipset overview enhanced ide controllers the amd-756 controller includes enhanced master mode pci and ide controllers with the following features: n ultra dma-33/66 support for a primary and secondary dual- drive port n transfer rates up to 33 mbytes per second supporting pio modes 1C4, multi-word dma mode-2 drivers, and up to 66 mbytes per second supporting the ultra dma-66 interface n sixteen-level doubleword prefetch and write buffers n commands can be interleaved between the two channels n bus master programming interface for compliance with sff-8038i 1.0 and microsoft windows ? 95 n full-featured scatter-gather capability n support for atapi-compliant devices n support for pci-native and ata-compatibility modes n complete bus mastering software driver support universal serial bus controller the amd-756 controller includes a universal serial bus (usb) controller with the following features: n usb 1.0 and ohci compliant n sixteen-level doubleword fifo for burst pci bus access n root hub and four ports n integrated physical-layer transceivers with over-current detection status on usb inputs n legacy keyboard and ps/2 mouse support
10 amd-756? peripheral bus controller AMD-750? chipset overview 23016aaugust 1999 plug-n-play support the amd-756 controller supports plug-n-play with the following features: n pci interrupts steerable to any of three interrupt channels n microsoft windows 98 and plug-n-play bios compliant n serial irq compliant power management the amd-756 controller includes the following sophisticated power management features: n supports advanced configuration and power interface power management (acpi 1.0 compliant) n supports legacy power management (apm 1.2 compliant) n supports soft-off and power-on suspend with hardware automatic wakeup n two general-purpose timers, one system-inactivity timer, and a 24-bit or 32-bit apci-compliant timer n dedicated external modem-ring input pin for system wakeup n normal, doze, sleep, suspend, and conserve modes n eighteen multiplexed general-purpose i/o pins n smbus implementation for jedec-compatible dimm identification and on-board device power/thermal control n primary and secondary interrupt differentiation for individual channels n clock throttling control n multiple internal and external smi# sources for flexible power management

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