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| product specification main features ! 8-bit resolution. ! adc gain adjust. ! 1.5 ghz full power input bandwidth. ! 1 gsps (min) sampling rate. ! sinad = 44.3 db (7.2 effective bits) sfdr = 58 dbc @ f s = 1 gsps, f in = 20 mhz : ! sinad = 42.9 db (7.0 effective bits) sfdr = 52 dbc @ f s = 1 gsps, f in = 500 mhz : ! sinad = 40.3db (6.8 effective bits) sfdr = 50 dbc @ f s = 1 gsps, f in = 1000 mhz (-3 db fs) ! 2-tone imd : -52dbc (489 mhz, 490 mhz) @ 1gsps. ! dnl = 0.3 lsb inl = 0.7 lsb. ! low bit error rate (10 -13 ) @ 1 gsps ! very low input capacitance : 3 pf ! 500 mvpp differential or single-ended analog inputs. ! differential or single-ended 50 ? ecl compatible clock inputs. ! ecl or lvds/hstl output compatibility. ! data ready output with asynchronous reset. ! gray or binary selectable output data ; nrz output mode. ! power consumption : 3.4 w @ tj = 70c typical ! radiation tolerance oriented design (150 krad (si) measured). applications ! digital sampling oscilloscopes. ! satellite receiver. ! electronic countermeasures / electronic warfare. ! direct rf down?conversion. screening ! atmel-grenoble standard screening level ! mil-prf-38535, qml level q for package version, dscc 5962-0050401qyc ! temperature range: up to -55c < tc ; tj < +125c description the ts8388bf is a monolithic 8?bit analog?to?digital converter, designed for digitizing wide bandwidth analog signals at very high sampling rates of up to 1 gsps. the ts8388bf is using an innovative architecture, including an on chip sample and hold (s/h), and is fabricated with an advanced high speed bipolar process. the on?chip s/h has a 1.5 ghz full power input bandwidth, providing excellent dynamic performance in undersampling applications (high if digitizing). f suffix : cqfp 68 ceramic quad flat pack adc 8-bit 1 gsps ts8388bf 1/ die form : jts8388b 2/ evaluation board : tsev8388bf 3/ demultiplexer : ts81102g0 : companion device available january 2002
2 ts8388bf product specification table of contents 1. simplified block diagram ..................................................................................................... ...............................3 2. functional description ....................................................................................................... .................................3 3. specifications ............................................................................................................... ...............................................4 3.1. absolute maximum ratings (see notes below) ................................................................................. ................................4 3.2. recommended conditions of use .............................................................................................. ............................................4 3.3. electrical operating characteristics....................................................................................... .......................................5 3.4. timing diagrams ............................................................................................................ ...............................................................9 3.5. explanation of test levels................................................................................................. .................................................. 10 3.6. functions description...................................................................................................... ...................................................... 10 3.7. digital output coding ...................................................................................................... ....................................................... 10 4. package description. ......................................................................................................... ...................................11 4.1. ts8388bf pin description................................................................................................... ...................................................... 11 4.2. ts8388bf pinout ............................................................................................................ .............................................................. 12 4.3. outline dimensions ? 68 pins cqfp .......................................................................................... ............................................. 13 4.4. thermal characteristics .................................................................................................... .................................................. 14 5. typical characterization results ............................................................................................. ................15 5.1. static linearity ? fs = 50 msps / fin = 10 mh z ...................................................................................................................... 15 5.2. effective number of bits versus power supplies variation................................................................... ................. 16 5.3. typical fft results ........................................................................................................ .......................................................... 17 5.4. spurious free dynamic range versus input amplitude ......................................................................... ..................... 18 5.5. dynamic performance versus analog input frequency .......................................................................... ................. 19 5.6. effective number of bits (enob) versus sampling frequency .................................................................. .............. 20 5.7. sfdr versus sampling frequency ............................................................................................. ......................................... 20 5.8. ts8388bf adc performances versus junction temperature ...................................................................... .............. 21 5.9. typical full power input bandwidth ......................................................................................... ........................................ 22 5.10. adc step response......................................................................................................... ...................................................... 23 6. definition of terms .......................................................................................................... ......................................24 7. ts8388bf main features....................................................................................................... ...................................26 7.1. timing informations ........................................................................................................ ......................................................... 26 7.2. principle of data ready signal control by drrb input command ............................................................... ........... 27 7.3. analog inputs (vin) (vinb) ................................................................................................. ....................................................... 27 7.4. clock inputs (clk) (clkb).................................................................................................. ....................................................... 28 7.5. noise immunity informations ................................................................................................ ................................................ 30 7.6. digital outputs ............................................................................................................ .............................................................. 30 7.7. out of range bit ............................................................................................................................... ............................................... 32 7.8. gray or binary output data format select ................................................................................... ................................ 33 7.9. diode pin 49 ............................................................................................................... ................................................................... 33 7.10. adc gain control pin 60 ................................................................................................... ................................................... 34 8. equivalent input / output schematics ......................................................................................... .............35 8.1. equivalent analog input circuit and esd protections........................................................................ ...................... 35 8.2. equivalent analog clock input circuit and esd protections.................................................................. ............... 35 8.3. equivalent data output buffer circuit and esd protections ................................................................................ 36 adc gain adjust equivalent input circuits and esd protections.................................................................. ...................... 36 8.5. gorb equivalent input schematic and esd protections........................................................................ .................... 37 drrb equivalent input schematic and esd protections ............................................................................ ............................. 37 9. tsev8388bf : device evaluation board ......................................................................................... ...............38 10. ordering information ........................................................................................................ .............................39 package device ................................................................................................................. ...................................................................... 39 10.2. evaluation board .......................................................................................................... ....................................................... 39 3 product specification ts8388bf 1. simplified block diagram 2. functional description the ts8388bf is an 8 bit 1gsps adc based on an advanced high speed bipolar technology featuring a cutoff frequency of 25 ghz. the ts8388bf includes a front-end master/slave track and hold stage (s/h), followed by an analog encoding stage and interpolati on circuitry. successive banks of latches are regenerating the analog residues into logical data before entering an error correction circuit ry and a resynchronization stage followed by 75 ? differential output buffers. the ts8388bf works in fully differential mode from analog inputs up to digital outputs. the ts8388bf features a full power input bandwidth of 1.5 ghz. control pin gorb is provided to select either gray or binary data output format. gain control pin is provided in order to adjust the adc gain. a data ready output asynchronous reset (drrb) is available on ts8388bf. the ts8388bf uses only vertical isolated npn transistors together with oxide isolated polysilicon resistors, which allow enhanc ed radiation tolerance (no performance drift measured at 150krad total dose). vin,vinb clk, clkb g=2 t/h g=1 t/h g=1 clock buffer resistor chain analog encoding block interpolation stages regeneration latches error correction & decode logic output latches & buffers 4 45 45 8 8 gain drrb dr,drb gorb data,datab or,orb master/slave track & hold 4 ts8388bf product specification 3. specifications 3.1. absolute maximum ratings (see notes below) parameter symbol comments value unit positive supply voltage v cc gnd to 6 v digital negative supply voltage dv ee gnd to -5.7 v digital positive supply voltage v plusd gnd-0.3 to 2.8 v negative supply voltage v ee gnd to -6 v maximum difference between negative supply voltages dv ee to v ee 0.3 v analog input voltages v in or v inb -1 to +1 v maximum difference between v in and v inb v in - v inb -2 to +2 v digital input voltage v d gorb -0.3 to v cc +0.3 v digital input voltage v d drrb v ee -0.3 to +0.9 v digital output voltage vo v plusd -3 to v plusd -0.5 v clock input voltage v clk or v clkb -3 to +1.5 v maximum difference between v clk and v clkb v clk - v clkb -2 to +2 v maximum junction temperature t j +135 o c storage temperature t stg -65 to +150 o c lead temperature (soldering 10s) t leads +300 o c notes : absolute maximum ratings are limiting values (referenced to gnd=0v), to be applied individually, while other parameters are wit hin specified operating conditions. long exposure to maximum rating may affect device reliability. the use of a thermal heat sink is mandatory (see thermal characteristics). 3.2. recommended conditions of use parameter symbol comments min. typ. max. unit positive supply voltage v cc 4.75 +5 5.25 v positive digital supply voltage v plusd ecl output compatibility gnd v v plusd lvds output compatibility +1.4 +2.4 +2.6 v negative supply voltages v ee, dvee -5.25 -5.0 -4.75 v differential analog input voltage (full scale) v in, v inb v in -v inb 50 ? differential or single-ended 113 450 125 500 137 550 mv mvpp clock input power level p clk p clkb 50 ? single?ended clock input 3 4 10 dbm operating temperature range t j commercial grade: ?c? industrial grade: ?v? military grade: ?m? 0 < tc ; tj < 90 -40 < tc; tj < 110 -55 < tc ; tj < +125 o c 5 product specification ts8388bf 3.3. electrical operating characteristics vee = dvee = -5 v ; v cc = +5 v ; v in -v inb = 500 mvpp full scale differential input ; digital outputs 75 or 50 ? differentially terminated ; tj (typical) = 70 c. full temperature range : up to ?55c 7 product specification ts8388bf parameter symb test level min typ max unit transient performance bit error rate (notes 2, 4) fs = 1 gsps fin = 62.5 mhz ber 4 1e-12 error/ sample adc settling time (note 2) v in -v inb = 400 mvpp ts 4 0.5 1 ns overvoltage recovery time (note 2) tor 4 0.5 1 ns ac performance single ended or differential input and clock mode, 50 % clock duty cycle (clk,clkb), binary output data format, tj. = 70 c, unless otherwise specified. signal to noise and distortion ratio (note 2) sinad fs = 1 gsps fin = 20 mhz 4 42 44 db fs = 1 gsps fin = 500 mhz 4 41 43 db fs = 1 gsps fin = 1000 mhz (-1db fs) 4 38 40 db fs = 50 msps fin = 25 mhz 1, 2, 6 40 44 db effective number of bits enob fs = 1 gsps fin = 20 mhz 4 7.0 7.2 bits fs = 1 gsps fin = 500 mhz 4 6.6 6.8 bits fs = 1 gsps fin = 1000 mhz (-1dbfs) 4 6.2 6.4 bits fs = 50 msps fin = 25 mhz 1, 2, 6 7.0 7.2 bits signal to noise ratio (note 2) snr fs = 1 gsps fin = 20 mhz 4 42 45 db fs = 1 gsps fin = 500 mhz 4 41 44 db fs = 1 gsps fin = 1000 mhz (-1dbfs) 4 41 44 db fs = 50 msps fin = 25 mhz 1, 2, 6 44 45 db total harmonic distortion (note 2) thd fs = 1 gsps fin = 20 mhz 4 50 54 db fs = 1 gsps fin = 500 mhz 4 46 50 db fs = 1 gsps fin = 1000 mhz (-1dbfs) 4 42 46 db fs = 50 msps fin = 25 mhz 1, 2, 6 46 51 db spurious free dynamic range (note 2) sfdr fs = 1 gsps fin = 20 mhz 4 52 57 dbc fs = 1 gsps fin = 500 mhz 4 47 52 dbc fs = 1 gsps fin = 1000 mhz (-1dbfs) 4 42 47 dbc fs = 1 gsps fin = 1000 mhz (-3dbfs) 4 45 50 dbc fs = 50 msps fin = 25 mhz 1, 2, 6 40 54 dbc two-tone inter-modulation distortion (note 2) imd 4 f in1 = 489 mhz @ f s = 1 gsps - 47 - 52 dbc f in2 = 490 mhz @ f s = 1 gsps 8 ts8388bf product specification parameter symb test level min typ max unit switching performance and characteristics ? see timing diagrams figure 1, figure 2 maximum clock frequency (note 14) f s 11.4gsps minimum clock frequency (note 15) f s 410 50msps minimum clock pulse width (high) tc1 4 0.280 0.500 50 ns minimum clock pulse width (low) tc2 4 0.350 0.500 50 ns aperture delay (note 2) ta 4 100 +250 400 ps aperture uncertainty (notes 2, 5) jitter 4 0.4 0.6 ps (rms) data output delay (notes 2, 10, 11, 12) tod 4 1150 1360 1660 ps output rise/fall time for data (20 % ? 80 %) (note 11 ) tr/tf 4 250 350 550 ps output rise/fall time for data ready (20 % ? 80 % ) (note 11 ) tr/tf 4 250 350 550 ps data ready output delay (notes 2,10, 11, 12) tdr 4 1110 1320 1620 ps data ready reset delay trdr 4 720 1000 ps data to data ready ? clock low pulse width (see timing diagram, notes 9, 13,14) tod- tdr 4 0 40 80 ps data to data ready output delay (50% duty cycle) (see timing diagram, notes 2, 15) @ 1gsps td1 4 420 460 500 ps data pipeline delay tpd 4 4 clock cycles note 1 : differential output buffers are internally loaded by 75 ? resistors. buffer bias current = 11 ma. note 2 : see definition of terms note 3 : histogram testing based on sampling of a 10 mhz sinewave at 50 msps. note 4 : output error amplitude < 4 lsb around worst code. note 5 : maximum jitter value obtained for single?ended clock input on the jts8388b die (chip on board) : 200 fs. (500 fs expected on ts8388bg) note 6 : digital output back termination options depicted in application notes figures 3,4,5 . note 7 : with a typical value of td = 465 ps, at 1 gsps, the timing safety margin for the data storing using the eclinps 10e452 output registers from motorola is of 315 ps, equally shared before and after the rising edge of the data ready signals (dr, drb). note 8 : the clock inputs may be indifferently entered in differential or single?ended, using ecl levels or 4 dbm typical power level into the 50 ? termination resistor of the inphase clock input. (4 dbm into 50 ? clock input correspond to 10 dbm power level for the clock generator.) note 9 : at 1gsps, 50/50 clock duty cycle, tc2 = 500 ps (tc1). tdr - tod = -100 ps (typ) does not depend on the sampling rate. note 10 : specified loading conditions for digital outputs : - 50 ? or 75 ? controlled impedance traces properly 50 / 75 ? terminated, or unterminated 75 ? controlled impedance traces. - controlled impedance traces far end loaded by 1 standard eclinps register from motorola.( e.g. : 10e452 ) ( typical input par asitic capacitance of 1.5 pf including package and esd protections. ) note 11 : termination load parasitic capacitance derating values : - 50 ? or 75 ? controlled impedance traces properly 50 / 75 ? terminated : 60 ps / pf or 75 ps per additionnal eclinps load. - unterminated ( source terminated ) 75 ? controlled impedance lines : 100 ps / pf or 150 ps per additionnal eclinps termination load. note 12 : apply proper 50 / 75 ? impedance traces propagation time derating values : 6 ps / mm (155 ps/inch) for tsev8388bf evaluation board. note 13 : values for tod and tdr track each other over temperature, ( 1 % variation for tod - tdr per 100 o c. temperature variation ). therefore tod - tdr variation over temperature is negligible. moreover, the internal ( onchip ) and package skews between each data tods and tdr effect can be considered as negligible.consequently, minimum values for tod and tdr are never more than 100 ps apart. the same is true for the tod and tdr maximum values (see advanced application notes about tod - tdr variation over temperature in section 7). note 14 : min value guarantees performance. max value guarantees functionality. note 15 : min value guarantees functionality. max value guarantees performance. 9 product specification ts8388bf 3.4. timing diagrams tc1 tc2 ta= 250 ps x x n+1 x n+2 x n+3 n figure 1 : ts8388bf timing diagram ( 1 gsps clock rate ) data ready reset , clock held at low level digital outputs (v in, v inb ) data ready (dr, drb) (clk, clkb) 1. n+5 td1=tc1+tdr-tod = tc1-40 ps = 460 ps ps data n-4 data n-3 data n data n -1 data n-2 tc=1000 ps x x n+4 tod = 1360 ps 1360 ps drrb 1ns (min) tdr = 1320 ps tpd: 4.0 clock periods 1000 ps trdr = 720 ps n-1 td2 = tc2+tod-tdr = tc2+40ps = 540 ps tdr = 1320 ps data n-5 data n+1 tc1 tc2 ta= 250ps x 3. n+1 x n+2 x n+3 n figure 2 : ts8388bf timing diagram ( 1 gsps clock rate ) data ready reset , clock held at high level digital outputs (v in, v inb ) data ready (dr, drb) (clk, clkb) 2. n+5 td1=tc1+tdr-tod = tc1-40 ps = 460 ps data n-4 data n-3 data n data n-1 data n-2 tc = 1000 ps x x n+4 tod = 1360 ps 1360 ps drrb 1ns (min) tdr = 1320 ps tpd: 4.0 clock periods 1000 ps trdr = 720ps n-1 td2 = tc2+tod-tdr = tc2+40ps = 540 ps tdr = 1120 ps data n-5 data n+1 10 ts8388bf product specification 3.5. explanation of test levels 1 100% production tested at +25 c (1) (for ?c? temperature range (2) ). 2 100 % production tested at +25 c (1) , and sample tested at specified temperatures (for ?v? and ?m? temperature ranges (2) ). 3 sample tested only at specified temperatures 4 parameter is guaranteed by design and characterization testing (thermal steady-state conditions at specified temperature). 5 parameter is a typical value only 6 100 % production tested over specified temperature range (for ?b/q? temperature range (2) ). only min and max values are guaranteed (typical values are issuing from characterization results). (1) unless otherwise specified, all tests are pulsed tests : therefore tj = tc = ta, where tj ,tc and ta are junction, case and ambient temperature respectively. (2) refer to ordering information chapter. 3.6. functions description name function vcc positive power supply vee analog negative power supply vplusd digital positive power supply gnd ground vin, vinb differential analog inputs clk, clkb differential clock inputs 11 product specification ts8388bf 4. package description. 4.1. ts8388bf pin description symbol pin number function gnd 5, 13, 27, 28, 34, 35, 36, 41, 42, 43, 50, 51, 52, 53, 58, 59 ground pins. to be connected to external ground plane. v plusd 1, 2, 16, 17, 18, 68 digital positive supply. (0v for ecl compatibility, +2.4v for lvds compatibility). (note 2) v cc 26, 29, 32, 33, 46, 47, 61 +5 v positive supply. v ee 30, 31, 44, 45, 48 -5 v analog negative supply. dv ee 8, 9, 10 -5 v digital negative supply. v in 54 (1) , 55 in phase (+) analog input signal of the sample and hold differential preamplifier. v inb 56, 57 (1) inverted phase (-) of analog input signal (v in ). clk 37 (1) , 38 in phase (+) ecl clock input signal. the analog input is sampled and held on the rising edge of the clk signal. clkb 39, 40 (1) inverted phase (-) of ecl clock input signal (clk). d0, d1, d2, d3, d4, d5, d6, d7 23, 21, 19, 14, 6, 3, 66, 64 in phase (+) digital outputs. b0 is the lsb. b7 is the msb. d0b, d1b, d2b, d3b, d4b, d5b, d6b, d7b 24, 22, 20, 15, 7, 4, 67, 65 inverted phase (-) digital outputs. b0b is the inverted lsb. b7b is the inverted msb. or 62 in phase (+) out of range bit. out of range is high on the leading edge of code 0 and code 256. orb 63 inverted phase (+) of out of range bit (or). dr 11 in phase (+) output of data ready signal. drb 12 inverted phase (-) output of data ready signal (dr). gorb 25 gray or binary select output format control pin. ? binary output format if gorb is floating or v cc . ? gray output format if gorb is connected at ground (0 v). gain 60 adc gain adjust pin. diod/drrb 49 this pin has a double function (can be left open or grounded if not used) : diod : die junction temperature monitoring pin. drrb : asynchronous data ready reset function note 1 : following pin numbers 37 (clk), 40 (clkb), 54 (v in ) and 57 (v inb ) have to be connected to gnd through a 50 ? resistor as close as possible to the package.(50 ? termination preferred option). note 2 : the common mode level of the output buffers is 1.2v below the positive digital supply. for ecl compatibility the positive digital supply must be set at 0v (ground ). for lvds compatibility (output common mode at +1.2v) the positive digital supply must be set at 2.4v. if the subsequent lvds circuitry can withstand a lower level for input common mode, it is recommended to lower the positive dig ital supply level in the same proportion in order to spare power dissipation. 12 ts8388bf product specification 4.2. ts8388bf pinout ts8388bf vplusd vplusd vplusd vplusd v plusd v plusd d2 d2b d1 d1b d0 d0b d3b d3 drb dr d4b d4 d5b d5 d6b d6 d7b d7 orb or top view : 13 product specification ts8388bf 4.3. outline dimensions ? 68 pins cqfp 1.133 ? 1.147 28 , 78 ? 29.13 .950 .006 24.13 0.152 0.8 bcs 20.32 bsc 0.050 bcs 1.27 bsc .950 .006 24.13 0.152 1.133 ? 1.147 28.78 ? 29.13 .023 .002 0.58 0.05 pin n o 1 index ? .005 z x y m . cqfp 68 68 pins ceramic quad flat pack ? top view .135 max 3.43 max .004 .005 ? .010 0.13 ? 0.25 0 o ? 8 o .027 ? .037 0.70 ? 0.95 .018 ? .035 0.46 ? 0.88 .075 .008 1.9 0.20 14 ts8388bf product specification 4.4. thermal characteristics although the power dissipation is low for this performance, the use of a heat sink is mandatory. you will find here below some advise on this topics. 4.4.1. t hermal resistance from junction to ambient : rthja the following table lists the converter thermal performance parameters, with or without heatsink. for the following measurements, a 50 x 50 x 16 mm heatsink has been used. (see drawing in part 4.4.3.) 4.4.2. t hermal resistance from junction to case : rthjc typical value for rthjc is given to 4.75 o c/w. 4.4.3. cqfp68 board assembly with a 50 x 50 x 16 mm external h eatsink air flow estimated tar g eted (m/s) without heatsink with heatsink 050 10 0,5 40 8,9 135 7,9 1,5 32 7,3 230 6,8 2,5 28 6,5 326 6,2 424 5,8 523,5 5,6 heatsink glued to backside of package or screwed and pressed with thermal grease j a thermal resistance ( o c / w ) cqfp68 on board 0 10 20 30 40 50 60 012345 air flow (m/s) rthja (deg/w) without heatsink with heatsink 24.13 28.96 15.0 1.3 3. 2 50.0 1.4 40 2.5 16.0 printed circuit interface : af-filled epoxy or thermal conductive g rease ? 100 aluminum heatsink 15 product specification ts8388bf 5. typical characterization results 5.1. static linearity ? fs = 50 msps / fin = 10 mhz 5.1.1. i ntegral n on l inearity 5.1.2. d ifferential n on l inearity lsb inl = +/- 0.7 lsb code signal frequency = 10mhz clock frequency = 50msps positive peak : 0.78 lsb negative peak : -0.73 lsb lsb dnl = +/- 0.4 lsb code signal frequency = 10mhz clock frequency = 50msps positive peak : 0.3 lsb negative peak : -0.39 lsb 16 ts8388bf product specification 5.2. effective number of bits versus power supplies variation 0 1 2 3 4 5 6 7 8 -7 -6,5 -6 -5,5 -5 -4,5 -4 effective number of bits = f ( veea ) ; fs = 500 msps ; fin = 100 mhz veea ( v) enob (bits) 0 1 2 3 4 5 6 7 8 33,544,555,566,57 effective number of bits = f ( vcc ) ; fs = 500 msps ; fin = 100 mhz vcc (v) enob (bits) 0 1 2 3 4 5 6 7 8 -6 -5,5 -5 -4,5 -4 -3,5 -3 effective number of bits = f ( veed ) ; fs = 500 msps ; fin = 100 mhz veed (v) enob (bits) 17 product specification ts8388bf 5.3. typical fft results 5.3.1 f s = 1 g sps , f in =20 mh z 5.3.2. f s = 1 gsps, f in = 495 mh z 5.3.3. f s = 1 gsps, f in = 995 mh z ( -3 d b f ull s cale input ) single ended or differential fs =1 gsps fin = 20 mhz eff. bits =7.2 sinad = 44.3 db snr = 44.7db thd = -54dbc sfdr = -57 dbc h3 h2 clock duty cycle = 50 % binary output coding h11 h12 single ended or differential fs =1 gsps fin=495mhz eff. bits =6.8 sinad =43 db snr = 44.1 db thd = -50 dbc sfdr= -52 dbc clock duty cycle = 50 % h3 h11 h14 h12 binary output coding h2 single ended or differential fs =1 gsps fin=995 mhz eff. bits =6.6 sinad =40.8 db snr = 44 db thd = -48 dbc sfdr= -50 dbc clock duty cycle = 50 % h2 h3 binary output coding h10 18 ts8388bf product specification 5.4. spurious free dynamic range versus input amplitude 5.4.1. sampling frequency f s =1 g sps ; i nput frequency f in =995 mh z ; g ray or b inary output coding fs = 1 gsps fin = 995 mhz full scale enob = 6.4 sinad = 40 db snr = 44db thd =- 46 dbc sfdr =- 47 dbc full scale magnitude (code) sfdr = -47 dbc h2 h3 -3db full scale fs = 1 gsps fin = 995 mhz (-3 db full scale) enob = 6.6 sinad = 40.8 db snr = 44db sfdr = -50dbc magnitude (code) thd = -48dbc sfdr = -50 dbc h2 h3 19 product specification ts8388bf 5.5. dynamic performance versus analog input frequency fs=1 gsps, fin = 0 up to 1600 mhz, full scale input (fs), fs -3 db clock duty cycle 50 / 50, binary/gray output coding, fully differential or single-ended analog and clock inputs 3 4 5 6 7 8 0 200 400 600 800 1000 1200 1400 1600 1800 input frequenc y ( mhz ) enob (db) -3 db fs fs 30 32 34 36 38 40 42 44 46 48 50 0 200 400 600 800 1000 1200 1400 1600 1800 input frequency (mhz) snr (db) fs -3 db fs -60 -55 -50 -45 -40 -35 -30 -25 -20 0 200 400 600 800 1000 1200 1400 1600 1800 input frequency (mhz) sfdr (dbc) -3 db fs fs 20 ts8388bf product specification 5.6. effective number of bits (enob) versus sampling frequency analog input frequency : fin = 495 mhz and nyquist conditions ( fin = fs / 2 ) clock duty cycle 50 / 50 , binary output coding 5.7. sfdr versus sampling frequency analog input frequency : fin = 495 mhz and nyquist conditions ( fin = fs / 2 ) clock duty cycle 50 / 50 , binary output coding 2 3 4 5 6 7 8 0 200 400 600 800 1000 1200 1400 1600 sampling frequency (msps) enob (db) fi n= fs/ 2 fi n=500 mhz -60 -55 -50 -45 -40 -35 -30 -25 -20 0 200 400 600 800 1000 1200 1400 1600 sampling frequency (msps) sfdr (dbc) fin= fs/2 fin=500 mhz 21 product specification ts8388bf 5.8. ts8388bf adc performances versus junction temperature 3 4 5 6 7 8 -40 -20 0 20 40 60 80 100 120 140 160 effective number of bits versus junction temperature fs = 1 gsps ; fin = 500 mhz ; duty cycle = 50% temperature ( o c ) enob (bits) 42 43 44 45 46 -60 -40 -20 0 20 40 60 80 100 120 signal to noise ratio versus junction temperature fs = 1 gsps ; fin = 507 mhz ; differential clock, single-ended analog input (vin=-1dbfs) temperature ( o c ) snr (db) 43 45 47 49 51 53 -60 -40 -20 0 20 40 60 80 100 120 total harmonic distorsion versus junction temperature fs = 1 gsps ; fin = 507 mhz ; differential clock, single-ended analog input (vin=-1dbfs) temperature ( o c) thd (db) 22 ts8388bf product specification 5.9. typical full power input bandwidth 1.5 ghz at -3 db (-2dbm full power input) 0 1 2 3 4 5 - 40 - 20 0 20 40 60 80 100 120 140 160 power consumption versus junction temperature fs = 1 g sps ; fi n = 500 mhz ; dut y cycl e = 50% tem per at ur e ( o c) power consumption (w ) -6 -5 -4 -3 -2 -1 0 100 300 500 700 900 1100 1300 1500 1700 frequency (mhz) magnitude (db) 23 product specification ts8388bf 5.10. adc step response test pulse input characteristics : 20% to 80% input full scale and rise time ~ 200ps. note : this step response was obtained with the tsev8388b chip on board (device in die form). 5.10.1. t est pulse digitized with 20 gh z dso 5.10.2. s ame test pulse digitized with ts8388bf adc n.b. : ripples are due to the test setup (they are present on both measurements) 50 mv/div 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 time (ns) vpp ~ 260 mv tr ~ 240 ps 50 mv/div 500 ps/div 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 200 150 100 50 0 adc code time (ns) tr ~ 280 ps 50 codes/div (vpp ~260 mv) 500 ps/div adc calculated rise time : between 150 and 200 p s. 24 ts8388bf product specification 6. definition of terms (ber) bit error rate probability to exceed a specified error threshold for a sample. an error code is a code that differs by more than +/- 4 lsb from the correct code. (bw) full power input bandwidth analog input frequency at which the fundamental component in the digitally reconstructed output has fallen by 3 db with respect to its low frequency value (determined by fft analysis) for input at full scale. (sinad) signal to noise and distortion ratio ratio expressed in db of the rms signal amplitude, set to 1db below full scale, to the rms sum of all other spectral components, including the harmonics except dc. (snr) signal to noise ratio ratio expressed in db of the rms signal amplitude, set to 1db below full scale, to the rms sum of all other spectral components excluding the five first harmonics. (thd) total harmonic distorsion ratio expressed in dbc of the rms sum of the first five harmonic components, to the rms value of the measured fundamental spectral component. (sfdr) spurious free dynamic range ratio expressed in db of the rms signal amplitude, set at 1db below full scale, to the rms value of the next highest spectral component (peak spurious spectral component). sfdr is the key parameter for selecting a converter to be used in a frequency domain application ( radar systems, digital receiver, network analyzer ?.). it may be reported in dbc (i.e., degrades as signal levels is lowered), or in dbfs (i.e. always related back to converter full scale). (enob) effective number of bits where a is the actual input amplitude and v is the full scale range of the adc under test (dnl) differential non linearity the differential non linearity for an output code i is the difference between the measured step size of code i and the ideal lsb step size. dnl (i) is expressed in lsbs. dnl is the maximum value of all dnl (i). dnl error specification of less than 1 lsb guarantees that there are no missing output codes and that the transfer function is monotonic. (inl) integral non linearity the integral non linearity for an output code i is the difference between the measured input voltage at which the transition occurs and the ideal value of this transition. inl (i) is expressed in lsbs, and is the maximum value of all | inl (i) | . (dg) differential gain the peak gain variation (in percent) at five different dc levels for an ac signal of 20% full scale peak to peak amplitude. f in = 5 mhz. (tbc) (dp) differential phase peak phase variation (in degrees) at five different dc levels for an ac signal of 20% full scale peak to peak amplitude. f in = 5 mhz. (tbc) (ta) aperture delay delay between the rising edge of the differential clock inputs (clk,clkb) (zero crossing point), and the time at which (v in, v inb ) is sampled. (jitter) aperture uncertainty sample to sample variation in aperture delay. the voltage error due to jitter depends on the slew rate of the signal at the sampling point. (ts) settling time time delay to achieve 0.2 % accuracy at the converter output when a 80% full scale step function is applied to the differential analog input. (ort) overvoltage recovery time time to recover 0.2 % accuracy at the output, after a 150 % full scale step applied on the input is reduced to midscale. (tod) digital data output delay delay from the falling edge of the differential clock inputs (clk,clkb) (zero crossing point) to the next point of change in the differential output data (zero crossing) with specified load. (td1) time delay from data to data ready time delay from data transition to data ready. (td2) time delay from data ready to data general expression is td1 = tc1 + tdr ? tod with tc = tc1 + tc2 = 1 encoding clock period. (tc) encoding clock period tc1 = minimum clock pulse width (high) tc = tc1 + tc2 tc2 = minimum clock pulse width (low) (tpd) pipeline delay number of clock cycles between the sampling edge of an input data and the associated output data being made available, (not taking in account the tod). for the ts8388bf the tpd is 4 clock periods. (trdr) data ready reset delay delay between the falling edge of the data ready output asynchronous reset signal (ddrb) and the reset to digital zero transition of the data ready output signal (dr). (tr) rise time time delay for the output data signals to rize from 20% to 80% of delta between low level and sinad - 1.76 + 20 log (a/v/2) enob = ??????????????? 6.02 25 product specification ts8388bf high level. (tf) fall time time delay for the output data signals to fall from 80% to 20% of delta between low level and high level. (psrr) power supply rejection ratio ratio of input offset variation to a change in power supply voltage. (nrz) non return to zero when the input signal is larger than the upper bound of the adc input range, the output code is identical to the maximum code and the out of range bit is set to logic one. when the input signal is smaller than the lower bound of the adc input range, the output code is identical to the minimum code, and the out of range bit is set to logic one. (it is assumed that the input signal amplitude remains within the absolute maximum ratings). (imd) intermodulation distortion the two tones intermodulation distortion ( imd ) rejection is the ratio of either input tone to the worst third order intermodulation products. the input tones levels are at ? 7db full scale. (npr) noise power ratio the npr is measured to characterize the adc performance in response to broad bandwidth signals. when using a notch-filtered broadband white-noise generator as the input to the adc under test, the noise power ratio is defined as the ratio of the average out-of-notch to the average in-notch power spectral density magnitudes for the fft spectrum of the adc output sample test. 26 ts8388bf product specification 7. ts8388bf main features 7.1. timing informations 7.1.1. t iming value for ts8388bf timing values as defined in 3.3 are advanced data, issuing from electric simulations and first characterizations results fitted with measurements. timing values are given at cqfp68 package inputs/outputs, taking into account package internal controlled impedance traces prop agation delays, gullwing pin model, and specified termination loads. propagation delays in 50/75 ohms impedance traces are not taken into account for tod and tdr. apply proper derating values corresponding to termination topology. the min/max timing values are valid over the full temperature range in the following conditions : note 1 : specified termination load (differential output data and data ready) : 50 ohms resistor in parallel with 1 standard eclinps register from motorola, (e.g : 10e452) (typical eclinps inputs shows a typical input capacitance of 1.5 pf (including package and esd protections) if addressing an output dmux, take care if some digital outputs do not have the same termination load and apply corresponding d erating value given below. note 2 : output termination load derating values for tod and tdr : ~ 35 ps/pf or 50 ps per additional eclinps load. note 3 :propagation time delay derating values have also to be applied for tod and tdr : ~ 6 ps/mm (155 ps/inch) for tsev8388b evaluation board. apply proper time delay derating value if a different dielectric layer is used. 7.1.2. p ropagation time considerations tod and tdr timing values are given from pin to pin and do not include the additional propagation times between device pins and input/output termination loads. for the tsev8388b evaluation board, the propagation time delay is 6ps/mm (155ps/inch) correspon ding to 3.4 (@10ghz) dielectric constant of the ro4003 used for the board. if a different dielectric layer is used (for instance teflon), please use appropriate propagation time values. td does not depend on propagation times because it is a differential data. (td is the time difference between data ready output delay and digital data output delay) td is also the most straightforward data to measure, again because it is differential : td can be measured directly onto termination loads, with matched oscilloscopes probes. 7.1.3. tod - tdr variation over temperature values for tod and tdr track each other over temperature (1 percent variation for tod - tdr per 100 degrees celsius temperature variation). therefore tod - tdr variation over temperature is negligible. moreover, the internal (onchip) and package skews between each da ta tods and tdr effect can be considered as negligible. consequently, minimum values for tod and tdr are never more than 100 ps apart. the same is true for the tod and tdr maximum val ues. in other terms : if tod is at 1150 ps, tdr will not be at 1620 ps ( maximum time delay for tdr ). if tod is at 1660 ps, tdr will not be at 1110 ps ( minimum time delay for tdr ) however, external tod - tdr values may be dicta ted by total digital datas skews between every tods (each digital data) and tdr : mcm board , bonding wires and output lines lengths differences, and output termination impedance mismatches. the external (on board) skew effect has not been taken into account for the specification of the minimum and maximum values for tod-tdr. 7.1.4. principle of operation the analog input is sampled on the rising edge of external clock input (clk,clkb) after ta (aperture delay) of typically 250ps . the digitized data is available after 4 clock periods latency (pipeline delay (tpd)), on clock rising edge, after 1360 ps typic al propagation delay tod. the data ready differential output signal frequency (dr,drb) is half the external clock frequency, that is it switches at the s ame rate as the digital outputs. the data ready output signal (dr,drb) switches on external clock falling edge after a propagation delay tdr of typically 1320 p s. a master asynchronous reset input command drrb ( ecl compatible single-ended input) is available for initializing the different ial data ready output signal ( dr,drb ) .this feature is mandatory in certain applications using interleaved adcs or using a single adc with demultiplexed outputs. actually, without data ready signal initialization, it is impossible to store the output digital datas i n a defined order. 27 product specification ts8388bf 7.2. principle of data ready signal control by drrb input command 7.2.1. data ready output signal reset the data ready signal is reset on falling edge of drrb input command, on ecl logical low level (-1.8v). drrb may also be tied t o vee = - 5v for data ready output signal master reset. so long drrb remains at logical low level, (or tied to vee = - 5v), the data ready output remains at logical zero and is independant of the external free running encoding clock. the data ready output signal (dr,drb) is reset to logical zero after trdr= 920 ps typical. trdr is measured between the -1.3v point of the falling edge of drrb input command and the zero crossing point of the different ial data ready output signal (dr,drb). the data ready reset command may be a pulse of 1 ns minimum time width. 7.2.2. data ready output signal restart the data ready output signal restarts on drrb command rising edge, ecl logical high levels (-0.8v). drrb may also be grounded, or is allowed to float, for normal free running data ready output signal. the data ready signal restart sequence depends on the logical level of the external encoding clock, at drrb rising edge instant : 1) the drrb rising edge occurs when external encoding clock input (clk,clkb) is low : the data ready output first rising edge occurs after half a clock period on the clock falling edge, after a delay time tdr = 13 20 ps already defined hereabove. 2) the drrb rising edge occurs when external encoding clock input (clk,clkb) is high : the data ready output first rising edge occurs after one clock period on the clock falling edge, and a delay tdr = 1320ps. consequently, as the analog input is sampled on clock rising edge, the first digitized data corresponding to the first acquisit ion ( n ) after data ready signal restart ( rising edge ) is always strobed by the third rising edge of the data ready signal. the time delay (td1) is specified between the last point of a change in the differential output data (zero crossing point) to t he rising or falling edge of the differential data ready signal (dr,drb) (zero crossing point). note 1 : for normal initialization of data ready output signal, the external encoding clock signal frequency and level must be contro lled. it is reminded that the minimum encoding clock sampling rate for the adc is 10 msps and consequently the clock cannot be stoppe d. note 2 : one single pin is used for both drrb input command and die junction temperature monitoring. pin denomination will be drrb/diod.( on former version denomination was diod. ) temperature monitoring and data ready control by drrb is not possible simultaneously. 7.3. analog inputs (vin) (vinb) the analog input full scale range is 0.5 volts peak to peak (vpp), or -2 dbm into the 50 ohms termination resistor. in differential mode input configuration, that means 0.25 volt on each input, or +/- 125 mv around zero volt. the input common mode is ground. the typical input capacitance is 3 pf for ts8388b in cqfp package. the input capacitance is mainly due to the package. differential inputs voltage span -125 125 [mv] -250 mv 250 mv vin 500mv full scale analog input t vinb (vin,vinb) = +/- 250 mv = 500 mv diff 0 volt differential versus single ended analog input operation the ts8388bf can operate at full speed in either differential or single ended configuration. this is explained by the fact the adc uses a high input impedance differential preamplifier stage, (preceeding the sample and h old stage), which has been designed in order to be entered either in differential mode or single?ended mode. 28 ts8388bf product specification this is true so long as the out of phase analog input pin vinb is 50 ohms terminated very closely to one of the neighboring shi eld ground pins (52, 53, 58, 59) which constitute the local ground reference for the inphase analog input pin (vin). thus the differential analog input preamplifier will fully reject the local ground noise ( and any capacitively and inductively coupled noise) as common mode effects. in typical single?ended configuration, enter on the (vin) input pin, with the inverted phase input pin (vinb) grounded through the 50 ohms termination resistor. in single?ended input configuration, the in-phase input amplitude is 0.5 volt peak to peak,centered on 0v. (or -2 dbm into 50 o hms.) the inverted phase input is at ground potential through the 50 ohms termination resistor. however, dynamic performances can be somewhat improved by entering either analog or clock inputs in differential mode. typical single ended analog input configuration vin or vinb vin or vinb double pad (pins 54, 55 or 56, 57) 50 ? (external) 50 ? reverse termination 1m ? 3 pf -250 250 [mv] 500 mv 500 mv full scale analog input t vinb vin vinb = 0v v in = +/- 250 mv ? 500 mv diff 7.4. clock inputs (clk) (clkb) the ts8388bf can be clocked at full speed without noticeable performance degradation in either differential or single ended con figuration. this is explained by the fact the adc uses a differential preamplifier stage for the clock buffer, which has been designed in o rder to be entered either in differential or single?ended mode. recommended sinewave generator characteristics are typically -120 dbc/hz phase noise floor spectral density, @ 1 khz from carr ier , assuming a single tone 4 dbm input for the clock signal. 7.4.1. single ended clock input (g round c ommon m ode ) although the clock inputs were intended to be driven differentially with nominal -0.8v / -1.8v ecl levels, the ts8388bf clock b uffer can manage a single?ended sinewave clock signal centered around 0 volt. this is the most convenient clock input configuration as it does n ot require the use of a power splitter. no performance degradation ( e.g. : due to timing jitter) is observed in this particular single?ended configuration up to 1.2gs ps nyquist conditions ( fin = 600 mhz ). this is true so long as the inverted phase clock input pin is 50 ohms terminated very closely to one of the neighbouring shield ground pin, which constitutes the local ground reference for the inphase clock input. thus the ts8388bf differential clock input buffer will fully reject the local ground noise ( and any capacitively and inductive ly coupled noise) as common mode effects. moreover, a very low phase noise sinewave generator must be used for enhanced jitter performance. the typical inphase clock input amplitude is 1 volt peak to peak, centered on 0 volt (ground) common mode. this corresponds to a typical clock input power level of 4 dbm into the 50 ohms termination resistor. do not exceed 10 dbm to avoid saturation of the preamplifier input transistors. the inverted phase clock input is grounded through the 50 ohms termination resistor. 29 product specification ts8388bf single ended clock input (ground common mode) vclk common mode = 0 volt vclkb=0 volt 4 dbm typical clock input power level (into 50 ohms termination resistor) [v] t vclk vclkb = ( 0 v ) -0.5v +0.5v clk or clkb 50 ? (external) 50 ? reverse termination 1m ? 0.4 pf clk or clkb double pad (pins 37, 38 or 39, 40) note 1 : do not exceed 10 dbm into the 50 ohms termination resistor for single clock input power level. 7.4.2. differential ecl clock input the clock inputs can be driven differentially with nominal -0.8v / -1.8v ecl levels. in this mode, a low phase noise sinewave generator can be used to drive the clock inputs, followed by a power splitter (hybrid junction) in order to obtain 180 degrees out of phase sinewave signals. biasing tees can be used for offseting the common mode voltage to ecl leve ls. note : as the biasing tees propagation times are not matching, a tunable delay line is required in order to ensure the signals to be 180 degrees out of phase especially at fast clock rates in the gsps range. differential clock inputs (ecl levels) -0.8v [mv] t -1.8v vclkb vclk common mode = -1.3 v clk or clkb 50 ? reverse termination 1m ? 0.4 pf -2v 50 ? (external) clk or clkb double pad (pins 37, 38 or 39, 40) 7.4.3. single ended ecl clock input in single?ended configuration enter on clk ( resp. clkb ) pin , with the inverted phase clock input pin clkb (respectively clk) connected to - 1.3v through the 50 ohms termination resistor. the inphase input amplitude is 1 volt peak to peak, centered on -1.3 volt common mode. single ended clock input (ecl): vclk common mode = -1.3 volt. vclkb = -1.3 volt -0.8v [v] t -1.8v vclk vclkb = -1.3 v 30 ts8388bf product specification 7.5. noise immunity informations circuit noise immunity performance begins at design level. efforts have been made on the design in order to make the device as insensitive as possible to chip environment perturbations resulting from the circuit itself or induced by external circuitry. (cascode stages isolation, internal damping resistors, clamps, internal (onchip) decoupling capacitors.) furthermore, the fully differential operation from analog input up to the digital outputs provides enhanced noise immunity by c ommon mode noise rejection. common mode noise voltage induced on the differential analog and clock inputs will be canceled out by these balanced differenti al amplifiers. moreover, proper active signals shielding has been provided on the chip to reduce the amount of coupled noise on the active inp uts : the analog inputs and clock inputs of the ts8388bf device have been surrounded by ground pins, which must be directly connected to the external ground plane. 7.6. digital outputs the ts8388bf differential output buffers are internally 75 ohms loaded. the 75 ohms resistors are connected to the digital grou nd pins through a -0.8v level shift diode (see figures 3,4,5 on next page). the ts8388bf output buffers are designed for driving 75 ohms (default) or 50 ohms properly terminated impedance lines or coaxia l cables. an 11 ma bias current flowing alternately into one of the 75 ohms resistors when switching ensures a 0.825 v voltage drop acros s the resistor (unterminated outputs). the vplusd positive supply voltage allows the adjustment of the output common mode level from -1.2v (vplusd=0v for ecl output compatibility) to +1.2v (vplusd=2.4v for lvds output compatibility). therefore, the single ended output voltages vary approximately between -0.8v and -1.625v, ( outputs unterminated ), around -1.2 v common mode voltage. three possible line driving and back-termination scenarios are proposed (assuming vplusd=0v) : 1 ) 75 ohms impedance transmission lines, 75 ohms differentially terminated (fig. 3) : each output voltage varies between -1v and -1.42v (respectively +1.4v and +1v), leading to +/- 0.41v =0.825 v in differential, around -1.21 v (respectively +1.21v) common mode for vplusd=0v (respectively 2.4v). 2 ) 50 ohms impedance transmission lines, 50 ohms differentially termination (fig. 4) : each output voltage varies between -1.02v and -1.35v (respectively +1.38v and +1.05v), leading to +/- 0.33v=660 mv in different ial, around - 1.18v (respectively +1.21v) common mode for vplusd=0v (respectively 2.4v). 3 ) 75 ohms impedance open transmission lines (fig. 5) : each output voltage varies between -1.6 v and -0.8 v (respectively +0.8v and +1.6v), which are true ecl levels, leading to +/- 0.8v=1.6v in differential, around -1.2v (respectively +1.2v) common mode for vplusd=0v (respectively 2.4v). therefore, it is possible to drive directly high input impedance storing registers, without terminating the 75 ohms transmissio n lines. in time domain, that means that the incident wave will reflect at the 75 ohms transmission line output and travel back to the g enerator ( i.e. the 75 ohms data output buffer ). as the buffer output impedance is 75 ohms, no back reflection will occur. note : this is no longer true if a 50 ohms transmission line is used, as the latter is not matching the buffer 75 ohms output imped ance. each differential output termination length must be kept identical . it is recommended to decouple the midpoint of the differential termination with a 10 nf capacitor to avoid common mode perturba tion in case of slight mismatch in the differential output line lengths. too large mismatches ( keep < a few mm ) in the differential line lengths will lead to switching currents flowing into the deco upling capacitor leading to switching ground noise. the differential output voltage levels ( 75 or 50 ohms termination ) are not ecl standard voltage levels, however it is possib le to drive standard logic ecl circuitry like the eclinps logic line from motorola. at sampling rates exceeding 800msps, it may be difficult to trigger the hp16500 or any other acquisition system with digital ou tputs. it becomes necessary to regenerate digital data and data ready by means of external amplifiers, in order to be able to test the ts8388bf at its optimum performance conditions. 31 product specification ts8388bf 7.6.1. differential output loading configurations ( levels for ecl compatibility ) -+ 11 ma dvee vplusd = 0v 75 ? 75 ? 75 ? 75 ? impedance 10 nf 75 ? 75 ? out -1v / -1.41v outb -1.41v / -1v differential output : 0.41v = 0.825v common mode level : -1.2v (-1.2v below vplusd level) figure 3 : differential output : 75 ? terminated -0.8v -+ 11 ma dvee vplusd = 0v 75 ? 75 ? 50 ? 50 ? impedance 10 nf 50 ? 50 ? out -1.02v / -1.35v outb -1.35v / -1.02v differential output : 0.33v = 0.660v common mode level : -1.2v (-1.2v below vplusd level) figure 4 : differential output : 50 ? terminated -0.8v -+ 11 ma dvee vplusd = 0v 75 ? 75 ? 75 ? 75 ? impedance out -0.8v / -1.6v outb -1.6v / -0.8v differential output : 0.8v = 1.6v common mode level : -1.2v (-1.2v below vplusd level) figure 5 : differential output : open loaded -0.8v 32 ts8388bf product specification 7.6.1. differential output loading configurations ( levels for lvds compatibility ) 7.7. out of range bit an out of range (or,orb) bit is provided that goes to logical high state when the input exceeds the positive full scale or fall s below the negative full scale. when the analog input exceeds the positive full scale, the digital output datas remain at high logical state, with (or,orb) at logical one. when the analog input falls below the negative full scale, the digital outputs remain at logical low state, with (or,orb) at lo gical one again. -+ 11 ma dvee vplusd = 2.4v 75 ? 75 ? 75 ? 75 ? impedance 10 nf 75 ? 75 ? out 1.4v / 0.99v outb 0.99v / 1.4v differential output : 0.41v = 0.825v common mode level : -1.2v (-1.2v below vplusd level) figure 6 : differential output : 75 ? terminated 1.6v -+ 11 ma dvee vplusd = 2.4v 75 ? 75 ? 50 ? 50 ? impedance 10 nf 50 ? 50 ? out 1.38v / 1.05v outb 1.05v / 1.38v differential output : 0.33v = 0.660v common mode level : -1.2v (-1.2v below vplusd level) figure 7 : differential output : 50 ? terminated 1.6v -+ 11 ma dvee vplusd = 2.4v 75 ? 75 ? 75 ? 75 ? impedance out 1.6v / 0.8v outb 0.8v / 1.6v differential output : 0.8v = 1.6v common mode level : -1.2v (-1.2v below vplusd level) figure 8 : differential output : open loaded 1.6v 33 product specification ts8388bf 7.8. gray or binary output data format select the ts8388bf internal regeneration latches indecision (for inputs very close to latches threshold) may produce errors in the lo gic encoding circuitry and leading to large amplitude output errors. this is due to the fact that the latches are regenerating the internal analog residues into logical states with a finite voltag e gain value (av) within a given positive amount of time ? (t) : av= exp ( ? (t)/ ) , with the positive feedback regeneration time constant. the ts8388bf has been designed for reducing the probability of occurrence of such errors to approximately 10 -13 (targeted for the ts8388bf at 1gsps). a standard technique for reducing the amplitude of such errors down to +/-1 lsb consists to output the digital datas in gray co de format. though the ts8388bf has been designed for featuring a bit error rate of 10 -13 with a binary output format, it is possible for the user to select between the binary or gray output data format, in order to reduce the amplitude of such errors when occurring, by storing gray output codes. digital datas format selection : binary output format if gorb is floating or vcc. gray output format if gorb is connected to ground (0v). 7.9. diode pin 49 one single pin is used for both drrb input command and die junction monitoring. the pin denomination is drrb/diod. temperature monitoring and data ready control by drrb is not possible simultaneously. (see section 7.2 for data ready reset input command). the operating die junction temperature must be kept below145 c, therefore an adequate cooling system has to be set up. the diode mounted transistor measured vbe value versus junction temperature is given below. 600 640 680 720 760 800 840 880 920 960 1000 -55 -35 -15 5 25 45 65 85 105 125 junction temperature (deg.c) vbe (mv) 34 ts8388bf product specification 7.10. adc gain control pin 60 the adc gain is adjustable by the means of the pin 60 (input impedance is 1m ? in parallel with 2pf) the gain adjust transfer function is given below : for more information, please refer to the document "demux and adcs application notes". 0,80 0,85 0,90 0,95 1,00 1,05 1,10 1,15 1,20 -500 -400 -300 -200 -100 0 100 200 300 400 500 vgain (command voltage) (mv) adc gain 35 product specification ts8388bf 8. equivalent input / output schematics 8.1. equivalent analog input circuit and esd protections 8.2. equivalent analog clock input circuit and esd protections gnd=0v vcc=+5v vclamp= +2.4v +1.65v -1.55v vee vee vcc gnd vin vinb vee=-5v pad capacitance 340ff pad capacitance 340ff -0.8v -5.8v 5.8v 0.8v 200 ? 200 ? 50 ? 50 ? note : the esd protection equivalent capacitance is 150 ff. e21v e21v -0.8v -5.8v vcc=+5v +0.8v gnd=0v vee vee=-5v clk vcc vee clkb pad capacitance 340ff pad capacitance 340ff -5.8v -5.8v -5.8v -5.8v -5.8v -5.8v 5.8v 5.8v 0.8v 0.8v 150 ? 150 ? 380 a 380 a note : the esd protection equivalent capacitance is 150 ff. 36 ts8388bf product specification 8.3. equivalent data output buffer circuit and esd protections 8.4. adc gain adjust equivalent input circuits and esd protections vplusd=0v to 2.4v dvee=-5v vee=-5v vee=-5v vee vee out outb -5.8v -5.8v 5.8v 5.8v 0.8v 0.8v 0.8v 0.8v i=11ma 75 ? 75 ? -3.7v pad capacitance 180 ff pad capacitance 180 ff note : the esd protection equivalent capacitance is 150 ff. vee vee=-5v vcc=+5v +1.6v pad capacitance 180 ff -0.8 v -5.8 v 0.8v 0.8v 5.8v 1 k ? 2 pf gnd 500 a 500 note : the esd protection equivalent capacitance is 150 ff. +0.8 v gnd 37 product specification ts8388bf 8.5. gorb equivalent input schematic and esd protections gorb: gray or binary select input; floating or tied to vcc -> binary 8.6. drrb equivalent input schematic and esd protections vcc=+5v vee=-5v gnd=0v -0.8v -0.8v -5.8v 5.8v 5.8v 5.8v 5 k ? 1 k ? 1 k ? 1 k ? 250 note : the esd protection equivalent capacitance is 150 ff. vee=-5v vee vcc=+5v gnd=0v -1.3v -2.6v 10 k ? 200 ? drrb 5.8 v pad capacitance 180 ff actual protection range: 6.6v above vee, in fact stress above gnd are clipped by the cb diode used for tj monitoring 0.8 v np1032c2 note : the esd protection equivalent capacitance is 150 ff. vee 38 ts8388bf product specification 9. tsev8388bf : device evaluation board for complete specification, see separate tsev8388bf document. general description the tsev8388bf evaluation board (eb) is a board which has been designed in order to facilitate the evaluation and the character ization of the ts8388bf device up to its 1.5 ghz full power bandwidth at up to 1 gsps in the military temperature range. the high speed of the ts8388bf requires careful attention to circuit design and layout to achieve optimal performance. this four metal layer board with internal ground plane has the adequate functions in order to allow a quick and simple evaluati on of the ts8388bf adc performances over the temperature range. the tsev8388bf evaluation board is very straightforward as it only implements the ts8388bf adc, sma connectors for input / out put accesses and a 2.54 mm pitch connector compatible with hp16500c high frequency probes. the board also implements a de?embedding fixture in order to facilitate the evaluation of the high frequency insertion loss of the input microstrip lines, and a die junction temperature measurement setting. the board is constituted by a sandwich of two dielectric layers, featuring low insertion loss and enhanced thermal characterist ics for operation in the high frequency domain and extended temperature range. the board dimensions are 130 mm x 130 mm. the board set comes fully assembled and tested, with the ts8388bf in cqfp68 package installed. 39 product specification ts8388bf 10. ordering information 10.1. package device 10.2. evaluation board the evaluation board is delivered with an adc and includes the heat sink. manufacturer prefix device or family temperature range : package : m : -55 < tc ; tj < 125 c v : -40 < tc ; tj < 110 c c : 0 < tc ; tj < 90 c f : cqfp68 gullwing ts 8388b m f b/q screening level : ___ : standard b/q : mil-prf-38535, qml level q ts (x) ev 8388b f za2 za2 : with mc100el16 digital receivers _: without receivers prototype board evaluation board prefix cqfp68 package 40 ts8388bf product specification atmel headquarters corporate headquarters 2325 orchard parkway san jose, ca 95131 tel (408) 441-0311 fax (408) 487-2600 europe atmel sarl route des arsenaux 41 casa postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia atmel asia, ltd. room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan atmel japan k.k. 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 atmel operations atmel colorado springs 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 tel (719) 576-3300 fax (719) 540-1759 atmel rousset zone industrielle 13106 rousset cedex france tel (33) 4-4253-6000 fax (33) 4-4253-6001 atmel smart card ics scottish enterprise technology park east kilbride, scotland g75 0qr tel (44) 1355-357-000 fax (44) 1355-242-743 atmel grenoble avenue de rochepleine bp 123 38521 saint-egreve cedex france tel (33) 4-7658-3000 fax (33) 4-7658-3480 fax-on-demand north america: 1-(800) 292-8635 international: 1-(408) 441-0732 e-mail literature@atmel.com web site http://www.atmel.com bbs 1-(408) 436-4309 ? atmel corporation 2001. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company?s standard warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without n otice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of at mel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel?s products are not authorized for use as critical components in life support devices or systems. marks bearing ? and/or ? are registered trademarks and trademarks of atmel corporation. terms and product names in this document may be trademarks of others. this product is manufactured and commercialized by atmel grenoble. for further information, please contact : atmel grenoble ? route departementale 128 ? bp 46 ? 91901 orsay cedex ? france phone +33 (0) 1 69 33 03 24 ? fax +33 (0) 1 69 33 03 21 email monique.lafrique@gfo.atmel.com ? web site http://www.atmel-grenoble.com for further technical information, please contact the technical support : email hotline-bdc@gfo.atmel.com |
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