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tl/d/12511 nm93c86al 16,384-bit serial interface, low voltage cmos eeprom (microwire synchronous bus) september 1996 nm93c86al 16,384-bit serial interface, low voltage cmos eeprom (microwire tm synchronous bus) general description the nm93c86al is 16,384 bits of cmos nonvolatile, elec- trically erasable memory available user organized as either 1024 16-bit registers or 2048 8-bit registers. the user orga- nization is determined by the status of the org input. the memory device is fabricated using national semiconduc- tor's floating gate cmos process for high reliability, high endurance, and low power consumption. the nm93c86al is available in an 8-pin so package for space considera- tions. the eeprom is microwire compatible for simple inter- facing to a wide variety of microcontrollers and microproc- essors. there are 7 instructions that operate the nm93c86al: read, erase/write enable, erase, write, erase/write disable, write all, and erase all. the nm93c86al defaults to the 1024 x 16 configuration if the org pin (pin 6) is left floating, as it is internally pulled up to v cc . features y 2.7v to 5.5v operation in all modes y typical active current of 100 m a; typical standby current of 1 m a y device status indication during programming mode y no erase required before write y reliable cmos floating gate technology y microwire compatible serial i/o y self-timed programming cycle y 40 years data retention y endurance: 10 6 data changes y packages available: 8-pin so, 8-pin dip block diagram tl/d/12511 1 tri-state is a registered trademark of national semiconductor corporation. microwire tm is a trademark of national semiconductor corporation. c 1996 national semiconductor corporation rrd-b30m96/printed in u. s. a. http://www.national.com
connection diagram dual-in-line package (n) and 8-pin so package (m8) tl/d/12511 3 top view see ns package number n08e and m08a pin names cs chip select sk serial data clock di serial data input do serial data output v ss ground org memory organizational select nc no connect v cc positive power supply ordering information commercial temp. range (0 cto a 70 c) order number nm93c86aln nm93c86alm8 extended temp. range ( b 40 cto a 85 c) order number NM93C86ALEN nm93c86alem8 automotive temp. range ( b 40 cto a 125 c) order number nm93c86alvn nm93c86alvm8 http://www.national.com 2
absolute maximum ratings (note 1) if military/aerospace specified devices are required, please contact the national semiconductor sales office/distributors for availability and specifications. ambient storage temperature b 65 cto a 150 c all input or output voltage with respect to ground v cc a 1to b 0.3v lead temperature (soldering, 10 sec.) a 300 c esd rating 2000v operating conditions ambient operating temperature nm93c86al 0 cto a 70 c nm93c86ale b 40 cto a 85 c nm93c86alv b 40 cto a 125 c power supply (v cc ) range 2.7v to 5.5v dc and ac electrical characteristics 2.7v s v cc k 4.5v symbol parameter part number condition min max units i cca operating current cs e v ih ,f sk e 250 khz 1 ma i ccs standby current cs e 0v, org e v cc or nc 50 m a i il input leakage v in e 0v to v cc (note 2) b 11 m a i ilo input leakage org tied to v cc b 11 org pin org tied to v ss b 2.5 2.5 m a (note 3) i ol output leakage v in e 0v to v cc b 11 m a v il input low voltage b 0.1 0.15 v cc v v ih input high voltage 0.8 v cc v cc a 1v v ol output low voltage i ol e 10 m a 0.2 v v oh output high voltage i oh eb 10 m a 0.9 v cc v f sk sk clock frequency (note 4) 0 250 khz t skh sk high time 1 m s t skl sk low time 1 m s t cs minimum cs low time (note 5) 1 m s t css cs set-up time 0.2 m s t dh do hold time 70 ns t dis di set-up time 0.4 m s t csh cs hold time 0 m s t dih di hold time 0.4 m s t pd1 output delay to ``1'' 2 m s t pd0 output delay to ``0'' 2 m s t sv cs to status valid 1 m s t df cs to do in tri-state 0.4 m s t wp write cycle time 15 ms http://www.national.com 3
dc and ac electrical characteristics 4.5v s v cc k 5.5v symbol parameter part number condition min max units i cca operating current cs e v ih ,f sk e 250 khz 1 ma i ccs standby current cs e 0v, org e v cc or nc 50 m a i il input leakage v in e 0v to v cc (note 2) b 11 m a i ilo input leakage org tied to v cc b 11 org pin org tied to v ss b 2.5 2.5 m a (note 3) i ol output leakage v in e 0v to v cc b 11 m a v il input low voltage b 0.1 0.8 v v ih input high voltage 2 v cc a 1v v ol1 output low voltage i ol e 2.1 ma 0.4 v v oh1 output high voltage i oh eb 400 m a 2.4 v v ol2 output low voltage i ol e 10 m a 0.2 v v oh2 output high voltage i oh eb 10 m av cc b 0.2 v f sk sk clock frequency (note 4) 0 1 mhz t skh sk high time nm93c86al 250 ns nm93c86ale/v 300 t skl sk low time 250 ns t cs minimum cs low time (note 5) 250 ns t css cs set-up time 50 ns t dh do hold time 70 ns t dis di set-up time 100 ns t csh cs hold time 0ns t dih di hold time 20 ns t pd1 output delay to ``1'' 500 ns t pd0 output delay to ``0'' 500 ns t sv cs to status valid 500 ns t df cs to do in tri-state 100 ns t wp write cycle time 10 ms http://www.national.com 4
capacitance t a ea 25 c, f e 1 mhz symbol test max units c out output capacitance 5 pf c in input capacitance 5 pf ac test conditions output load 1 ttl gate and c l e 100 pf input pulse levels 0.4v and 2.4v timing measurement reference level input 1v and 2v output 0.8v and 2.0v note 1: stress ratings above those listed under ``absolute maximum ratings'' may cause permanent damage to the device. this is a stress rating only and operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: typical leakage values are in the 20 na range. note 3: the org pin may draw l 1 m a when in the x8 mode due to an internal pull-up transistor. note 4: the shortest allowable sk clock period e 1/f sk (as shown under the f sk parameter). maximum sk clock speed (minimum sk period) is determined by the interaction of several ac parameters stated in the datasheet. within this sk period, both t skh and t skl limits must be observed. therefore, it is not allowable to set 1/t sk e t skh(minimum) a t skl(minimum) for shorter sk cycle time operation. note 5: cs (chip select) must be brought low (to v il ) for an interval of t cs in order to reset all internal device registers (device reset) prior to beginning another opcode cycle. (this is shown in the opcode diagrams in the following pages.) http://www.national.com 5
interface pin description chip select (cs): chip select performs several functions. it is used to differ- entiate between various devices on the same microwire bus. the rising edge resets the internal circuitry of the de- vice, a function necessary prior to initiating a new cycle. chip select (as shown on block diagram) also gates the data input (di) and serial clock (sk) input, to disable these functions. in the case of these eeproms, chip select can- not be tied high even if it is the only device on the bus. chip select must be held high continuously during the course of clocking in the start bit, op-code address, and data-in or data-out. otherwise the internal circuits will reset and the cycle will have to be started again with a new start bit. chip select initiates the internal programming cycle. the falling edge of chip select will start the internal asynchro- nous programming cycle after a programming op-code has been entered (erase, write, erase all, or write all). in con- junction with chip select, data-out (do) will indicate when programming is complete. if the internal programming is in- complete, then data-out pin will be low. then when the internal programming is complete, the data-out pin will be high (see timing diagrams). serial clock (sk): the serial clock input is used to clock all start bits, op- codes, data, addresses, and data bits into or out of the eeproms. the clock's rising edge controls the input and output of bits. the falling edge has no effect on the device. the serial clock is not necessary for the asynchronous ready/busy polling function. the serial clock is in a ``don't care'' at any time chip select is low. it is also in a ``don't care'' state prior to clocking in a start bit, or during ready/busy polling. during either of these last two conditions, data-in (di) must be held at a low level, otherwise a new start bit will be interpreted. data-in (di): the data-in pin receives the start bit, address, and input data synchronously. each bit is clocked in on the rising edge of sk. di is gated by chip select to provide a high degree of noise immunity. data-in is routed to both the instruction shift register and the data shift register. after the start bit is clocked into the last bit of the instruction register, the clock is switched to the data register to receive input data. to avoid false reading of a start bit, it is safer to keep the data- in pin at low level when not in use. data-out (do): the data-out pin sends read data onto the microwire bus and it is clocked out on the rising edge of the serial clock. during the read cycle, the do output begins to drive actively after the last address bit (a0) is clocked in. data-out also carries the device's status during the asyn- chronous programming cycle. the data-out pin drives low while the device is still in its internal programming cycle. after the eeprom has completed this internal program- ming, data-out will drive high. this is accomplished while chip select is held high. finally, if chip select is pulsed low to high, data-out pin will again produce a pulse high. thus indicating the com- pletion of the programming cycle. to clear the ready/busy polling, it is necessary to raise chip select and clock in another start bit. once the start bit is clocked in, data-out will return to the high impedance state. it is not necessary to continue with a cycle after this start bit has been clocked in, although it is permissible to start a new cycle with this start bit. this clearing of ready/ busy status may be necessary if a bidirectional data bus is used (data-in tied to data-out) as the data-out output will interfere with the new data being presented on the data-in pin. this connecting of the two data pins is used for three- wire interface schemes. organization (org): the organization input (org) is available on the nm93c86al device and it is used to control the internal organization of the memory. the two selectable organiza- tions are 16-bit words and 8-bit words. by connecting the org pin to v cc , 16-bit words are selected. in contrast, by connecting the org pin to gnd, 8-bit words are selected. if the org pin is left floating, then default setting is the 16-bit word. when in the 8-bit mode, one additional address bit is required in the instruction sequence since the depth of the memory is doubled. http://www.national.com 6
instruction set for the nm93c86al the nm93c86al has 7 instructions as described below. note that the msb of any instruction is a ``1'' and is viewed as a start bit in the interface sequence. the next 2 bits carry the op code, the next 10 (or 11) bits carry the address for selection of 1 of 1024 16-bit registers or 1 of 2048 8-bit registers, depending on memory array organization. 1024 by 16-bit organization (nm93c86al when org e v cc or nc) instruction sb op-code address data function 2 bits 10 bits 16 bits read 1 10 a9 a0 read data stored in selected register. ewen 1 00 11xxxxxxxx enables programming modes. ewds 1 00 00xxxxxxxx disables all programming modes. erase 1 11 a9 a0 erases selected register. write 1 01 a9 a0 d15 d0 writes data pattern d15 d0 into selected register. eral 1 00 10xxxxxxxx erases all registers. wral 1 00 01xxxxxxxx d15 d0 writes data pattern d15 d0 into all registers. 2048 by 8-bit organization (nm93c86al when org e gnd) instruction sb op-code address data function 2 bits 11 bits 18 bits read 1 10 a10 a0 read data stored in selected register. ewen 1 00 11xxxxxxxxx enables programming modes. ewds 1 00 00xxxxxxxxx disables all programming modes. erase 1 11 a10 a0 erases selected register. write 1 01 a10 a0 d7 d0 writes data pattern d7 d0 into selected register. eral 1 00 10xxxxxxxxx erases all registers. wral 1 00 01xxxxxxxxx d7 d0 writes data pattern d7 d0 into all registers. functional description device org pin memory logic configuration y of address bits nm93c86al 0 2048 x 8 11 bits 1 1024 x 16 10 bits programming the programming cycle for both devices is automatically started after entering the d0 data bit; independent of the status of the cs input pin. this feature allows a program- ming instruction (erase/write/eral/wral) to be can- celled at any time before entering the last data bit (d0). this is accomplished by forcing the cs input pin low (for t cs )at any time before the do data bit is clocked in. note that the cs input pin can be brought low after the d0 bit is clocked in, to maintain compatibility with the other family members, but is not necessary to start a programming cycle. in all programming modes the ready/busy status of the device can be determined by polling the do pin. after clock- ing in the last bit of the instruction sequence and with the cs held ``high'', the do pin will exit the high impedance state and indicate the ready/busy status of the device. do e logical ``0'' indicates that programming is still in prog- ress and no other instruction can be executed. do e logi- cal ``1'' indicates that the device is ready for another in- struction. if cs is forced ``low'' the do pin will return to the high impedance state. after the programming cycle has been completed and do e logical ``1'', the do pin can be reset back to the high impedance state by clocking a logical ``1'' into the di pin. (this is also performed with the start bit on all op codes, thus clocking an instruction has the same effect.) read (read) the read instruction outputs serial data on the do pin. after a read instruction is received, the instruction and ad- dress are decoded, followed by data transfer from the se- lected memory register into a serial-out shift register. a dummy bit (logical 0) precedes the serial data output string. output data changes are initiated by a low to high transition of the sk clock after the last address bit (a0) is clocked in. http://www.national.com 7
functional description (continued) erase/write enable (ewen) when v cc is applied to the part, it ``powers up'' in the erase/write disable (ewds) state. therefore, all program- ming modes must be preceded by an erase/write enable (ewen) instruction. once an erase/write enable instruc- tion is executed, programming remains enabled until an erase/write disable (ewds) instruction is executed or v cc is removed from the part. erase/write disable (ewds) to protect against accidental data overwrites, the erase/ write disable (ewds) instruction disables all programming modes and should follow all programming operations. exe- cution of a read instruction is independent of both the ewen and ewds instructions. erase (erase) the erase instruction will program all bits in the specified register to the logical ``1'' state. the self-timed programming cycle is initiated on the rising edge of the sk clock as the last address bit (a0) is clocked in. at this point cs, sk, and di become don't care states. after starting an erase cycle the do pin indicates the ready/busy status of the chip if cs is held ``high''. do e logical ``0'' indicates that program- ming is still in progress. do e logical ``1'' indicates that the register, at the address specified in the instruction, has been erased. write (write) the write instruction is followed by 16 bits of data (or 8 bits of data when using the nm93c86al in the x8 organi- zation) to be written into the specified address. note that if the cs is brought ``low'' before clocking in all of the data bits, then the write instruction will be aborted. the self- timed programming cycle is initiated on the rising edge of the sk clock as the last data bit (d0) is clocked in. at this point, cs, sk and di become don't care states. no separate erase cycle is required before a write instruction. as in the erase instruction, after starting a write cycle, the do pin indicates the ready/busy status of the chip if cs is held ``high''. do e logical ``0'' indicates that program- ming is still in progress. do e logical ``1'' indicates that the register, at the address specified in the instruction, has been written and that the part is ready for another instruction. erase all (eral) the eral instruction will simultaneously program all regis- ters in the memory array to the logical ``1'' state. write all (wral) the wral instruction will simultaneously program all regis- ters with the data pattern specified in the instruction. timing diagrams for the nm93c86al synchronous data timing tl/d/12511 4 http://www.national.com 8
timing diagrams (continued) organization of address and data fields for the nm93c86al org organization a n d n v cc or nc 1024 x 16 a9 d15 v ss 2048 x 8 a10 d7 read tl/d/12511 5 ewen do e tri-state tl/d/12511 6 ewds do e tri-state tl/d/12511 7 erase tl/d/12511 8 http://www.national.com 9
timing diagrams (continued) write tl/d/12511 9 eral tl/d/12511 10 wral tl/d/12511 11 http://www.national.com 10
physical dimensions inches (millimeters) unless otherwise noted molded small out-line package (m8) ns package number m08a http://www.national.com 11
nm93c86al 16,384-bit serial interface, low voltage cmos eeprom (microwire synchronous bus) physical dimensions inches (millimeters) unless otherwise noted (continued) molded dual-in-line package (n) ns package number n08e life support policy national's products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of national semiconductor corporation. as used herein: 1. life support devices or systems are devices or 2. a critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. national semiconductor national semiconductor national semiconductor national semiconductor corporation europe hong kong ltd. japan ltd. 1111 west bardin road fax: a 49 (0) 180-530 85 86 13th floor, straight block, tel: 81-043-299-2308 arlington, tx 76017 email: europe.support @ nsc.com ocean centre, 5 canton rd. fax: 81-043-299-2408 tel: 1(800) 272-9959 deutsch tel: a 49 (0) 180-530 85 85 tsimshatsui, kowloon fax: 1(800) 737-7018 english tel: a 49 (0) 180-532 78 32 hong kong fran 3 ais tel: a 49 (0) 180-532 93 58 tel: (852) 2737-1600 http://www.national.com italiano tel: a 49 (0) 180-534 16 80 fax: (852) 2736-9960 national does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and national reserves the right at any time without notice to change said circuitry and specifications.

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