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1/29 january 2006 m41st84w 3.0/3.3v i 2 c serial rtc with supervisory functions rev 7.0 key features automatic battery switchover and deselect ? power-fail deselect, v pfd = 2.60v (nom) ? switchover, v so = 2.50v (nom) 400khz i 2 c serial interface 3.0/3.3v operating voltage ?v cc = 2.7 to 3.6v ultra-low battery supply current of 500na (max) rohs compliance lead-free components are compliant with the rohs directive. serial rtc features 400khz i 2 c 44 bytes of general purpose nvram counters for: ? seconds, minutes, hours, day, date, month, and year ?century ? 10ths/100ths of seconds ? clock calibration register allows compensation for crystal variations over temperature programmable alarm with interrupt ? functions during battery back-up mode power-down timestamp (ht bit) 2.5 to 5.5v oscillator operating voltage 32khz oscillator with integrated load capacitance (12.5pf) microprocessor supervisory features programmable watchdog timer ? 62.5ms to 128s time-out period power-on reset/low voltage detect output pfi/pfo with 1.25v reference figure 1. 16-pin soic package nvram supervisory features non-volatizes external lpsram ? automatically switches to back-up battery and deselects (write-protects) external lpsram via chip-enable gate ? power-fail deselect (write protect) voltage, v pfd = 2.60v (nom) ? switchover , v so = 2.50v (nom) battery low flag other features programmable squarewave generator (1hz to 32khz) ?40c to +85c operation packaged in a 16-lead soic 16 1 so16 (mq)
m41st84w 2/29 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 serial rtc features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 microprocessor supervisory features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. 16-pin soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 nvram supervisory features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 other features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. 16-pin soic connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 5. hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2-wire bus characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6. serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 7. acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 8. bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 9. slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 10.read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 11.alternate read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 write mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 data retention mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 12.write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 timekeeper? registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3. timekeeper? register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 calibrating the clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 13.crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 14.clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 15.alarm interrupt reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 16.back-up mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3/29 m41st84w reset input (rstin). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 17.rstin timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6. reset ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 power-fail input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 output driver pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 battery low warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 t rec bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 initial power-on defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. t rec definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 table 8. default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 9. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10. dc and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 18.ac testing input/output waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 13. crystal electrical characteristics (externally supplied) . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 19.power down/up mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 14. power down/up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 20.so16 ? 16-lead plastic small outline, package outline. . . . . . . . . . . . . . . . . . . . . . . . . 26 table 15. so16 ? 16-lead plastic small outline, package mechanical data . . . . . . . . . . . . . . . . . 26 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 16. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 17. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
m41st84w 4/29 summary description the m41st84w serial real-time clock is built in a low power cmos sram process. it has a 64- byte memory space with 44 bytes of nvram and 20 memory-mapped rtc registers (see table 3., page 14 ). the rtc registers are configured in binary coded decimal (bcd) format. a built-in, low power 32.768khz oscillator (external crystal controlled) provides the time base for the timekeeping and calendar functions. the basic clock/calendar functions are handled by the first eight rtc registers, while the other twelve bytes provide status/control for the alarm, watch- dog, and square wave functions. addresses and data are transferred serially via the two line, bi-directional i 2 c interface. the built-in address register is incremented automatically af- ter each write or read data byte. the m41st84w has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power fail- ure occurs. the energy needed to sustain the sram and clock operations can be supplied by a small lithium button-cell supply when a power fail- ure occurs. functions available to the user include a non-volatile, time-of-day clock/calendar, alarm interrupts, watchdog timer and programmable square wave output. other features include a power-on reset as well as an additional input (rstin ) which can also generate an output reset (rst ). the eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24 hour bcd format. corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically. the m41st84w is supplied in a 16-lead soic package. figure 2. logic diagram table 1. signal names ai03677 scl v cc m41st84w v ss sda rstin irq/ft/out sqw wdi pfi rst pfo v bat xi xo xi oscillator input xo oscillator output irq /ft/out interrupt/frequency test/out output (open drain) pfi power fail input pfo power fail output rst reset output (open drain) rstin reset input scl serial clock input sda serial data input/output sqw square wave output wdi watchdog input v cc supply voltage v bat battery supply voltage v ss ground nc no connect
5/29 m41st84w figure 3. 16-pin soic connections figure 4. block diagram note: 1. open drain output ai03678 8 2 3 4 5 6 7 9 10 11 12 13 14 16 15 1 rstin wdi irq/ft/out sda v bat pfi nc sqw scl nc pfo v ss rst xo xi v cc m41st84w ai03931 compare v pfd = 2.65v v cc compare v so = 2.5v v int v bl = 2.5v bl compare crystal 400khz i 2 c interface real time clock calendar 44 bytes user ram rtc w/alarm & calibration watchdog square wave sda scl 1.25v pfi pfo rstin por sqw rst (1) wdi wdf af irq/ft/out (1) v bat 32khz oscillator compare (internal)
m41st84w 6/29 figure 5. hardware hookup note: 1. user-supplied crystal ai03680 v cc pfo scl wdi rstin pfi v ss v bat irq/ft/out sqw rst sda xo xi m41st84w unregulated voltage regulator v cc v in to rst to led display to nmi to int r1 32khz (1) xtal r2 from mcu
7/29 m41st84w operating modes the m41st84w clock operates as a slave device on the serial bus. access is obtained by imple- menting a start condition followed by the correct slave address (d0h). the 64 bytes contained in the device can then be accessed sequentially in the following order: 1. tenths/hundredths of a second register 2. seconds register 3. minutes register 4. century/hours register 5. day register 6. date register 7. month register 8. year register 9. control register 10. watchdog register 11 - 16. alarm registers 17 - 19. reserved 20. square wave register 21 - 64. user ram the m41st84w clock continually monitors v cc for an out-of tolerance condition. should v cc fall below v pfd , the device terminates an access in progress and resets the device address counter. inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out-of-tolerance system. when v cc falls below v so , the device automati- cally switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. as system power returns and v cc rises above v so , the battery is disconnected, and the power supply is switched to external v cc . write protection continues until v cc reaches v pfd (min) plus t rec (min). for more information on battery storage life refer to application note an1012. 2-wire bus characteristics the bus is intended for communication between different ics. it consists of two lines: a bi-direction- al data signal (sda) and a clock signal (scl). both the sda and scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. ? changes in the data line, while the clock line is high, will be interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy. both data and clock lines remain high. start data transfer. a change in the state of the data line, from high to low, while the clock is high, defines the start condition. stop data transfer. a change in the state of the data line, from low to high, while the clock is high, defines the stop condition. data valid. the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowl- edges with a ninth bit. by definition a device that gives out a message is called ?transmitter?, the receiving device that gets the message is called ?receiver?. the device that controls the message is called ?master?. the de- vices that are controlled by the master are called ?slaves?. acknowledge. each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge relat- ed clock pulse. a slave receiver which is ad- dressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low dur- ing the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must sig- nal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case the transmitter must leave the data line high to enable the master to generate the stop condition.
m41st84w 8/29 figure 6. serial bus data transfer sequence figure 7. acknowledgement sequence ai00587 data clock data line stable data valid start condition change of data allowed stop condition ai00601 data output by receiver data output by transmitter sclk from master start clock pulse for acknowledgement 12 89 msb lsb
9/29 m41st84w figure 8. bus timing requirements sequence table 2. ac characteristics note: 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.7 to 3.6v (except where noted). 2. transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of scl. symbol parameter (1) min max unit f scl scl clock frequency 0 400 khz t buf time the bus must be free before a new transmission can start 1.3 s t f sda and scl fall time 300 ns t hd:dat (2) data hold time 0 s t hd:sta start condition hold time (after this period the first clock pulse is generated) 600 ns t high clock high period 600 ns t low clock low period 1.3 s t r sda and scl rise time 300 ns t su:dat data setup time 100 ns t su:sta start condition setup time (only relevant for a repeated start condition) 600 ns t su:sto stop condition setup time 600 ns ai00589 sda p tsu:sto tsu:sta thd:sta sr scl tsu:dat tf thd:dat tr thigh tlow thd:sta tbuf s p
m41st84w 10/29 read mode in this mode the master reads the m41st84w slave after setting the slave address (see figure 9., page 10 ). following the write mode control bit (r/w =0) and the acknowledge bit, the word address ?an? is written to the on-chip address pointer. next the start condition and slave ad- dress are repeated followed by the read mode control bit (r/w =1). at this point the master trans- mitter becomes the master receiver. the data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. the address pointer is only incremented on reception of an acknowledge clock. the m41st84w slave transmitter will now place the data byte at address an+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to ?an+2.? this cycle of reading consecutive addresses will continue until the master receiver sends a stop condition to the slave transmitter (see figure 10., page 11 ). the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). the update will resume ei- ther due to a stop condition or when the pointer increments to a non-clock or ram address. note: this is true both in read mode and write mode. an alternate read mode may also be implement- ed whereby the master reads the m41st84w slave without first writing to the (volatile) address pointer. the first address that is read is the last one stored in the pointer (see figure 11., page 11 ). figure 9. slave address location ai00602 r/w slave address start a 01000 11 msb lsb
11/29 m41st84w figure 10. read mode sequence figure 11. alternate read mode sequence ai00899 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address s start r/w slave address ack ai00895 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x slave address
m41st84w 12/29 write mode in this mode the master transmitter transmits to the m41st84w slave receiver. bus protocol is shown in figure 12., page 12 . following the start condition and slave address, a logic '0' (r/ w =0) is placed on the bus and indicates to the ad- dressed device that word address an will follow and is to be written to the on-chip address pointer. the data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next memory location within the ram on the reception of an acknowledge clock. the m41st84w slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address (see figure 9., page 10 ) and again after it has received the word address and each data byte. data retention mode with valid v cc applied, the m41st84w can be ac- cessed as described above with read or write cycles. should the supply voltage decay, the m41st84w will automatically deselect, write pro- tecting itself when v cc falls between v pfd (max) and v pfd (min). this is accomplished by internally inhibiting access to the clock registers. at this time, the reset pin (rst ) is driven active and will remain active until v cc returns to nominal levels. when v cc falls below the battery back-up switchover voltage (v so ), power input is switched from the v cc pin to the external battery, and the clock registers and sram are maintained from the attached battery supply. all outputs become high impedance. on power up, when v cc returns to a nominal value, write protec- tion continues for t rec . the rst signal also re- mains active during this time (see figure 19., page 25 ). for a further more detailed review of lifetime calcu- lations, please see application note an1012. figure 12. write mode sequence ai00591 bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address
13/29 m41st84w clock operation the eight byte clock register (see table 3., page 14 ) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. tenths/hundredths of sec- onds, seconds, minutes, and hours are contained within the first four registers. note: a write to any clock register will result in the tenths/hundredths of seconds being reset to ?00,? and tenths/hundredths of seconds cannot be written to any value other than ?00.? bits d6 and d7 of clock register 03h (century/ hours register) contain the century enable bit (ceb) and the century bit (cb). setting ceb to a '1' will cause cb to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (de- pending upon its initial state). if ceb is set to a '0,' cb will not toggle. bits d0 through d2 of register 04h contain the day (day of week). registers 05h, 06h, and 07h contain the date (day of month), month and years. the ninth clock register is the control register (this is described in the clock calibration section). bit d7 of register 01h con- tains the stop bit (st). setting this bit to a '1' will cause the oscillator to stop. if the device is expect- ed to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce cur- rent drain. when reset to a '0' the oscillator restarts within one second. the eight clock registers may be read one byte at a time, or in a sequential block. the control reg- ister (address location 08h) may be accessed in- dependently. provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. if a clock ad- dress is being read, an update of the clock regis- ters will be halted. this will prevent a transition of data during the read. power-down time-stamp when a power failure occurs, the halt update bit (ht) will automatically be set to a '1.' this will pre- vent the clock from updating the timek eeper ? registers, and will allow the user to read the exact time of the power-down event. resetting the ht bit to a '0' will allow the clock to update the time- keeper registers with the current time. for more information, see application note an1572. timekeeper ? registers the m41st84w offers 12 additional internal reg- isters which contain the alarm, watchdog, flag, square wave and control data. these registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as biport ? timekeeper cells). the external copies are independent of internal func- tions except that they are updated periodically by the simultaneous transfer of the incremented inter- nal copy. the internal divider (or clock) chain will be reset upon the completion of a write to any clock address. the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). the update will resume ei- ther due to a stop condition or when the pointer increments to a non-clock or ram address. timekeeper and alarm registers store data in bcd. control, watchdog and square wave reg- isters store data in binary format.
m41st84w 14/29 table 3. timekeeper ? register map keys: s = sign bit ft = frequency test bit st = stop bit 0 = must be set to zero bl = battery low flag (read only) bmb0-bmb4 = watchdog multiplier bits ceb = century enable bit cb = century bit out = output level afe = alarm flag enable flag rb0-rb1 = watchdog resolution bits wds = watchdog steering bit abe = alarm in battery back-up mode enable bit rpt1-rpt5 = alarm repeat mode bits wdf = watchdog flag (read only) af = alarm flag (read only) sqwe = square wave enable rs0-rs3 = sqw frequency ht = halt update bit tr = t rec bit address data function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h 0.1 seconds 0.01 seconds seconds 00-99 01h st 10 seconds seconds seconds 00-59 02h 0 10 minutes minutes minutes 00-59 03h ceb cb 10 hours hours (24 hour format) century/hours 0-1/00-23 04htr0000 day of week day 01-7 05h 0 0 10 date date: day of month date 01-31 06h00010m month month 01-12 07h 10 years year year 00-99 08h out ft s calibration control 09h wds bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 0ah afe sqwe abe al 10m alarm month al month 01-12 0bh rpt4 rpt5 ai 10 date alarm date al date 01-31 0ch rpt3 ht ai 10 hour alarm hour al hour 00-23 0dh rpt2 alarm 10 minutes alarm minutes al min 00-59 0eh rpt1 alarm 10 seconds alarm seconds al sec 00-59 0fhwdfaf0bl0 0 0 0 flags 10h00000000reserved 11h00000000reserved 12h00000000reserved 13h rs3 rs2 rs1 rs0 0 0 0 0 sqw
15/29 m41st84w calibrating the clock the m41st84w is driven by a quartz controlled oscillator with a nominal frequency of 32,768hz. the devices are tested not exceed +/?35 ppm (parts per million) oscillator frequency error at 25 o c, which equates to about +/?1.53 minutes per month. when the calibration circuit is properly em- ployed, accuracy improves to better than 2 ppm at 25c. the oscillation rate of crystals changes with tem- perature (see figure 13., page 16 ). therefore, the m41st84w design employs periodic counter cor- rection. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the di- vide by 256 stage, as shown in figure 14., page 16 . the number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration bits occupy the five lower order bits (d4-d0) in the control register (08h). these bits can be set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit; '1' indi- cates positive calibration, '0' indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 osc illator cycles. if a bi- nary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or ?2.034 ppm of adjustment per calibra- tion step in the calibration register. assuming that the oscillator is running at exactly 32,768hz, each of the 31 increments in the calibration byte would represent +10.7 or ?5.35 seconds per month which corresponds to a total range of +5.5 or ?2.75 minutes per month. two methods are available for ascertaining how much calibration a given m41st84w may require. the first involves setting the clock, letting it run for a month and comparing it to a known accurate ref- erence and recording deviation over a fixed period of time. calibration values, including the number of seconds lost or gained in a given period, can be found in application note an934: tim ekeeper calibration. this allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. the designer could provide a simple utility that ac- cesses the calibration byte. the second approach is better suited to a manu- facturing environment, and involves the use of the irq /ft/out pin. the pin will toggle at 512hz, when the stop bit (st, d7 of 01h) is '0,' the fre- quency test bit (ft, d6 of 08h) is '1,' the alarm flag enable bit (afe, d7 of 0ah) is '0,' and the watchdog steering bit (wds, d7 of 09h) is '1' or the watchdog register (09h = 0) is reset. any deviation from 512hz indicates the degree and direction of oscillator frequency shift at the test temperature. for example, a reading of 512.010124hz would indicate a +20 ppm oscillator frequency error, requiring a ?10 (xx001010) to be loaded into the calibration byte for correction. note that setting or changing the calibration byte does not affect the frequency test output frequen- cy. the irq /ft/out pin is an open drain output which requires a pull-up resistor to v cc for proper operation. a 500 to 10k resistor is recommended in order to control the rise time. the ft bit is cleared on power-down.
m41st84w 16/29 figure 13. crystal accuracy across temperature figure 14. clock calibration ai00999b ?160 0 10203040506070 frequency (ppm) temperature c 80 ?10 ?20 ?30 ?40 ?100 ?120 ?140 ?40 ?60 ?80 20 0 ?20 ? f = k x (t ?t o ) 2 k = ?0.036 ppm/ c 2 0.006 ppm/ c 2 t o = 25 c 5 c f ai00594b normal positive calibration negative calibration
17/29 m41st84w setting alarm clock registers address locations 0ah-0eh contain the alarm set- tings. the alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. it can also be pro- grammed to go off while the m41st84w is in the battery back-up to serve as a system wake-up call. bits rpt5-rpt1 put the alarm in the repeat mode of operation. table 4., page 17 shows the possible configurations. codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. when the clock information matches the alarm clock settings based on the match criteria defined by rpt5-rpt1, the af (alarm flag) is set. if afe (alarm flag enable) is also set, the alarm condi- tion activates the irq /ft/out pin. note: if the address pointer is allowed to incre- ment to the flag register address, an alarm con- dition will not cause the interrupt/flag to occur until the address pointer is moved to a different ad- dress. it should also be noted that if the last ad- dress written is the ?alarm seconds,? the address pointer will increment to the flag address, causing this situation to occur. the irq /ft/out output is cleared by a read to the flags register as shown in figure 15. . a sub- sequent read of the flags register is necessary to see that the value of the alarm flag has been reset to '0.' the irq /ft/out pin can also be activated in the battery back-up mode. the irq /ft/out will go low if an alarm occurs and both abe (alarm in bat- tery back-up mode enable) and afe are set. the abe and afe bits are reset during power-up, therefore an alarm generated during power-up will only set af. the user can read the flag register at system boot -up to determine if an alarm was generated while the m41st84w was in the dese- lect mode during power-up. figure 16., page 18 il- lustrates the back-up mode alarm timing. figure 15. alarm interrupt reset waveform table 4. alarm repeat modes rpt5 rpt4 rpt3 rpt2 rpt1 alarm setting 11111once per second 11110once per minute 11100once per hour 11000once per day 10000once per month 00000once per year ai03664 irq/ft/out active flag 0fh 0eh 10h high-z
m41st84w 18/29 figure 16. back-up mode alarm waveform watchdog timer the watchdog timer can be used to detect an out- of-control microprocessor. the user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. bits bmb4-bmb0 store a binary multiplier and the two lower order bits rb1-rb0 select the resolu- tion, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. the amount of time-out is then determined to be the multiplica- tion of the five-bit multiplier value with the resolu- tion. (for example: writing 00001110 in the watchdog register = 3*1, or 3 seconds). note: accuracy of timer is within the selected resolution. if the processor does not reset the timer within the specified period, the m41st84w sets the wdf (watchdog flag) and generates a watchdog inter- rupt or a microprocessor reset. the most significant bit of the watchdog register is the watchdog steering bit (wds). when set to a '0,' the watchdog will activate the irq /ft/out pin when timed-out. when wds is set to a '1,' the watchdog will output a negative pulse on the rst pin for t rec . the watchdog register, ft, afe, abe and sqwe bits will reset to a '0' at the end of a watchdog time-out when the wds bit is set to a '1.' the watchdog timer can be reset by two methods: 1) a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (wdi) or 2) the microprocessor can perform a write of the watchdog register. the time-out period then starts over. note: the wdi pin should be tied to v ss if not used. in order to perform a software reset of the watch- dog timer, the original time-out period can be writ- ten into the watchdog register, effectively restarting the count-down cycle. should the watchdog timer time-out, and the wds bit is programmed to output an interrupt, a value of 00h needs to be written to the watchdog register in order to clear the irq /ft/out pin. this will also disable the watchdog function until it is again pro- grammed correctly. a read of the flags register will reset the watchdog flag (bit d7; register 0fh). the watchdog function is automatically disabled upon power-up and the watchdog register is cleared. if the watchdog function is set to output to the irq /ft/out pin and the frequency test (ft) function is activated, the watchdog function pre- vails and the frequency test function is denied. ai03920 v cc irq/ft/out v pfd abe, afe bits in interrupt register af bit in flags register high-z v so high-z trec
19/29 m41st84w square wave output the m41st84w offers the user a programmable square wave function which is output on the sqw pin. the rs3-rs0 bits located in 13h establish the square wave output frequency. these frequencies are listed in table 5. . once the selection of the sqw frequency has been completed, the sqw pin can be turned on and off under software con- trol with the square wave enable bit (sqwe) lo- cated in register 0ah. table 5. square wave output frequency square wave bits square wave rs3 rs2 rs1 rs0 frequency units 0000none? 0 0 0 1 32.768 khz 0 0 1 0 8.192 khz 0 0 1 1 4.096 khz 0 1 0 0 2.048 khz 0 1 0 1 1.024 khz 0110512hz 0111256hz 1000128hz 100164hz 101032hz 101116hz 11008hz 11014hz 11102hz 11111hz
m41st84w 20/29 power-on reset the m41st84w continuously monitors v cc . when v cc falls to the power fail detect trip point, the rst pulls low (open drain) and remains low on power-up for t rec after v cc passes v pfd (max). the rst pin is an open drain output and an appro- priate pull-up resistor should be chosen to control rise time. reset input (rstin ) the m41st84w provides an independent input which can generate an output reset. the duration and function of this reset is identical to a reset gen- erated by a power cycle. table 6., page 20 and figure 17., page 20 illustrate the ac reset charac- teristics of this function. pulses shorter than t rlrh will not generate a reset condition. rstin is inter- nally pulled up to v cc through a 100k ? resistor. figure 17. rstin timing waveform note: with pull-up resistor table 6. reset ac characteristics note: 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.7 to 3.6v (except where noted). 2. pulse width less than 50ns will result in no reset (for noise immunity). 3. programmable (see table 8., page 22 ) symbol parameter (1) min max unit t rlrh (2) rstin low to rstin high 200 ns t rhrsh (3) rstin high to rst high 40 200 ms ai03682 rst (1) rstin trlrh trhrsh
21/29 m41st84w power-fail input/output the power-fail input (pfi) is compared to an in- ternal reference voltage (1.25v). if pfi is less than the power-fail threshold (v pfi ), the power-fail output (pfo) will go low. this function is intended for use as an under-voltage detector to signal a failing power supply. typically pfi is connected through an external voltage divider (see figure 5., page 6 ) to either the unregulated dc input (if it is available) or the regulated output of the v cc reg- ulator. the voltage divider can be set up such that the voltage at pfi falls below v pfi several millisec- onds before the regulated v cc input to the m41st84w or the microprocessor drops below the minimum operating voltage. during battery back-up, the power-fail comparator turns off and pfo goes (or remains) low. this oc- curs after v cc drops below v pfd (min). when pow- er returns, pfo is forced high, irrespective of v pfi for the write protect time (t rec ), which is the time from v pfd (max) until the inputs are recognized. at the end of this time, the power-fail comparator is enabled and pfo follows pfi. if the comparator is unused, pfi should be connected to v ss and pfo left unconnected. century bit bits d7 and d6 of clock register 03h contain the century enable bit (ceb) and the century bit (cb). setting ceb to a ?1? will cause cb to tog- gle, either from a ?0? to ?1? or from ?1? to ?0? at the turn of the century (depending upon its initial state). if ceb is set to a ?0?, cb will not toggle. output driver pin when the ft bit, afe bit and watchdog register are not set, the irq /ft/out pin becomes an out- put driver that reflects the contents of d7 of the control register. in other words, when d7 (out bit) and d6 (ft bit) of address location 08h are a '0,' then the irq /ft/out pin will be driven low. note: the irq /ft/out pin is an open drain which requires an external pull-up resistor. battery low warning the m41st84w automatically performs battery voltage monitoring upon power-up and at factory- programmed time intervals of approximately 24 hours. the battery low (bl) bit, bit d4 of flags register 0fh, will be asserted if the battery voltage is found to be less than approximately 2.5v. the bl bit will remain asserted until completion of bat- tery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. if a battery low is generated during a power-up se- quence, this indicates that the battery is below ap- proximately 2.5 volts and may not be able to maintain data integrity in the sram. data should be considered suspect and verified as correct. a fresh battery should be installed. if a battery low indication is generated during the 24-hour interval check, this indicates that the bat- tery is near end of life. however, data is not com- promised due to the fact that a nominal v cc is supplied. in order to insure data integrity during subsequent periods of battery back-up mode, the battery should be replaced. the battery may be re- placed while v cc is applied to the device. the m41st84w only monitors the battery when a nominal v cc is applied to the device. thus appli- cations which require extensive durations in the battery back-up mode should be powered-up peri- odically (at least once every few months) in order for this technique to be beneficial. additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. t rec bit bit d7 of clock register 04h contains the t rec bit (tr). t rec refers to the automatic continuation of the deselect time after v cc reaches v pfd . this al- lows for a voltage setting time before writes may again be performed to the device after a power- down condition. the t rec bit will allow the user to set the length of this deselect time as defined by table 7., page 22 . initial power-on defaults upon initial application of power to the device, the following register bits are set to a '0' state: watch- dog register, tr, ft, afe, abe, and sqwe. the following bits are set to a '1' state: st, out, and ht (see table 8., page 22 ).
m41st84w 22/29 table 7. t rec definitions note: 1. default setting table 8. default values note: 1. wds, bmb0-bmb4, rb0, rb1. 2. state of other control bits undefined. 3. uc = unchanged maximum rating stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 9. absolute maximum ratings note: 1. for so package, standard (snpb) lead finish: reflow at peak temperature of 225c (total thermal budget not to exceed 180 c for between 90 to 150 seconds). 2. for so package, lead-free (pb-free) lead finish: reflow at peak temperature of 260c (total thermal budget not to exceed 245 c for greater than 30 seconds). caution: negative undershoots below ?0.3v are not allowed on any pin while in the battery back-up mode. t rec bit (tr) stop bit (st) t rec time units min max 009698ms 0140 200 (1) ms 1 x 50 2000 s condition tr st ht out ft afe abe sqwe watchdog register (1) initial power-up (battery attach) (2) 0111000 0 0 subsequent power-up (with battery back-up) (3) uc uc 1 uc 0 0 0 0 0 symbol parameter value unit t stg storage temperature (v cc off, oscillator off) ?55 to 150 c t sld (1) lead solder temperature for 10 seconds 260 c v io input or output voltages ?0.3 to v cc + 0.3 v v cc supply voltage ?0.3 to 4.6 v i o output current 20 ma p d power dissipation 1 w
23/29 m41st84w dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 10. dc and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 18. ac testing input/output waveforms note: 50pf for m41st84w. table 11. capacitance note: 1. effective capacitance measured with power supply at 3v. sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs deselected. parameter m41st84w v cc supply voltage 2.7 to 3.6v ambient operating temperature ?40 to 85c load capacitance (c l ) 50pf input rise and fall times 50ns input pulse voltages 0.2 to 0.8v cc input and output timing ref. voltages 0.3 to 0.7v cc ai02568 0.8v cc 0.2v cc 0.7v cc 0.3v cc symbol parameter (1,2) min max unit c in input capacitance 7 pf c io (3) input / output capacitance 10 pf t lp low-pass filter input time constant (sda and scl) 50 ns
m41st84w 24/29 table 12. dc characteristics note: 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.7 to 3.6v (except where noted). 2. rstin internally pulled-up to v cc through 100k ? resistor. wdi internally pulled-down to v ss through 100k ? resistor. 3. outputs deselected. 4. for pfo and sqw pins (cmos). 5. for irq /ft/out, rst pins (open drain): if pulled-up to supply other than v cc , this supply must be equal to, or less than 3.0v when v cc = 0v (during battery back-up mode). 6. for rechargeable back-up, v bat (max) may be considered v cc . table 13. crystal electrical characteristics (externally supplied) note: 1. load capacitors are integrated within the m41st84w. circuit board layout considerations for the 32.768khz crystal of min imum trace lengths and isolation from rf generating signals should be taken into account. 2. stmicroelectronics recommends the kds dt-38: 1ta/1tc252e127, tuning fork type (thru-hole) or the dmx-26s: 1tjs125fh2a212, (smd) quartz crystal for industrial temperature operations. kds can be contacted at kouhou@kdsj.co.jp or ht- tp://www.kdsj.co.jp for further information on this crystal type. sym parameter test condition (1) m41st84w unit min typ max i bat battery current osc on t a = 25c, v cc = 0v, v bat = 3v 400 500 na battery current osc off 50 na i cc1 supply current f = 400khz 0.75 ma i cc2 supply current (standby) scl, sda = v cc ? 0.3v or v ss + 0.3v 0.50 ma i li (2) input leakage current 0v v in v cc 1 a input leakage current (pfi) ?25 2 25 na i lo (3) output leakage current 0v v out v cc 1 a v ih input high voltage 0.7v cc v cc + 0.3 v v il input low voltage ?0.3 0.3v cc v v bat battery voltage 2.5 3.0 3.5 (6) v v oh output high voltage (4) i oh = ?1.0ma 2.4 v v ol output low voltage i ol = 3.0ma 0.4 v output low voltage (open drain) (5) i ol = 10ma 0.4 v pull-up supply voltage (open drain) rst , i rq /ft/out 3.6 v v pfd power fail deselect 2.55 2.60 2.70 v v pfi pfi input threshold v cc = 3v(w) 1.225 1.250 1.275 v pfi hysteresis pfi rising 20 70 mv v so battery back-up switchover 2.5 v symbol parameter (1,2) typ min max unit f 0 resonant frequency 32.768 khz r s series resistance 50 k ? c l load capacitance 12.5 pf
25/29 m41st84w figure 19. power down/up mode ac waveforms table 14. power down/up ac characteristics note: 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 2.7 to 3.6v (except where noted). 2. v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occurring until 200s after v cc passes v pfd (min). 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. 4. programmable (see table 7., page 22 ) symbol parameter (1) min typ max unit t f (2) v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) v pfd (min) to v ss v cc fall time 10 s t pfd pfi to pfo propagation delay 15 25 s t r v pfd (min) to v pfd (max) v cc rise time 10 s t rb v ss to v pfd (min) v cc rise time 1s t rec(4) power up deselect time 40 200 ms ai03681 v cc inputs (per control input) outputs don't care high-z tf tfb tr trb tdr valid valid (per control input) recognized recognized v pfd (max) v pfd (min) v so trec rst pfo
m41st84w 26/29 package mechanical information figure 20. so16 ? 16-lead plastic small outline, package outline note: drawing is not to scale. table 15. so16 ? 16-lead plastic small outline, package mechanical data symbol mm inches typ. min. max. typ. min. max. a 1.75 0.069 a1 0.10 0.25 0.004 0.010 a2 1.60 0.063 b 0.35 0.46 0.014 0.018 c 0.19 0.25 0.007 0.010 d 9.80 10.00 0.386 0.394 e 3.80 4.00 0.150 0.158 e1.27??0.050?? h 5.80 6.20 0.228 0.244 l 0.40 1.27 0.016 0.050 a0808 n16 16 cp 0.10 0.004 so-b e n cp b e a2 d c l a1 h a 1
27/29 m41st84w part numbering table 16. ordering information scheme for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: m41st 84w mq 6 e device type m41st supply voltage and write protect voltage 84w = v cc = 2.7 to 3.6v; 2.55v v pfd 2.70v package mq = so16 temperature range 6 = ?40 to 85c shipping method for so16: blank = tubes (not for new design - use e) e = ecopack package, tubes f = ecopack package, tape & reel tr = tape & reel (not for new design - use f)
m41st84w 28/29 revision history table 17. document revision history date version revision details august 2000 1.0 first issue 24-aug-00 1.2 block diagram added (figure 4 ) 08-sep-00 1.3 so16 package measures change 18-dec-00 2.0 reformatted, toc added, and pfi input leakage current added (table 12 ) 18-jun-01 2.1 addition of t rec information, table changed, one added (tables 3 , 7 ); changes to pfi/pfo graphic (see figure 4 ); change to dc and ac characteristics, order information (tables 12 , 2 , 16 ); note added to ?setting alarm clock registers? section; added temp./voltage info. to tables (table 11 , 12 , 13 , 2 , 14 ); addition of default values (table 8 ); textual improvements 25-jun-01 2.2 special note added in clock operation, page 13 26-jul-01 3.0 change in product maturity 07-aug-01 3.1 improve text for ?setting the alarm clock? section 20-aug-01 3.2 change v pfd values in document 06-sep-01 3.3 dc characteristics v bat changed; pfi hysteresis (pfi rising) spec. added; and crystal electrical characteristics series resistance spec. changed (tables 12 , 13 ) 03-dec-01 3.4 change read/write mode sequence drawings (figure 10 , 12 ); change in v pfd lower limit for 5v (m41st84y) part only (table 12 , 16 ) 14-jan-02 3.5 change series resistance (table 13 ) 01-may-02 3.6 change t rec definition (table 7 ); modify reflow time and temperature footnote (table 9 ) 03-jul-02 3.7 modify dc and crystal electrical characteristics footnotes, default values (tables 12 , 13 , 8 ) 01-aug-02 3.8 add marketing status (figure 2 ; table 16 ) 16-jun-03 4.0 new si changes (table 14 , 6 , 7 , 8 ) 15-jun-04 5.0 reformatted; added lead-free information; update characteristics (figure 13 ; table 9 , 12 , 16 ) 18-oct-04 6.0 add marketing status (figure 2 ; table 16 ) 10-jan-06 7.0 updated template, lead-free text, characteristics (figure 2 , 3 , 6 , 7 ; table 1 , 2 , 6 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 16 )
29/29 m41st84w information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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