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w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 1 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 the amd-760? mpx platform for the amd athlon? mp processor m ulti p rocessing with e x tended p erformance jessie j. johnson advanced micro devices, inc. advanced micro devices, inc. advanced micro devices, inc. advanced micro devices, inc. one amd place sunnyvale, ca 94088 pid# 25787a
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 2 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 table of contents introduction.................................................................................................. 3 amd-760? mpx platform overview........................................................ 3 supported processors ................................................................................... 4 platform architecture................................................................................... 5 smart mp technology ................................................................................. 8 dual amd athlon? system bus ..................................................10 innovative bus-snooping capability..............................................17 optimized moesi cache-coherency protocol ..............................19 ddr memory subsystem ...........................................................................21 agp- 4 x graphics subsystem....................................................................22 ata-100 storage subsystem .....................................................................23 primary (66mhz) and secondary (33mhz) pci bus interfaces ................24 ac-97 audio interface ...............................................................................26 appendix.....................................................................................................28 glossary of terms...........................................................................28 what is bus snooping?...................................................................28 agp graphics background.............................................................29 amd overview ..............................................................................33
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 3 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 introduction high-performance?scalability?manageability?all are key terms to describe a class of power platforms intended for mission-critical applications required of servers and workstations. the amd-760? mpx platform is a high-performance, two-way multiprocessing (mp) system solution designed for server- and workstation-class applications. building upon its predecessor (the amd-760 mp chipset), the amd-760 mpx platform offers m ulti p rocessor e x tended (mpx) performance beyond the original performance of the amd-760 mp platform. consisting of the amd athlon? mp processor and the amd-760 mpx chipset, this solution offers scalable processing capability, high-bandwidth memory and i/o performance, and sophisticated system management capability to support a wide range of computing infrastructures. this white paper describes the amd-760 mpx platform, architecture, and underlying technologies. amd-760? mpx platform overview the amd-760 mpx platform addresses the server and workstation sectors by offering the following high-level features: ? uniprocessor and two-way symmetric multiprocessing capability ? dual point-to-point 266mhz amd athlon system buses designed to support up to 2.1gb/s transfer rate per system bus ? 266mhz ddr (double data rate) memory interface supporting up to 4gb of memory space using registered pc2100 dimms. ecc (error correcting code) memory is also supported ? agp-4x graphics interface, backwards-compatible with agp-1x and 2x modes ? primary 66mhz/64-bit/32-bit pci 2.2-compliant pci bus interface ? secondary 33mhz/32-bit pci 2.2-compliant pci bus interface ? ac-97 audio interface
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 4 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 ? eide storage controller subsystem supporting ata-33/66/100mb/s data rates ? system management functions as shown in figure 1, these features are packaged in a two-chip core logic solution consisting of the amd-762? system controller (northbridge) and the amd-768? peripheral bus controller (southbridge). when implemented with amd athlon mp processor technology, these elements combine to deliver outstanding performance to server- and workstation-class systems. processor (1) amd-762 tm system controller amd-768 tm peripheral bus controller processor (0) agp-4x slot 4 registered pc2100 ddr dimm slots - two 66mhz 64-bit pci bus slots - three 33mhz 32-bit pci bus slots peripheral connectors eide & floppy drive connectors vrm slots figure 1: amd-760? mpx motherboard platform supported processors amd manufacturers a wide range of microprocessors to support a multitude of market segments and applications. the amd-760 mpx platform supports amd processors designed specifically for multiprocessing. the amd processors shown in table 1 are supported by the amd-760 mpx platform.
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 5 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 table 1: amd processor front-side bus speed and corresponding memory support processor model processor clock speed supported front- side bus speeds supported ddr sdram memory amd athlon? mp all speed grades 266mhz pc2100 two-way multiprocessing is supported only in the configurations shown in table 2. table 2: supported two-way multiprocessor configurations processor slot (0) processor slot (1) configurations model fsb speed processor clock speed model fsb speed processor clock speed amd athlon? configuration 1 amd athlon mp 266mhz same frequency as processor (1) 1 amd athlon mp 266mhz same frequency as processor (0) 1 the multiprocessor configurations allowed are those in which both processor sockets are populated with processors of the same model, front-side bus speed, and processor clock speeds. an amd athlon mp processor cannot coexist in the same system with any other processor model other than another amd athlon mp nor can different speed grades of the amd athlon mp processor coexist in the same system. platform architecture servers and workstations leverage similar underlying technologies as fundamental building blocks. both classes of systems require high-performance computing capability, high-capacity memory elements, and robust i/o (input/output) subsystems. these platforms, however, begin to diverge in the areas of scalability, graphics, and i/o control. workstations, for example, require high-end graphics, mid-level storage capabilities, and limited i/o expansion. on the other hand, servers do not require high-end graphics, but instead require ?scalable? high-performance computing capabilities, massive high- performance storage engines, and an i/o subsystem that is robust enough to concurrently support a multitude of high-speed networking and storage subsystems. 1 all amd athlon mp processor speed grades are supported, however, processor (0) and processor (1) must operate at the same processor clock frequency. the amd-760 mpx platform does not support configurations in which processor (0) and processor (1) are operating at different processor clock frequencies.
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 6 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 early in the design process, amd engineers faced the extreme challenge of developing an architecture that was powerful, robust, and cost-effective, yet flexible enough to support the diverging demands of both server- and workstation-class systems. their answer: the amd-760 mpx platform. amd-762 tm agp 4x slot ddr memory eide (33/66/100) usb 2 4 smbus pci bus (66mhz/32-bit/64-bit) flash sio lpc bus slot slot amd-768 tm peripheral bus controller pci bus (33mhz/32-bit) slot slot slot scsi ethernet gpio signals ps/2 keyboard ps/2 mouse serial port parallel port audio codec ac-97 link 66mhz 266mhz processor (0) processor (1) 266mhz 266mhz apic bus system management rtc/cmos 64-bit 32-bit figure 2: amd-760? mp platform high-level architecture as shown in figure 2, the amd-760 mpx platform employs pga-socketed (socket a) amd processor-based technology as the high-performance system engine(s) of choice. the amd-760 mpx design supports a single processor for workstation-class systems or low-end servers, leaving a second available processor socket for future expansion. customers will enjoy the security of knowing their original investment is protected with a system that can be scaled as their computing demands grow. customers can upwardly scale the processing capability of their system in one of several ways: 1. in a uniprocessor configuration, the system can be upgraded by replacing the original single processor with a faster or improved amd athlon mp processor. 2. in a multiprocessor configuration, the system can be upgraded by adding a second amd processor (of the same model and clock speed as the first
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 7 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 processor), thus enabling symmetric multiprocessing and significantly boosting system performance. (refer to table 2 for supported multiprocessor configurations.) 3. replacing the original single processor with a faster amd processor, and adding a second processor of equivalent model and speed. (refer to table 2 for supported multiprocessor configurations.) in high-end workstation and mid-range server applications, where maximum performance is required from the onset, systems can be shipped with two processors, immediately enabling the benefits of symmetric multiprocessing. the system logic is partitioned as follows: the amd-762 system controller houses the high-speed elements critical to system performance. contained in the amd-762 controller are the following subsystems: ? dual point-to-point 266mhz amd athlon system bus interfaces, supporting up to two processors ? 266mhz ddr memory interface, supporting up to 4gb of memory space using pc2100 registered ddr memory dimms. ecc memory is also supported ? agp-4x graphics interface ? 66mhz/64-bit/32-bit pci bus interface ? 949-pin plastic ccga (ceramic column grid array) package ? 2.5v core for detailed descriptions, refer to the amd-762 system controller data sheet .
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 8 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 the amd-768 peripheral bus controller compliments the amd-762 system controller by offering a robust i/o subsystem along with sophisticated system management capability. embedded are the following features: ? primary 66mhz/64-bit/32-bit pci bus interface ? secondary 33mhz/32-bit pci bus interface ? ac-97 audio interface ? ata-33/66/100 eide interface ? four-port ohci usb host controller ? lpc (low pin count) bus ? system management interface ? smbus interface ? real time clock (rtc) ? 256 bytes cmos memory ? i/o apic interrupt controller ? random number generator ? 32-gpio pins ? 492-pin ball grid array (bga) package ? 3.3v core and output drivers; 5v tolerant input buffers for detailed descriptions, refer to the amd-768 peripheral bus controller datasheet. smart mp technology ghz, mips, mops, and gb/s are measures of raw computing power. however, for revolutionary breakthroughs in system performance, raw computing power is not enough ? the system has to be ?smart? as well. amd introduces smart mp technology ? a new multiprocessing architecture enabling faster performance beyond traditional multiprocessor system architectures. smart mp technology consists of the following architectural features: ? dual point-to-point high-speed system buses ? innovative bus-snooping capability ? optimized moesi cache-coherency protocol
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 9 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 the amd-760 mpx platform implements dual point-to-point high-speed system buses (shown in figure 3), which allows two processors to run independently without the overhead of sharing a common system bus (shown in figure 4). performance delays caused by bus arbitration and bus ownership transitions are eliminated in this architecture, allowing each processor to perform as if it has a dedicated channel to system resources. the split-transaction nature of the amd athlon system bus, combined with its independent data and command channels, delivers a high-speed front-side bus solution for amd athlon mp processors. bus snooping is a critical mechanism in maintaining a system?s data coherency. while one processor is accessing memory, the second processor must snoop or ?listen? to bus activity and determine if the current memory access affects its memory space. if so, then appropriate measures must be taken to ensure that all affected processors and bus masters have the most accurate data available. amd?s smart mp technology implements a performance-oriented snooping mechanism. the processors leverage the independent processor-to-system, system-to- processor, and data channels of the amd athlon system bus to create a ?virtual? snooping channel. a processor can transfer data while concurrently receiving snoop information, or a processor can broadcast snoop information while concurrently receiving data. the net effect is that concurrency is achieved, and system performance is enhanced. in some non-split-transactions, shared-bus architectures, snooping activity is ?focused? only on the current access occurring on the shared system bus. hence, there may be less opportunity for concurrent data transfers that are independent of the current snoop activity. amd multiprocessing platforms implement the moesi cache-coherency protocol . the moesi protocol offers a potential performance advantage over systems implementing mesi protocol. the additional ?owner? state allows the processor cache ?owning? the data to supply data directly to the second processor requesting access to the cached block. the requesting processor no longer has to wait for the owning processor to write the requested data back to main memory before the data is accessible. instead, the owning processor supplies the requested data directly to the requesting processor. this scheme reduces memory traffic, and allows faster access to cached data.
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 10 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 dual amd athlon? system bus 2 server- and workstation-class platforms require high-performance and scalable compute capability. a key element impacting these requirements is the system bus linking the processor(s) to the system logic. throughout the industry, this bus is generally termed the ?front-side bus.? processor (0) processor (1) amd-762? system controller amd-768? peripheral bus controller pci bus pc2100 ddr memory amd athlon? system bus - 266mhz - double data rate - 64-bit data path - split transaction amd athlon system bus - 266mhz - double data rate - 64-bit data path - split transaction figure 3: dual point-to-point amd athlon? system bus architecture as shown in figure 3, the amd-760 mpx platform employs the amd athlon system bus as the high-speed interface between the processor(s) and system elements. optimized for server and workstation applications, the amd athlon system bus offers the following attributes: ? 266mhz 3 operation, designed to deliver a peak throughput of up to 2.1gb/s per system bus ? split-transaction architecture ? cache-coherency protocol 2 the amd athlon system bus is also referred to as the amd system bus.
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 11 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 ? ecc capability ? 64-bit data path ? packetized request transactions to achieve symmetric multiprocessing capability, amd chose a dual point-to- point independent bus topology as opposed to the shared bus architecture depicted in figure 4. the dual point-to-point architecture offers the following advantages over the shared bus architecture: ? processors on the amd athlon system bus can concurrently burst information to and from the system. the shared bus architecture allows only one processor at a time to transfer data. ? latency is reduced, as processors on the amd athlon system bus will not have to arbitrate for system bus control. ? signal loading, integrity, and termination are much simpler from a design perspective with only one processor per system bus. processor (0) processor (1) system controller i/o subsystem shared cpu local bus interconnect/io bus system memory figure 4: generic shared cpu local bus architecture 3 the 266mhz rate refers to a physical clock operating at 133mhz in which information is transferred on each clock edge. hence, this is calculated as (133mhz clock) x (2 transfers/clock) = 266m transfers/sec = 266mhz.
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 12 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 split-transaction bus architectures have existed in mini, mid-range, and mainframe computer systems for many years. only recently have these architectures moved into the desktop market. in essence, split-transaction architecture is a bus transaction technique in which serialized transactions are decoupled and allowed to execute concurrently, or in an overlapping fashion. this technique leverages the latencies in the system to increase overall system performance. this architecture is different from traditional microprocessor bus architectures in which the address, control, and data buses operate collectively as a single pipe (see figure 5). the traditional architecture allows only a single transaction to occur at a time, thus creating a serializing effect. 4 processor system address bus control bus data bus a traditional cpu local bus employs multiple buses that operate together as a single bus (pipe) ? allowing only one transaction at a time (serialized transactions). pipe figure 5: traditional microprocessor cpu local bus figure 6 is an example that illustrates the serialization nature of the non-split transaction type buses. bus transactions can be decomposed into an address/control phase and a data phase. in the case where the processor is reading data from the system, during the address/control phase, address and control information is broadcast to the system. the 4 techniques such as pipelining and delayed transaction are used to circumvent this type of issue; however, these techniques will be ignored in this white paper to simplify the discussion.
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 13 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 processor must wait for the system to respond with valid data before a new transaction can be launched. 5 the length of the delay depends on the type of device (memory, disk drive, etc.) being accessed, its associated latency, and its readiness to deliver data. in figure 6, note how the data phase times can vary from transaction to transaction. in this example, it takes 15 units of time to complete three transactions. address/control (1) data (1) data (2) address/control (2) data (3) address/control (3) 1 510 15 time units transaction #1 transaction #2 transaction #3 figure 6: example of serialized transaction nature of non-split transaction bus architectures split-transaction architecture improves performance by taking advantage of the data phase latencies, and allowing other transactions to launch as the processor (or system) is waiting for the current data phase to complete. hence, transactions overlap, concurrency is achieved, and system performance is increased. 5 techniques such as pipelining and delayed transaction are used to circumvent this type of issue; however, these techniques will be ignored in this white paper to simplify the discussion.
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 14 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 system controller amd athlon? mp processor 266mhz data bus 266mhz system-to- processor bus 266mhz processor- to-system bus figure 7: amd athlon? system bus components as shown in figure 7, the amd athlon system bus is composed of three separate buses that operate independently and concurrently: 1. processor-to-system bus 2. system-to-processor bus 3. data bus note that each bus runs at 266mhz. the processor-to-system bus is the channel in which the processor issues requests/commands (memory read, memory write, etc.) to the system. this is a uni- directional bus controlled only by the processor. data is not transferred on this bus; only packets containing command, address, and other information are transferred. data information is transferred over the data bus. the system-to-processor bus is the channel in which the system issues requests/commands to the processor. this is also a uni-directional bus controlled only by the system controller. similar to the processor-to-system bus, only packets?request and
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 15 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 command information?are transferred on this bus. data information is transferred over the data bus. the data bus is a bi-directional bus used to transfer data packets between the processor and system elements in response to requests from their respective buses. each data packet contains an id tag for association with the corresponding processor-to-system or system-to-processor request. note: refer to the amd athlon? system bus specification for more details on bus architecture and operation. as shown in figure 8, the three independent, high-performance channels (and support logic) enable split-transaction capability. processor requests (pr) and system requests (sr) can be sent concurrently and independently. system data (sd) and processor data (pd) can be returned to the requestor immediately or at a later time, depending on availability. ordering is mitigated by instantiating a unique id associating the request with the corresponding data. pr5 amd athlon? processor system pr4 pr3 pr2 pr1 sr1 sr2 sr3 sr4 sr5 pd1 sd1 processor-to-system bus system-to-processor bus data bus pd2 pd3 sd2 pd4 sd3 sd4 pd5 sd5 figure 8: amd athlon? system bus split-transaction example
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 16 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 the net effect of split-transaction capability is improved performance. as shown in figure 9, concurrency is achieved by decoupling the processor-to-system transactions from the system-to-processor transactions, and by decoupling the data response from the associated request. compared to the non-split transaction example shown in figure 6, the time to complete three transactions has been reduced from 15 time units to 11 time units. 6 address/control (1) data (1) data (2) data (3) address/control (3) 1 510 15 time units address/control (2) system-to-processor bus processor-to-system bus data bus figure 9: example illustrating the concurrency offered by split-transaction bus architecture the amd athlon system bus also supports error checking and correcting across the system bus to evaluate data integrity. note: when running two processors, both processors must run at the same clock frequencies. also, the amd athlon system bus and ddr memory subsystem are locked in frequency. whether running one processor or two processors, the amd athlon system bus and ddr memory subsystem must operate at the same speed. in summary, the amd athlon system bus offers high-speed communication between the processor and the system. the dual point-to-point multiprocessor topology, 6 these performance numbers are arbitrary examples used for concept illustration only.
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 17 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 split-transaction capability, and error checking and correcting features all combine to deliver outstanding performance and protection for mission-critical applications. innovative bus-snooping capability the architecture of the amd athlon system bus (and its dual-bus implementation on the amd-760 mpx chipset) provides an innovative bus-snooping capability that contributes to overall system performance. as memory transactions (memory reads, memory writes?etc.) are requested by each processor, bus ?snooping? must occur to determine if the transactions impact another processor or system element. bus snooping is the process in which the system (processors, core logic, and bus-masters) monitor and track memory requests to ensure data coherency. (refer to page 30 for a simple analogy on bus snooping.) the amd-760 mpx platform takes advantage of the independent processor-to- system, system-to-processor, and data channels of the front-side bus to facilitate performance bus snooping. processor (0) processor (1) amd-762 tm system controller memory processor to system system to processor data processor to system system to processor data mr amd-768 tm peripheral bus controller sr mr pci bus sr snooping channel figure 10: example 1 ? bus-snooping channel
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 18 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 figure 10 illustrates an example of bus snooping on the amd-760 mpx platform. processor (0) launches a m emory r equest (mr) to the system to obtain data or instructions that are not currently in its cache. the system controller translates this request into a s noop r equest (sr) and queries processor (1) to determine if processor (1) has the requested data. processor (1) will respond to the request via messaging on its processor-to-system bus. if processor (1) has the data, it will return the data to processor (0), otherwise the system controller will fetch the data from main memory. in essence, a virtual snooping channel is created between processor (0), processor (1), and the system controller. while the snooping is occurring, note that processor (0) can concurrently receive messaging and data on its system-to-processor/data buses, and that processor (1) can concurrently transmit messaging and data over its processor-to-system/data buses. the processors have the potential to concurrently perform transfers that are unrelated to the current snoop activity. this concurrency plays a significant role in improved performance over other multiprocessing architectures. processor (0) processor (1) amd-762 tm system controller memory processor-to-system system-to-processor data processor-to-system system-to-processor data sr amd-768 tm peripheral bus controller sr mr pci bus mr snooping channel figure 11: bus-snooping channel example ? processor (1) to processor (0)
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 19 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 figure 11 illustrates a bus-snooping transaction/channel in the reverse direction (from processor (1) to processor (0). note also, that the system has to monitor transactions from the pci bus as part of the snooping process. pci bus-masters have the potential of accessing memory spaces cached by the processors. hence, the system controller must snoop pci traffic and generate snoop requests to the processors. figure 12 illustrates a virtual snooping channel created between the pci bus and the processors. processor (0) processor (1) amd-762 tm system controller memory processor-to-system system-to-processor data processor-to-system system-to-processor data amd-768 tm peripheral bus controller sr mr pci bus snooping channel figure 12: bus-snooping channel example ? pci bus-master to processor (0) optimized moesi cache-coherency protocol although there are several cache-coherency protocols implemented on various platforms, the mesi and moesi protocols are the most popular in the industry. mesi and moesi are acronyms representing the cache states in the system. ? mesi ? modified, exclusive, shared, invalid ? moesi ? modified, owner, exclusive, shared, invalid
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 20 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 the amd-760 mpx platform implements the moesi cache-coherency protocol. the moesi protocol is similar to the mesi protocol; however, an additional state (owner) is added, offering increased performance potential over its mesi counterpart. the addition of the owner state allows the processor owning the cache block to directly supply cache data to the requestor. in this respect, the requestor does not have to wait for main memory to be updated to receive the requested data. processor (1) salaries m-16 daisy pci bus-master 0 data 76 password john $100.00 processor (0) salaries m-16 daisy password john $100.00 main memory 11 12 08 09 10 07 line-0 line-1 line-2 line-0 line-1 line-2 snoop/system logic 04 05 06 00 01 03 figure 13: system cache state before transaction as an example, figure 13 shows an amd-760 mpx platform-based architecture with two processors. each processor/cache (color coded) is mapped to a unique memory space in main memory. in this example, the corresponding cache lines match the corresponding main memory image. also note, that the pci bus-master has an assigned memory map in main memory. suppose that processor (1) needed financial information from main memory that is currently ?owned? by the cache in processor (0) (line-2). also, suppose that the pci bus-master concurrently needed to write data to its own allocated memory block in main memory. because of the moesi cache-coherency protocol and the amd-760 mpx architecture, these two operations can occur concurrently. as shown in figure 14,
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 21 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 because processor (0) is the ?owner,? processor (0) can supply the information directly to processor (1) without processor (1) having to access main memory. main memory is free to be accessed by the pci bus-master. due to the amd-760 mpx architecture, the transfer of data from processor (0) to processor (1), and the data transfer from the pci bus-master to main memory can take place at the same time. this concurrency increases performance in scenarios where these conditions occur. in some alternative architectures, main memory would have to be updated first, and the pci bus-master would have to wait for the memory update to complete before it could perform a transaction to its corresponding space in main memory. processor (1) $100.00 m-16 daisy pci bus-master 0 data 76 password john $100.00 processor (0) salaries m-16 daisy password john $100.00 main memory 11 12 08 09 10 07 line-0 line-1 line-2 line-0 line-1 line-2 snoop/system logic 04 05 06 00 01 03 data 76 figure 14: system state after memory transaction again, the moesi architecture improves system performance by allowing data owners to supply data directly to the requestor without consuming memory bandwidth. ddr memory subsystem the amd-760 mpx platform implements the latest evolution in high- performance memory technology?double data rate (ddr) sdram. ddr memory is
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 22 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 a natural extension of current pc100/pc133 sdram technology. however, ddr offers higher performance at a competitive cost. similar to the amd athlon system bus, the ddr memory subsystem is designed to deliver a peak transfer rate of up to 2.1gb/s. to satisfy the large memory requirements of server- and workstation-class systems, the amd-762 system controller supports up to 4gb of memory space and provides interfacing for four registered dimm slots. note: unbuffered memory dimms are not supported. in applications requiring minimal fault tolerant capability, the amd-760 mpx ddr memory subsystem supports ecc memory and provides detection and correction of single-bit errors. agp- 4 x graphics subsystem the graphics subsystem is a critical element of high-performance workstations. the amd-760 mpx platform implements agp (accelerated graphics port) technology as its graphics subsystem of choice. the intent of the amd-760 mpx platform is to increase overall system performance by eliminating data-movement bottlenecks, allowing a more efficient match to the compute performance offered by faster amd processors. increasing performance without impacting system cost is a difficult design challenge; however, agp graphics technology offers the perfect balance to satisfy even the most extreme user. the amd-762 system controller is equipped with an agp-4x graphics interface designed to provide powerful graphics capability to the workstation desktop. optimized to run concurrently with the amd athlon system bus and ddr memory interface, high- end graphics adapters can truly utilize up to 1gb/s of bandwidth potential offered by the agp-4x subsystem. server applications typically do not require high-end graphics capability. the amd-762 system controller?s agp-4x interface is backwards-compatible with lower
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 23 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 performance agp-1x and agp-2x modes. this feature allows system designers the flexibility to leverage lower-cost agp graphics adapters in their system solutions, thus reducing overall platform cost. ata-100 storage subsystem due to the physical/mechanical nature of hard drives, the storage subsystem is one of the slowest elements within all computer systems. this has a significant impact on overall system performance, since all operating system and software applications are initially loaded from the hard drive. essentially, the storage subsystem ?data pipe? becomes a critical bottleneck in the system. to alleviate this performance issue, the amd-760 mpx platform implements a storage subsystem controller that offers increased data transfer rates between the eide hard drive controller and the actual storage device (hard drive, cd/cd-r/cdrw, dvd, etc.). as shown in figure 15, the amd-768 peripheral bus controller embeds an eide storage controller that offers data transfer rates of 33mb/s, 66mb/s, and 100mb/s. these data transfer rates are compliant with the ata/udma-33/66/100 standards (shown in table 3). although 5400 rpm drives are supported, optimal eide storage subsystem performance is obtained when the ata-100 mode is used in conjunction with hard drives that operate at spindle speeds of 7200 rpm or higher.
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 24 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 processor (0) processor (1) amd-762? system controller amd-768? peripheral bus controller pci bus pc2100 ddr memory 266mhz amd athlon? system bus 266mhz amd athlon system bus ata-33/66/100 eide 266mhz primary channel secondary channel figure 15: the amd-760? mpx chipset eide controller supporting ata-33/66/100mb/s speeds table 3: amd-760? mp chipset eide interface speeds ata mode data transfer rate ata/udma 33 33mb/sec. ata/udma 66 66mb/sec. ata/udma 100 100mb/sec. primary (66mhz) and secondary (33mhz) pci bus interfaces to increase system performance, the amd-760 mpx chipset implements a dual pci bus architecture. as shown in figure 16, the dual pci bus architecture consists of a 66mhz/64-bit/32-bit primary pci bus interface , and a 33mhz/32-bit secondary pci bus interface .
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 25 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 amd-762 tm agp-4x slot ddr memory eide (33/66/100) usb 2 4 smbus pci bus (66mhz/32-bit/64-bit) flash sio lpc bus slot slot amd-768 tm peripheral bus controller pci bus (33mhz/32-bit) slot slot slot scsi ethernet gpio signals ps/2 keyboard ps/2 mouse serial port parallel port audio codec ac-97 link 66mhz 266mhz processor (0) processor (1) 266mhz 266mhz apic bus system management rtc/cmos 64-bit 32-bit figure 16: amd-760? mxp architecture illustrating pci bus connectivity the primary pci bus interface serves two functions: 1. high-speed 66mhz/32-bit interface between the core-logic elements (amd-762 system controller and amd-768 peripheral bus controller). 2. high-speed expansion card support for 66mhz/64-bit/32-bit pci bus-master adapter cards. although the amd-762 system controller provides a 64-bit data path on the primary pci interface, the amd-768 peripheral bus controller only uses the lower 32- bits, since it is only a 32-bit device (64-bit bandwidth is not required by the amd-768 peripheral bus controller). however, the amd-762 system controller can support up to two 66mhz/64-bit/32-bit pci adapter cards, allowing high-speed devices (such as storage, communication, and networking devices) to stream data quickly. the secondary pci bus interface provides a 33mhz/32-bit pci interface for traditional pci devices. the amd-768 peripheral bus controller provides arbitration
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 26 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 capability within its secondary pci bus to support up to eight pci devices. 7 these eight devices can be a mixture of slots and on-board motherboard components. 8 table 4 lists the peak data transfer rates associated with each of the pci buses. these buses allow the system integrator the flexibility to balance cost and performance. for example, in workstation applications, inexpensive 33mhz/32-bit network adapters can be used for connectivity, while higher-performance 66mhz/64-bit adapters can be used to enable a fast scsi storage subsystem. in server applications, high-performance 66mhz/64-bit adapters can be used to enable a massive raid storage subsystem or to accommodate several high-speed multi-port networking/communication adapters. table 4: pci bus 66mhz and 33mhz peak data transfer rates with 32-bit and 64-bit data paths pci bus data path width peak bandwidth primary 66mhz, 64-bit data path 528mb/sec. primary 66mhz, 32-bit data path 264 mb/sec. secondary 33mhz, 32-bit data path 132mb/sec. ac-97 audio interface the amd-760 mpx chipset integrates an ac-97 interface 9 within the amd-768 peripheral bus controller to enable two-channel (left and right) audio onto the platform. as shown in figure 17, a motherboard ac-97 audio codec can be attached to this interface (along with the appropriate connectors) to provide an inexpensive base audio solution for workstation applications. this feature offers two advantages. 1. the system integrator doesn?t have to suffer the additional cost of a more expensive pci audio card solution. 7 req/gnt#[6:0] pairs are allocated for secondary pci bus slots and on-board devices. a separate pair of signals (preq/pgnt#) is dedicated to a priority pci device. 8 amd designs and tests its reference design motherboards to support three secondary pci slots. if more slots or additional motherboard devices are desired, the system designer must perform the appropriate analysis and testing to ensure signal integrity and proper operation. 9 ac-97 soft modem capability is not supported by the amd-760 mpx chipset.
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 27 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 2. since pci slots are limited by the motherboard form-factor, a valuable pci slot is not consumed by a pci audio adapter, allowing the pci slot to be used to enable a more critical function (such as networking, scsi storage subsystem, etc). amd-768 tm peripheral bus controller ac-97 audio codec ac-97 link l/r audio-out l/r audio-in microphone-in audio connectors motherboard figure 17: ac-97 audio support as shown, two-channel audio capability includes the following: ? left and right audio-out ? left and right audio-in ? microphone-in the system designer can choose from a variety of supported codecs to meet a range of cost and performance objectives.
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 28 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 appendix glossary of terms agp? accelerated graphics port bga? ball grid array codec? coder\decoder ddr? double data rate ecc? error correcting code i/o? input/output mp? multiprocessor sba? side-band addressing what is bus snooping? imagine sharing a checking account with several co-workers. it becomes very important to monitor who made deposits, who made withdrawals, and when the transactions occurred. the objective is to ensure that each person understands the current balance of the account and the pending transactions before a check is written, and hopefully the account will never be overdrafted. now imagine the process that each of the participants has to perform before he or she writes and commits a check. 1. what is the current balance? 2. what are the pending transactions from myself and the other account participants? 3. is anyone trying to access the account now, and what type of transaction is occurring? 4. based on these questions, is the current/pending balance enough to cover the check that is about to be written? can this transaction be committed without penalty? simply, the objective is to understand whether or not the current balance is accurate and to obtain the accurate balance before the transaction is committed. the situation to be avoided is an overdraft, to which a severe penalty will be charged.
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 29 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 this scenario is similar to the issues encountered in multiprocessing systems when several processors and bus-masters must share main memory. the system must ensure that each processor obtains accurate and timely information within a dynamic shared environment. the data obtained by each processor must be ?coherent,? before the processors act on the data. just as an overdraft must be avoided in the shared checking account example, ?incoherent? data must be avoided in multiprocessing systems, otherwise errors will result with severe effects. bus snooping is the process of monitoring memory transactions in a multiprocessor system to ensure that the memory transaction requestor (typically a processor or bus-master) receives accurate and timely data. the bus-snooping process and mechanisms must ensure that data is coherent throughout the system, otherwise an error will occur. similar to the thought process steps in the shared checking account example, the processors and core-logic elements must execute a similar process to ensure coherency. if a processor is performing a memory transaction, the following must be determined: 1. is the data requested contained in the requestor?s cache? if so, is it stale data or is it accurate data? 2. if the data is stale, is the accurate version in main memory or in another processor?s cache? 3. if the data is in another processor?s cache, has the other processor recently changed the data? all of this analysis and the actions that move and update the data to maintain coherency is part of the bus-snooping process. bus-snooping and data-coherency maintenance is the system responsibility (i.e., a concerted effort by the processors, core- logic, and participating bus-masters). agp graphics background to understand the advantages and benefits of agp graphics, it is necessary to understand the issues that agp technology has resolved. figure 18 shows an architectural diagram of a generic pci bus-based graphics subsystem. in this architecture, the graphics
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 30 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 subsystem resides on the pci bus. note that the pci bus graphics adapter embeds its own local memory on the adapter card. although this architecture performed well in its time frame, several issues arose that motivated the need for agp: 1. upgrading graphics memory is expensive, as memory modules must be added to the graphics card, or the graphics card must be replaced entirely. 2. since some graphics data (such as textures and other information) are stored in main memory, the pci-based graphics card must access main memory via the pci bus. these accesses may occur frequently, particularly if the graphics adapter has a small amount of local memory. unfortunately, the graphics card must compete with other pci bus peripherals for pci bus bandwidth. 3. if the graphics adapter must make frequent pci bus accesses, other pci bus peripherals may become starved for pci bus bandwidth. processor southbridge texture northbridge system memory eide usb 2 4 pci bus (33mhz/32-bit) flash sio lpc bus pci graphics adapter slot slot slot slot graphics memory system architecture with pci bus-based graphics adapter. - graphics adapter has local memory. - adapter accesses system memory for textures or stores in local memory. figure 18: older system architecture showing pci bus-based graphics figure 19 illustrates how agp technology elegantly resolves the issues facing pci bus graphics architecture. the amd-762 system controller (the northbridge element of the amd-760 mpx chipset) embeds the system?s agp graphics interface. the agp interface utilizes the 66mhz pci bus protocol in tandem with a side-band addressing
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 31 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 (sba) bus for concurrent posting of commands from the graphics card to the agp logic embedded in the northbridge (see figure 20). the northbridge embeds read/write and command queues (buffers) to allow full-speed data and command transport between the agp device and the amd-762 system controller, and concurrent full-speed data transport between the amd-762 system controller and the ddr memory subsystem. amd-762 tm agp-4x slot ddr memory eide (33/66/100) usb 2 4 smbus pci bus (66mhz/32-bit/64-bit) flash sio lpc bus slot slot amd-768 tm peripheral bus controller pci bus (33mhz/32-bit) slot slot slot scsi ethernet gpio signals ps/2 keyboard ps/2 mouse serial port parallel port audio codec ac-97 link 66mhz 266mhz processor (0) processor (1) 266mhz 266mhz apic bus system management rtc/cmos graphics textures 64-bit 32-bit local memory agp graphics adapter figure 19: amd-762? system controller agp graphics architecture showing use of system memory for graphics operations the architectures shown in figure 19 and figure 20 produce the following benefits: ? the native architecture of agp graphics subsystem (66mhz pci bus interface with side-band addressing, and embedded northbridge agp logic) offers significant raw performance improvement over pci bus-based graphics subsystems. ? the agp architecture allows the agp graphics subsystem to view and use main memory just like its own local memory?meaning that the agp graphics card shares system memory. the agp graphics card cannot distinguish between system memory and local memory, as it all appears as local memory. to the end-user, graphics performance can be enhanced by
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 32 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 increasing system memory (inexpensive), rather than by adding expensive graphics memory. ? the graphics subsystem no longer has to compete for pci bus bandwidth to access data in system memory. this benefit allows the graphics subsystem to run at full speed with minimal interruption from other components in the system. it also increases system concurrency?meaning that the processor, agp graphics subsystem, and pci bus device can run independently and concurrently, thus increasing system performance. ? pci bus devices no longer have to compete with the graphics adapter for pci bus bandwidth. pci bus availability has been increased with the removal of the graphics subsystem from the pci bus. agp textures system memory 66mhz pci bus signaling sba bus agp device northbridge request queue data 0 data 1 data n rqst n rqst 1 rqst 0 data queue agp logic allows concurrent request/command and data transactions (de-coupled data transactions) figure 20: high-level agp interface diagram showing bus architecture and embedded northbridge components over time, the agp graphics subsystem has scaled to increasing levels of performance. as shown in figure 20 there are several modes (data transfer rates) that have evolved over time. analogous to gears on a sports car transmission, first gear is the original agp-1x mode, offering a data transfer rate of up to 264mb/sec. second gear is
w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r w h i t e p a p e r page 33 amd-760? mpx platform for the amd athlon? mp processor january 4, 2002 agp-2x mode, doubling the data transfer rate to up to 528mb/sec. finally, third gear is agp-4x, offering the highest performance data transfer rate of up to 1gb/sec. (the notation 2x and 4x are relative to the original agp-1x mode). in the future, higher performance modes (overdrive and turbo gears, perhaps) may be added. table 5: agp modes and corresponding peak bandwidths agp graphics mode peak bandwidth (data transfer rate) agp-1x up to 264mb/sec. agp-2x up to 528mb/sec. agp-4x up to 1gb/sec. note: the amd-760 mpx chipset is designed to support all modes shown in table 5. amd overview amd is a global supplier of integrated circuits for the personal and networked computer and communications markets with manufacturing facilities in the united states, europe, and asia. amd produces microprocessors, flash memory devices, and support circuitry for communications and networking applications. founded in 1969 and based in sunnyvale, california, amd had revenues of $4.6 billion in 2000. (nyse: amd). ? 2002 advanced micro devices, inc. all rights reserved. amd, the amd arrow logo, amd athlon, amd-760, amd-762, amd-768 and combinations thereof are trademarks of advanced micro devices, inc. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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