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amendment ? copyright 2000 advanced micro devices, inc. all rights reserved. publication# 21914 rev: b amendment/ 1 issue date: february 2000 am186 ? cc/ch/cu microcontrollers users manual this document amends the am186?cc/ch/cu microcontrollers users manual , order #21914b. it consists of these parts: n documentation defects and corrections on page 1 lists corrections to be made in page number order. n changed figures on page 10 provides edited versions of changed tables and figures. n an index is included at the end of this amendment. documentation defects and corrections table 1 on page 2 lists defects that have been found in the am186?cc/ch/cu microcontrollers users manual, order #21914b. defects are listed in page order. each entry lists the following: n page number n item to be corrected n original text (or description of text to change) n corrected text (or description of change to make) n comment explaining the change entries that correct text in a diagram or figure do not contain the entire diagram or figure. if graphical information is changed, the table refers to the page in this amendment where the changed figure can be found. square brackets ( [ ] ) are used to indicate a description of the text or change to be made, as opposed to the actual text. unchanged portions of a paragraph are replaced by an ellipsis (...) in entries where this might make the change easier to find. the whole paragraph is included if it is useful for understanding why the change was made.
2 am186?cc/ch/cu microcontrollers users manual amendment amendment table 1. corrections to the am186?cc/ch/cu microcontrollers users manual , rev. b page item original text change to comment chapter 1 architectural overview 1-10 1.4.3.2 general- purpose dma channels (chapter 8) , 2nd paragraph external peripherals support dma transfers through the external dma request pins (drq1Cdrq0). each general-purpose channel accepts a dma request from one of three sources: the dma request signals (drq1Cdrq0), timer 2, or the uarts. (note that timer 2 acts only as a dma request source; no data is transferred to or from timer 2.)... external peripherals support dma transfers through the external dma request pins (drq1Cdrq0). each general-purpose channel can accept synchronized dma requests from these sources: the dma request signals (drq1Cdrq0), timer 2, or the uarts. (note that timer 2 acts only as a dma request source; no data is transferred to or from timer 2.) in addition, system software can initialize and start unsynchronized dma transfers... note that this paragraph intentionally omits usb as a dma request source. usb requests are mentioned in the subsequent paragraph in the manual. chapter 3 system overview 3-5 3.4 initialization and reset , 3rd paragraph from bottom, 2nd sentence pins are latched on the deassertion of res , and therefore are not affected by an internal watchdog- timer-generated reset. some pin states are latched only on the deassertion of res , and therefore are not affected by an internal watchdog-timer-generated reset. 3-16 table 3-7 signal descriptions , reserved pins on the am186ch hdlc microcontroller, the rsvd_75 pin should be tied externally to v ss . on the am186ch hdlc microcontroller, pins rsvd_75, rsvd_76, rsvd_80, rsvd_81, and rsvd_101Crsvd_104 and are reserved. on the am186cc and am186cu microcontrollers, pins rsvd_101C rsvd_104 are reserved unless pinstrap {usbxcvr } is sampled low on the rising edge of reset. on the am186cu usb microcontroller, pins rsvd_119C rsvd_116 are reserved. all other reserved pins should not be connected. some pins are reserved only on certain microcontrollers or in a particular pinstrap configuration. on the am186ch hdlc microcontroller, pins rsvd_75, rsvd_76, rsvd_80, rsvd_81, and rsvd_101Crsvd_104 are reserved. on the am186cc and am186cu microcontrollers, pins rsvd_101C rsvd_104 are reserved unless pinstrap {usbxcvr } is sampled low on the rising edge of reset. on the am186cu usb microcontroller, pins rsvd_119C rsvd_116 are reserved. with one exception, all reserved pins should be left unconnected. the exception is that, on the am186ch hdlc microcontroller, the rsvd_75 pin should be tied externally to v ss . clarify reserved pin usage. chapter 7 interrupts 7-20 7.5.7 software-related considerations , second bullet writing a zero to the appropriate channel bit in the interrupt request (reqst) register clears the pending interrupt. this facility provides a simple way to clear a spurious edge- triggered interrupt that may have occurred when initially configuring a pio pin as an interrupt source. writing a zero to the appropriate channel bit in the interrupt request (reqst) register clears the pending edge-triggered interrupt. this facility provides a simple way to clear a spurious edge-triggered interrupt that may have occurred when initially configuring a pio pin as an interrupt source. note that for level-triggered interrupts, the interrupt source must be cleared to clear the interrupt.
am186?cc/ch/cu microcontrollers users manual amendment 3 amendment chapter 8 dma controller 8-1 8.1 overview , end of fourth paragraph, marked cc ...each general-purpose channel accepts a dma request from one of four sources: the dma request signals (drq1Cdrq0), timer 2, the uarts, or the usb peripheral controller. (note that timer 2 acts only as a dma request source; no data is transferred to or from timer 2.) ...each general-purpose channel can accept synchronized dma requests from four sources: the dma request signals (drq1Cdrq0), timer 2, the uarts, or the usb peripheral controller. (note that timer 2 acts only as a dma request source; no data is transferred to or from timer 2.) in addition, system software can initialize and start unsynchronized dma transfers. 8-1 8.1 overview , end of fifth paragraph, marked ch ...each general-purpose channel accepts a dma request from one of three sources: the dma request signals (drq1Cdrq0), timer 2, or the uarts. (note that timer 2 acts only as a dma request source; no data is transferred to or from timer 2.) ...each general-purpose channel can accept synchronized dma requests from four sources: the dma request signals (drq1Cdrq0), timer 2, or the uarts. (note that timer 2 acts only as a dma request source; no data is transferred to or from timer 2.) in addition, system software can initialize and start unsynchronized dma transfers. 8-2 end of partial first paragraph (marked cu on the manuals previous page) ...each general-purpose channel accepts a dma request from one of four sources: the dma request signals (drq1Cdrq0), timer 2, the uarts, or the usb peripheral controller. (note that timer 2 acts only as a dma request source; no data is transferred to or from timer 2.) ...each general-purpose channel can accept synchronized dma requests from four sources: the dma request signals (drq1Cdrq0), timer 2, the uarts, or the usb peripheral controller. (note that timer 2 acts only as a dma request source; no data is transferred to or from timer 2.) in addition, system software can initialize and start unsynchronized dma transfers. 8-18 figure 8-4 source- synchronized general-purpose dma transfers , cycle labels at top of figure fetch cycle fetch cycle fetch cycle deposit cycle second phase of transfer is deposit cycle. 8-19 last paragraph on page a dma request is not acknowledged from the same source for four processor clock cycles after the end of the deposit cycle. in a source- synchronized dma transfer, the drq signal must be deasserted at least four clocks before the end of the transfer.... in a source-synchronized dma transfer, the drq signal must be deasserted at least four clocks before the end of the transfer.... delete first sentence of paragraph. table 1. corrections to the am186?cc/ch/cu microcontrollers users manual , rev. b (continued) page item original text change to comment
4 am186?cc/ch/cu microcontrollers users manual amendment amendment 8-20 first paragraph on page a destination-synchronized transfer differs from a source-synchronized transfer in that the four cycle delay allows the destination device to deassert its drq signal four clocks before another request is latched. without this delay, the destination device would not have time to deassert its drq signal. because of the four extra cycles, a destination- synchronized dma channel allows other bus masters to take the bus during the idle states. a destination-synchronized transfer differs from a source-synchronized transfer in that a destination- synchronized drq is masked off for four cycles after the deassertion of the wr signal. this allows an external or internal device to use wr , in conjunction with chip selects or address lines, to signal the end of the deposit cycle. the destination- synchronized device must then deassert drq within four cycles in order to signal that the device is not ready for the next dma transfer. while the destination-synchronized drq is masked off, the bus can be accessed by the cpu or other, possibly lower priority, bus masters. rewrite the paragraph. 8-25 next to last paragraph on page, last two sentences for this reason, the high-speed uart has an additional overrun error-immediate (oerim) interrupt bit that is not placed in the fifo. software can monitor or interrupt on oerim to detect and correct this sort of system programming error. for this reason, the high-speed uart has additional overrun error- immediate (oerim) and break immediate (brkim) interrupt bits that are not placed in the fifo. when the receive fifo is enabled, software can monitor or interrupt on oerim or brkim to detect and correct this sort of system programming error. note: the brkim bit is not available in parts released prior to revision c1. for processor revision information, see the prl register description in the am186cc/ch/cu register set manual , order #21916b [and its amendment, order #21916b/1]. add brkim bit. 8-28 8.5.7.3 smartdma? channel memory overview , third paragraph [existing third paragraph] [add note after paragraph] note: the smartdma channel descriptor rings must reside in 16-bit memory. the buffers pointed to by the descriptors can be in either 8-bit or 16-bit memory. table 1. corrections to the am186?cc/ch/cu microcontrollers users manual , rev. b (continued) page item original text change to comment
am186?cc/ch/cu microcontrollers users manual amendment 5 amendment 8-43 8.5.9 software-related considerations software must stop dma operation before writing to the gdxcon1 register, or the results are unpredictable. stopping the smartdma channel has no effect while a request is pending on the channel. before stopping the channel, make sure the requesting peripheral (hdlc channel or usb endpoint) is stopped. software must stop dma operation before writing to the gdxcon1 register, or the results are unpredictable. stopping the smartdma channel has no effect while a request is pending on the channel. before stopping the channel, make sure the requesting peripheral (hdlc channel or usb endpoint) is stopped. if the requesting peripheral is stopped by an error, the error handler should stop the smartdma channel before clearing the status bit. otherwise the smartdma request might be reasserted before software can stop the channel. chapter 9 programmable i/o signals 9-2 figure 9-1 pio operation block diagram , pullup/ pulldown resistor value 100k 50 k- w correct resistor value. 9-5 9.5.2 defining the pio signal as input or output , last sentence on page the internal pullup and pulldown resistors each have a value of approximately 10 k w . the internal pullup and pulldown resistors each have a value of approximately 50 k w . chapter 11 watchdog timer 11-1 11.1 overview , last sentence of first paragraph. ... resout signal, which is pulled low during an external reset and can be pulled low during an internal reset. ... resout signal, which is pulled high during an external reset and can be pulled high during an internal reset. resout is active high, not active low. chapter 13 asynchronous serial ports 13-5 13.5.1.1.2 transmitting data , steps 1 and 2. 1. verify that the thre bit in the (h)spstat register is set to 1 to ensure the transmit register can be written without loss of data. 2. if fifos are being used (high- speed uart only), instead of polling the thre bit, verify that the fifo is not yet full (tthrsh bit in the hspstat register is set to 1). 1. verify that the thre bit in the (h)spstat register is set to 1 to ensure the transmit register can be written without loss of data. note: if fifos are not used, software must verify that the thre bit is set to 1 even if the temt bit was set in the (h)spstat register before the previous write. 2. if fifos are being used (high- speed uart only), software can omit polling the thre bit only if it is certain there is space in the fifo. the fifo contains 16 empty slots if the temt bit is set. the fifo contains at least eight empty slots if hardware sets the tthrsh bit in the hspstat register after software has cleared it. table 1. corrections to the am186?cc/ch/cu microcontrollers users manual , rev. b (continued) page item original text change to comment
6 am186?cc/ch/cu microcontrollers users manual amendment amendment 13-7 13.5.1.3 autobaud mode , step 7 7. wait for the abaud bit in the hspcon1 register to go to 0 to indicate that the autobaud operation is complete. the computed baud divisor is automatically copied into the hspbdv register, and the autobaud (abaud) bit in the hspcon1 register is cleared. 7. wait for the abaud bit in the hspcon1 register to go to 0 to indicate that the autobaud operation is complete. the computed baud divisor is automatically copied into the hspbdv register, and the autobaud (abaud) bit in the hspcon1 register is cleared. this also sets the abdone bit in the hspstat register. note: the abdone bit is not available in parts released prior to revision c1. for processor revision information, see the prl register description in the am186cc/ch/cu register set manual , order #21916b [and its amendment, order #21916b/1]. 13-13 13.5.4 cts/rtr hardware flow control , second and third paragraphs in the cts/rtr protocol, the receiver asserts clear-to-send (cts) whenever there is room in the receiver for more data. the transmitting device should sample cts before beginning transmission of each frame. cts is deasserted when the start bit is detected for the last frame that can be read without data loss. when fifos are disabled, cts is deasserted after the start bit for each frame is detected and remains deasserted until the data is read from the receive data register. when the receive fifo is enabled, cts is deasserted after the start bit is received for the last frame that will fit in the fifo. the transmitter samples ready-to- receive (rtr) before transmitting the start bit of each frame. the rtr signal is not sampled during frame transmission. this allows the receiving device to deassert rtr any time before the end of the stop bit. the transmitter does not begin transmitting the start bit for the next frame while rtr is deasserted. in the cts/rtr protocol, the uarts ready-to-receive (rtr) output is connected to the attached devices clear-to-send (cts) input, and the attached devices rtr output is connected to the uarts cts input. (i.e., the cts and rtr signals are cross-connected.) the receiver asserts rtr whenever there is room in the receiver for more data. the transmitting device should sample this signal (at its cts input) before beginning transmission of each frame. the receiver deasserts rtr when the start bit is detected for the last frame that can be read without data loss. when fifos are disabled, the receiver deasserts rtr after the start bit for each frame is detected, and holds rtr deasserted until the data is read from the receive data register. when the receive fifo is enabled, the receiver deasserts rtr after the start bit is received for the last frame that will fit in the fifo. the transmitter samples its cts input before transmitting the start bit of each frame. the cts input is not sampled during frame transmission. this allows the receiving device to deassert its rtr output any time before the end of the stop bit. the transmitter does not begin transmitting the start bit for the next frame while its cts input is deasserted. clarify. table 1. corrections to the am186?cc/ch/cu microcontrollers users manual , rev. b (continued) page item original text change to comment
am186?cc/ch/cu microcontrollers users manual amendment 7 amendment 13-17C 13-19 discussion of autobaud enhancement; changes throughout [references to registers hspab0C hspab3] [add a new register hspab4 at offset 27e, and modify text accordingly. wherever the text states that the abthrsh3 bit field in the hspab3 register must contain the largest threshold, specify the abthrsh4 bit field in the hspab4 register instead. also add the following note:] note: the hspab4 register is not available in parts released prior to revision c1. for processor revision information, see the prl register description in the am186cc/ch/cu register set manual , order #21916b [and its amendment, order #21916b/1]. to maintain compatibility with existing software that does not initialize the hspab4 register, the hspab3 register can contain the largest abthrshx value, in which case the hspab4 register must be cleared or left in its default disabled state (00h). 13-18 figure 13-9 autobaud enhancement [existing figure] [replace with figure 13-9 on page 10 of this amendment.] update and clarify figure. 13-19 table 13-5 uarts interrupt sources [existing table] [add new row before overrun error on receive fifo:] break on receive fifo, rsie (off), brkim (off) add brkim bit. 13-20 13.5.7 break detection and generation , first paragraph [existing first paragraph.] [add new sentence and note:] if the receive fifo is enabled (high- speed uart only), the break immediate (brkim) status bit indicates the break condition as soon as it occurs; the fer and brk status bits are not set until the corresponding character is loaded into the hsprxd register. note: the brkim bit is not available in parts released prior to revision c1. for processor revision information, see the prl register description in the am186cc/ch/cu register set manual , order #21916b [and its amendment, order #21916b/1]. add brkim bit. table 1. corrections to the am186?cc/ch/cu microcontrollers users manual , rev. b (continued) page item original text change to comment
8 am186?cc/ch/cu microcontrollers users manual amendment amendment chapter 14 synchronous serial port 14-4 14.5.1 usage , item #5 5. wait for the dr/dt bit in the ssstat register to go to 0 to indicate the transmit or receive has completed. 5. wait for the dr/dt bit in the ssstat register to go to 1 to indicate the transmit or receive has completed. chapter 16 hdlc external serial interface configuration (tsas) 16-5 16.3 system design , first sentence lists the signals that are multiplexed with other microcontroller functions. table 16-1 lists the signals that are multiplexed with other microcontroller functions. chapter 17 general circuit interface (gci) 17-8 figure 17-3 gci terminal mode frame structure [existing figure] [change to new figure 17-3, shown on page 10 of this amendment.] change fsc signal waveform. chapter 18 universal serial bus (usb) 18-4 last paragraph before figure [existing text] [add the following sentence:] in these examples, software defines a pio input (pio_usb_detect) to monitor the usbs v usb signal, and a pio output (pio_usb_vcc) to control the 1.5 k- w pullup on usbd+. clarify pio use in example. figure 18-2 usb with internal transceiver [existing figure] [change to new figure 18-2, shown on page 11 of this amendment.] add pulldown to v usb . clarify pio use in example. 18-5 figure 18-3 usb with external transceiver [existing figure] [change to new figure 18-3, shown on page 12 of this amendment.] add pulldown to v usb . 18-30 18.5.12 endpoint definitions , second paragraph the usb specification, version 1.0 defines the endpoint configuration process: the usb specification, version 1.0 defines the endpoint configuration process. change colon at end of sentence to a period. 18.5.12 endpoint definitions , third paragraph host software should only set configuration and interface values that match a device descriptor returned by the device in response to a get_descriptor command. however, the usb hardware accepts as valid any configuration or feature setting in the range of 0d to 3d, regardless of the available descriptors. to help ensure reliable operation in any usb environment, device software can define a minimal descriptor (i.e., endpoint 0 with no bandwidth allocation) for any configuration and interface settings that it does not define otherwise. note: host software should only set configuration and interface values that match a device descriptor returned by the device in response to a get_descriptor command. however, the usb hardware accepts as valid any configuration or feature setting in the range of 0d to 3d, regardless of the available descriptors. to help ensure reliable operation in any usb environment, device software can define a minimal descriptor (i.e., endpoint 0 with no bandwidth allocation) for any configuration and interface settings that it does not define otherwise. remove quotation marks. paragraph is not a quotation. table 1. corrections to the am186?cc/ch/cu microcontrollers users manual , rev. b (continued) page item original text change to comment
am186?cc/ch/cu microcontrollers users manual amendment 9 amendment appendix a register summary a-8 cntctl register, bit 7 res hndshk add bit. a-9 iepctl register, bit 7 aepctl register, bit 7 bepctl register, bit 7 a-10 cepctl register, bit 7 depctl register, bit 7 a-11 hspstat register, bit 13 res brkim add bit. hspstat register, bit 11 res abdone add bit. hspimsk register, bit 13 res brkim add bit. hspimsk register, bit 11 res abdone add bit. hspabx registers [existing rows] [add a row for the new hspab4 register, similar to the other hspabx registers, with offset 27eh, default location fe7eh, default value 0h, and bit fields abdiv4 and abthrsh4.] add register. table 1. corrections to the am186?cc/ch/cu microcontrollers users manual , rev. b (continued) page item original text change to comment
10 am186?cc/ch/cu microcontrollers users manual amendment amendment changed figures for your convenience, the following pages contain edited copies of some figures. figures with minor text changes are not reproduced here; see table 1 beginning on page 2 for complete change descriptions. replace figure 13-9 on page 13-18 of the manual with the following figure. figure 13-9 autobaud enhancement change figure 17-3 on page 17-8 to the following. the new figure changes the fsc waveform. figure 17-3 gci terminal mode frame structure abdiv0 abthrsh0 abthrsh1 abthrsh2 abthrsh4 abdiv1 abdiv2 abdiv4 (largest) calc. divisor abdiv3 abthrsh3 } } } } } } calc. divisor (smallest) calculated programmed thresholds resulting divisor divisor (example) notes: 1. if the calculated divisor is larger than the largest abthrshx bit field value, the resulting divisor is the same as the calculated divisor. 2. the abthrsh4 or abthrsh3 bit field must contain the largest threshold value. if the abthrsh4 bit field is not the largest threshold, it must be 0. the remaining abthrshx bit fields must be programmed with successively smaller thresholds for lower-numbered abthrshx bit fields. if all five thresholds are not needed, the lowest-numbered abthrshx bit fields (abthrsh0, abthrsh1, etc.) can be cleared or left in their default disabled state (00h). possible divisors b1 b2 mon0 dc/i0 mx mr ic1 ic2 mon1 c/i1 mx mr tic 8-bits 8-bits 8-bits 2-bits 2-bits 2-bits 8-bits 8-bits 8-bits 4-bits 8-bits 6-bits 8-bits 8-bits 8-bits gci subframe 0 gci subframe 1 gci subframe 2 fsc dd/ du
am186?cc/ch/cu microcontrollers users manual amendment 11 amendment change figure 18-2 on page 18-4 to the following. the new figure adds a 100 k- w pulldown resistor to v usb and a note to clarify pio use in the example. figure 18-2 usb with internal transceiver n-channel fet am186cc/cu microcontroller dg s d s g 1.5 k- w pio_usb_detect 1 pio_usb_vcc 1 usbdC [udmns] usbd+ [udpls] v usb usbdC usbd+ gnd 1 2 3 4 usb type b r1 2 r2 2 notes: 1. for the pio_usb_detect and pio_usb_vcc signals, select pio pins that default to input operation. if a pio with an internal pullup resistor is used, add a 10 k- w external pulldown resister to override the internal 50 k- w pullup. see table 9-1 on page 9-3 [of the manual] for pio signal defaults. 2. the usb specification requires a driver impedance between 29 w and 44 w on the usbd+ and usbdC signals. for information about driver characteristics and selecting a series resistor value, see the data sheets for the am186cc and am186cu microcontrollers. 100 k- w v cc n-channel fet
12 am186?cc/ch/cu microcontrollers users manual amendment amendment change figure 18-3 on page 18-5 to the following. the new figure adds a 100 k- w pulldown resistor to v usb and a note to clarify pio use in the example. figure 18-3 usb with external transceiver pio_usb_detect 1 pio_usb_vcc 1 dg s d s g usb type b v usb usbdC usbd+ gnd 1 2 3 4 utxdmns[rsvrd_102] utxdpls[rsvrd_101] uxvoe [rsvrd_103] uxvrcv[rsvrd_104] udmns[usbdC] udpls[usbd+] 1.5 k- w r1 2 r2 2 notes: 1. for the pio_usb_detect and pio_usb_vcc signals, select pio pins that default to input operation. if a pio with an internal pullup resistor is used, add a 10 k- w external pulldown resister to override the internal 50 k- w pullup. see table 9-1 on page 9-3 [of the manual] for pio signal defaults. 2. the usb specification requires a driver impedance between 29 w and 44 w on the usbd+ and usbdC signals. for information about driver characteristics and selecting a series resistor value, see the documentation for the external transceiver. am186cc/cu microcontroller 100 k- w v cc n-channel fet n-channel fet
am186?cc/ch/cu microcontrollers users manual amendment index-1 amendment index numerics 16-bit memory, and smartdma channel, 4 a abaud bit, 6 abdone bit, 6, 9 asynchronous serial port (uart), 4C7 autobaud detection, 6 enhancement, 7, 9 b break-immediate bit, 4, 7, 9 brkim bit, 4, 7, 9 c changed figures, 10 clearing an edge-triggered interrupt request, 2 cts signal, 6 d deposit cycle, dma transfers, 3 dma request sources, 2C3 transfers, figure, 3 e edge-triggered interrupt request, clearing, 2 ellipsis in changed text, 1 f fer bit, 7 fetch cycle, dma transfers, 3 fifo and immediate status bits, 4, 7 figures, changed, 10 frame structure figure, gci terminal mode, 8, 10 fsc signal waveform figure, 8, 10 g gci terminal mode frame structure figure, 8, 10 h hspabx registers, 7, 9 hspimsk register, 9 hspstat register, 5C6, 9 i immediate status bits, 4, 7, 9 initialization and reset, 2 interrupt request (reqst) register, clearing bits, 2 interrupt sources table, 7 n no-connect pins, 2 o oerim bit, 4 overrun error immediate bit, 4 p pin states, latched on reset, 2 pinstrap, {usbxcvr }, 2 pio pullup or pulldown resistor, 5 pulldown resistor pio, 5 v usb signal, 8, 11C12 pullup resistor pio, 5 usbd+ signal, 8
advance information index-2 am186?cc/ch/cu microcontrollers users manual amendment r reqst register, 2 reserved pins, 2 reset, watchdog-timer-generated, 2 resistor, pulldown, v usb signal, 8, 11C12 resout signal, 5 rsvd_xx pins, 2 rtr/cts protocol, 6 s serial port, asynchronous (uart), 4C7 smartdma channel, 4C5 software, unsynchronized dma, 2C3 source synchronized dma transfers figure, 3 spurious interrupt, clearing, 2 square brackets in changed text, 1 synchronized dma, 2C3 u unsynchronized dma, 2C3 usb with internal transceiver, figure, 8, 11C12 {usbxcvr } pinstrap, 2 v v usb signal, 8, 11C12 w watchdog-timer-generated reset, 2
advance information am186?cc/ch/cu microcontrollers users manual amendment index-3
am186?cc/ch/cu microcontrollers users manual amendment amendment trademarks amd, the amd logo, and combinations thereof, lan, am186, am188, and smartdma are trademarks of advanced micro devices, inc. other product names used in this publication are for identification purposes only and may be trademarks of their respective com panies. disclaimer the contents of this document are provided in connection with advanced micro devices, inc. ("amd") products. amd makes no repr esentations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make c hanges to speci- fications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or oth erwise, to any in- tellectual property rights is granted by this publication. except as set forth in amd's standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, th e implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. amd's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical impla nt into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd's p roduct could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discont inue or make changes to its products at any time without notice. ? 2000 advanced micro devices, inc. all rights reserved.

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