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rev.1.00, jul.24.2003, page 1 of 13 R1LV0408C-I series wide temperature range version 4 m sram (512-kword 8-bit) rej03c0098-0100z rev. 1.00 jul.24.2003 description the R1LV0408C-I is a 4-mbit static ram organized 512-kword 8-bit. R1LV0408C-I series has realized higher density, higher performance and low power consumption by employing cmos process technology (6-transistor memory cell). the R1LV0408C-I series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. it has packaged in 32-pin sop, 32-pin tsop ii and 32-pin stsop. features ? single 3 v supply: 2.7 v to 3.6 v ? access time: 55/70 ns (max) ? power dissipation: ? active: 6 mw/mhz (typ) ? standby: 2.4 w (typ) ? completely static memory. ? no clock or timing strobe required ? equal access and cycle times ? common data input and output. ? three state output ? directly ttl compatible. ? all inputs and outputs ? battery backup operation. ? operating temperature: ? 40 to +85 c
R1LV0408C-I series rev.1.00, jul.24.2003, page 2 of 13 ordering information type no. access time package r1lv0408csp-5si 55 ns 525-mil 32-pin plastic sop (32p2m-a) r1lv0408csp-7li 70 ns r1lv0408csb-5si 55 ns 400-mil 32-pin plastic tsop ii (32p3y-h) r1lv0408csb-7li 70 ns r1lv0408csa-5si 55 ns 8mm 13.4mm stsop (32p3k-b) r1lv0408csa-7li 70 ns
R1LV0408C-I series rev.1.00, jul.24.2003, page 3 of 13 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 cc a11 a9 a8 a13 we# a18 a15 v a17 a16 a14 a12 a7 a6 a5 a4 oe# a10 cs# i/o7 i/o6 i/o5 i/o4 i/o3 v i/o2 i/o1 i/o0 a0 a1 a2 a3 ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss v a15 a17 we# a13 a8 a9 a11 oe# a10 cs# i/o7 i/o6 i/o5 i/o4 i/o3 cc (top view) 32-pin sop 32-pin tsop 32-pin stsop (top view) pin description pin name function a0 to a18 address input i/o0 to i/o7 data input/output cs# ( cs ) chip select oe# ( oe ) output enable we# ( we ) write enable v cc power supply v ss ground
R1LV0408C-I series rev.1.00, jul.24.2003, page 4 of 13 block diagram ? i/o0 i/o7 cs# we# oe# a3 a2a1a0 a6 a5 v v cc ss row decoder memory matrix 2,048 2,048 column i/o column decoder input data control timing pulse generator read/write control a4 a7 a11 a9 a8 a15 a18 a10 a13 a17 a16 a14 a12 lsb msb lsb msb
R1LV0408C-I series rev.1.00, jul.24.2003, page 5 of 13 operation table we# cs# oe# mode v cc current i/o0 to i/o7 ref. cycle h not selected i sb , i sb1 high-z ? h l h output disable i cc high-z ? h l l read i cc dout read cycle l l h write i cc din write cycle (1) l l l write i cc din write cycle (2) note: h: v ih , l: v il , : v ih or v il absolute maximum ratings parameter symbol value unit power supply voltage relative to v ss v cc ? 0.5 to +4.6 v terminal voltage on any pin relative to v ss v t ? 0.5* 1 to v cc + 0.5* 2 v power dissipation p t 0.7 w operating temperature topr ? 40 to +85 c storage temperature range tstg ? 65 to +150 c storage temperature range under bias tbias ? 40 to +85 c notes: 1. v t min: ? 3.0 v for pulse half-width 30 ns. 2. maximum voltage is +7.0 v. dc operating conditions (ta = ? 40 to +85 c) parameter symbol min typ max unit supply voltage v cc 2.7 3.0 3.6 v v ss 0 0 0 v input high voltage v ih 2.2 ? v cc + 0.3 v input low voltage v il ? 0.3* 1 ? 0.6 v note: 1. v il min: ? 3.0 v for pulse half-width 30 ns.
R1LV0408C-I series rev.1.00, jul.24.2003, page 6 of 13 dc characteristics parameter symbol min typ * 1 max unit test conditions input leakage current |i li | ? ? 1 a vin = v ss to v cc output leakage current |i lo | ? ? 1 a cs# = v ih or oe# = v ih or we# = v il or v i/o = v ss to v cc operating current i cc ? 5 10 ma cs# = v il , others = v ih / v il , i i/o = 0 ma average operating current i cc1 ? 8 25 ma min. cycle, duty = 100%, cs# = v il , others = v ih /v il i i/o = 0 ma i cc2 ? 2 5 ma cycle time = 1 s, duty = 100%, i i/o = 0 ma, cs# 0.2 v, v ih v cc ? 0.2 v, v il 0.2 v standby current i sb ? 0.1 0.3 ma cs# = v ih standby current to +85 c i sb1 ? ? 20* 2 a vin 0 v, cs# v cc ? 0.2 v ? ? 10* 3 a to +70 c i sb1 ? ? 16* 2 a ? ? 8* 3 a to +40 c i sb1 ? 0.7* 2 10* 2 a ? 0.7* 3 3* 3 a ? 40 c to +25 c i sb1 ? 0.5* 2 10* 2 a ? 0.5* 3 3* 3 a output low voltage v ol ? ? 0.4 v i ol = 2.1 ma v ol2 ? ? 0.2 v i ol = 100 a output high voltage v oh 2.4 ? ? v i oh = ? 1.0 ma v oh2 v cc ? 0.2 ? ? v i oh = ? 0.1 ma notes: 1. typical values are at v cc = 3.0 v, ta = +25 c and specified loading, and not guaranteed. 2. l version. ( ? 7li) 3. sl version. ( ? 5si) capacitance (ta = +25 c, f = 1.0 mhz) parameter symbol min typ max unit test conditions note input capacitance cin ? ? 8 pf vin = 0 v 1 input/output capacitance c i/o ? ? 10 pf v i/o = 0 v 1 note: 1. this parameter is sampled and not 100% tested.
R1LV0408C-I series rev.1.00, jul.24.2003, page 7 of 13 ac characteristics (ta = ? 40 to +85 c, v cc = 2.7 v to 3.6 v, unless otherwise noted.) test conditions ? input pulse levels: v il = 0.4 v, v ih = 2.4 v ? input rise and fall time: 5 ns ? input and output timing reference levels: 1.5 v ? output load: 1 ttl gate + c l (50 pf) (r1lv0408c-5i) 1 ttl gate + c l (100 pf) (r1lv0408c-7i) (including scope and jig) read cycle R1LV0408C-I -5 -7 parameter symbol min max min max unit notes read cycle time t rc 55 ? 70 ? ns address access time t aa ? 55 ? 70 ns chip select access time t co ? 55 ? 70 ns output enable to output valid t oe ? 30 ? 35 ns chip select to output in low-z t lz 10 ? 10 ? ns 2 output enable to output in low-z t olz 5 ? 5 ? ns 2 chip deselect to output in high-z t hz 0 20 0 25 ns 1, 2 output disable to output in high-z t ohz 0 20 0 25 ns 1, 2 output hold from address change t oh 10 ? 10 ? ns
R1LV0408C-I series rev.1.00, jul.24.2003, page 8 of 13 write cycle R1LV0408C-I -5 -7 parameter symbol min max min max unit notes write cycle time t wc 55 ? 70 ? ns chip selection to end of write t cw 50 ? 60 ? ns 4 address setup time t as 0 ? 0 ? ns 5 address valid to end of write t aw 50 ? 60 ? ns write pulse width t wp 40 ? 50 ? ns 3, 12 write recovery time t wr 0 ? 0 ? ns 6 write to output in high-z t whz 0 20 0 25 ns 1, 2, 7 data to write time overlap t dw 25 ? 30 ? ns data hold from write time t dh 0 ? 0 ? ns output active from end of write t ow 5 ? 5 ? ns 2 output disable to output in high-z t ohz 0 20 0 25 ns 1, 2, 7 notes: 1. t hz , t ohz and t whz are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. this parameter is sampled and not 100% tested. 3. a write occurs during the overlap (t wp ) of a low cs# and a low we#. a write begins at the later transition of cs# going low or we# going low. a write ends at the earlier transition of cs# going high or we# going high. t wp is measured from the beginning of write to the end of write. 4. t cw is measured from cs# going low to the end of write. 5. t as is measured from the address valid to the beginning of write. 6. t wr is measured from the earlier of we# or cs# going high to the end of write cycle. 7. during this period, i/o pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 8. if the cs# low transition occurs simultaneously with the we# low transition or after the we# transition, the output remain in a high impedance state. 9. dout is the same phase of the write data of this write cycle. 10. dout is the read data of next address. 11. if cs# is low during this period, i/o pins are in the output state. therefore, the input signals of the opposite phase to the outputs must not be applied to them. 12. in the write cycle with oe# low fixed, t wp must satisfy the following equation to avoid a problem of data bus contention. t wp t dw min + t whz max
R1LV0408C-I series rev.1.00, jul.24.2003, page 9 of 13 timing waveform read timing waveform (we# = v ih ) t aa t co t rc t lz t oe t olz t hz t ohz valid data valid address high impedance address cs# oe# dout t oh
R1LV0408C-I series rev.1.00, jul.24.2003, page 10 of 13 write timing waveform (1) (oe# clock) t wc t cw t wp t as t ohz t dw t dh t aw t wr *8 address oe# cs# we# dout din valid data valid address high impedance
R1LV0408C-I series rev.1.00, jul.24.2003, page 11 of 13 write timing waveform (2) (oe# low fixed) address cs# we# dout din t wc t cw t wr t aw t wp t as t whz t ow t oh t dw t dh *11 *9 *10 *8 valid data valid address high impedance
R1LV0408C-I series rev.1.00, jul.24.2003, page 12 of 13 low v cc data retention characteristics (ta = ? 40 to +85 c) parameter symbol min typ* 4 max unit test conditions* 3 v cc for data retention v dr 2 ? ? v cs# v cc ? 0.2 v, vin 0 v data retention current to +85 c i ccdr * 1 ? ? 20 a v cc = 3.0 v, vin 0 v i ccdr * 2 ? ? 10 cs# v cc ? 0.2 v to +70 c i ccdr * 1 ? ? 16 a i ccdr * 2 ? ? 8 to +40 c i ccdr * 1 ? 0.7 10 a i ccdr * 2 ? 0.7 3 ? 40 c to +25 c i ccdr * 1 ? 0.5 10 a i ccdr * 2 ? 0.5 3 chip deselect to data retention time t cdr 0 ? ? ns see retention waveform operation recovery time t r t rc * 5 ? ? ns notes: 1. this characteristic is guaranteed only for l version. 2. this characteristic is guaranteed only for sl version. 3. cs# controls address buffer, we# buffer, oe# buffer, and din buffer. in data retention mode, vin levels (address, we#, oe#, i/o) can be in the high impedance state. 4. typical values are at v cc = 3.0 v, ta = +25 c and specified loading, and not guaranteed. 5. t rc = read cycle time. low v cc data retention timing waveform (cs# controlled) v cc 4.5 v 2.4 v 0 v cs# t cdr t r cs# v cc ? 0.2 v v dr data retention mode
R1LV0408C-I series rev.1.00, jul.24.2003, page 13 of 13 keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but ther e is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation p roduct best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporat ion or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, origin ating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reas ons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest produ ct information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracie s or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas te chnology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp oration assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used un der circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor wh en considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or u ndersea repeater use. 6. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com copyright ? 2003. renesas technology corporation, all rights reserved. printed in japan. colophon 0.0
R1LV0408C-I series rev.1.00, jul.24.2003, page 14 of 13 revision record rev. date contents of modification drawn by approved by 1.00 jul. 24, 2003 initial issue

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