View IBM11S1325LP_2877836.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IBM11S1325LP ibm11s2325lp 1m/2m x 32 so dimm module 75h1720 sa14-4472-01 revised 6/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 1 of 22 features ? 72-pin small outline dual-in-line memory module ? performance: ? high performance cmos process ? single 3.3 0.3v power supply ? low active current consumption ? all inputs & outputs are lvttl(3.3v) compatible ? extended data out (edo) access cycle ? refresh modes: ras-only, cbr, hidden and self refresh ? 1024 refresh cycles distributed across 128ms ? 10/10 addressing (row/column) ? optimized for use in byte-write non-parity appli- cations. ? au contacts description the ibm11s2325lp is an 8mb industry standard 72-pin 4-byte small outline dual in-line memory module (so dimm). the module is organized as a 2mx32 dual bank high speed memory array that is intended for use in 16, 32 and 64 bit applications. it is manufactured with four 1mx16 tsop devices, each in a 400mil package. the IBM11S1325LP is a 4mb half populated ver- sion, manufactured with two 1mx16 tsop devices and is organized as a single bank 1mx32 high speed memory array. the use of edo drams allows for a reduction in cycle time from 40ns (fast page) to 25ns (edo, 60ns sort). the use of tsop packages allows for tight dimm spacing (.3 on center). input loading is consistent with 4mb device-based assemblies due to the addition of discrete capacitors maximizing compatibility at the system level. these assemblies are intended for use in space constrained and or low power applications. the ibm 72-pin so dimms provide a high perfor- mance, flexible 4-byte interface in a 2.35 long foot- print. -60 t rac ras access time 60ns t cac cas access time 15ns t aa access time from address 30ns t rc cycle time 104ns t hpc edo mode cycle time 25ns card outline (front) 1 (back) 2 71 72 ibm11s2320nl2m x 3212/8, 5.0v, au. ibm11s2320nn2m x 3212/8, 3.3v, au. discontinued (9/98 - last order; 3/99 last ship)
?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 2 of 22 75h1720 sa14-4472-01 revised 6/97 ibm11s2325lp IBM11S1325LP 1m/2m x 32 so dimm module pin description ras0, ras2 row address strobe (4mb) ras0 - ras3 row address strobe (8mb) cas0 - cas3 column address strobe we read/write input a0 - a9 address inputs dq0-7, 9-16, 18-25, 27-34 data input/output v cc power (+3.3v) v ss ground nc no connect pd1 - pd7 presence detects pinout pin# name pin# name pin# name pin# name pin# name pin# name 1 v ss 13 a1 25 dq13 37 dq18 49 dq20 61 v cc 2 dq0 14 a2 26 dq14 38 dq19 50 dq21 62 dq32 3 dq1 15 a3 27 dq15 39 v ss 51 dq22 63 dq33 4 dq2 16 a4 28 a7 40 cas0 52 dq23 64 dq34 5 dq3 17 a5 29 nc 41 cas2 53 dq24 65 nc 6 dq4 18 a6 30 v cc 42 cas3 54 dq25 66 pd2 7 dq5 19 nc 31 a8 43 cas1 55 nc 67 pd3 8 dq6 20 nc 32 a9 44 ras0 56 dq27 68 pd4 9 dq7 21 dq9 33 ras3* 45 ras1* 57 dq28 69 pd5 10 v cc 22 dq10 34 ras2 46 nc 58 dq29 70 pd6 11 pd1 23 dq11 35 dq16 47 we 59 dq31 71 pd7 12 a0 24 dq12 36 nc 48 nc 60 dq30 72 v ss 1. * ras1 and ras3 are nc on 4mb so dimm. ordering information part number organization speed dimensions power notes IBM11S1325LP-60t 1m x 32 60ns 2.35 x 1 x .0965 3.3v ibm11s2325lp-60t 2m x 32 60ns 2.35 x 1 x .1496 3.3v discontinued (9/98 - last order; 3/99 last ship)
IBM11S1325LP ibm11s2325lp 1m/2m x 32 so dimm module 75h1720 sa14-4472-01 revised 6/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 3 of 22 block diagram we u1 ras lcas ucas a0 - a9 oe dq dq dq0 - dq7 dq9 - dq16 we u2 ras lcas ucas a0 - a9 oe dq dq dq18 - dq25 dq27 - dq34 we cas0 ras0 cas1 cas2 ras2 a0 - a9 cas3 we u3 ras lcas ucas a0 - a9 oe dq dq dq0 - dq7 dq9 - dq16 we u4 ras lcas ucas a0 - a9 oe dq dq dq18 - dq25 dq27 - dq34 we cas0 ras1 cas1 cas2 ras3 a0 - a9 cas3 applies to both 4mb and 8mb sodimms applies to 8mb sodimm only discontinued (9/98 - last order; 3/99 last ship)
ibm11s2325lp IBM11S1325LP 1m/2m x 32 so dimm module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 4 of 22 75h1720 sa14-4472-01 revised 6/97 truth table function ras cas we row address column address all dq bits standby h x x x x high impedance read l l h row col valid data out early-write l l l row col valid data in edo mode - read: 1st cycle l h ? l h row col valid data out subsequent cycles l h ? l h n/a col valid data out edo mode - write: 1st cycle l h ? l l row col valid data in subsequent cycles l h ? l l n/a col valid data in ras-only refresh l h x row n/a high impedance cas-before- ras refresh h ? l l h x x high impedance hidden refresh read l ? h ? l l h row col data out write l ? h ? l l l ? h row col data in self refresh h ? l l h x x high impedance presence detect pin 1m x 32 2m x 32 -60 -60 pd1 nc nc pd2 v ss v ss pd3 v ss v ss pd4 nc v ss pd5 nc nc pd6 nc nc pd7 v ss v ss 1. nc= open , v ss = gnd discontinued (9/98 - last order; 3/99 last ship)
IBM11S1325LP ibm11s2325lp 1m/2m x 32 so dimm module 75h1720 sa14-4472-01 revised 6/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 5 of 22 absolute maximum ratings symbol parameter rating units notes 3.3 volt v cc power supply voltage -0.5 to + 4.6 v 1 v in input voltage -0.5 to min (v cc + 0.5, 4.6) v1 v out output voltage -0.5 to min (v cc + 0.5, 4.6) v1 t opr operating temperature 0 to +70 c 1 t stg storage temperature -55 to +150c c 1 p d power dissipation 1mx32 0.8 w 1 2mx32 1.5 w 1, 2 i out short circuit output current 50 ma 1 1. stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and device functio nal operation at or above the conditions indicated is not implied. exposure to absolute maximum rating conditions for extended peri - ods may affect reliability. 2. maximum power occurs when all banks are active (refresh cycle). recommended dc operating conditions (t a = 0 to 70 c) symbol parameter 3.3 volt units notes min typ max v cc supply voltage 3.0 3.3 3.6 v 1 v ih input high voltage 2.0 v cc + 0.5 v 1, 2 v il input low voltage -0.5 0.8 v 1, 2 1. all voltages referenced to v ss . 2. v ih may overshoot to v cc + 1.2v for pulse widths of 4.0ns with 3.3 volt. additionally, v il may undershoot to -2.0v for pulse widths 4.0ns. pulse widths measured at 50% points with amplitude measured peak to dc reference. capacitance (t a = 0 to +70 c, v cc = 3.3 0.3v) symbol parameter 1m x 32 max 2m x 32 max units c i1 input capacitance (a0-a9) 35 45 pf c i2 input capacitance (4mb: ras0, 8mb: ras0, 1) 16 16 pf c i2 input capacitance (4mb: ras2, 8mb: ras2, 3) 16 16 pf c i4 input capacitance ( cas) 15 22 pf c i5 input capacitance ( we) 36 50 pf c io input - output capacitance (dq0-dq34) 16 23 pf discontinued (9/98 - last order; 3/99 last ship)
ibm11s2325lp IBM11S1325LP 1m/2m x 32 so dimm module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 6 of 22 75h1720 sa14-4472-01 revised 6/97 dc electrical characteristics (t a = 0 to +70c, v cc = 3.3 0.3v) symbol parameter 1mx32 2mx32 units notes min max min max i cc1 operating current average power supply operating current ( ras, cas, address cycling: t rc = t rc min) 210 210 ma 1, 2, 3 i cc2 standby current (ttl) power supply standby current ( ras = cas 3 v ih ) 24ma i cc3 ras only refresh current average power supply current, ras only mode ( ras cycling, cas 3 v ih : t rc = t rc min) 210 210 ma 1, 3, 4 i cc4 edo mode current average power supply current, fast page mode ( ras = v il , cas, address cycling: t pc = t pc min) 80 80 ma 1, 2, 3 i cc5 standby current (cmos) power supply standby current ( ras = cas = v cc - 0.2v) .2.4ma i cc6 cas before ras refresh current average power supply current, cas before ras mode ( ras, cas, cycling: t rc = t rc min) 210 210 ma 1, 3, 4 i cc7 self refresh current average power supply current during self refresh (cbr cycle with ras 3 t rass (min)) 400 400 m a 4 i i(l) input leakage current input leakage current, any input (0.0 v in (v cc < 6.0v)) all other pins not under test = 0v ras -5 +5 -5 +5 m a cas -5 +5 -10 +10 add & we -10 +10 -20 +20 i o(l) output leakage current (d out is disabled, 0.0 v out v cc ) -5 +5 -10 +10 m a v oh output high level output "h" level voltage (i out = -2ma @ 2.4v) 2.4 2.4 v v ol output low level output "l" level voltage (i out = +2ma @ 0.4v) 0.4 0.4 v 1. i cc1 , i cc3 , i cc4 and i cc6 depend on cycle rate. 2. i cc1 , i cc4 depend on output loading. speci?ed values are obtained with the output open. 3. address can be changed once or less while ras = v il . in the case of i cc4 , it can be changed once or less when cas = v ih . 4. refresh current is speci?ed for one bank discontinued (9/98 - last order; 3/99 last ship)
IBM11S1325LP ibm11s2325lp 1m/2m x 32 so dimm module 75h1720 sa14-4472-01 revised 6/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 7 of 22 ac characteristics (t a = 0 to +70 c, v cc = 3.3v 0.3v) 1. an initial pause of 200 m s is required after power-up followed by 8 ras only refresh cycles before proper device operation is achieved. in case of using the internal refresh counter, a minimum of 8 cas before ras refresh cycles instead of 8 ras only refresh cycles is required. 2. ac measurements assume t t =2ns. 3. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. also, transition times are measured between v ih and v il . 4. when both cas0 & cas1 or cas2 & cas3 go low at the same time, all 16 bits of data are read/written into the device. cas0 & cas1 or cas2 & cas3 ( cas s to the same dram) cannot be staggered within the same read/write cycle. read, write, and refresh cycles (common parameters) symbol parameter -60 units notes min max t rc random read or write cycle time 104 ns t rp ras precharge time 40 ns t cp cas precharge time 10 ns t ras ras pulse width 60 10k ns t cas cas pulse width 10 10k ns t asr row address setup time 0 ns t rah row address hold time 10 ns t asc column address setup time 0 ns t cah column address hold time 10 ns t rcd ras to cas delay time 14 45 ns 1 t rad ras to column address delay time 12 30 ns 2 t rsh ras hold time 10 ns t csh cas hold time 45 ns t crp cas to ras precharge time 5 ns t dzc cas delay time from d in 0ns t t transition time (rise and fall) 2 30 ns 1. operation within the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is specified as a reference point only: if t rcd is greater than the specified t rcd (max) limit, then access time is controlled by t cac . 2. operation within the t rad (max) limit ensures that t rac (max) can be met. t rad (max) is speci?ed as a reference point only: if t rad is greater than the speci?ed t rad (max) limit, then access time is controlled by t aa . discontinued (9/98 - last order; 3/99 last ship)
ibm11s2325lp IBM11S1325LP 1m/2m x 32 so dimm module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 8 of 22 75h1720 sa14-4472-01 revised 6/97 write cycle symbol parameter -60 units notes min max t wcs write command set up time 0 ns 1 t wch write command hold time 10 ns t wp write command pulse width 10 ns t rwl write command to ras lead time 10 ns t cwl write command to cas lead time 10 ns t ds d in setup time 0ns t dh d in hold time 10 ns 1. t wcs is not a restrictive operating parameter. it is included in the data sheet as an electrical characteristic only. if t wcs 3 t wcs (min), the cycle is an early write cycle and the data pin will remain open circuit (high impedance) through the entire cycle. if neither of the above condition is not satisfied, the condition of the data out (at access time) is indeterminate. read cycle symbol parameter -60 units notes min max t rac access time from ras 60 ns 1, 2, 3 t cac access time from cas 15 ns 1, 3 t aa access time from address 30 ns 2, 3 t rcs read command setup time 0 ns t rch read command hold time to cas 0 ns 4 t rrh read command hold time to ras 0 ns 4 t ral column address to ras lead time 30 ns t clz cas to output in low-z 0 ns 3 t cdd cas to d in delay time 15 ns t off output buffer turn-off delay 15 ns 5, 6 1. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 2. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is speci?ed as a reference point only. if t rad is greater than the speci?ed t rad (max.) limit, then access time is controlled by t aa . 3. measured with the speci?ed current load and 100pf at v ol = 0.8v and v oh = 2.0v. 4. either t rch or t rrh must be satis?ed for a read cycle. 5. t off (max) de?nes the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 6. t off is referenced from the rising edge of ras or cas, which ever is last. discontinued (9/98 - last order; 3/99 last ship)
IBM11S1325LP ibm11s2325lp 1m/2m x 32 so dimm module 75h1720 sa14-4472-01 revised 6/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 9 of 22 extended data out cycle symbol parameter -60 units notes min. max. t hcas cas pulse width (edo mode) 10 10k ns t hpc edo mode cycle time (read/write) 25 ns t doh data-out hold time from cas 5 ns t whz output buffer turn-off delay from we 0 10 ns t wpz we pulse width to output disable at cas high 10 ns t cprh ras hold time from cas precharge 35 ns t cpa access time from cas precharge 35 ns 1 t rasp edo mode ras pulse width 60 125k ns 1. measured with the specified current load and 100pf at v ol = 0.8v and v oh = 2.0v. refresh cycle symbol parameter -60 units notes min max t chr cas hold time ( cas before ras refresh cycle) 10 ns t csr cas setup time ( cas before ras refresh cycle) 5ns t wrp we setup time ( cas before ras refresh cycle) 10 ns t wrh we hold time ( cas before ras refresh cycle) 10 ns t rpc ras precharge to cas hold time 5 ns t ref refresh period 128 ms 1 1. 1024 refreshes are required every 128ms. self refresh cycle symbol parameter -60 units notes min. max. t rass ras pulse width during self refresh cycle 100 m s 1 t rps ras precharge time during self refresh cycle 104 ns 1 t chs cas hold time during self refresh cycle -50 ns 1, 2 t chd cas hold time from ras falling during self refresh cycle 350 m s 1, 2 1. when using self refresh mode, the following refresh operations must be performed to ensure proper dram operation: if row addresses are being refreshed in a evenly distributed manner over the refresh interval using cbr refresh cycles, then only one cbr cycle must be performed immediately after exit from self refresh. if row addresses are being refreshed in any other manner (ror - distributed/burst; or cbr-burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from self refresh. 2. if t rass >t chd (min) then t chd applies. if t rass t chd (min) then t chs applies. discontinued (9/98 - last order; 3/99 last ship)
ibm11s2325lp IBM11S1325LP 1m/2m x 32 so dimm module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 10 of 22 75h1720 sa14-4472-01 revised 6/97 read ras v ih v il v ih v il address v ih v il we v ih v il v ih v il d out v oh v ol d in row column valid data out t ras t rp t rc t cas t csh t crp t rah t asc t cah t asr t rad t rcs t dzc t clz t cac t rac hi-z hi-z t rrh : h or l t rcd hi-z t rsh t ral t cal t aa lcas t cdd t rch t off t wrp t wrh note 1 note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. ucas discontinued (9/98 - last order; 3/99 last ship)
IBM11S1325LP ibm11s2325lp 1m/2m x 32 so dimm module 75h1720 sa14-4472-01 revised 6/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 11 of 22 write cycle (early write) t rc ras v ih v il v ih v il address v ih v il we v ih v il v ih v il d out v oh v ol d in row column t ras t rp t rcd t csh t crp t rah t asc t cah t asr t rad t wcs hi-z : h or l valid data in t wch t ds t dh t cas t rsh t wp t wrp t wrh note 1 note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. lcas ucas discontinued (9/98 - last order; 3/99 last ship)
ibm11s2325lp IBM11S1325LP 1m/2m x 32 so dimm module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 12 of 22 75h1720 sa14-4472-01 revised 6/97 extended data out mode read cycle t rp t hcas data out 1 data out 2 we ras row address column 1 column 2 column n t doh t doh t clz t cac v ih v il t asr t rah t asc t asc t cah t cah d out t rasp t cprh t crp t rsh t hcas t hcas t hpc t asc t csh t rad t rcs t cac t cpa t cpa t aa t aa t rac t aa hi-z : h or l t ral v ih v il v ih v il v ih v il v oh v ol t rcd t cp t cp t rrh t rch t wp t cac data out n t off t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional . doing so will facilitate compatibility with future edo drams. t ar t cah lcas ucas discontinued (9/98 - last order; 3/99 last ship)
IBM11S1325LP ibm11s2325lp 1m/2m x 32 so dimm module 75h1720 sa14-4472-01 revised 6/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 13 of 22 extended data out mode read cycle ( we control) t rp data out 1 data out 2 we ras row address column 1 column 2 column n t clz t cac v ih v il t asr t rah t asc t asc t cah t cah t cah d out t rasp t cprh t crp t rsh t hcas t hcas t hpc t asc t csh t rad t rcs t cac t cpa t cpa t aa t aa t rac t aa hi-z : h or l t ral v ih v il v ih v il v ih v il v oh v ol t rcd t cp t cp t rrh t rch t cac data out n t off t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. t hcas t wpz t wpz t rch t rcs t rcs t rch t whz t whz t ar lcas ucas discontinued (9/98 - last order; 3/99 last ship)
ibm11s2325lp IBM11S1325LP 1m/2m x 32 so dimm module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 14 of 22 75h1720 sa14-4472-01 revised 6/97 extended data out mode write cycle t hcas t rp ras row address we column 1 column 2 column n data in 1 data in 2 data in n t asr t rah t cah t wch t dh d in t rasp t rsh t hcas t hcas t hpc t rad t asc t asc t csh t cah t asc t cah t wch t wcs t wch t wcs t wcs t ds t ds t dh t dh t ds : h or l t cwl t rwl t wp t wp t wp v ih v il v ih v il v ih v il v ih v il v ih v il t rcd t cp t cp t crp t wrp note 1 t wrh note 1: implementing we at ras time during a read or write cycle is optional. doing so will facilitate compatibility with future edo drams. lcas ucas discontinued (9/98 - last order; 3/99 last ship)
IBM11S1325LP ibm11s2325lp 1m/2m x 32 so dimm module 75h1720 sa14-4472-01 revised 6/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 15 of 22 hidden refresh cycle (read) ras v ih v il v ih v il address v ih v il we v ih v il v ih v il d out v oh v ol d in row column valid data out t ras t ras t rp t rc t crp t rah t asc t cah t asr t rad t rcs t dzc t cdd t clz t cac t rac hi-z hi-z : h or l t rp t chr rsh t rcd t t rrh t wrp t wrh t rc t ral t off t aa hi-z lcas ucas discontinued (9/98 - last order; 3/99 last ship)
ibm11s2325lp IBM11S1325LP 1m/2m x 32 so dimm module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 16 of 22 75h1720 sa14-4472-01 revised 6/97 hidden refresh cycle (write) ras v ih v il v ih v il address v ih v il we v ih v il v ih v il d out v oh v ol d in row column valid data t ras t ras t rp t rc t crp t rah t asc t cah t asr hi-z : h or l t rp t chr rsh t t ds t dh t wch wcs t t wrp t wrh t rc t wp t rcd lcas ucas discontinued (9/98 - last order; 3/99 last ship)
IBM11S1325LP ibm11s2325lp 1m/2m x 32 so dimm module 75h1720 sa14-4472-01 revised 6/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 17 of 22 self refresh cycle (sleep mode) ras v ih v il v ih v il we v ih v il t rass t rps t crp d out v oh v ol hi-z : h or l t off t cp t csr t wrh t wrp t rpc t chd t chs notes: 1. address is h or l 2. once t rass (min) is provided and ras remains low, the dram will be in self refresh, commonly known as sleep mode. 3. if t rass > t chd (min) then t chd applies. if t rass t chd (min) then t chs applies. lcas ucas discontinued (9/98 - last order; 3/99 last ship)
ibm11s2325lp IBM11S1325LP 1m/2m x 32 so dimm module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 18 of 22 75h1720 sa14-4472-01 revised 6/97 ras only refresh cycle ras v ih v il v ih v il address v ih v il d out v oh v ol row t ras t rp t rc t rah t asr hi-z note: we, d in are h or l t rpc t crp : h or l lcas ucas discontinued (9/98 - last order; 3/99 last ship)
IBM11S1325LP ibm11s2325lp 1m/2m x 32 so dimm module 75h1720 sa14-4472-01 revised 6/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 19 of 22 cas before ras refresh cycle ras v ih v il v ih v il we v ih v il d in v oh v ol t ras t rp d out v oh v ol hi-z : h or l t off hi-z t chr rc t t wrh t wrp t note: address is h or l rpc t cp t cdd t rpc t csr t wrh t wrp t csr lcas ucas discontinued (9/98 - last order; 3/99 last ship)
ibm11s2325lp IBM11S1325LP 1m/2m x 32 so dimm module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 20 of 22 75h1720 sa14-4472-01 revised 6/97 layout drawing note: all dimensions are typical unless otherwise stated. millimeters inches 59.69 2.35 1.27 pitch .050 1.00 width .039 (2x) 0 3.1877 .1255 2.00 .0787 51.66 2.034 44.45 1.750 2.00 min .0787 front 4.00 .157 25.4 17.78 1.80 .0709 1.00 .700 3.80 .1496 max. side (8mb) 1.00 + _ .039 + _ 0.10 .0039 7.96 .331 min. 5.00 .197 2.45 .0965 max. side (4mb) 7.96 1.00 + _ .039 + _ 0.10 .0039 .331 min. 3.175 .125 discontinued (9/98 - last order; 3/99 last ship)
IBM11S1325LP ibm11s2325lp 1m/2m x 32 so dimm module 75h1720 sa14-4472-01 revised 6/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 21 of 22 revision log rev contents of modi?cation 4/96 initial release of combined spec for 1m x 32, 2m x 32. includes -6r speed sort offering. (originally released as spec #s 50h4742 and 50h4743) 6/97 removal of 5.0v, -6rns, and 70ns parts from this specification we for hidden refresh write cycle in the truth table was changed updated currents/power based on dram die revision discontinued (9/98 - last order; 3/99 last ship)
intern ational business machines corp.1998 printed in the united states of america all rights reserved ibm and the ibm logo are registered trademarks of the ibm corporation. this document may contain preliminary information and is subject to change by ibm without notice. ibm assumes no responsibility or liability for any use of the information contained herein. nothing in this document shall operate as an express or implied lice nse or indemnity under the intellectual property rights of ibm or third parties. the products described in this document are not inten ded for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. no warranties of any kind, including, but not limited to, the implied warranties of merchantability or fitness for a particular purpose, are offered in this document . for more information contact your ibm microelectronics sales representative or visit us on world wide web at http://www.chips.ibm.com ibm microelectronics manufacturing is iso 9000 compliant. a discontinued (9/98 - last order; 3/99 last ship)

▲Up To Search▲

Price & Availability of IBM11S1325LP

	To Download IBM11S1325LP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .