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lxt905 universal 10base-t transceiver with 3.3v support datasheet the lxt905 universal 10base-t transceiver is designed for ieee 802.3 physical layer applications. it provides, in a single cmos device, all the active circuitry for interfacing most standard 802.3 controllers to 10base- t media. lxt905 functions include manchester encoding/decoding, receiver squelch and transmit pulse shaping, jabber, link integrity testing, and reversed polarity detection/correction. the lxt905 drives the 10base-t twisted-pair cable with only a simple isolation transformer using a single 3.3v or 5v power supply. integrated filters simplify the design work required for fcc- compliant emi performance. applications product features cable modems hub/switched dedicated lans for 10base-t desktop 10base-t lan adapter boards usb to ethernet converters transparent 3.3 v or 5 v operation integrated filters ? simplifies fcc compliance integrated manchester encoder/decoder 10base-t compliant transceiver automatic polarity correction sqe enable/disable four led drivers full duplex capability power-down mode with tristate available in 28-pin plcc and 32-pin lqfp packages commercial temperature range ( 0 to +70oc) extended temperature range (-40 to +85oc) as of january 15, 2001, this document replaces the level one document order number: 249271-001 lxt905 universal 10base-t transceiver with 3.3v support datasheet . january 2001
datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the lxt905 may contain design defects or errors known as errata which may cause the product to deviate from published specifica tions. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel?s website at http://www.intel.com. copyright ? intel corporation, 2001 *third-party brands and names are the property of their respective owners.
datasheet 3 universal 10base-t transceiver with 3.3v support ? lxt905 contents 1.0 pin assignments and signal descriptions ...................................................... 8 2.0 functional description ...........................................................................................10 2.1 introduction..........................................................................................................10 2.2 controller compatibility modes ...........................................................................10 2.3 transmit function................................................................................................10 2.4 jabber control function ......................................................................................12 2.5 sqe function ......................................................................................................13 2.6 receive function.................................................................................................13 2.7 polarity reverse function ...................................................................................14 2.8 collision detection function................................................................................14 2.9 loopback functions ............................................................................................15 2.9.1 internal loopback...................................................................................15 2.9.2 external loopback/full duplex...............................................................15 2.10 link integrity test function .................................................................................15 3.0 application information .........................................................................................17 3.1 introduction..........................................................................................................17 3.1.1 termination circuitry ..............................................................................17 3.1.2 twisted-pair interface ............................................................................17 3.1.3 rbias pin ..............................................................................................17 3.1.4 crystal information .................................................................................17 3.1.5 magnetic information..............................................................................17 3.2 typical 10base-t application ............................................................................18 3.3 dual network support - 10base-t and token ring...........................................19 3.4 simple 10base-t connection ............................................................................21 4.0 test specifications ..................................................................................................22 4.1 timing diagrams for mode 1(md1 = low, md0 = low) ......................................25 4.2 timing diagrams for mode 2 (md1=low, md0=high) ........................................27 4.3 timing diagrams for mode 3 (md1 = high, md0 = low) ....................................29 4.4 timing diagrams for mode 4 (md1 = high, md0 = high) ...................................31 5.0 mechanical specifications ....................................................................................34
lxt905 ? universal 10base-t transceiver with 3.3v support 4 datasheet figures 1 lxt905 block diagram ......................................................................................... 7 2 lxt905 pin assignments...................................................................................... 8 3 lxt905 tpo output waveform .......................................................................... 10 4 jabber control function...................................................................................... 12 5 sqe function...................................................................................................... 13 6 collision detection function................................................................................ 14 7 link integrity test function ................................................................................. 16 8 intel controller application (mode 2)................................................................... 18 9 lxt905/380c26 interface for dual 10base-t and token ring support (mode 4).............................................................................................................. 20 10 lxt905/mc68en360 interface for full duplex 10base-t (mode 1) ................. 21 11 mode 1 rclk/start-of-frame timing ................................................................ 25 12 mode 1 rclk/end-of-frame timing .................................................................. 26 13 mode 1 transmit timing .................................................................................... 26 14 mode 1 col output timing ............................................................................... 27 15 mode 2 rclk/start-of-frame ............................................................................ 27 16 mode 2 rclk/end-of-frame timing .................................................................. 28 17 mode 2 transmit timing .................................................................................... 28 18 mode 2 col output timing ............................................................................... 29 19 mode 3 rclk/start-of-frame timing ................................................................ 29 20 mode 3 rclk/end-of-frame timing................................................................... 30 21 mode 3 transmit timing .................................................................................... 30 22 mode 3 col output timing ............................................................................... 31 23 mode 4 rclk/start-of-frame timing ................................................................ 31 24 mode 4 rclk/end-of-frame timing .................................................................. 32 25 mode 4 transmit timing .................................................................................... 32 26 mode 4 col output timing ............................................................................... 33 27 lxt905pc package specifications ................................................................... 34 28 LXT905LC package specifications .................................................................... 35
datasheet 5 universal 10base-t transceiver with 3.3v support ? lxt905 tables 1 lxt905 signal descriptions .................................................................................. 8 2 controller compatibility mode options................................................................11 3 loopback modes .................................................................................................15 4 suitable crystals .................................................................................................17 5 absolute maximum values..................................................................................22 6 recommended operating conditions .................................................................22 7 i/o electrical characteristics ...............................................................................22 8 tp electrical characteristics ...............................................................................23 9 switching characteristics ....................................................................................23 10 rclk/start-of-frame timing...............................................................................23 11 rclk/end-of-frame timing................................................................................24 12 transmit timing...................................................................................................24 13 miscellaneous timing..........................................................................................24 14 plastic leaded chip carrier ...................................................................34 15 quad flat package......................................................................................35
lxt905 ? universal 10base-t transceiver with 3.3v support 6 datasheet revision history revision date description 2.7 10/00 change resistor values for figures 7, 8, and 9.
universal 10base-t transceiver with 3.3v support ? lxt905 datasheet 7 figure 1. lxt905 block diagram mode select logic controller compatibility / loopback / link test manchester encoder squelch/ link detect manchester decoder watch-dog timer loopback control pulse shaper & filter collision/ polarity detect/ correct cmo s tx collision logic rx slicer xtal osc rc rc li tclk clki clko ten cd ledl rclk rxd col txd md0 md1 tpop tpon tpip tpin lbk dsqe ledc/fde ledt/pdn ledr d
lxt905 ? universal 10base-t transceiver with 3.3v support 8 datasheet 1.0 pin assignments and signal descriptions figure 2. lxt905 pin assignments table 1. lxt905 signal descriptions lqfp pin # plcc pin # symbol i/o description 13 20 27 28 29 1 22 ? ? ? vcc1 vcc2 vcc3 vcc4 vcc5 ? ? ? ? ? power inputs 1 thru 5. power supply inputs of 3.3v or 5v. 30 31 2 3 clki clko i o crystal oscillator. a 20 mhz crystal must be connected across these pins, or a 20 mhz clock applied at clki with clko left open. 11 12 21 32 15 23 4 ? gnd1 gnd2 gnd3 gnd4 ? ? ? ? ground. 15 lbki loopback . when high, forces internal loopback. disables collision and the transmission of both data and link pulses. pulled low internally 1 . 26 teni transmit enable . enables data transmission and starts the watch-dog timer (wdt). synchronous to tclk. pulled low internally 1 . 37 tclko transmit clock . a 10 mhz clock output. this clock signal should be directly connected to the transmit clock input of the controller. 48 txdi transmit data . input signal containing nrz data to be transmitted on the network. txd should be connected directly to the transmit data output of the controller. pulled low internally 1 . 59 colo collision signal . output that drives the collision detect input of the controller. 1. externally pull-up or pull-down each pin separately using a 10k ?, 1% termination resistor or tie directly to v cc or ground. 2. do not allow this pin to float. if unused, tie high. lbk ten tclk txd col ledc/fde ledt/pdn 25 24 23 22 21 20 19 5 6 7 8 9 10 11 12 13 14 15 16 17 18 4 3 2 1 28 27 26 md0 tpon gnd2 vcc2 tpop dsqe rbias gnd3 clko clki vcc1 tpin tpip md1 ledr ledl cd gnd1 rclk rxd li lbk ten tclk txd col ledc/fde ledt/pdn ledr 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 ledl cd gnd1 gnd2 vcc1 rclk rxd li 9 10 11 12 13 14 15 16 md1 md0 tpon gnd3 vcc2 tpop dsqe rbias 24 23 22 21 20 19 18 17 gnd4 clko clki vcc5 vcc4 vcc3 tpin tpip LXT905LC/le xx xxxxxx xxxxxxxx part # lot # fpo # rev # lqfp lxt905pc/pe xx xxxxxx xxxxxxxx part # lot # fpo # rev # plcc
universal 10base-t transceiver with 3.3v support ? lxt905 datasheet 9 610 ledc/ fde o i led collision or full duplex enable . ledc is an open drain driver for the collision indicator pulls low during collision. led ? on ? (which is low output) time is extended by approximately 100 ms. fde enables full duplex mode (external loopback) if tied low externally. pulled high internally 1 . 711 ledt/ pdn o i led transmit or power down. ledt is an open drain driver for the transmit indicator. led ? on ? (which is low output) time is extended by approximately 100 ms. output is pulled low during transmit. 2 if externally tied low, the lxt905 goes to power down state ( pdn ). in power- down mode, all logic inputs and outputs are tristated. 812 ledro led receive . open drain driver for the receive indicator led. led ? on ? ( i.e. , low output) time is extended by approximately 100 ms. output is pulled low during receive. pulled high internally 1 . 913 ledlo led link . open drain driver for link integrity indicator. output is pulled low during link test pass. pulled high internally 1 . 10 14 cd o carrier detect . an output for notifying the controller that activity exists on the network. 14 16 rclk o receive clock . a recovered 10 mhz clock that is synchronous to the received data and connected to the controller receive clock input. 15 17 rxd o receive data . output signal connected directly to the receive data input of the controller. 16 18 li i link enable . controls link integrity test; enabled when li is high, disabled when li is low. 17 19 rbias i bias circuitry . a 7.5 k ? 1% resistor to ground at this pin controls operating circuit bias. 18 20 dsqe i sqe disable . when dsqe is high, the sqe function is disabled. when dsqe is low, the sqe function is enabled. sqe should be disabled for normal operation in hub/switch/repeater applications. pulled low internally 1 . 19 22 21 24 tpop tpon o o twisted-pair outputs . differential outputs to the twisted-pair cable. the outputs are pre-equalized. 23 24 25 26 mdo mdi i i mode select 0 and 1. mode select pins determine controller compatibility mode in accordance with table 2 . pulled low internally 1 . 25 26 27 28 tpip tpin i i twisted-pair inputs. a differential input pair from the twisted-pair cable. receive filter is integrated on-chip. no external filters are required. table 1. lxt905 signal descriptions (continued) lqfp pin # plcc pin # symbol i/o description 1. externally pull-up or pull-down each pin separately using a 10k ?, 1% termination resistor or tie directly to v cc or ground. 2. do not allow this pin to float. if unused, tie high.
lxt905 ? universal 10base-t transceiver with 3.3v support 10 datasheet 2.0 functional description 2.1 introduction the lxt905 universal 10base-t transceiver performs the physical layer signaling (pls) and media attachment unit (mau) functions as defined by the ieee 802.3 specification. it functions as an integrated pls/mau for use with 10base-t twisted-pair networks. the lxt905 interfaces a back-end controller to a twisted-pair (tp) cable. the controller interface includes transmit and receive clock and nrz data channels, as well as mode control logic and signaling. the twisted-pair interface comprises two circuits: twisted-pair input (tpi) and twisted-pair output (tpo). in addition to the two basic interfaces, the lxt905 contains an internal crystal oscillator and four led drivers for visual status reporting. functions are defined from the back-end controller side of the interface. the lxt905 transmit function refers to data transmitted by the back end to the twisted-pair network. the lxt905 receive function refers to data received by the back end from the twisted-pair network. the lxt905 performs all required functions defined by the ieee 802.3 10base-t mau specification such as collision detection, link integrity testing, signal quality error messaging, jabber control, and loopback. 2.2 controller compatibility modes the lxt905 is compatible with most industry standard controllers including devices produced by advanced micro devices (amd), intel, fujitsu, national semiconductor, seeq, motorola and texas instruments. four different control signal timing and polarity schemes (modes 1 through 4) are required to achieve this compatibility. mode select pins md0 and md1 determine controller compatibility modes as listed in table 2 . refer to the test specifications section for timing diagrams and parameters. 2.3 transmit function the lxt905 receives nrz data from the controller at the txd input as shown in the block diagram, and passes it through a manchester encoder. the encoded data is then transferred to the twisted-pair network (the tpo circuit). the advanced integrated pulse shaping and filtering network produces the output signal on tpon and tpop, shown in figure 3 . the tpo output is pre-distorted and prefiltered to meet the 10base-t jitter template. an internal continuous resistor- capacitor filter is used to remove any high-frequency clocking noise from the pulse shaping figure 3. lxt905 tpo output waveform
universal 10base-t transceiver with 3.3v support ? lxt905 datasheet 11 circuitry. integrated filters simplify the design work required for fcc compliant emi performance. during idle periods, the lxt905 transmits link integrity test pulses on the tpo circuit (if li is enabled and lbk is disabled). table 2. controller compatibility mode options controller mode md1 md0 mode 1 - for motorola mc68en360 or compatible controllers (amd am7990) low low mode 2 - for intel 82596 or compatible controllers 1 low high mode 3 - for fujitsu mb86950, mb86960 or compatible controllers (seeq 8005) 2 high low mode 4 - for ti tms380c26 or compatible controllers high high 1. refer to intel application note 51 (mac interface design guide for intel controllers) when designing with intel controllers. 2. seeq controllers require inverters on clki, lbk, rclk and col.
lxt905 ? universal 10base-t transceiver with 3.3v support 12 datasheet 2.4 jabber control function figure 4 is a state diagram of the lxt905 jabber control function. the lxt905 on-chip watch- dog timer (wdt) prevents the dte from locking into a continuous transmit mode. when a transmission exceeds the time limit, the wdt disables the transmit and loopback functions and activates the col pin. once the lxt905 is in the jabber state, the txd circuit must remain idle for a period of 0.25 to 0.75 seconds before it exits the jabber state. figure 4. jabber control function no output nonjabber output start_xmit_max_timer power on do=active jab xmit=disable lpbk=disable ci=sqe unjab wait start_unjab_timer xmit=disable lpbk=disable ci=sqe do=active ? xmit_max_timer_done do=idle do=idle unjab_ timer_done do=active ? unjab_timer_not_done
universal 10base-t transceiver with 3.3v support ? lxt905 datasheet 13 2.5 sqe function the lxt905 supports the signal quality error (sqe) function as shown in figure 5 . after every successful transmission on the 10base-t network, the lxt905 transmits the sqe signal for 10 bit times (bt) 5bt on the col pin of the device. the sqe can be disabled for repeater/switch applications. when dsqe is set high, the sqe function is disabled. when dsqe is low, the sqe function is enabled. 2.6 receive function the lxt905 receive function acquires timing and data from the twisted-pair network (the tpi circuit). valid received signals are passed through the on-chip filters and manchester decoder then output as decoded nrz data and receive timing on the rxd and rclk pins, respectively. an internal rc filter and an intelligent squelch function discriminate noise from link test pulses and valid data streams. the receive function is activated only by valid data streams above the squelch level with proper timing. if the differential signal at the tpi circuit inputs falls below 85% of the threshold level (unsquelched) for 8 bit times (typical), the lxt905 receive function enters the idle state. the lxt905 automatically corrects reversed polarity on the tpi circuit. figure 5. sqe function xmit=disable sqe_test_timer_done dsqe=1 do=active output idle output detected power on sqe wait test start_sqe_test__wait_timer sqe test start_sqe_test_timer ci=sqe sqe_test__wait_timer_done ? xmit=enable do=idle ? dsqe=0
lxt905 ? universal 10base-t transceiver with 3.3v support 14 datasheet 2.7 polarity reverse function the lxt905 polarity reverse function uses both link pulses and end-of-frame data to determine polarity of the received signal. if link integrity testing is disabled, polarity detection is based only on received data. a reversed polarity condition is detected when eight consecutive opposite receive link pulses are detected without receipt of a link pulse of the expected polarity. reversed polarity is also detected if four consecutive frames are received with a reversed start-of-idle. whenever a correct polarity frame or a correct link pulse is received, these two counters are reset to zero. if the lxt905 enters the link fail state and no valid data or link pulses are received within 96 to 128 ms, the polarity is reset to the default non-flipped condition. polarity correction is always enabled. 2.8 collision detection function a collision is defined as the simultaneous presence of valid signals on both the tpi circuit and the tpo circuit. the lxt905 reports collisions to the back-end via the col pin. if the tpi circuit becomes active while there is activity on the tpo circuit, the tpi data is passed to the back-end over the rxd circuit, disabling normal loopback. figure 6 is a state diagram of the lxt905 collision detection function. figure 6. collision detection function idle power on a collision tpo=txd rxd=tpi col=active output tpo=txd rxd=txd input rxd=tpi ten=active ? tpi=idle ? xmit=enable ten=active ? tpi=active ? xmit=enable a a ten=active ? tpi=active ? xmit=enable ten=active ? tpi=idle ten=idle + xmit=disable ten=idle tpi=idle tpi=active
universal 10base-t transceiver with 3.3v support ? lxt905 datasheet 15 2.9 loopback functions 2.9.1 internal loopback the lxt905 provides standard loopback mode as specified in the ieee specification for the twisted-pair port, as well as a forced internal loopback mode. loopback mode operates in conjunction with the transmit function. data transmitted by the mac is internally looped back within the lxt905 from the txd pin through the manchester encoder/decoder to the rxd pin and returned to the mac. standard loopback mode is disabled when a data collision occurs, clearing the rxd circuit for the tpi data. standard loopback is also disabled during link fail, jabber, and full-duplex states. loopback is always enabled during forced internal loopback mode. 2.9.2 external loopback/full duplex the lxt905 also provides an external loopback test mode for system-level testing. when both ledc/fde and lbk are low, the lxt905 enables external loopback and full-duplex mode. internal loopback circuits, sqe, and collision detection are disabled. refer to table 3 for a summary of loopback and duplex modes. 2.10 link integrity test function figure 7 is a state diagram of the lxt905 link integrity test function. the link integrity test is used to determine the status of the receive side twisted-pair cable. link integrity testing is enabled when li is tied high. when enabled, the receiver recognizes link integrity pulses which are transmitted in the absence of receive traffic. if no serial data stream or link integrity pulses are detected within 50~150 ms, the chip enters a link fail state and disables the transmit and normal loopback functions. the lxt905 ignores any link integrity pulse with interval less than 2~7 ms. the lxt905 remains in the link fail state until it detects either a serial data packet or two or more link integrity pulses. table 3. loopback modes pin settings mode description lbk ledc/ fde low low disable internal loopback. enable external loopback test mode and full-duplex mode. low high standard loopback mode (default). data transmitted by the mac is internally looped back and returned to the mac except during collision. standard loopback is disabled when a data collision occurs, clearing rxd for data on the twisted-pair port. high low not used. high high forced internal loopback. transmit data is looped back on the receive data bus and the twisted-pair port is ignored.
lxt905 ? universal 10base-t transceiver with 3.3v support 16 datasheet figure 7. link integrity test function idle test start_link_loss_timer start_link_test_min_timer power on link test fail reset link_count=0 xmit=disable rcvr=disable lpbk=disable link_loss_timer_done ? tpi=idle ? link_test_rcvd=false tpi=active + (link_test_rcvd=true ? link_test_min_timer_done) link test fail wait xmit=disable rcvr=disable lpbk=disable link_count=link_count + 1 link test fail start_link_test_min_timer start_link_test_max_timer xmit=disable rcvr=disable lpbk=disable link_test_rcvd=false ? tpi=idle tpi=active tpi=active link_test_rcvd=idle ? tpi=idle link test fail extended xmit=disable rcvr=disable lpbk=disable tpi=active + link_count=lc_max link_test_min_timer_done ? link_test_rcvd=true (tpi=idle ? link_test_max_timer_done) + (link_test_min_timer_not_done ? link_test_rcvd=true) tpi=idle ? do=idle
universal 10base-t transceiver with 3.3v support ? lxt905 datasheet 17 3.0 application information 3.1 introduction figures 7 through 9 show typical lxt905 applications. these diagrams group similar pins; they do not portray the actual chip pinout. the controller interface pins; transmit data (txd), transmit clock (tclk) transmit enable (ten), receive data (rxd), receive clock (rclk), collision signal (col) and carrier detect (cd) pins are at the upper left. power and ground pins are at the bottom of each diagram. v cc 1 and v cc 2 use a single power supply with decoupling capacitors installed between the power and ground busses. v cc may be powered by a 5v or 3.3v supply. 3.1.1 termination circuitry several i/o pins are internally pulled-up or pulled-down to keep the signals from floating. it is recommended to hard-wire these pins either high or low. externally pull-up pins (ledt/pdn , ledc/fde, ledr, ledl) and pull-down pins (lbk, ten, txd, dsqe, mdo, mdi) separately using a 10k ? , 1% resistor or tie directly to v cc or ground. 3.1.2 twisted-pair interface the twisted-pair interface (tpop/n and tpip/n) is at the upper right. the i/o pairs have impedance-matching resistors for 100 ? utp, but no external filters are required. 3.1.3 rbias pin the rbias pin sets the levels for the lxt905 output drivers. the lxt905 requires a 7.5k ? , 1% resistor directly connected between the rbias pin and ground. this resistor should be located as close to the device as possible. keep the traces as short as possible and isolated from all other high speed signals. 3.1.4 crystal information based on limited evaluation, table 4 lists some of the suitable crystals. designers should test and validate all crystals before committing to a specific component. 3.1.5 magnetic information the lxt905 requires a 1:1 turns ratio for the receive transformer and a 1:2 turns ratio for the transmit transformer. application note 073 lists transformers suitable for the applications described in this data sheet. designers are advised to test and validate all magnetics before committing to a specific component. table 4. suitable crystals manufacturer part number mtron mp-1 mp-2
lxt905 ? universal 10base-t transceiver with 3.3v support 18 datasheet 3.2 typical 10base-t application figure 8 is a typical lxt905 application. the dte is connected to a 10base-t network through the twisted-pair rj-45 connector. with md0 tied high and md1 grounded, the lxt905 logic and framing are set to mode 2 (compatible with intel 82596 controllers*). connect 20 mhz system clock input at clki. (leave clko open.) the li pin externally controls the link test function. * refer to intel application note 51 (mac interface design guide for intel controllers) when designing with intel controllers. figure 8. intel controller application (mode 2) clko clki txd ten tclk rclk rxd cd col md0 md1 dsqe li lbk ledl ledc/fde ledt/pdn vcc1 vcc2 100 pf 50 ? 1% not connected power down full duplex +5v 10k 10k 10k line status gnd1 gnd2 rbias programming options link test enable loopback enable 82596 back-end/ controller interface 20 mhz system clock clk txd rts txc rxc rxd crs cdt lxt905 50 ? 1% 11.8 ? 1% 11.8 ? 1% 0.1 f 100 pf rj-45 tpin tpip tpon tpop 6 5 4 3 2 1 1 3 16 14 11 9 6 8 1:2 1:1 to 10 base-t twisted-pair network 7.5 k ? 1% 1 1 optional: centertap capacitor may improve emc depending on board layout and system design. 0.1 f
universal 10base-t transceiver with 3.3v support ? lxt905 datasheet 19 3.3 dual network support - 10base-t and token ring figure 9 shows the lxt905 with a texas instruments 380c26 commprocessor. the 380c26 is compatible with mode 4 (md0 and md1 both high). when used with the 380c26, both the lxt905 and a tms38054 token ring transceiver can be tied to a single rj-45 allowing dual network support from a single connector.
lxt905 ? universal 10base-t transceiver with 3.3v support 20 datasheet figure 9. lxt905/380c26 interface for dual 10base-t and token ring support (mode 4) txd ten tclk rclk rxd cd col lbk md0 md1 li ledr ledc/fde ledt/pdn ledl vcc1 vcc2 100 pf 50 ? 1% +5v line status gnd2 gnd3 rbias to ti tms38054 token ring transceiver lxt905 50 ? 1% 11.8 ? 1% 11.8 ? 1% 0.1 f 100 pf rj-45 tpin tpip tpon tpop 6 5 4 3 2 1 1 3 16 14 11 9 6 8 1:2 1:1 to 10 base-t twisted-pair network 7.5 k ? 1% 20 pf 20 mhz clki clko 1 20 pf txd txe txc rxc rxd crs col lbk 380c26 0.1 f gnd1 300 300 300 300 green red red red from ti tms38054 token ring transceiver additional magnetics and switching logic (not shown) are required to implement the dual network solution. 2 optional: centertap capacitor may improve emc depending on board layout and system design. 2 1
universal 10base-t transceiver with 3.3v support ? lxt905 datasheet 21 3.4 simple 10base-t connection figure 10 shows a simple 10base-t application using an lxt905 transceiver and a motorola mc68en360. the mc68en360 is compatible with mode 1 (md0 and md1 both low). figure 10. lxt905/mc68en360 interface for full duplex 10base-t (mode 1) rclk tclk txd rxd ten cd col lbk dsqe ledc/fde md0 md1 ledl vcc1 vcc2 li 100 pf 1 +5v gnd2 gnd3 rbias lxt905 100 ? 11.8 ? 1% 11.8 ? 1% not connected 100 pf rj-45 tpin tpip tpon tpop 6 5 4 3 2 1 1 3 16 14 11 9 6 8 1:2 1:1 to 10 base-t twisted-pair network 7.5 k ? 1% ledc/fde requires an open-collector driver. clki clko clk1-4 clk1-4 txd rxd rts cd cts scc1 0.1 f gnd1 300 ? green mc68en360 20 mhz system clock 10 k ? parallel i/o +5v +5v 1
lxt905 ? universal 10base-t transceiver with 3.3v support 22 datasheet 4.0 test specifications note: the minimum and maximum values in table 5 through table 13 and figure 11 through figure 26 represent the performance specifications of the lxt905 and are guaranteed by test, except where noted by design. minimum and maximum values in table 7 through table 13 apply over the recommended operating conditions specified in table 6 . table 5. absolute maximum values parameter symbol min max units supply voltage v cc -0.3 +6 v ambient operating temperature (commercial) t op 0+70 o c ambient operating temperature (extended) t op -40 +85 o c storage temperature t st -65 +150 o c caution: exceeding these values may cause permanent damage. functional operation under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 6. recommended operating conditions parameter symbol min typ max units recommended supply voltage 1 v cc 3.135 5.0 5.25 v recommended operating temperature (commercial) t op 0 ? +70 o c recommended operating temperature (extended) t op -40 ? +85 o c 1. voltage is with respect to ground unless specified otherwise. table 7. i/o electrical characteristics parameter sym min typ 1 max units test conditions input low voltage 2 v il ?? 0.8 v input high voltage 2 v ih 2.0 ?? v output low voltage v ol ?? 0.4 v i ol = 1.6 ma v ol ?? 10 %v cc i ol < 10 a output low voltage (open drain led driver) v oll ?? 0.7 %v cc i oll = 10 ma output high voltage v oh 2.4 ?? vi oh = 40 a v oh 90 ?? %v cc i oh < 10 a output rise time tclk & rclk cmos ?? 315nsc load = 20 pf ttl ?? 215ns output fall time tclk & rclk cmos ?? 315nsc load = 20 pf ttl ?? 215ns clki rise time (externally driven) ??? 10 ns 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. limited functional tests are performed at these input levels. the majority of functional tests are performed at levels of 0v and 3v. this applies to all inputs except tpip and tpin.
universal 10base-t transceiver with 3.3v support ? lxt905 datasheet 23 clki duty cycle (externally driven) ?? 50/50 40/60 % supply current normal mode i cc ? 40 80 ma idle mode i cc ? 70 100 ma transmitting on tp power down mode i cc ? 0.01 1 a table 8. tp electrical characteristics parameter symbol min typ 1 max units test conditions transmit output impedance z out ? 5 ? ? transmit timing jitter addition 2 ?? 6.4 10 ns 0 line length for internal mau transmit timing jitter added by the mau and pls sections 2, 3 ?? 3.5 5.5 ns after line model specified by ieee 802.3 for 10base-t internal mau receive input impedance z in ? 24 ? k ? between tpip/tpin differential squelch threshold v ds 300 420 585 mv 5 mhz square wave input 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. parameter is guaranteed by design; not subject to production testing. 3. ieee 802.3 specifies maximum jitter additions at 0.5 ns from the encoder, and 3.5 ns from the mau. table 9. switching characteristics parameter symbol minimum typical 1 maximum units jabber timing maximum transmit time ? 20 ? 150 ms unjab time ? 250 ? 750 ms link integrity timing time link loss receive ? 50 ? 150 ms link min receive ? 2 ? 7ms link max receive ? 50 ? 150 ms link transmit period ? 810 24ms 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. table 10. rclk/start-of-frame timing parameter symbol min typ 1 max units decoder acquisition time t data ? 1300 1500 ns cd turn-on delay t cd ? 400 550 ns receive data setup from rclk mode 1 t rds 60 70 ? ns modes 2, 3, and 4 t rds 30 45 ? ns 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. table 7. i/o electrical characteristics parameter sym min typ 1 max units test conditions 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. limited functional tests are performed at these input levels. the majority of functional tests are performed at levels of 0v and 3v. this applies to all inputs except tpip and tpin.
lxt905 ? universal 10base-t transceiver with 3.3v support 24 datasheet receive data hold from rclk mode 1 t rdh 10 20 ? ns modes 2, 3, and 4 t rdh 30 45 ? ns rclk shut off delay from cd assert (mode 3) tsws ? 100 ? ns table 11. rclk/end-of-frame timing parameter type sym mode 1 mode 2 mode 3 mode 4 units rclk after cd off min t rc 51 ? 5bt rcv data through-put delay max t rd 400 375 375 375 ns cd turn-off delay 2 max t cdoff 500 475 475 475 ns receive block out after ten off 3 typical 1 t ifg 550 ?? bt rclk switching delay after cd off typical 1 tswe ?? 120 (80) ? ns 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. cd turnoff delay measured from middle of last bit: timing specification is unaffected by the value of the last bit. 3. blocking of carrier detect is disabled during full duplex operation. table 12. transmit timing parameter symbol minimum typical 1 maximum units ten setup from tclk t ehch 22 ?? ns txd setup from tclk t dsch 22 ?? ns ten hold after tclk t chel 5 ?? ns txd hold after tclk t chdu 5 ?? ns transmit start-up delay t stud ? 350 450 ns transmit through-put delay t tpd ? 338 350 ns 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. table 13. miscellaneous timing parameter symbol minimum typical 1 maximum units col (sqe) delay after ten off 2 t sqed 0.65 ? 1.6 s col (sqe) pulse duration 2 t sqep 500 ? 1500 ns power down recovery time t pdr ? 25 ? ms 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. when sqe is enabled (dsqe is low). table 10. rclk/start-of-frame timing parameter symbol min typ 1 max units 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing.
universal 10base-t transceiver with 3.3v support ? lxt905 datasheet 25 4.1 timing diagrams for mode 1(md1 = low, md0 = low) (figure 11 through figure 14) figure 11. mode 1 rclk/start-of-frame timing 1 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1 0 1 t cd t data tpip/tpin cd rclk rxd t rds t rdh 0 1 0 0 0 1 0 1 0
lxt905 ? universal 10base-t transceiver with 3.3v support 26 datasheet figure 12. mode 1 rclk/end-of-frame timing figure 13. mode 1 transmit timing 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 t rd t cdoff tpip/tpin cd rclk rxd t rc t chel t ehch t chdu ten tclk txd tpo t tpd t dsch t stud
universal 10base-t transceiver with 3.3v support ? lxt905 datasheet 27 4.2 timing diagrams for mode 2 (md1=low, md0=high) (figure 15 through figure 18) figure 14. mode 1 col output timing t sqep t sqed ten col figure 15. mode 2 rclk/start-of-frame 1 0 1 0 1 0 1 1 1 0 1 0 1 t cd t rds t rdh cd rclk rxd t data tpip/tpin 1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 0 note: 1. rxd changes at the rising edge of rclk. the controller is sampled at the falling edge .
lxt905 ? universal 10base-t transceiver with 3.3v support 28 datasheet figure 16. mode 2 rclk/end-of-frame timing figure 17. mode 2 transmit timing 1 0 1 0 1 0 1 0 0 t rd tpip/tpin cd rclk rxd 1 0 1 0 1 0 1 0 0 t cdoff note: 1. rxd changes at the rising edge of rclk. the controller is sampled at the falling edge . t chel t ehch t chdu ten tclk txd tpo t dsch t tpd t stud
universal 10base-t transceiver with 3.3v support ? lxt905 datasheet 29 4.3 timing diagrams for mode 3 (md1 = high, md0 = low) (figure 19 through figure 22) figure 18. mode 2 col output timing t sqed ten col t ifg t sqep note: 1. cd output is disabled for a maximum of 55 bit times after ten turns off. figure 19. mode 3 rclk/start-of-frame timing 1 0 1 0 1 0 1 1 1 0 1 0 1 t rds t rdh t data cd rclk rxd tpip/tpin 1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 t cd t sws recovered from input data stream generated from tclk note: 1. rxd changes at the rising edge of rclk. the controller is sampled at the falling edge.
lxt905 ? universal 10base-t transceiver with 3.3v support 30 datasheet figure 20. mode 3 rclk/end-of-frame timing figure 21. mode 3 transmit timing t rd t cdoff cd rclk rxd t swe recovered clock generated from tclk 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 tpip/tpin note: 1. rsd changes at the rising edge of rclk. the controller is sampled at the falling edge. t chel t ehch t chdu ten tclk txd tpo t stud t dsch t tpd
universal 10base-t transceiver with 3.3v support ? lxt905 datasheet 31 4.4 timing diagrams for mode 4 (md1 = high, md0 = high) (figure 23 through figure 26) figure 22. mode 3 col output timing t sqed ten col t sqep figure 23. mode 4 rclk/start-of-frame timing 1 0 1 0 1 0 1 1 1 0 1 0 1 t cd t data crs rclk rxd tpip/tpin t rds t rdh 1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 note: 1. rxd changes at the falling edge of rclk. the controller is sampled at the rising edge.
lxt905 ? universal 10base-t transceiver with 3.3v support 32 datasheet figure 24. mode 4 rclk/end-of-frame timing figure 25. mode 4 transmit timing 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 t rd tpip/tpin cd rclk rxd t cdoff n ote: 1. rxd changes at the falling edge of rclk. the controller is sampled at the rising edge. t chel t ehch t chdu ten tclk txd tpo t dsch t stud t tpd
universal 10base-t transceiver with 3.3v support ? lxt905 datasheet 33 figure 26. mode 4 col output timing t sqep t sqed ten col
5.0 mechanical specifications figure 27. lxt905pc package specifications table 14. plastic leaded chip carrier dim inches millimeters min max min max a 0.165 0.180 4.191 4.572 a 1 0.090 0.120 2.286 3.048 a 2 0.062 0.083 1.575 2.108 b 0.050 ? 1.270 ? c 0.026 0.032 0.660 0.813 d 0.485 0.495 12.319 12.573 d 1 0.450 0.456 11.430 11.582 f 0.013 0.021 0.330 0.533 28-pin plcc part number lxt905pc (commercial temperature range) part number lxt905pe (extended temperature range) a 2 a d f a 1 c b d 1 d c l
universal 10base-t transceiver with 3.3v support ? lxt905 datasheet 35 figure 28. LXT905LC package specifications e / 2 e d d 1 e e 1 all dimensions in millimeters a 1 a 2 a 0 - 7 0.08/0.20 r. o b m 11/13 8 places o 0 min. o l 1.00 ref. 0.20 min. 0.08 r. min. - h - - c - 32-pin lqfp part number LXT905LC (commercial temperature range) part number lxt905le (extended temperature range) table 15. quad flat package dim. all dimensions in millimeters min. typ. max. notes a------1.60 a 1 0.05 0.10 0.15 a 2 1.35 1.40 1.4 d 9.00 bsc. 5 d 1 7.00 bsc. 6, 7, 8 e 9.00 bsc 5 e 1 7.00 bsc 6, 7, 8 l 0.45 0.60 0.75 m 0.15 --- --- b 0.30 0.37 0.45 9 e 0.80 bsc. notes: 1. all dimensions are in millimeters. 2. this package conforms to jedec publication 95 registration mo-136, variation bc. 3. datum plane -h- located at mold parting line and is coincident with leads where leads exit plastic body at bottom of parting line. 4. measured at seating plane -c-. 5. measured at datum plane -h-. 6. dimensions d1 and e1 do not include mold protrusion. allowable mold protrusion is 0.254 mm. 7. package top dimensions are smaller than bottom dimensions. top of package will not overhang bottom of package. 8. dimension b does not include dambar protrusion. allowable dambar protrusion is no more than 0.08 mm.

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