129 morgan drive, norwood ma 02062 - 1 - voice: (781) 551 - 9450 fax: (781) 440 - 9528 email: sales@apogeeddx.com copyright a pogee technology, inc 2001 january 2002 (all rights reserved) doc #07010002 - 03 ddx multichannel digital audio processor errata a] when using the sample rate converter (src), it is mandatory to apply a valid input signal to the ddx - 4100 prior to unmuting. failure to do so will result in large dc offsets applied to speaker outpu ts which may damage loudspeakers. to ensure proper operation using the s/pdif input, be sure to poll the ?s/pdif status? bit (register 0x77, bit 1 which determines s/pdif lock) indicating a valid input signal prior to unmuting. bit 1 will report logic ? 0? for a valid s/pdif input signal or logic ?1? for an invalid signal. delay unmuting until after a valid signal is detected. to ensure proper operation using the serial i2s inputs or ac97, valid clock signals must be applied to ddx - 4100 pins 3,4 (lrcki/s ync, bicki/bit_clk) prior to unmuting. the ?src status? bit (register 0x77, bit 0 which determines src lock), does not provide a correct indication prior to receiving a valid input signal . the ? src status ? b it 0 will indicate src lock , log ic ?0?, whether or not valid input signals are applied. subsequent to receiving a valid input signal, the ?src status? bit operates as intended , i.e. removing the input signal will cause an out - of - lock indication . b] it is recommended to configure the device using a 24.576mhz crystal . be sure the ?pll_factor? bit in cra is clea red (configuration register a, subaddress 0x5b, bit 7= ?0?). this is the default value following hardware reset (pin 7) being deasserted or writing to the ?reset register? (subaddress 0x00) via i 2 c. the alternate 6.144mhz crystal is not recommended. whe n using the 6.144mhz crystal, difficulties have been observed following power - up which may appear as i 2 c related. these include unexpected muting or failure to un - mute when commanded, poor s/n ratio which improves after power cycling, or high dc output wi th no audio. these operational difficulties can be solved by substituting a 24.576mhz crystal and clearing the pll_factor. c] v dd should be limited to 3.4v maximum for proper operation . ddx - 4100 errata
129 morgan drive, norwood ma 02062 - 2 - voice: (781) 551 - 9450 fax: (781) 440 - 9528 email: sales@apogeeddx.com copyright a pogee technology, inc 2001 january 2002 (all rights reserved) doc #07010002 - 03 d] when using the ddx - 4100 in dual processor configuratio n, there is an operational error when using the combination of i 2 c address = 0011 111x (sa {pin 11} connected to vdd) and serial i 2 s input sdi1 (pin 1). the serial data input sdi1 will not operate per the datasheet in this configuration. using i 2 c addres s = 0011 110x (sa {pin 11} connected to ground) the device operates properly as described in the datasheet. single processor configurations are not affected by this error, provided the sa pin is connected to ground. there are two choices for a corrective a ction. the first choice is to ground sa pin 11 on both ics, causing both ics to have the same i 2 c address = 0011 110x, and use two separate i 2 c clock pins (scl pin 10) from the system microcontroller, one for each ic, to address the two processors indep endently. when communicating with the first processor, the scl signal connected to the second must remain static and vice versa. the advantage is that full functionality is achieved and no other changes are required. the disadvantage is that there is an additional signal required from the system microcontroller. first choice: ground sa on both controllers sda scl 1 scl2 sda sdi1 scl sdi2 sa sda sdi1 scl sdi2 sa
129 morgan drive, norwood ma 02062 - 3 - voice: (781) 551 - 9450 fax: (781) 440 - 9528 email: sales@apogeeddx.com copyright a pogee technology, inc 2001 january 2002 (all rights reserved) doc #07010002 - 03 the second choice is to ground the sdi1 pin (pin 1) on the ddx - 4100 when the sa pin (pin 11) is co nnected to v dd . this means that you cannot use this input disabling l and r outputs on this device and so only the ls and rs surround outputs will be available. second choice: ground sa on one controller for f urther information please contact apogee technology applications engineering. sda scl sda sdi1 scl sdi2 sa sda sdi1 scl sdi2 sa v dd
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