?1 cxl5515m/p e94904-st cmos-ccd 1h delay line for pal description the cxl5515m/p are cmos-ccd delay line ics designed for processing video signals. this ics provide a 1h delay time for pal chroma signals including the external lowpass filter. features single 5v power supply low power consumption built-in peripheral circuit built-in tripling pll circuit center bias mode absolute maximum ratings (ta = 25?) supply voltage v dd +6 v operating temperature topr ?0 to +60 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d cxl5515m 350 mw cxl5515p 480 mw recommended operating range (ta = 25?c) v dd 5v 5% recommended clock conditions (ta = 25?c) input clock amplitude v clk 0.2 to 1.0vp-p (0.4vp-p typ.) clock frequency f clk 4.433619mhz input clock waveform sine wave block diagram and pin configuration (top view) input signal amplitude v sig 500mvp-p (typ.), 575mvp-p (max.) functions 848-bit ccd register clock driver auto bias circuit input center bias circuit sample and hold circuit tripling pll circuit inverted output structure cmos-ccd sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. auto-bias circuit ccd (848 bit) output circuit (s/h 1 bit) bias circuit pll timing circuit clock driver bias circuit a bias circuit b 5 6 7 8 v dd vco out vco in clk 2 3 4 1 in ab out v ss cxl5515m cxl5515p 8 pin sop (plastic) 8 pin dip (plastic)
?2 cxl5515m/p pin description electrical characteristics (ta = 25?, v dd =5v, f clk = 4.433619mhz, v clk = 400mvp-p, sine wave) see ?lectrical characteristics test circuit? 1 2 3 4 5 6 7 8 in ab out v ss clk vco in vco out v dd i o o i i o signal input auto-bias dc output signal output gnd clock input (fsc) vco input vco output (3fsc) 5v power supply >10k 40 to 500 >10k pin no. symbol i/o description impedance supply current low frequency gain frequency response differential gain differential phase s/h pulse coupling s/n ratio i dd gl f r dg dp cp sn 200khz 500mvp-p sine wave 200khz ? ? 4.434mhz 150mvp-p sine wave 5-staircase wave (see note 4.) 5-staircase wave (see note 4.) no signal input 50% white video signal (see note 6.) a 10 15 20 ma 1 a b ? 0 2 db 2 b ?.7 ?.7 2.7 db 3 dc035%4 d c 0 3 5 degree 4 f a 350 mvp-p 5 e d 52 56 db 6 item symbol conditions min. typ. max. unit 12 sw conditions note b ? ? c
?3 cxl5515m/p note 1. this is the ic supply current value during clock and signal input. 2. gl is the output gain of out pin when a 500mvp-p, 200khz sine wave is fed to in pin. gl = 20 log out pin output voltage [mvp-p] [db] 500 [mvp-p] 3. indicates the dissipation at 4.434mhz in relation to 200khz. from the output voltage at out pin when a 150mvp-p, 200khz sine wave is fed to in pin, and from the output voltage at out pin when a 150mvp-p, 4.434mhz sine wave is fed to the same, calculation is made according to the following formula. f r = 20 log out pin output voltage (4.434mhz) [mvp-p] [db] out pin output voltage (200khz) [mvp-p] 4. in fig. below, the differential gain (dg) and the differential phase (dp), are tested with a vector scope when the 5-staircase wave is fed. 5. leakage of internal clock components and related high frequency component to the output signal, during no signal input, is tested. 150mv 1h 64 s 350mv 150mv 500mv test value [mvp-p]
?4 cxl5515m/p 6. s/n ratio during a 50% white video signal input shown in fig. below is tested at the video noise meter, in bpf 100khz to 5mhz, sub carrier trap mode. clock 1h 64 s 175mv 150mv 325mv 400mvp-p (typ.) f sc (4.433619mhz) sine wave
?5 cxl5515m/p v dd vco out vco in clk in ab out v ss cxl5515m/p 0.1 6.8 2200p 0.1 0.1 fsc (4.433619mhz) 400mvp-p sine wave 5v 200khz 500mvp-p sine wave a 200khz 150mvp-p sine wave b 4.434mhz 150mvp-p sine wave c 5-staircase wave d 50% white video signal e f 1 sw1 oscilloscope spectrum analyzer vector scope noise meter b sw2 2.2k +15v c a lpf note1) d bpf note 2) note1) note 2) [db] frequency [hz] 6m 13.3m ? ?0 0 lpf frequency response [db] frequency [hz] 6m 13.3m ? ?0 0 bpf frequency response 50 200 5 6 7 8 2 3 4 1 3 3 electrical characteristics test circuit
?6 cxl5515m/p application circuit v dd vco out vco in clk in ab out v ss cxl5515m/p 0.1 6.8 2200p 0.1 0.1 fsc (4.433619mhz) 400mvp-p sine wave 5v 1 33k 2 3 4 1 5 6 7 8 1 470 56k 1k lpf 5v 2.2k output transistor used npn: 2sc403 7 when vco out (7pin) in use 5v 2.2k 3fsc out 1.8k 2sc403 input transistor used npn: 2sa403 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
?7 cxl5515m/p example of representative characteristics 4.75 supply current vs. supply voltage supply voltage [v] 5 5.25 10 15 20 supply current [ma] ?0 supply current vs. ambient temperature ambient temperature [?] 40 80 10 14 20 supply current [ma] 12 18 16 060 20 4.75 low frequency gain vs. supply voltage supply voltage [v] 5 5.25 ? ? 1 low frequency gain [db] 0 4.75 frequency response vs. supply voltage supply voltage [v] 5 5.25 ? ? 0 frequency response [db] ? low frequency gain vs. ambient temperature ? ? 1 low frequency gain [db] 0 ?0 ambient temperature [?] 40 80 060 20 4.75 differential gain vs. supply voltage supply voltage [v] 5 5.25 0 2 10 differential gain [%] 6 8 4
?8 cxl5515m/p frequency response vs. ambient temperature ? ? 0 frequency response [db] ? ?0 ambient temperature [?] 40 80 060 20 differential gain vs. ambient temperature 0 2 10 differential gain [%] 6 8 4 ?0 ambient temperature [?] 40 80 060 20 frequency response ?0 ? 2 gain [db] ? 10k frequency [hz] 10m 100k 1m ? 0 ?
?9 cxl5515m/p package outline unit : mm cxl5515m cxl5515p m package structure molding compound lead treatment lead material package weight epoxy / phenol resin solder plating 42 alloy 85 1 4 4.4 ?0.1 + 0.3 1.27 0.4 ?0.05 + 0.1 0.12 0?to 10 1.25 ?0.15 + 0.4 0.15 ?0.05 + 0.1 0.10 6.4 0.4 a 0.1 ?0.1 + 0.15 0.5 0.2 5.0 ?0.1 + 0.4 0.1g sop-8p-l03 * sop008-p-0225-a 8pin sop (plastic) detail a sony code eiaj code jedec code sony code eiaj code jedec code package structure package material lead treatment lead material package weight epoxy resin solder plating copper alloy 8pin dip (plastic) 300mil 9.4 ?0.1 + 0.4 2.54 1 4 5 8 1.2 0.15 0.5 0.1 3.0 min 0.5 min 3.7 ?0.1 + 0.4 7.62 6.4 ?0.1 + 0.3 0.25 ?0.05 + 0.1 0?to 15 0.5g dip-8p-01 * dip008-p-0300-a
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