cmos-ccd 1h delay line for pal description the cxl5505m/p are cmos-ccd delay line ics that provide 1h delay time for pal signals including the external low-pass filter. features single 5v power supply low power consumption 100mw (typ.) built-in peripheral circuits built-in quadruple pll circuit functions 1130-bit ccd register clock driver auto-bias circuit input clamp circuit sample-and-hold circuit pll circuit structure cmos-ccd absolute maximum ratings (ta = 25?) supply voltage v dd 6v operating temperature topr ?0 to +60 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d cxl5505m 400 mw cxl5505p 800 mw recommended operating condition (ta = 25?) supply voltage v dd 5 5% v recommended clock conditions (ta = 25?) input clock amplitude v clk 0.3 to 1.0 vp-p (0.5vp-p typ.) clock frequency f clk 4.433619 mhz input clock waveform sine wave input signal amplitude v sig 575mvp-p (max.) (at internal clamp condition) ?1 e90731b7x-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxl5505m/p cxl5505m 14 pin sop (plastic) cxl5505p 14 pin dip (plastic) blook diagram and pin configuration (top view) output circuit (s/h 1bit) clk 1 2 3 4 5 7 8 auto-bias circuit timing circuit ccd (1130bit) clock driver bias circuit (a) bias circuit (b) clamp circuit 6 vco in v dd ab out vg2 vg1 in 9 10 11 12 13 14 v ss v ss vco out v ss v dd pc out pll
? 2 cxl5505m/p * description of pin 3 (vg2) control of input signal clamp condition 0v ........ sync tip clamp condition 5v ........ center bias condition center biased to approx. 2.1v by means of the ic internal resistance (approx. 10k ). in this mode, the input signal is limited to apl 50% and the maximum input signal amplitude is 200mvp-p. c l a m p l e v e l i n p u t w a v e f o r m o u t p u t w a v e f o r m pin description pin no. symbol description impedance 1 2 3 * 4 5 6 7 8 9 10 11 12 13 14 in vg1 vg2 out v ss v ss vco out clk v dd pc out vco in v dd ab v ss signal input gate bias 1 dc output gate bias 2 dc input signal output gnd gnd vco output clock input power supply (5v) phase comparator output vco input power supply (5v) auto-bias dc output gnd (sub) > 10k at no clamp 40 to 500 > 10k 600 to 200k i o i o o i o i o i/o
? 3 cxl5505m/p electrical characteristics (ta = 25 c, v dd = 5v, f clk = 4.433619mhz, v clk = 500mvp-p, sine wave) see "electrical characteristics test circuit" notes (1) this is the ic supply current value during clock and signal input. (2) gl is the output gain of out pin when a 500mvp-p, 200khz sine wave is fed to in pin. gl = 20 log [db] (3) indicates the dissipation at 4.43mhz in relation to 200khz. from the output voltage at out pin when a 150mvp-p, 200khz sine wave is fed to in pin, and from the output voltage at out pin when a 150mvp-p, 4.43mhz sine wave is fed to same, calculation is made according to the following formula. fr = 20 log [db] ? ? a a b c d d f e 11 ? ? 0 0 52 20 0 ? 3 3 56 29 2 0 5 5 350 ma db db % degree mvp-p db 1 2 3 4 4 5 6 unit note max. min. typ. item symbol test condition sw condition 1 a a b a a b a 2 b b c c a d 3 200khz, 500mvp-p, sine wave 200khz ? ? 4.43mhz, 150mvp-p, sine wave 5-staircase wave (see note 4) 5-staircase wave (see note 4) no signal input 50% white video signal (see note 6) i dd gl fr dg dp cp sn supply current low frequency gain frequency response differential gain differential phase s/h pulse coupling s/n ratio out pin output voltage [mvp-p] 500 [mvp-p] out pin otuput voltage (4.43mhz) [mvp-p] out pin output voltage (200khz) [mvp-p]
? 4 cxl5505m/p 0 . 3 t o 1 . 0 v p - p ( 0 . 5 v p - p t y p . ) f s c ( 4 . 4 3 3 6 1 9 m h z ) s i n e w a v e (4) in figure below, differential gain (dg) and differential phase (dp) are tested with a vector scope when the 5-staircase wave is fed. input waveform (5) the internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. (6) s/n ratio during a 50% white video signal input shown in figure below is tested at a video noise meter, in bpf 100khz to 5mhz, sub carrier trap mode. input waveform clock 1 h 6 4 s 1 5 0 m v 3 5 0 m v 5 0 0 m v 1 5 0 m v 1 h 6 4 s 1 5 0 m v 1 7 5 m v 3 2 5 m v t e s t v a l u e ( m v p - p )
? 5 cxl5505m/p electrical characteristics test circuit 1 0 0 0 p 1 a b v d d v c o i n c l k 1 0 0 0 p 8 2 k 3 . 3 0 . 1 c l k f s c ( 4 . 4 3 3 6 1 9 m h z ) 0 . 5 v p - p s i n e w a v e i n v g 2 o u t v s s a b s w 2 1 m 5 v 1 s w 1 c 2 0 0 k h z 5 0 0 m v p - p s i n e w a v e 2 0 0 k h z 1 5 0 m v p - p s i n e w a v e 4 . 4 3 m h z 1 5 0 m v p - p s i n e w a v e 5 - s t a i r c a s e w a v e 5 0 % w h i t e v i d e o s i g n a l a b d e a s w 3 2 . 1 k 9 v b c d o s c i l l o s c o p e s p e c t r u m a n a l y z e r v e c t o r s c o p e n o i s e m e t e r n o t e 1 ) n o t e 2 ) 3 3 l p f b p f n o t e 1 ) l p f f r e q u e n c y r e s p o n s e 0 3 5 0 7 m 1 7 . 7 m f r e q u e n c y [ h z ] [ d b ] n o t e 2 ) b p f f r e q u e n c y r e s p o n s e 7 m 1 7 . 7 m f r e q u e n c y [ h z ] 2 0 0 1 0 0 0 p 0 3 5 0 [ d b ] f 1 2 3 4 5 7 8 6 9 1 0 1 1 1 2 1 3 1 4 v s s p c o u t v d d v s s v g 1 v c o o u t 1 0 0 0 p 3 . 3 0 . 1 1 k
? 6 cxl5505m/p application circuit 1 0 0 0 p 1 0 0 0 p 3 . 3 0 . 1 1 f s c ( 4 . 4 3 3 6 1 9 m h z ) 0 . 5 v p - p s i n e w a v e 1 m 1 3 3 0 k 5 v i n p u t 4 7 0 5 6 0 k 1 k l p f 2 7 p 2 2 0 0 2 2 0 0 5 v 2 2 0 0 1 o u t p u t t r a n s i s t o r u s e d p n p : 2 s a 1 1 7 5 t r a n s i s t o r u s e d n p n : 2 s c 2 7 8 5 d e l a y t i m e 1 9 0 n s ( e x . t h 3 2 8 l n l s - 2 6 2 0 t o u k o u m a d e ) a a ( n o n - i n v e r t e d s i g n a l ) a ( n o n - i n v e r t e d s i g n a l ) a a ( i n v e r t e d s i g n a l ) 1 2 3 4 5 7 6 8 9 1 0 1 1 1 2 1 3 1 4 1 0 0 0 p 3 . 3 0 . 1 8 2 k 1 k 1 . 8 k 7 1 . 8 k 2 s c 4 0 3 5 v 4 f s c w h e n v c o o u t ( p i n 7 ) i n u s e d . application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 7 cxl5505m/p example of representative characteristics 0 2 0 a m b i e n t t e m p e r a t u r e [ c ] s u p p l y c u r r e n t v s . a m b i e n t t e m p e r a t u r e s u p p l y c u r r e n t [ m a ] 2 0 3 0 1 0 8 0 2 0 4 0 6 0 0 2 0 a m b i e n t t e m p e r a t u r e [ c ] l o w f r e q u e n c y g a i n v s . a m b i e n t t e m p e r a t u r e l o w f r e q u e n c y g a i n [ d b ] 0 2 2 8 0 2 0 4 0 6 0 1 1 0 2 0 a m b i e n t t e m p e r a t u r e [ c ] f r e q u e n c y r e s p o n s e v s . a m b i e n t t e m p e r a t u r e f r e q u e n c y r e s p o n s e [ d b ] 2 0 3 8 0 2 0 4 0 6 0 1 0 2 0 a m b i e n t t e m p e r a t u r e [ c ] d i f f e r e n t i a l g a i n v s . a m b i e n t t e m p e r a t u r e d i f f e r e n t i a l g a i n [ % ] 6 1 0 0 8 0 2 0 4 0 6 0 8 4 2 4 . 7 5 s u p p l y v o l t a g e [ v ] l o w f r e q u e n c y g a i n v s . s u p p l y v o l t a g e l o w f r e q u e n c y g a i n [ d b ] 1 2 2 5 . 2 5 5 0 1 4 . 7 5 s u p p l y v o l t a g e [ v ] s u p p l y c u r r e n t v s . s u p p l y v o l t a g e s u p p l y c u r r e n t [ m a ] 2 0 3 0 1 0 5 . 2 5 5
? 8 cxl5505m/p 4 . 7 5 s u p p l y v o l t a g e [ v ] f r e q u e n c y r e s p o n s e v s . s u p p l y v o l t a g e f r e q u e n c y r e s p o n s e [ d b ] 2 0 3 5 . 2 5 5 1 d i f f e r e n t i a l g a i n v s . s u p p l y v o l t a g e d i f f e r e n t i a l g a i n [ % ] 6 1 0 0 8 4 2 4 . 7 5 s u p p l y v o l t a g e [ v ] 5 . 2 5 5 f r e q u e n c y r e s p o n s e f r e q u e n c y [ h z ] g a i n [ d b ] 4 2 6 0 2 1 0 k 1 m 1 0 0 k 1 0 m
? 9 cxl5505m/p package outline unit: mm 1 4 p i n s o p ( p l a s t i c ) 9 . 9 0 . 1 + 0 . 4 0 . 4 5 0 . 1 1 . 2 7 7 . 9 0 . 4 5 . 3 0 . 1 + 0 . 3 6 . 9 0 . 5 0 . 2 0 . 2 0 . 0 5 + 0 . 1 0 . 1 0 . 0 5 + 0 . 2 1 . 8 5 0 . 1 5 + 0 . 4 m 0 . 2 4 s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 / c o p p e r a l l o y s o p - 1 4 p - l 0 1 s o p 0 1 4 - p - 0 3 0 0 0 . 2 g 1 7 1 4 8 0 . 1 5 1 4 p i n d i p ( p l a s t i c ) 1 9 . 2 0 . 1 + 0 . 4 1 2 . 5 4 7 8 1 4 6 . 4 0 . 1 + 0 . 3 0 . 2 5 0 . 0 5 + 0 . 1 7 . 6 2 0 t o 1 5 3 . 7 0 . 1 + 0 . 4 0 . 5 m i n 0 . 5 0 . 1 3 . 0 m i n 1 . 2 0 . 1 5 s o n y c o d e e i a j c o d e j e d e c c o d e d i p - 1 4 p - 0 1 d i p 0 1 4 - p - 0 3 0 0 s i m i l a r t o m o - 0 0 1 - a h p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 / c o p p e r a l l o y 0 . 9 g cxl5505m cxl5505p
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