1 features oscillator has precise duty cycle limit and frequency control 500khz current mode operation automatic feed forward compensation separate latching pwms for cycle-by-cycle current limiting internally trimmed reference with undervoltage lockout switchable second output two high current totem pole outputs input undervoltage lockout with hysteresis low start-up and operating current package options 16l pdip & so wide cs3865c high performance dual channel current mode controller with enable 1 sync 2 3 4 5 6 7 8 c t r t v fb 1 comp 1 sense 1 v out 1 gnd 16 15 14 13 12 11 10 9 v cc v ref enable 2 v fb 2 comp 2 sense 2 v out 2 pwr gnd cs3865c description block diagram december, 2001 - rev. 3 on semiconductor 2000 south county trail, east greenwich, ri 02818 tel: (401)885?600 fax: (401)885?786 n. american technical support: 800-282-9855 web site: www.cherry?emi.com archive device not recommended for new design the cs3865c is a high perfor- mance, fixed frequency, dual cur- rent mode controller. it is used in off-line and dc to dc converter applications and require a mini- mum number of external compo- nents. this integrated circuit fea- tures a unique oscillator for precise duty cycle limit and frequency con- trol, a temperature compensated reference, two high gain error amplifiers, two current sensing comparators, and two high current totem pole outputs ideally suited for driving power mosfets. one of the outputs v out 2 is switchable via the enable 2 pin. also included are protective fea- tures consisting of input and refer- ence undervoltage lockouts each with hysteresis, cycle-by-cycle cur- rent limiting, and a latch for single pulse metering of each output. the cs3865c has a 14v start volt- age and is pin compatible with the mc34065h. + - + - v ref sync oscillator error amp 1 error amp 2 latching pwm 2 latching pwm 1 v ref undervoltage lockout 5.0v ref v cc undervoltage lockout v cc v fb 1 comp 1 enable 2 v fb 2 comp 2 c t r t gnd pwr gnd sense 2 v out 2 sense 1 v out 1
2 electrical characteristics: v cc = 15v, r t = 8.2k ? , c t = 3.3nf, for typical values t a =25?, for min/max values t a is the operating ambient temperature range that applies [note 3]. parameter test conditions min typ max unit absolute maximum ratings total power supply and zener current ........................................................................................... ..............................50ma output current, source or sink (note 1)........................................................................................ ...................................1.0a output energy (capacitive load per cycle) ...................................................................................... .................................5.0 j current sense, enable and voltage .............................................................................................. ........................-0.3 to +5.5v feedback inputs high state (voltage)........................................................................................................... ...............................5.5v low state (reverse current) .................................................................................................... ..................-5.0ma error amp output sink current.................................................................................................. ....................................10ma storage temperature range ...................................................................................................... ..........................-65 to +150? operating junction temperature................................................................................................. ..................................+150? operating ambient temperature.................................................................................................. ...........................0 to +70? lead temperature soldering wave solder (through hole styles only) .................................................................................10 sec. max, 260? peak reflow (smd styles only) ..................................................................................60 sec. max above 183 ?, 230? peak cs3865c reference section reference output voltage, i out =1.0ma, t j =25? 4.9 5.0 5.1 v v ref line regulation 11v v cc 15v 2.0 20.0 mv load regulation 1.0ma i out 10ma 3.0 25.0 mv total output variation over 4.85 5.15 v line, load and temperature output short circuit current 30 100 ma oscillator and pwm sections total frequency variation 11v v cc 15v, t low t a t high 46.5 49.0 51.5 khz over line and temperature frequency change with 11v v cc 15v 0.2 1.0 % voltage duty cycle at each output maximum 46.0 49.5 52.0 % sync input current high state v in =2.4v 170 250 a low state v in =0.8v 80 160 error amplifiers voltage feedback input v out =2.5v 2.42 2.50 2.58 v input bias current v fb =5.0v -0.1 -1.0 a open-loop voltage gain v out =2.0 to 4.0v 65 100 db unity gain bandwidth t j =25? (note 6) 0.7 1.0 mhz power supply rejection ratio v cc =11v to 15v 60 90 db output current source v out =3.0v, v fb =2.3v -0.45 -1.00 ma sink v out =1.2v, v fb =2.7v 2.00 12.00 ma output voltage swing high state, r l =15k to ground, v fb =2.3v 5.0 6.2 v low state, r l =15k to v ref , v fb = 2.7v 0.8 1.1
3 cs3865c parameter test conditions min typ max unit note 1: maximum package power dissipation limits must be observed. note 3: adjust v cc above the start-up threshold before setting to 15v. note 4: this parameter is measured at latch trip point with v fb =0v. note 5: comparator gain is defined as: a v = note 6: these parameters are guaranteed by design but not 100% tested in production. note 7: low duty cycle pulse techniques are used during test to main- tain junction temperature as close to ambient as possible: t low =0? ; t high =+70? ? v compensation ? v current sense current sense section current sense input (notes 4 and 5) 2.75 3.00 3.25 v/v voltage gain maximum current sense (note 4) 430 480 530 mv input threshold input bias current -2.0 -10.0 a propagation delay current sense input to output (n ote 6) 150 300 ns output 2 enable pin enable pin voltage high state output 2 enabled 3.5 v ref v low state output 2 disabled 0.0 1.5 v low state input current v il = 0v 100 250 400 a drive outputs output voltage low state i sink =20ma 0.1 0.4 v i sink =200ma 1.6 2.5 v high state i source =20ma 13.0 13.5 v i source =200ma 12.0 13.4 v output voltage with v cc =6.0v, i sink =1.0ma 0.1 1.1 v uvlo activated output voltage rise time c l =1.0nf (note 6) 28 150 ns output voltage fall time c l =1.0nf (note 6) 25 150 ns undervoltage lockout section start-up threshold cs3865c 13 14 15 v minimum operating voltage 9.0 10.0 11.0 v after turn-on hysteresis 4v total device start-up current v cc =12v 0.6 1.0 ma operating current (note 7) 20 25 ma power supply zener voltage i cc =30ma 15.5 17.0 19.0 v electrical characteristics: v cc = 15v, r t = 8.2k ? , c t = 3.3nf, for typical values t a =25?, for min/max values t a is the operating ambient temperature range that applies [note 3].
4 cs3865c package pin description package pin # pin symbol function typical performance characteristics 100pf 1.0nf 10k 30k 50k 100k 300k 500k 1.0m f osc oscillator frequency (hz) 4.0 6.0 8.0 10 12 14 16 r t timing resistor (k ? ) t a =25 c 2 .2 n f 3.3nf 5.0nf c t =10nf v cc = 15v 220pf 330pf 500pf 10k 30k 50k 100k 300k 500k 1.0m f osc oscillator frequency (hz) 38 40 42 44 46 48 50 maximum duty cycle (%) v cc = 15v r t = 4.0k ? to 16k ? c l = 15pf t a = 25 c out 2 out 1 max. output duty cycle vs. oscillator frequency timing resistor vs. oscillator frequency 10k 100k 1.0k 10k 100k 1.0m 10m f, frequency (hz) -20 0 20 40 60 80 100 a vol , open-loop voltage gain (db) v cc = 15v v o = 1.5v to 2.5v r l = 100k ? t a = 25 c gain phase 180 150 120 90 60 30 0 phase margin (degrees) 0 1.0 2.0 3.0 4.0 5.0 7.0 error amp output voltage (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 vth, current sense input threshhold (v) 6.0 v cc = 15v t a = 125 c t a = 25 c t a = -55 c current sense input threshold vs. error amp output voltage error amp open-loop gain & phase vs. frequency 16 l pdip & so wide 1 sync a p ositive going pulse applied to this input will synchronize the oscillator. a dc voltage within the range of 2.4v to 5.5v will inhibit the oscillator. 2c t timing capacitor c t connects pin to ground setting oscillator fre- quency. 3r t resistor r t connects to ground setting the charge current for c t . its value must be between 4.0k and 16k. 4v fb 1 the inverting input of error amplifier 1. normally it is connected to the switching power supply output. 5 comp 1 the output of error amplifier 1, for loop compensation. 6 sense 1 output 1 pulse by pulse current limit. 7v out 1 drives the power switch at output 1. 8 gnd logic ground 9 pwr gnd power ground. power device return is connected to this pin. 10 v out 2 drives the power switch at output 2. 11 sense 2 output 2 pulse by pulse current limit. 12 comp 2 output of error amplifier 2, for loop compensation. 13 v fb 2 inverting input of error amplifier 2. normally it is connected to the switching power supply output. 14 enable 2 output 2 disable. a logic low at this pin disables v out 2 . 15 v ref 5.0v reference output. it can source current in excess of 30ma. 16 v cc the positive supply of the ic.
5 the cs3865c is a high performance, fixed frequency, dual channel current mode pwm controller specifically designed for off-line and dc to dc converter applications. it offers the designer a cost effective solution with minimal external components where independent regulation of two power converters is required. each channel contains a high gain error amplifier, current sensing comparator, pulse width modulator latch, and totem pole output driver. the oscillator, reference, and undervoltage lockout circuits are common to both channels. the oscillator uses precise frequency and duty cycle con- trol. the frequency is programmed by the values r t and c t . capacitor, c t , is charged and discharged by an equal magnitude internal current source and sink, generating a symmetrical 50 percent duty cycle waveform at c t . the oscillator peak and valley thresholds are 3.5v and 1.6v respectively. the source/sink current magnitude is con- trolled by resistor r t . for proper operation over tempera- ture range, its value should be between 4.0k ? and 16k ? . as c t charges and discharges, an internal blanking pulse is generated that alternately drives the inputs of the upper and lower nor gates high. this, in conjunction with a precise amount of delay time introduced into each chan- nel, produces well defined non-overlapping output duty cycles. the second output, v out 2 is enabled while c t is charging, and the primary is enabled during the discharge. even at 500khz, each output is capable of approximately 44% duty cycle, making this controller suitable for high frequency power conversion applications. in many noise sensitive applications, it may be necessary to synchronize the converter with an external system clock. this can be accomplished by applying an external clock signal. for reliable synchronization, the oscillator fre- quency should be set about 10% slower than the clock fre- quency. the rising edge of the clock signal applied to sync, terminates c t ? charging and v out 2 ? conduction. by tailoring the clock waveform symmetry, accurate duty cycle clamping of either output can be achieved. each channel contains a fully-compensated error amplifi- er. the output and inverting input nodes are accessible. the amplifier features a typical dc voltage gain of 100 db, and a unity gain bandwidth of 1.0 mhz with 71 degrees of phase margin. the non-inverting input is internally biased at 2.5v. the converter output voltage is typically divided down and monitored by the inverting input through a resistor divider. the maximum input bias current is -1.0 a which will cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider resistance. error amplifier oscillator operating description cs3865c typical performance characteristics: continued 0 20 40 60 80 100 120 i ref , reference source current (ma) -24 -20 -16 -12 -8.0 -4.0 0 ? v ref , reference voltage (mv) v cc = 15v t a = ?5 c t a = 125 c t a = 25 c -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c) i sc , reference short circuit current (ma) 120 100 80 60 reference short circuit current vs. temperature reference voltage change vs. source current source saturation (load to ground) v cc =15v 80 s pulsed load 120hz rate t a =25 c t a = ?5 c t a = ?5 c t a =25 c sink saturation (load to v cc ) gnd 0 200 400 600 800 output load current (ma) v sat , output saturation voltage (v) v cc 0 -1.0 -2.0 2.0 1.0 0 0 4.0 8.0 12 16 20 v cc, supply voltage (v) 0 8.0 16 24 32 r t =8.2k ? c t =3.3nf v fb 1.2=0v current sense 1.2=0v t a =25 c i cc, supply current (ma) supply current vs. supply voltage cs3865c output saturation voltage vs. load current
6 the error amp is compensated externally thru the v fb and comp pins. its output voltage is offset by two diode drops ( 1.4v) and divided by three before it connects to the inverting input of the current sense comparator. this guarantees that both outputs are disabled when the error amplifier output is at its lowest state which occurs when the power supply is operating at light or no-load condi- tions, or at the beginning of a soft-start interval. the minimum allowable error amplifier feedback resis- tance is limited by the amplifier? source current capability (0.5 ma) and the output voltage (v oh ) required to reach the current sense comparator 0.5v clamp level with the error amplifier inverting input at ground. this condition happens during initial system start up or when the sensed output is shorted: r f(min) = 5800 ? the cs3865c operates as a current mode controller. output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the error amplifier output. thus the error signal controls the peak inductor current on a cycle-by-cycle basis. the current sense comparator-pwm latch combination ensures that only a single pulse appears at the drive output (v out ) during any given oscil- lator cycle. the current is converted to a voltage by con- necting a sense resistor r sense in series with the source of output switch q1 and ground. this voltage is monitored through the sense 1,2 pins and compared to a voltage derived from the error amp output. the peak current under normal operating conditions is controlled by the voltage at comp where: i pk = abnormal operating conditions occur when the power supply output is overloaded or if output voltage is too high. under these conditions, the current sense compara- tor threshold will be internally clamped to 0.5v. therefore the maximum peak switch current is: i pk(max) = erratic operation due to noise pickup can result if there is an excessive reduction of the ipk (max) clamp voltage. a narrow spike on the leading edge of the current wave- form can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. the addition of an r c filter on the current sense input reduces this spike to an acceptable level. two undervoltage lockout comparators have been incor- porated to guarantee that the ic is fully functional before the output stages are enabled. power supply terminal (v cc ) and the reference output (v ref ) are monitored by separate comparator. each has built-in hysteresis to pre- vent erratic output behavior as their respective thresholds are crossed. the upper and lower thresholds of the v cc comparator are 14v and 10v respectively. the v ref comparator disables the drive outputs until the internal circuitry is functional. this comparator has upper and lower thresholds of 3.6v and 3.4v. a 17v zener is con- nected as a shunt regulator from v cc to ground to protect the ic and power mosfet gate from excessive voltage. the guaranteed minimum operating voltage after turn-on is 11v. each channel contains a single totem-pole output stage that is specifically designed for direct drive of power mosfet?. the outputs have up to 1.0a peak current capability and have a typical rise and fall time of 28 ns with a 1.0nf load. internal circuitry has been added to keep the outputs in active pull-down mode whenever an undervoltage lockout is active, eliminating the need for an external pull-down resistor. although the outputs are optimized for mosfet?, they can easily supply the negative base current required by bipolar npn transistors for enhanced turn-off. since the outputs do not contain internal current limits an external series resistor will be required to prevent the peak output current from exceeding the 1.0a maximum rating. the sink saturation (v ol ) is less than 0.4v at 100ma. a separate ground pin, pwr gnd, is provided. properly implemented, will significantly reduce the level of switch- ing transient noise imposed on the control circuitry. this becomes important when the i pk(max) clamp level is reduced. this input is used to switch v out 2 . v out 1 is used to control circuitry that runs continuously, e.g. volatile memory, the system clock, or a remote controlled receiver. v out 2 out- put can control the high power circuitry that is turned off when not needed. the 5.0v bandgap reference is trimmed to 2.0% toler- ance. the reference has short circuit protection and is capable of sourcing 30ma for powering any additional external circuitry. voltage reference enable 2 outputs and power ground undervoltage lockout 0.5v r sense v(comp) ?1.4v 3r sense current sense comparator and pwm latch 3 x 0.5v + 1.4v 0.5ma operating description continued cs3865c
7 high frequency circuit layout techniques are imperative to prevent pulse-width jitter. this is usually caused by exces- sive noise pick-up imposed on the current sense and volt- age feed-back inputs. noise immunity can be improved by lowering circuit impedances at these points. the printed circuit board layout should contain a ground plane with low current signal and high current switch and output grounds returning on separate paths back to the input fil- ter capacitor. ceramic bypass capacitors (0.1 f) connected directly to v cc and v ref may be required to improve noise filtering. they provide a low impedance path for filtering the high frequency noise. all high current loops should be kept as short as possible using heavy copper runs. the error amp compensation circuitry and the converter out- put voltage-divider should be located close to the ic and as far as possible from the power switch and other noise generating components. design considerations operating description: continued + - + - + - + + + + - + - + - r t c t v fb 1 reference regulator v ref uvlo 3.4v 14v 2.5v r r 20k ? v ref sync 1.0ma 2r 0.5v 250 a r 1.0ma 2r error amp 2 comp 1 enable 2 v fb 2 comp 2 gnd pwr gnd r 0.5v current sense comparator 1 current sense comparator 1 r s q r s r pwm latch 2 pwm latch 1 v cc uvlo v cc 17v v in v out 1 v out 2 sense 1 q1 q2 r sense 1 sense 2 r sense 2 + - + - error amp 1 v out 1 v out 2 c out 2 c out 1 5.0v q oscillator internal bias c f1 + l 1 d 1 l 2 d 2 + + c f2 r fb 1 r fb 2 r fb 3 r fb 4 v out 2 v out 1 dual boost regulator applications diagram cs3865c sync c t latch 1 ?et?input comp 1 sense 1 v out 1 latch 1 ?eset?input enable 2 latch 2 ?et?input comp 2 sense 2 latch 2 ?eset?input v out 2 0v timing diagram
8 thermal data 16 lead 16 lead pdip so r jc typ 42 23 c/w r ja typ 80 105 ?/w d lead count metric english max min max min 16l pdip 19.69 18.67 .775 .735 16l so 10.50 10.10 .413 .398 package specification package dimensions in mm (inches) ordering information package thermal data cs3865c part number description cs3865cgn16 16l pdip cs3865cgdw16 16l so wide cs3865cgdwr16 16l so wide (tape & reel) on semiconductor and the on logo are trademarks of semiconductor components industries, llc (scillc). on semiconductor reserves the right to make changes without further notice to any products herein. for additional infor- mation and the latest available information, please contact your local on semiconductor representative. ?semiconductor components industries, llc, 2000 archive device not recommended for new design 1.27 (.050) bsc 7.60 (.299) 7.40 (.291) 10.65 (.419) 10.00 (.394) d 0.32 (.013) 0.23 (.009) 1.27 (.050) 0.40 (.016) ref: jedec ms-013 2.49 (.098) 2.24 (.088) 0.51 (.020) 0.33 (.013) 2.65 (.104) 2.35 (.093) 0.30 (.012) 0.10 (.004) surface mount wide body (dw); 300 mil wide plastic dip (n); 300 mil wide 0.39 (.015) min. 2.54 (.100) bsc 1.77 (.070) 1.14 (.045) d some 8 and 16 lead packages may have 1/2 lead at the end of the package. all specs are the same. .203 (.008) .356 (.014) ref: jedec ms-001 3.68 (.145) 2.92 (.115) 8.26 (.325) 7.62 (.300) 7.11 (.280) 6.10 (.240) .356 (.014) .558 (.022)
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