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ltc2859/LTC2861 1 285961fb 20mbps rs485 transceivers with integrated switchable termination the ltc ? 2859 and LTC2861 are low power, 20mbps rs485/422 transceivers operating on 5v supplies. the receiver includes a logic-selectable 120 termination, one-eighth unit load supporting up to 256 nodes per bus, and a failsafe feature that guarantees a high output state under conditions of ? oating or shorted inputs. the driver features a logic-selectable low-emi 250kbps operating mode, and maintains a high output impedance over the entire common mode range when disabled or when the supply is removed. excessive power dissipation caused by bus contention or a fault is prevented by current limiting all outputs and by a thermal shutdown. enhanced esd protection allows the ltc2859 and LTC2861 to withstand 15kv (human body model) on the transceiver interface pins without latchup or damage. low power rs485/rs422 transceiver level translator backplane transceiver integrated, logic-selectable 120 termination resistor 20mbps max data rate no damage or latchup to esd: 15kv hbm high input impedance supports 256 nodes 250kbps low-emi mode guaranteed failsafe receiver operation over the entire common mode range current limited drivers and thermal shutdown delayed micropower shutdown (5a max) power up/down glitch-free driver outputs low operating current (900a max in receive mode) meets all tia/eia-485-a speci? cations available in 10-pin 3mm 3mm dfn, 12-pin 4mm 3mm dfn and 16-pin ssop packages ltc2859 at 20mbps part number duplex package ltc2859 half dfn-10 LTC2861 full ssop-16, dfn-12 typical application features applications description product selection guide l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 285961 ta02 20ns/div 2v/div di yCz y z re te ro de di slo r d 2859/61 ta01 ltc2859 120 re ro te de di slo r d ltc2859 120 re ro te de di slo r d ltc2859 120
ltc2859/LTC2861 2 285961fb supply voltage (v cc ) ................................... ?0.3v to 7v logic input voltages ( re, de, di, te, slo ) ... ?0.3v to 7v interface i/o: a, b, y, z ...................................... (v cc ?15v) to +15v (a-b) or (b-a) with terminat or enabled .................6v receiver output voltage (ro) ........ ?0.3v to (v cc +0.3v) (note 1) operating temperature (note 4) ltc2859c, LTC2861c .............................. 0c to 70c ltc2859i, LTC2861i ............................. ?40c to 85c storage temperature range ................... ?65c to 125c lead temperature (soldering, 10 sec) gn package ...................................................... 300c top view dd package 10-lead ( 3mm 3mm ) plastic dfn 10 9 6 7 8 4 5 3 2 1 v cc b a slo gnd ro re de di te 11 exposed pad (pin 11) pcb gnd connection t jmax = 125c,
ltc2859/LTC2861 3 285961fb the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c, v cc = 5v unless otherwise noted (note 2). symbol parameter conditions min typ max units driver |v od | differential driver output voltage r = , i o = 0ma, v cc = 4.5v (figure 1) r = 27 (rs485), v cc = 4.5v (figure 1) r = 50 (rs422), v cc = 4.5v (figure 1) 1.5 2.0 v cc v cc v cc v v v 6 |v od | change in magnitude of driver differential output voltage for complementary output states r = 27 or r = 50 (figure 1) 0.2 v v oc driver common mode output voltage r = 27 or r = 50 (figure 1) 3.0 v 6 |v oc | change in magnitude of driver common mode output voltage for complementary output states r = 27 or r = 50 (figure 1) 0.2 v i ozd driver three-state (high impedance) output current on y and z de = ov, v o = C7v, +12v (LTC2861 only) 10 a i osd maximum driver short-circuit current C7v (y or z) 12 (figure 2) 120 250 ma receiver i in2 receiver input current (a, b) de = te = 0v, v cc = 0v or 5v, v a or v b = 12v, other at 0v 125 a de = te = 0v, v cc = 0v or 5v, v a or v b = C7v, other at 0v C100 a v th receiver differential input threshold voltage C7v v cm 12 0.2 v 6 v th receiver input hysteresis v cm = 0v 25 mv v oh receiver output high voltage i 0 = C4ma, v id = 200mv, v cc = 4.5v 2.4 v v ol receiver output low voltage i 0 = 4ma, v id = C200mv, v cc = 4.5v 0.4 v i ozr receiver three-state (high impedance) output current on ro re = 5v, 0v v o v cc 1 a r in receiver input resistance re = 5v or 0v, de = te = 0v C7v v a = v b 12v 96 125 k r term receiver input terminating resistor te = 5v, v ab = 2v, v b = C7, 0, 10v (figure 7) 108 120 156 logic v ih logic input high voltage de, di, re , te, slo , v cc = 4.5v 2v v il logic input low voltage de, di, re , te, slo , v cc = 4.5v 0.8 v i in1 logic input current de, di, re , te, slo 010 a supplies i shdn supply current in shutdown mode de = 0v, re = v cc , te = 0v 05 a i ccr supply current in receive mode no load, de = 0v, re = 0v, te = 0v 540 900 a i cct supply current in transmit mode no load, de = v cc , re = v cc , slo = v cc , te = 0v 630 1000 a i ccts supply current in transmit slo mode no load, de = v cc , re = v cc , slo = 0v, te = 0v 670 1100 a i ccl supply current in loopback mode (both driver and receiver enabled) no load, de = v cc , re = 0v, slo = v cc , te = 0v 660 1100 a i ccrt supply current in termination mode de = 0v, re = v cc , te = v cc , slo = v cc 640 1180 a electrical characteristics
ltc2859/LTC2861 4 285961fb note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime.. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to device ground unless otherwise speci? ed. note 3: maximum data rate is guaranteed by other measured parameters and is not tested directly. symbol parameter conditions min typ max units driver in normal mode ( slo high) f max maximum data rate note 3 20 mbps t plhd , t phld driver input to output r diff = 54, c l = 100pf (figure 3) 10 50 ns 6 t pd driver input to output difference |t plhd -t phld | r diff = 54, c l = 100pf (figure 3) 16 ns t skewd driver output y to output z r diff = 54, c l = 100pf (figure 3) 16 ns t rd , t fd driver rise or fall time r diff = 54, c l = 100pf (figure 3) 4 12.5 ns t zld , t zhd , t lzd , t hzd driver enable or disable time r l = 500, c l = 50pf, re = 0 (figure 4) 70 ns t zhsd , t zlsd driver enable from shutdown r l = 500, c l = 50pf, re = v cc (figure 4) 8s t shdn time to shutdown (de = , re = v cc ) or (de = 0, re b ) (figure 4) 100 ns driver in slo mode ( slo low) f maxs maximum data rate note 3 250 kbps t plhds, t phlds driver input to output r diff = 54, c l = 100pf (figure 3) 0.95 1.5 s 6 t pds driver input to output difference |t plhr -t phlr | r diff = 54, c l = 100pf (figure 3) 50 500 ns t skewds driver output a to output b r diff = 54, c l = 100pf (figure 3) 200 500 ns t rds, t fds driver rise or fall time r diff = 54, c l = 100pf (figure 3) 0.9 1.5 s t zhds, t zlds driver enable time r l = 500, c l = 50pf, re = 0 (figure 4) 300 ns t lzds, t hzds driver disable time r l = 500, c l = 50pf, re = 0 (figure 4) 70 ns t zhsds, t zlsds driver enable from shutdown r l = 500, c l = 50pf, re = v cc (figure 4) 8s t shdns time to shutdown (de = 0, re = b ) or (de = , re = v cc ) (figure 4) 500 ns receiver t plhr , t phlr receiver input to output c l = 15pf, v cm = 1.5v, |v ab | = 1.5v, t r and t f < 4ns (figure 5) 50 70 ns t skewr differential receiver skew |t plhr -t phlr | c l = 15pf (figure 5) 16 ns t rr , t fr receiver output rise or fall time c l = 15pf (figure 5) 3 12.5 ns t zlr , t zhr , t lzr , t hzr receiver enable/disable r l = 1k, c l =15pf, de = v cc (figure 6) di = 0 or v cc 50 ns t zhsr , t zlsr receiver enable from shutdown r l = 1k, c l = 15pf, de = 0v (figure 6) di = 0 or v cc 8s t rten , t rtz termination enable or disable time v b = 0v, v ab = 2v, re = v cc , de = 0v (figure 7) 100 s the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c, v cc = 5v, t e = 0 unless otherwise noted (note 2). note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may result in device degradation or failure. switching characteristics
ltc2859/LTC2861 5 285961fb figure 1. driver dc characteristics figure 2. driver output short-circuit current figure 4. driver enable and disable timing measurement figure 3. driver timing measurement test circuits gnd or v cc + v oc C r r z y gnd or v cc di driver + v od C C7v to +12v z y di driver i osd + C 2859/61 f01-2 1/2 v o t skewd , t skewds t plhd , t plhds t phld , t phlds t rd , t rds t fd , t fds v o ov v cc r diff c l c l z y y, z di (y-z) 2859/61 f03 driver 00 90% 10% 90% 10% di 1/2 v cc 1/2 v cc 1/2 v cc t zld , t zlds , t zlsd , t zlsds t zhd , t zhds , t zhsd , t zhsds t lzd , t lzds 0.5v 0.5v t hzd , t hzds, t shdn, t shdns v o ov v cc v cc gnd or v cc v cc or gnd r l r l c l c l z y de v cc or gnd v ol v oh y or z de z or y ov 2859/61 f04 di driver
ltc2859/LTC2861 6 285961fb figure 5. receiver propagation delay measurements figure 6. receiver enable/disable time measurements figure 7. termination resistance and timing measurements test circuits 1/2 v cc t plhr t skewr = t plhr C t phlr t phlr t rr t fr 1/2 v cc v o v ab C v ab v cc c l v cm v ab /2 v ab /2 b a ro a-b 2859/61 f05 receiver 90% 10% 90% 10% 0v 0v ro 1/2 v cc 1/2 v cc v o 1/2 v cc t zlr , t zlsr t zhr , t zhsr t lzr 0.5v 0.5v t hzr 0v v cc v cc r l ro c l re v cc or gnd v ol v oh ro re ro 0v 2859/61 f06 b a v cc or 0v di = 0v or v cc 0v or v cc receiver t rten t rtz v cc b a i a te 2859/61 f07 receiver 90% 10% 0v te + C + C v ab v b r term = i a v ab 1/2 v cc ro
ltc2859/LTC2861 7 285961fb receiver skew vs temperature driver skew vs temperature driver propagation delay vs temperature r term vs temperature driver output low/high voltage vs output current driver differential output voltage vs temperature receiver propagation delay vs temperature supply current vs data rate t a = 25c, v cc = 5v, unless otherwise noted. receiver output voltage vs output current (source and sink) typical performance characteristics temperature (c) C40 receiver skew (ns) 0 1 040 80 120 285961 g01 2 C20 20 60 100 v ab = 1.5v c l = 15pf temperature (c) C40 0 driver skew (ns) C1 1 2 040 80 120 285961 g02 3 C20 20 60 100 r diff = 54 c l = 100pf slo = v cc temperature (c) C40 driver prop delay (ns) 80 285961 g03 040 C20 100 20 60 120 12 14 16 10 8 6 4 18 r diff = 54 c l = 100pf slo = v cc temperature ( c ) C40 resistance () 115 125 120 285961 g04 105 95 0 40 80 C20 20 60 100 135 110 120 100 130 output current (ma) 010 0 output voltage (v) 2 5 20 40 50 285961 g05 1 4 3 30 60 70 v oh v ol temperature ( c ) C40 output voltage (v) 3 4 5 20 60 120 285961 g06 2 1 0 C20 0 40 80 100 r = 54 r = 100 r = output current (ma) 0 output voltage (v) 3 4 5 4 285961 g07 2 1 0 1 2 3 5 sink source temperature ( c ) C40 prop delay (ns) 50 60 120 285961 g08 40 30 0 40 80 C20 20 60 100 70 45 55 35 65 v ab = 1.5v c l = 15pf 10 100 data rate (mbps) 0 supply current (ma) 20 40 60 10 30 50 285961 g09 1 0.1 r = 54 r = 100 r =
ltc2859/LTC2861 8 285961fb ro (pin 1): receiver output. if the receiver output is enabled ( re low) and a > b by 200mv, then ro will be high. if a < b by 200mv, then ro will be low. if the receiver inputs are open, shorted, or terminated without a valid signal, ro will be high. re (pin 2): receiver enable. a low enables the receiver. a high input forces the receiver output into a high imped- ance state. de (pin 3): driver enable. a high on de enables the driver. a low input will force the driver outputs into a high imped- ance. if re is high with de and te low, the part will enter a low power shutdown state. di (pin 4): driver input. if the driver outputs are enabled (de high), then a low on di forces the driver positive output low and negative output high. a high on di, with the driver outputs enabled, forces the driver positive output high and negative output low. (dd/de/gn) te (pin 5): internal termination resistance enable. a high input will connect a termination resistor (120 typical) between pins a and b. gnd (pins 6,11/6,13/6): ground. pins 11 and 13 are backside thermal pad, connected to ground. slo (pins 7/7/11): driver slew rate control. a low input will force the driver into a reduced slew rate mode. y (pins -/8/12): positive driver output for LTC2861. z (pins -/9/13): negative driver output for LTC2861. b (pins 9/10/14): negative receiver input (and negative driver output for ltc2859). a (pins 8/11/15): positive receiver input (and positive driver output for ltc2859). v cc (pins 10/12/16): positive supply. 4.5v < v cc < 5.5v. bypass with 0.1f ceramic capacitor. pin functions
ltc2859/LTC2861 9 285961fb ltc2859 logic inputs de re te mode a, b ro terminator 0 0 0 receive r in enabled off 0 0 1 receive with term r in enabled on 0 1 0 shutdown r in hi-z off 0 1 1 term only r in hi-z on 1 0 0 transmit with receive driven enabled off 1 0 1 transmit with receive and term driven enabled on 1 1 0 transmit driven hi-z off 1 1 1 transmit with term driven hi-z on LTC2861 logic inputs de re te mode a, b y, z ro terminator 0 0 0 receive r in hi-z enabled off 0 0 1 receive with term r in hi-z enabled on 0 1 0 shutdown r in hi-z hi-z off 0 1 1 term only r in hi-z hi-z on 1 0 0 transmit with receive r in driven enabled off 1 0 1 transmit with receive and term r in driven enabled on 1 1 0 transmit r in driven hi-z off 1 1 1 transmit with term r in driven hi-z on ltc2859 LTC2861 function tables block diagrams 120 de ro di a (15kv) te b (15kv) z (15kv) y (15kv) sleep/shutdown logic and delay receiver driver re slo 120 de ro di a (15kv) te b (15kv) sleep/shutdown logic and delay receiver driver re slo 2859/61 bd
ltc2859/LTC2861 10 285961fb driver the driver provides full rs485 and rs422 compatibility. when enabled, if di is high, y-z is positive for the full duplex device (LTC2861) and a-b is positive for the half- duplex device (ltc2859). when the driver is disabled, both outputs are high- impedance. for the full duplex LTC2861, the leakage on the driver output pins is guaranteed to be less than 10a over the entire common mode range of C7v to +12v. on the half-duplex ltc2859, the impedance is dominated by the receiver input resistance, r in . driver overvoltage and overcurrent protection the driver outputs are protected from short circuits to any voltage within the absolute maximum range of (v cc C15v) to +15v. the maximum current in this condition is 250ma. if the pin voltage exceeds about 10v, current limit folds back to about half of the peak value to reduce overall power dissipation and avoid damaging the part. the ltc2859/LTC2861 also feature thermal shutdown protection that disables the driver, terminator, and receiver in case of excessive power dissipation. slo mode: slew limiting for emi emissions control the ltc2859/LTC2861 feature a logic-selectable reduced- slew mode ( slo mode) that softens the driver output edges to control the high frequency emi emissions from equipment and data cables. the reduced slew rate mode is entered by taking the slo pin low, where the data rate is limited to about 250kbps. slew limiting also mitigates the adverse effects of imperfect transmission line termination caused by stubs or mismatched cables. figures 8a and 8b show the LTC2861 driver outputs in normal and slo mode with their corresponding frequency spectrums operating at 250kbps. slo mode signi? cantly reduces the high frequency harmonics. figure 8a. driver output in normal mode driver output at 125khz into 100 resistor frequency spectrum of the same signal figure 8b. driver output in slo mode driver output at 125khz into 100 resistor frequency spectrum of the same signal applications information 285961 f08a y, z yCz 2s/div 1v/div yCz 1.25mhz/div 10db/div 285961 f08b y, z yCz 2s/div 1v/div yCz 1.25mhz/div 10db/div
ltc2859/LTC2861 11 285961fb receiver and failsafe with the receiver enabled, when the absolute value of the differential voltage between the a and b pins is greater than 200mv, the state of ro will re? ect the polarity of (a-b). the ltc2859/LTC2861 have a failsafe feature that guaran- tees the receiver output to be in a logic high state when the inputs are either shorted, left open, or terminated (externally or internally), but not driven for more than about 3s. the delay prevents signal zero crossings from being interpreted as shorted inputs and causing ro to go high inadvertently. this failsafe feature is guaranteed to work for inputs spanning the entire common mode range of C7v to +12v. the receiver output is internally driven high (to v cc ) or low (to ground) with no external pull-up needed. when the receiver is disabled the ro pin becomes hi-z with leakage of less than 1a for voltages within the supply range. receiver input resistance the receiver input resistance from a or b to ground is guaranteed to be greater than 96k when the termina- tion is disabled. this is 8x higher than the requirements for rs485 standard and thus this receiver represents a one-eighth unit load. this, in turn, means that 8x the standard number of receivers, or 256 total, can be con- nected to a line without loading it beyond what is called out in the rs485 standard. the input resistance of the receivers is unaffected by enabling/disabling the receiver and by powering/unpowering the part. the equivalent input resistance looking into a and b is shown in figure 9. the termination resistor cannot be enabled by te if the device is unpowered or in thermal shutdown mode. switchable termination proper cable termination is very important for good signal ? delity. if the cable is not terminated with its char- acteristic impedance, re? ections will result in distorted waveforms. the ltc2859/LTC2861 are the ? rst rs485 transceivers to offer integrated switchable termination resistors on the receiver input pins. this provides the tremendous advan- tage of being able to easily change, through logic control, the proper line termination for optimal performance when con? guring transceiver networks. when the te pin is high, the termination resistor is en- abled and the differential resistance from a to b is 120. figure 10 shows the i/v characteristics between pins a and b with the termination resistor enabled and disabled. figure 10. curve trace between a and b with termination enabled and disabled figure 9. equivalent input resistance into a and b (on the ltc2859, valid if driver is disabled) applications information 60 60 a te b 2859/61 f09 >96k >96k
ltc2859/LTC2861 12 285961fb the resistance is maintained over the entire rs485 common mode range of C7v to +12v as shown in figure 11. the integrated termination resistor has a high frequency response which does not limit performance at the maximum speci? ed data rate. figure 12 shows the magnitude and phase of the termination impedance vs frequency. supply current the unloaded static supply currents in the ltc2859/ LTC2861 are very low typically under 700a for all modes of operation without the internal terminator enabled. in applications with resistively terminated cables, the supply current is dominated by the driver load. for example, when using two 120 terminators with a differential driver output voltage of 2v, the dc current is 33ma, which is sourced by the positive voltage supply. this is true whether the terminators are external or internal such as in the ltc2859/ LTC2861. power supply current increases with toggling data due to capacitive loading and this term can increase signi? cantly at high data rates. figure 13 shows supply current vs data rate for two different capacitive loads (for the circuit con? guration of figure 3). high speed considerations a ground plane layout is recommended for the ltc2859/ LTC2861. a 0.1f bypass capacitor less than one quarter inch away from the v cc pin is also recommended. the pc board traces connected to signals a/b and z/y (LTC2861) should be symmetrical and as short as possible to maintain good differential signal integrity. to minimize capacitive effects, the differential signals should be separated by more than the width of a trace and should not be routed on top of each other if they are on different signal planes. care should be taken to route outputs away from any sensitive inputs to reduce feedback effects that might cause noise, jitter, or even oscillations. for example, in the full duplex LTC2861, di and a/b should not be routed near the driver or receiver outputs. the logic inputs of the ltc2859/LTC2861 have 50mv of hysteresis to provide noise immunity. fast edges on the outputs can cause glitches in the ground and power supplies which are exacerbated by capacitive loading. if a logic input is held near its threshold (typically 1.5v), a noise glitch figure 11. termination resistance vs common mode voltage figure 12. termination magnitude and phase vs frequency figure 13. supply current vs data rate applications information common mode voltage (v) C10 resistance () 130 140 10 285961 f11 120 110 C5 0 5 15 150 frequency (mhz) 10 C1 0 20 40 60 80 100 120 140 magnitude () 10 0 10 1 10 2 285961 f12 C25 C20 C15 C10 C5 0 phase (degrees) magnitude phase 10 5 data rate (kbps) 10 2 45 50 55 60 65 70 75 current (ma) 10 3 10 4 285961 f13 r diff = 54 c l = 1000pf c l = 100pf
ltc2859/LTC2861 13 285961fb 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 0.10 bottom view?xposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ?0.05 (dd10) dfn 1103 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.675 0.05 3.50 0.05 package outline 0.25 0.05 0.50 bsc from a driver transition may exceed the hysteresis levels on the logic and data inputs pins causing an unintended state change. this can be avoided by maintaining normal logic levels on the pins and by slewing inputs through their thresholds by faster than 1v/s when transitioning. good supply decoupling and proper line termination also reduces glitches caused by driver transitions. cable length vs data rate for a given data rate, the maximum transmission distance is bounded by the cable properties. a typical curve of cable length vs data rate compliant with the rs485 standard is shown in figure 14. three regions of this curve re? ect different performance limiting factors in data transmis- sion. in the ? at region of the curve, maximum distance is determined by resistive losses in the cable. the downward sloping region represents limits in distance and data rate due to ac losses in the cable. the solid vertical line represents the speci? ed maximum data rate in the rs485 standard. the dashed lines at 250kbps and 20mbps show the maximum data rates of the ltc2859/LTC2861 in low- emi and normal modes, respectively. figure 14. cable length vs data rate (rs485 standard shown in solid lines) dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699) applications information 285961 f14 data rate (bps) cable length (ft) 10k 1m 10m 100k 100m 100 1k 10 10k low-emi mode max data rate rs485 max data rate normal mode max data rate package description
ltc2859/LTC2861 14 285961fb 4.00 0.10 (2 sides) 3.00 0.10 (2 sides) note: 1. drawing proposed to be a variation of version (wged) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?xposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 2.50 ref 1 6 12 7 pin 1 notch r = 0.20 or 0.35 45 chamfer pin 1 top mark (note 6) 0.200 ref 0.00 ?0.05 (ue12/de12) dfn 0806 rev d 2.50 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 3.30 0.10 0.25 0.05 0.50 bsc 1.70 0.05 3.30 0.05 0.50 bsc 0.25 0.05 gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 15 14 13 .189 ?.196* (4.801 ?4.978) 12 11 10 9 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .0532 ?.0688 (1.35 ?1.75) .008 ?.012 (0.203 ?0.305) typ .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ?.165 .0250 bsc .0165 .0015 .045 .005 inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side de/ue package 12-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1695) gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) package description
ltc2859/LTC2861 15 285961fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. multi-node network with end termination using ltc2859 typical applications te = 5v te = 5v te = 0v r d te = 0v r d 2859/61 ta04 r d ltc2859 r d ltc2859 ltc2859 ltc2859
ltc2859/LTC2861 16 285961fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 0108 rev b ? printed in usa part number description comments ltc485 low power rs485 interface transceiver i cc = 300a (typ) ltc491 differential driver and receiver pair i cc = 300a ltc1480 3.3v ultralow power rs485 transceiver 3.3v operation ltc1483 ultralow power rs485 low emi transceiver controlled driver slew rate ltc1485 differential bus transceiver 10mbaud operation ltc1487 ultralow power rs485 with low emi, shutdown and high input impedance up to 256 transceivers on the bus ltc1520 50mbps precision quad line receiver channel-to-channel skew 400ps (typ) ltc1535 isolated rs485 full-duplex transceiver 2500v rms isolation in surface mount package ltc1685 52mbps rs485 transceiver with precision delay propagation delay skew 500ps (typ) lt1785 60v fault protected rs485 transceiver 60v tolerant, 15kv esd failsafe 0 application (idle state = logic 0) related parts typical application 2859/61 ta03 "a" "b" a b r d ltc2859 120 i1 ro i2 di 100k v cc

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