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? complete b3zs analog to nrz digital ds3/ sts-1 line interface unit in a compact 2.6 square inch, 50-pin dip module ? single +5v power supply ? analog inputs and outputs are transformer coupled ? meets dsx cross connect frame mask requirements (ansi standard t1.102-1993) ? adaptive equalization for zero to 900 feet of cable ? input dynamic range of 20 db (100mv - 0.95v) ? meets ds3/sts-1 jitter requirements of bellcore technical references ? full loopback capability ? coding violation and loss of signal detection for received signal ? txc-20153d has monitor pin for received signal input. txc-20153g has pull-up for external clock input and improved performance margins. ? speeds time to market for prototype development ? eases parts inventory and acquisition ? eases field maintenance the ds3/sts-1 line interface module (ds3lim-sn) is a complete and compact full duplex analog line to digital terminal interface. it converts b3zs-encoded line sig- nals, in either ds3 asynchronous or sts-1 synchro- nous format, to and from nrz data and clock signals. in addition to the synchronous signal option, this module offers other improvements relative to the transwitch ds3 line interface module (ds3lim, txc-20049d), which it can replace in some existing ds3 applications. sensitive analog circuitry meets ds3/sts-1 perfor- mance requirements for signal recovery and transmis- sion, with direct line connection via on-board transformers. integration of functions into a single mod- ule frees the user from complex printed circuit board design and testing for the ds3/sts-1 analog section, reducing the time required for applications development and product introduction. ? ds3/sts-1 interface for quick time to market products ds3lim-sn ds3/sts-1 line interface module nrz clock/data output txc-20153d, txc-20153g document number: txc-20153-mb ed. 2, august 1998 u.s. patent no. 5,119,326 u.s. and/or foreign patents issued or pending copyright 1998 transwitch corporation transwitch, txc and xbert are registered trademarks of transwitch corporation ds3lim-sn txc-20153d/txc-20153g ds3/sts-1 line interface module nrz data and clock out nrz data and clock in line side terminal side b3zs analog input (from bnc connector) b3zs analog output (to bnc connector) status coding violation control external reference clock: 44.736 mhz (ds3) 51.840 mhz (sts-1) data sheet applications description features transwitch corporation ? 3 enterprise drive ?? ? ? shelton, connecticut 06484 usa tel: 203-929-8810 fax: 203-926-9453 www.transwitch.com
-2 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g table of contents s ection page product overview ..................................................................................................4 block diagram .......................................................................................................5 block diagram description ....................................................................................5 pin diagram ..........................................................................................................7 pin descriptions ....................................................................................................7 absolute maximum ratings and environmental limitations ................................12 power requirements ..........................................................................................12 input and output parameters ..............................................................................13 timing characteristics ........................................................................................16 operation ...................................................................................................... 21-27 receiver input requirements ......................................................................21 interfering tone tolerance ...........................................................................21 receiver output specifications ....................................................................21 transmitter specifications ............................................................................22 ais and loopback control signal arbitration ...............................................22 jitter transfer ...............................................................................................23 jitter generation ..........................................................................................23 jitter tolerance ............................................................................................ 23 interference margin...................................................................................... 25 physical design of motherboard ..................................................................26 functional differences between the ds3lim-sn and ds3lim modules ...........27 circuit diagrams ........................................................................................... 29-31 package information ...........................................................................................32 ordering information ...........................................................................................34 related products ................................................................................................34 standards documentation sources .............................................................. 35-36 list of data sheet changes .......................................................................... 37-38 documentation update registration form * ..................................................41 * please note that transwitch provides documentation for all of its products. customers who are using a transwitch product, or planning to do so, should register with the transwitch marketing department to receive relevant updated and supplemental documentation as it is issued. they should also contact the applications engineering department to ensure that they are provided with the latest available in- formation about the product, especially before undertaking development of new designs incorporating the product.
-3 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g list of figures figure 1. ds3lim-sn block diagram ...............................................................5 figure 2. ds3lim-sn pin diagram ...................................................................7 figure 3a. ds3 interface isolated pulse mask ..................................................16 figure 3b. ds3 interface isolated pulse mask equations .................................17 figure 3c. sts-1 interface isolated pulse mask equations .............................17 figure 3d. sts-1 interface eye diagram mask ................................................18 figure 4. nrz transmit input timing...............................................................19 figure 5. nrz receive output timing ............................................................20 figure 6. coding violation pulse timing .........................................................20 figure 7a. ds3lim-sn input jitter tolerance for ds3 (category i)...................24 figure 7b. ds3lim-sn input jitter tolerance for ds3 (category ii)..................24 figure 7c. ds3lim-sn input jitter tolerance for sts-1 ..................................24 figure 8. interference margin test configuration ...........................................25 figure 9. power supply and ground connections ..........................................26 figure 10. ds3lim-sn circuit diagram (txc-20153d, -20153g edition 1) .....30 figure 11. ds3lim-sn circuit diagram (txc-20153g edition 2) .....................31 figure 12. ds3lim-sn simplified outline drawing ..........................................32 figure 13. installation without motherboard socket .........................................33 figure 14. installation with motherboard socket ..............................................33
-4 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g product overview the ds3lim-sn module employs transwitchs latest ds3/sts-1 receiver/transmitter vlsi device on a small printed circuit board assembly with line-coupling transformers and dual-port terminal interface circuits. use of the transwitch art vlsi device (advanced ds3/sts-1 receiver/transmitter, txc-02020) provides improved performance and reduced cost relative to the transwitch ds3lim module, which is based on the ds3-only ds3rt receiver/transmitter vlsi device. in addition to the sts-1 synchronous capability, the art device has on-board agc, equalization and output amplification, functions which had to be provided with external compo- nents on the ds3lim. the ds3lim-sn is mechanically compatible with the ds3lim and is intended to supersede it for both existing and new applications. the reduced cost and improved performance (wider dynamic range, simultaneous loop- back capability) are advantages for existing applications, providing that certain constraints imposed by electri- cal differences from the ds3lim can be accommodated (see the section below entitled functional differences between ds3lim-sn and ds3lim modules). for new applications the sts-1 capability and sin- gle power supply are additional advantages. three versions of the ds3lim-sn module are available, with two different product numbers and part numbers (please see the ordering information section). the txc-20153d product is the original version. it provides a pin (mon, pin 46) for monitoring the received signal input at the 75 ohm terminating resistor on the secondary side of the input transformer. since this pin has electrical characteristics different from those of the correspond- ing pin on the ds3lim module, the txc-20153d may not be suitable for substitution in ds3lim applications where this pin is not used for monitoring but has a termination that takes advantage of the superior ds3lim output characteristics. the txc-20153g product was introduced for use in such applications. the first version of the txc-20153g (edition 1) has two layout differences relative to the txc-20153d: it has no monitor output connection to pin 46, and it has a pull-up resistor on the external clock input (dck, pin 27). however, this edi- tion 1 is less immune to noise than the txc-20153d. in applications where excessive board noise is present, and when receiving a signal greater than 800 mv peak, bit errors may occur. edition 2 of the txc-20153g was introduced for use in such applications. it is identical to edition 1, except for a modification to the receive input circuit that provides 4 db attenuation of the input signal at the input to the art device.
-5 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g block diagram figure 1. ds3lim-sn block diagram block diagram description a block diagram for the ds3lim-sn module is shown in figure 1, which is explained below. in the receive direction, the ds3lim-sn receives a bipolar b3zs-encoded ds3 or sts-1 signal from the line via a bnc or other connector. this signal (rx_b3zs) is ac-coupled into the ds3lim-sn through a 1:1 trans- former (xfmr). from the transformer, the signal is terminated into a 75 ohm resistance, either as a single 75 ohm shunt resistor or as a 27/47 ohm resistor pair that provides 4 db attenuation at its junction (in txc- 20153g edition 2 only). the resulting signal is then routed to the input of an automatic gain control (agc) cir- cuit in the art device (dotted outline). a monitor pin (mon) is provided for observing the received signal in the txc-20153d only. the agc provides the adaptive equalizer circuit with a constant signal level. the equalizer is switched in and out to recover narrow or wide width ds3/sts-1 signals, respectively. from the equalizer, the bipolar signal is connected to the los detector and clock recovery blocks. the line signal is monitored for transitions, and a loss of signal indication is provided on the signal pin labelled rxlos . receive line receive terminal interface interface xfmr agc/ adaptive equalizer los detector clock recovery b3zs decoder ds3 ais generator b3zs encoder output control loopback controls xfmr tx i/o control rx i/o control rx terminal interface mux tx terminal interface mux tc1 tc2 td1 td2 rc1 rc2 rd1 rd2 slct rxdis rxais rt tr txdis txlev txais dck rx_b3zs tx_b3zs transwitch art device mon rxlos cv p n p n c transmit line transmit terminal interface interface tr rt (txc-20153d only) rgnd +5vdcr tgnd +5vdct (txc-20153g only) 4 db atten. (txc-20153g, edition 2, only)
-6 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g the clock recovery block requires an external 44.736 mhz (ds3) or 51.840 mhz (sts-1) clock (dck) with a stability of 200 ppm. the stability of dck must be increased to 20 ppm if the transmit or receive ais fea- tures are used. the average time to recover the clock is approximately 1 ms when the line signal is applied. the b3zs (bipolar with 3-zero substitution) line coded data is decoded by the b3zs decoder block. indications of coding violation errors, other than normal b3zs coding substitutions, are provided on the signal pin cv. the decoder detects coding violation errors in the same fashion as the telecommunication techniques corpora- tions tberd ? model 305 ds3 analyzer for system test purposes, but some differences may be encountered when testing with scientific atlanta or wandel and goltermann equipment. these errors can occur because of noise and other impairments on the line. the application that uses the ds3lim-sn can count the cv pulses over a known time interval to calculate a close estimate for the bit error rate (ber) performance of the line. the ds3lim-sn provides the capability to generate and insert a ds3 alarm indication signal (ais) into the nrz receive data signal at the rd1 or rd2 pins. a low placed on the rxais pin enables the ds3 ais insertion from the ds3 ais generator block. this pin may be connected to the receive loss of signal (rxlos ) pin to generate ais. the ds3lim-sn does not provide a corresponding capability for sts-1 operation. the decoded signal is processed by the receive i/o control and receive terminal interface multiplexer blocks. two receive output ports consisting of a clock and data signal are provided. the first receive output port has pins labelled rc1 and rd1; the second is labelled rc2 and rd2. only one port can be active at a time. data (rd1/rd2) is clocked out of the ds3lim-sn with respect to the falling edge of the receive clock (rc1/rc2). the selection of the receive output port is controlled by the state of the select pin (slct, high for port 1). the unused port is forced into a high impedance state. in addition, the two receive ports can both be disabled and forced into a high impedance state by placing a low on the rxdis pin. in the transmit direction, two transmit ports consisting of clock and data are also provided. the first transmit port has pins labelled tc1 and td1; the second is labelled tc2 and td2. transmit input data (td1/td2) is clocked into the ds3lim-sn on positive transitions of the clock signal (tc1/tc2). as in the receiver section, the slct pin determines the transmit input port selection (high for port 1). the transmit input clock and data signals are processed by the transmit terminal interface multiplexer and transmit i/o control blocks. the incoming data is encoded by the b3zs encoder. in the b3zs line code, each block of three consecutive zeros is removed and replaced by either of two codes that contain bipolar violations. these replacement codes are b0v and 00v, where b represents a pulse that conforms to the bipolar rule and v represents a pulse violating the rule. the choice of these codes is made so that an odd number of bipolar conforming pulses (b) is transmitted between consecutive bipolar violation pulses (v). the encoded data is connected to the output control block, which contains the formatting circuitry to transform the b3zs-encoded data into pulses that meet the requirements for the ds3 or sts-1 line rates and a 75-ohm driver for the 1:1 out- put transformer. this block also provides the capability to transmit a ds3 alarm indication signal (ais), which is independent of the transmit data. a low placed on the txais pin enables the transmit ds3 ais insertion. a low placed on the txdis pin deactivates the transmit output. when txdis is set low, the output impedance of the tx_b3zs port becomes a high impedance state. the output control block contains a feature to adjust the output signal for cables longer than 50 feet, which is activated by setting the txlev pin low. in addition to the alarms and control signals, the ds3lim-sn provides two loopback capabilities for testing transmit and receive loopback via the loopback controls block. transmit-to-receive (terminal) loopback con- nects the data path from the transmit i/o control block output to the receive i/o control block input, and dis- ables the external receiver input. transmit-to-receive loopback is activated by placing a low on the tr signal pin. receive-to-transmit (line) loopback connects the receive data output path to the transmit input circuits and disables the nrz transmit input. receive-to-transmit loopback is activated by placing a low on the rt pin. ter- minal and line loopbacks may be applied together, or at the same time as ds3 ais insertion into the receive or transmit data output signals, as described under the heading ais and loopback control signal arbitration in the operation section of this data sheet.
-7 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g pin diagram note: some pins do not perform the functions suggested by their labels, as explained in the pin descriptions section. figure 2. ds3lim-sn pin diagram pin descriptions symbol * pin no. i/o/p ** type *** name/function tx_b3zs 1, 2 o analog transmit ds3/sts-1 b3zs output: these pins are ac-coupled, b3zs-encoded ds3 or sts-1 output sig- nals. they may be applied directly to a 75 w bnc con- nector. it is recommended that pin 2 should be connected to the center pin and pin 1 to the shield of the bnc connector. under normal operation, this output has a 75 w source impedance. when txdis is low, this out- put is placed into a high-impedance disabled condition. tgnd 3, 4, 5, 6, 7 p transmit ground: ground pin for transmit side circuitry. txdis 8 i ttlp transmit disable: an active low on this pin disables the ds3 or sts-1 transmitted signal. an external 10k w pull- up resistor to +5v is required to enable transmission. -5vdct 9, 10 p unused: these pins are not connected within the mod- ule, which does not require a -5v power supply. they may be connected to the -5v power supply in applica- tions originally designed to use the ds3lim module. otherwise they must be left floating. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 rx_b3zs rx_b3zs rgnd rgnd mon/nc rgnd rgnd -5vdcr -5vdcr +5vdcr +5vdcr +5vdcr rxdis slct rxlos cv rc2 rc1 txloc rxais txais rd1 rd2 dck tx_b3zs tx_b3zs tgnd tgnd tgnd tgnd tgnd txdis -5vdct -5vdct +5vdct +5vdct +5vdct equalize equalize rt tr asel0 asel1 txlev tc1 tc2 td1 td2 clk8 rxerr t1 t2 j1 c2 u1 c4 l1 c17 c1 c3 l2 transwitch txc-02020 r11 r17 c12 r14 r7 c19 r8 u3 u2 r1/r21 r20 c25 * not e: symbols used here are the same as for the ds3lim module, although there are some pins for which the function is different or absent in the ds3lim-sn, as indicated under name/function. ** note: i=input; o=output; p=power *** note: see the input and output parameters section below for digital input and output type definitions.
-8 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g +5vdct 11, 12, 13 p transmit +5vdc: +5v, 5% dc power supply for trans- mit side circuitry. equalize 14, 15 -- -- unused: these pins are not connected within the mod- ule, which does not require a strap for short cable equal- ization. they may be left open or joined together for applications originally designed to use the ds3lim mod- ule. rt 16 i ttlp receive-to-transmit loopback: an active low enables the receive (line) loopback feature. this loop- back connects the receive terminal nrz data and clock outputs to the transmit terminal nrz data and clock inputs, and disables the nrz transmit inputs. (see note 1) tr 17 i ttlp transmit-to-receive loopback: an active low enables the transmit (terminal) loopback feature. this loopback connects the b3zs transmit line outputs to the b3zs receive line inputs, and disables the ds3/sts-1 receive line signal input. (see note 1) asel0 asel1 18 19 -- -- -- -- unused: these pins are not connected within the mod- ule, which does not require amplifier gain select bias. each may be connected to +5v by a 10k w resistor in applications originally designed to use the ds3lim mod- ule. otherwise they must be left floating. txlev 20 i ttl transmit level: this pin alters the shape of the trans- mitted pulse to meet ansi t1.102 pulse mask require- ments at the dsx with different cable lengths. the pin must be pulled high (with a 10k w resistor to +5v) for cables shorter than 50 feet and must be set low for cables between 50 and 450 feet long. for applications originally designed to use the ds3lim module to meet ansi mask requirements with 0-450 feet of cable this pin is tied low, and the ds3lim-sn may not operate cor- rectly with short cables. the transmit output mode is indeterminate if txlev is left floating. tc1 21 i ttlr transmit input clock #1: when a high is placed on the slct lead, tc1 is the input pin for the nrz transmit clock. this clock has a 50% 5% duty cycle. tc2 22 i ttlr transmit input clock #2: when a low is placed on the slct lead, tc2 is the input pin for the nrz transmit clock. this clock has a 50% 5% duty cycle. td1 23 i ttl ds3/sts-1 transmit input data port 1: data is clocked in on positive transitions of tc1. this port is enabled by placing a high on the slct lead. symbol * pin no. i/o/p ** type *** name/function note 1: an external 10k w pull-up resistor to +5v is required to disable loopback. setting rt and tr low simultaneously will enable both line and terminal side loopbacks (see operation section for additional information on ais and loopback control signal arbitration).
-9 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g td2 24 i ttl ds3/sts-1 transmit input data port 2: data is clocked in on positive transitions of tc2. this port is enabled by placing a low on the slct lead. clk8 25 -- -- unused: this pin is not connected within the module, which does not require an 8 khz clock input as a time base for bit error rate measurement. the pin may have this clock connected in applications originally designed to use the ds3lim module. otherwise it must be left floating. rxerr 26 o tied low unused: this pin is tied low within the module to simu- late a low receive bit error rate indication for applications originally designed to use the ds3lim module, in which this pin goes high to indicate a high error rate. this pin should otherwise be left floating, since the ds3lim-sn does not indicate error rate. dck 27 i cmos external clock : an external 44.736 mhz (ds3) or 51.840 mhz (sts-1) clock having a stability of 200 ppm ( 20 ppm if the ais feature is used), and a duty cycle of 50% 5%. if the duty cycle is relaxed, the trans- mitted mask may not meet pulse mask requirements. (see note 4.) rd2 28 o ttl4ma ds3/sts-1 receive output data port 2: data is clocked out on negative transitions of rc2 (see note 1). this port is enabled by placing a low on the slct lead. when this port is disabled, by placing a high on slct or a low on the rxdis control lead, the output goes to a high impedance state. rd1 29 o ttl4ma ds3/sts-1 receive output data port 1: data is clocked out on negative transitions of rc1 (see note 1). this port is enabled by placing a high on the slct lead. when this port is disabled, by placing a low on slct or a low on the rxdis control lead, the output goes to a high impedance state. txais 30 i ttlp transmit ais: an active low placed on this pin disables the transmit data input, and causes a ds3 alarm indica- tion signal to be generated and sent as transmitted data on the tx_b3zs output when the module is operating with ds3 signals. (see notes 2 and 3.) symbol * pin no. i/o/p ** type *** name/function note 1: data is also clocked out on negative clock transitions in the ds3lim module. the edition 3 data sheet for this module incorrectly specifies positive transitions in the pin description. note 2: an external 10k w pull-up resistor to +5v is required to enable data and disable the ais. note 3: ds3 ais is defined as a valid m-frame with proper subframe structure. the data payload is a 1010 ... sequence starting with a 1 after each overhead bit. overhead bits are as follows: f0=0, f1=1, m0=0, m1=1; c-bits are set to 0; x-bits are set to 1; and p-bits are set for valid parity. note 4: in the txc-20153g module, the dck input is connected to the transmit +5vdc supply line via a 10 k w pull-up resistor and its input current characteristics are modified accordingly.
- 10 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g rxais 31 i ttlp receive ais: an active low placed on this pin disables the receive data, input, and causes a ds3 alarm indica- tion signal to be generated and sent on the rd1 or rd2 output pins when the module is operating with ds3 sig- nals. (see notes 2 and 3) txloc 32 o pulled high unused: this pin is pulled high within the module to simulate an error-free indication for applications origi- nally designed to use the ds3lim module, in which this pin goes low to indicate that the transmit input clock (tc1, tc2) is stuck high or low. this pin should other- wise be left floating, since the ds3lim-sn does not indi- cate loss of clock. rc1 33 o cmos8ma ds3/sts-1 receive output clock port 1: this port is enabled by placing a high on the slct lead. when this port is disabled by placing a low on slct or a low on the rxdis control lead, the output goes to a high imped- ance state. rc2 34 o cmos8ma ds3/sts-1 receive output clock port 2: this port is enabled by placing a low on the slct lead. when this port is disabled by placing a high on slct or a low on the rxdis control lead, the output goes to a high imped- ance state. cv 35 o cmos coding violation: a positive pulse having a duration of one clock cycle is provided on this pin whenever a b3zs coding violation occurs. rxlos 36 o cmos receive loss of signal: an active low alarm is gener- ated when 175 75 consecutive zeros appear in the incoming data stream. it is cleared when ones pulse density is in the range of 28% to 33% (or more than 33%) for 175 75 consecutive pulses. slct 37 i cmosr select port 1 or 2: the ports are enabled and disabled according to the following table: symbol * pin no. i/o/p ** type *** name/function select high low rd1 enabled high z rc1 enabled high z td1 enabled disabled tc1 enabled disabled rd2 high z enabled rc2 high z enabled td2 disabled enabled tc2 disabled enabled
- 11 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g rxdis 38 i cmosr receive disable ports 1 and 2: an active low placed on this pin disables port 1 (rd1 and rc1), and port 2 (rd2 and rc2). the data and clock output signal leads are forced to a high impedance state. an external 10k w pull-up resistor to +5v is required to enable port 1 and port 2. +5vdcr 39, 40, 41 p receive +5vdc: +5v, 5% dc power supply input for receive side circuitry. -5vdcr 42, 43 p unused: these pins are not connected within the mod- ule, which does not require a -5v power supply. they may be connected to the -5v power supply in applica- tions originally designed to use the ds3lim module. otherwise they must be left floating. rgnd 44, 45, 47, 48 p receive ground: ground pins for receive side circuitry. mon/nc 46 o/- analog/- for txc-20153d: ds3/sts-1 received signal monitor point: this out- put is directly tied to the terminating resistor after trans- former coupling. care must be taken to ensure very short trace lengths to the mon buffer, or oscillation of the agc may occur. if a monitor output is not required, it is suggested that this pin be left open. for txc-20153g (edition 1 and edition 2): no connect: this pin is not connected within the mod- ule, which provides no capability to monitor the received input signal. this pin may be connected to an external termination in applications originally designed to use the ds3lim module, but it should otherwise be treated as a no connect pin and should be left floating. rx_b3zs 49, 50 i analog receive ds3/sts-1 b3zs input: these pins are the ac-coupled b3zs-encoded ds3 or sts-1 input signal. they may come directly from a 75 w ohm bnc connec- tor. if these signals originate from a bnc connector, it is recommended that the center pin should be connected to pin 50 and the shield to pin 49. symbol * pin no. i/o/p ** type *** name/function
- 12 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g absolute maximum ratings and environmental limitations notes: 1. conditions exceeding the min or max values may cause permanent failure. exposure to conditions near the min or max values for extended periods may impair device reliability. 2. pre-assembly storage in non-drypack conditions is not recommended. please refer to the instructions on the caution label on the drypack bag in which the modules are supplied. power requirements parameter symbol min max unit conditions +5v supply voltages v dd +7.0 v note 1 dc input voltage v in -0.5 v dd + 0.5 v note 1 storage temperature range t s -55 150 o c note 1 ambient operating temperature t a 070 o c 0 ft/min linear airflow moisture exposure level me 5 level per eia/jedec jesd22-a112-a relative humidity, in-circuit rh 0 100 % non-condensing. note 2. parameter min typ max unit test conditions v dd 4.75 5.0 5.25 v i dd 290 ma v dd = 5.25v p dd 1.5 w v dd = 5.25v
- 13 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g input and output parameters input parameters for cmos input parameters for cmosr note: input has a 100k (nominal) internal pull-up resistor. input parameters for ttl input parameters for ttlp note: all ttlp inputs have an internal pull-up resistor. parameter min typ max unit test conditions v ih v dd - (v dd / 3) v dd + 0.3 v v il - 0.3 (v dd / 3) v i ih - 10 m av dd = 5.25v i il 10 m av dd = 5.25v input capacitance 10 pf parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current 50 120 m av dd = 5.25 input capacitance 5.5 pf parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current 10 m av dd = 5.25 input capacitance 5.5 pf parameter min typ max unit test conditions v ih 2.0 v dd + 0.3 v v il - 0.3 0.8 v i ih - 10 m av dd = 5.25v i il 550 m av dd = 5.25v input capacitance 10 pf
- 14 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g input parameters for ttlr note: input has a 100k (nominal) internal pull-up resistor. output parameters for cmos output parameters for cmos8ma output parameters for ttl4ma parameter min typ max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current 50 120 m av dd = 5.25 input capacitance 5.5 pf parameter min typ max unit test conditions v oh v dd - 0.5 v 4 ma source v ol 0.5 v 4 ma sink i oh - 4.0 ma v dd = 4.75v i ol 4.0 ma v dd = 4.75v t rise 1.7 2.7 4.2 ns c load = 15 pf t fall 1.9 2.8 4.1 ns c load = 15 pf parameter min typ max unit test conditions v oh v dd - 0.5 v v dd = 4.75; i oh = -8.0 ma v ol 0.4 v v dd = 4.75; i ol = 8.0 ma i ol 8.0 ma i oh -8.0 ma t rise 1.3 2.4 3.8 ns c load = 25 pf t fall 1.1 1.8 2.5 ns c load = 25 pf parameter min typ max unit test conditions v oh 2.4 v v dd = 4.75; i oh = -4.0 ma v ol 0.6 v v dd = 4.75; i ol = 4.0 ma i ol 4.0 ma i oh -4.0 ma t rise 2.8 6.5 9.2 ns c load = 15 pf t fa l l 1.3 2.3 3.4 ns c load = 15 pf
- 15 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g receiver sensitivity input parameters for transformer coupling output parameters for transformer coupling parameter min typ max unit test conditions dynamic range 100 950 mvp parameter min typ max unit test conditions return loss - 26 db ds3: 22.368 mhz; 25 o c sts-1: 25.920 mhz; 25 o c isolation voltage 300 vrms turns ratio 1:1 input impedance 67.5 75 82.5 ohms parameter min typ max unit test conditions isolation voltage 300 vrms turns ratio 1:1 output impedance (txdis = 1) 67.5 75 82.5 ohms output impedance (txdis = 0) 100k 200k ohms
- 16 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g timing characteristics detailed timing diagrams for the ds3lim-sn are illustrated in figures 3 through 6. all output times are mea- sured with the maximum load capacitance appropriate for the pin type. timing parameters are measured at signal levels of (v oh + v ol )/2 for outputs or (v ih + v il )/2 for inputs. line side timing characteristics the line side signal characteristics are designed so that the output meets the requirements of ansi standard t1.102-1993. when terminated into a test load of 75 w 5% using att 734a coaxial cable the ds3lim-sn module will meet the ds3 or sts-1 interface isolated pulse masks defined below in figures 3a through 3c for a cable length of 0 to 450 feet. for sts-1 pulse sequences, the output also meets the sts-1 interface eye dia- gram mask shown in figure 3d. figure 3a. ds3 interface isolated pulse mask maximum* minimum* * note: the ds3 curves shown are approximate representations of the equations in figure 3b. the corresponding sts-1 curves (not shown) would be slightly different, as indicated by the equations in figure 3c. **note: ui = 1 / (system clock frequency) 0.8 0.6 0.4 0.2 0 0.0 -0.4 -0.8 +0.4 +0.8 +1.2 +1.6 1.0 normalized amplitude time, t, in unit intervals (ui)**
- 17 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g figure 3b. ds3 interface isolated pulse mask equations figure 3c. sts-1 interface isolated pulse mask equations curve time in unit intervals normalized amplitude maximum minimum -0.85 < t< -0.68 -0.68 < t< 0.36 0.36 < t< 1.4 -0.85 < t< -0.36 -0.36 < t< 0.36 0.36 < t< 1.4 0.03 0.5 1+ sin (1+ ) [ p 2 t 0.34 ] +0.03 - 0.03 0.5 1+ sin (1+ ) [ p 2 t 0.18 ] - 0.03 0.08 + 0.407e -1.84(t-0.36) - 0.03 curve (upper) curve (lower) curve time in unit intervals normalized amplitude maximum minimum -0.85 < t< -0.68 -0.68 < t< 0.26 0.26 < t< 1.4 -0.85 < t< -0.38 -0.38 < t< 0.36 0.36 < t< 1.4 0.03 0.5 1+ sin (1+ ) [ p 2 t 0.34 ] +0.03 - 0.03 0.5 1+ sin (1+ ) [ p 2 t 0.18 ] - 0.03 0.1 + 0.61e -2.4(t-0.26) - 0.03 curve (upper) curve (lower)
- 18 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g *note: ui = 1 / (system clock frequency) note - both inner and outer regions are symmetric about zero amplitude axis. figure 3d. sts-1 interface eye diagram mask outer region corner points inner region corner points point time amplitude point time amplitude a -0.5 0.426 i -0.245 0.214 b -0.261 0.904 j -0.187 0.455 c -0.136 1.03 k -0.104 0.67 d -0.028 1.03 l -0.017 0.67 e 0.094 0.883 m 0.077 0.581 f 0.187 0.723 n 0.18 0.14 g 0.31 0.566 o -0.054 0.16 h0.50.426 0 0.25 0.5 0.75 1 -0.25 -0.5 -0.75 -1 -0.5 -0.25 0 0.25 0.5 a b c d e f g h i j k m l n o time in unit intervals (ui) * normalized amplitude
- 19 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g terminal side timing characteristics figure 4. nrz transmit input timing note: tc1 , tc2 symmetry is measured about the 1.4vdc threshold in order to assure symmetric output waveforms. parameter symbol min typ max unit tc1, tc2 ds3 input clock period t cyc 22.353 ns tc1, tc2 sts-1 input clock period t cyc 19.290 ns tc1, tc2 high time t pwh 10 ns tc1, tc2 duty cycle (t pwh /t cyc )--45 55% td1, td2 set-up time to tc1 - , tc2 - t su 4.0 ns td1, td2 hold time after tc1 - , tc2 - t h 3.0 ns data valid data valid data valid tc1,tc2 td1,td2 t su t pwh t h t cyc (input) (input) 1.4v
- 20 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g figure 5. nrz receive output timing note: rc1, rc2 symmetry is measured about the 50% amplitude point. figure 6. coding violation pulse timing *note: ui = 1 / (system clock frequency) parameter symbol min typ max unit rc1, rc2 ds3 output clock period t cyc 22.353 ns rc1, rc2 sts-1 output clock period t cyc 19.290 ns rc1, rc2 high time t pwh 10 ns rc1, rc2 duty cycle (t pwh /t cyc )--45 55% rd1, rd2 output delay after rc1 , rc2 (rxais = 1) t od(1) 1.0 5.5 ns rd1, rd2 output delay after rc1 , rc2 (rxais = 0) t od(1) 1.0 6.5 ns cv output delay after rc1 , rc2 t od(2) 1.0 5.5 ns parameter symbol min typ max unit* cv pulse width t pw 0.9 1.0 1.1 ui cv pulse high time t pwh 0.8 0.9 1.0 ui cv delay from occurrence of violation t d 7.0 ui rc1,rc2 rd1,rd2 cv t pwh t cyc t od(1) t od(2) (output) (output) (output) t pw t pwh cv (output)
- 21 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g operation receiver input requirements *note: refer to the operation - jitter tolerance subsection below for ds3 and sts-1 minimum requirements and measured values. interfering tone tolerance the ds3lim-sn will properly recover clock and present error-free output to the receive terminal side interface* in the presence of a sinusoidal interfering tone signal at the following line rates: interfering tone tolerance *note: see figure 8: interference margin test configuration receiver output specifications parameter value interface cable at&t 728a/734a coaxial (or equivalent) bit rate: ds3 44.736 mbit/s 20 ppm sts-1 51.840 mbit/s 20 ppm line code b3zs input signal amplitude: 100 mvp - 0.95 vp ac (differential input) cable length 0 - 900 feet input return loss: ds3 > 26 db at 22.368 mhz with external 75 w resistor sts-1 > 26 db at 25.920 mhz with external 75 w resistor input resistance > 5k w signal-to-noise toler- ance no greater than either the value produced by adjacent pulses in the data stream or 10% of the peak pulse amplitude, whichever is greater. input jitter tolerance as defined by figures 7a, 7b and 7c: input jitter tolerance* data rate (mbit/s) tone frequency (mhz) maximum tone level 51.84 25.97 -20 db 44.736 22.4 -20 db parameter value clock recovery jitter peaking 1 db maximum clock recovery pll pull-in time < 100 m s sequences reported as coding violations ++, --, not b0v, not 00v, three or more consecutive zeros (excessive zeros)
- 22 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g transmitter specifications note: a 75 w 5% output load is assumed in these specifications. measurements made at transmitter unless otherwise noted. *note: ui = 1 / (system clock frequency) ais and loopback control signal arbitration the response of the module to combinations of the rxais ,txais ,rt and tr input signals is tabulated below: note: x = dont care * these signals may only be applied (active low) when the module is operating with ds3 signals. parameter value tx_b3zs output charac- teristics, txlev low: the two pulse shapes specified below are to be measured at the end of 50- 450 feet of cable, terminated by a 75 w resistor. pulse shape (ds3) as defined by figure 2 in ansi ti.404-1994 pulse shape (sts-1) as defined by figure 4-10 in gr-253-core, issue 2, december 1995 amplitude 0.81 volts 10% for ds3; + 0.95 for sts-1 output jitter 0.05 ui maximum with jitter-free input clock on tc1, tc2 tx_b3zs output charac- teristics, txlev high: the two pulse shapes specified below are to be measured at the end of 0-50 feet of cable, terminated by a 75 w resistor. pulse shape (ds3) as defined by figure 2 in ansi ti.404-1994 pulse shape (sts-1) as defined by figure 4-10 in gr-253-core, issue 2, december 1995 amplitude 0.67 volts 10% for ds3; + 0.8 for sts-1 output jitter 0.05 ui maximum with jitter-free input clock on tc1, tc2 r x ais *t x ais *rt (line) t r (term.) terminal output line output 1 1 1 1 normal normal 1 0 x 1 normal ais 1 0 x 0 term loopback ais 0 1 1 x ais normal 0 1 0 x ais line loopback 00 xx ais ais 1 1 1 0 term loopback normal 1 1 0 1 normal line loopback 1 1 0 0 term loopback line loopback
- 23 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g jitter transfer transfer of jitter through an individual unit of digital equipment is characterized by the relationship between the applied input jitter and the resulting output jitter as a function of frequency. for ds3, bellcore technical reference gr-499-core, issue 1, december 1995 further describes and defines jitter transfer. for sts-1, bellcore technical reference gr-253-core, issue 2, december 1995 further describes and defines jitter transfer. in a looped back configuration (through the receive path and externally looped back through the transmit path), in the absence of applied input jitter the amount of jitter introduced by the ds3lim-sn is maximum 0.065 unit intervals (uis, where ui is 1 / system clock frequency) of peak-to-peak jitter over a jitter frequency range of 20 hz to 1 mhz (filter with high-pass of 10 hz and a low-pass of 1.1 mhz). with applied input jitter, the maximum output jitter is the applied input jitter plus the above jitter introduced by the ds3lim-sn. jitter generation jitter generation is the process whereby jitter appears at the output port of an individual unit of digital equip- ment in the absence of applied input jitter. for ds3, bellcore technical reference gr-499-core, issue 1, december 1995 specifies the maximum jitter generation to be 1.0 ui of peak-to-peak at the output of the terminal receiver for category i equipment. for sts-1, bellcore technical reference gr-253-core, issue 2, december 1995 specifies the maximum jit- ter generation to be 1.5 ui peak-to-peak maximum at the output of the terminal receiver for category i equip- ment. in a looped back configuration (through the transmit path and externally looped back through the receive path), the ds3/sts-1 jitter generation within the ds3lim-sn is 0.145 ui peak-to-peak maximum for all frequencies specified in these two standards. jitter tolerance ds3: input jitter tolerance is the maximum amplitude of sinusoidal jitter at a given jitter frequency, which, when mod- ulating the signal at an equipment port, results in no more than two errored seconds cumulative, where these errored seconds are integrated over successive 30-second measurement intervals, and the jitter amplitude is increased in each succeeding measurement interval. requirements for input jitter tolerance are specified in terms of compliance with a jitter mask, which represents a combination of points. each point corresponds to minimum amplitude of sinusoidal jitter at a given jitter fre- quency which, when modulating the signal at an equipment input port, results in two or fewer errored seconds in a 30-second measurement interval. bellcore technical reference gr-499-core, issue 1, december 1995 specifies the minimum requirement mask for category i and category ii equipment, which are shown in fig- ures 7a and 7b. jitter tolerance within the ds3lim-sn meets and exceeds the performance requirements. figures 7a and 7b present the bellcore ds3 minimum jitter tolerance requirement masks for category i and category ii, respec- tively, and show the measured performance of the ds3lim-sn, which exceeds both requirements. sts-1: for sts-1, jitter tolerance is specified in bellcore technical reference gr-253-core, issue 2, december 1995. the minimum requirement mask is shown in figure 7c.
- 24 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g jitter tolerance within the ds3lim-sn meets and exceeds performance requirements. figure 7c presents the bellcore sts-1 minimum jitter tolerance requirement mask and the measured sts-1 performance of the ds3lim-sn. figure 7a. ds3lim-sn input jitter tolerance for ds3 (category i) figure 7b. ds3lim-sn input jitter tolerance for ds3 (category ii) figure 7c. ds3lim-sn input jitter tolerance for sts-1 5 0.1 sinusoidal input jitter amplitude (ui, peak-peak, jitter frequency (hz, log scale) 10 2.3k 60k 300k 50 khz measured* -20 db/decade minimum required * 20 ui is the maximum measurement limit of the test equipment. 20 note: ui = 22.35 ns log scale) 10 0.3 sinusoidal input jitter amplitude (ui, peak-peak, jitter frequency (hz, log scale) 10 2.3k 22.3k 300k 50 khz measured* -20 db/decade minimum required * 20 ui is the maximum measurement limit of the test equipment. 20 note: ui = 22.35 ns log scale) -20 db/decade 1.5 0.15 30 300 2k 20k measured* minimum required jitter frequency 20 15 50 khz sinusoidal input jitter amplitude (ui, peak-peak, * 20 ui is the maximum measurement limit of the test equipment. (hz, log scale) note: ui = 19.29 ns log scale)
- 25 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g interference margin the interference margin of the ds3lim-sn is measured using the test configuration shown in figure 8. figure 8. interference margin test configuration wavetek 166 ds3lim-sn rx in tx out rx out tx in sine wave rate | 1 /2 hp3784a test set 2 15 -1 pattern rate | 1 attenuator line out line in passive combiner note: wavetek generator is set for same pk-pk voltage as test pattern at 0 db attenuator setting. signal | 1 , mhz vcc, v min attenuation for no errors, db ds3 44.736 4.75 - 5.25 20 sts-1 51.84 4.75 20
- 26 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g physical design of motherboard high-frequency design techniques must be employed for layout of the printed circuit board on which the ds3lim-sn module is mounted. the following guidelines and suggestions should be adhered to for a suc- cessful board design. at the ds3 and sts-1 frequencies it is important to use high-frequency layout tech- niques. the techniques discussed below are the bare minimum set that should be used. a solid ground plane should be used. solid in this instance means that the impedance from any point in the plane to the board ground connection should be low. this is very important in regards to the location of the analog ds3lim-sn device since its snr can be severely degraded by i*z drops in these planes. under no circumstances should a ds3lim-sn ground pin be connected to ground through a trace. the trace has a finite impedance at high frequencies; it is not a short. ground currents through the trace impedance will cause voltage noise. do not use a solid power plane. break the +5v power plane into regions as shown in figure 9. additionally, there should be a +5v region for board logic. use as wide a path as possible back to the common connecting point. if the power and ground planes are placed in adjacent layers there will be an additional noise reduction due to capacitive coupling. for example, a six-layer board could be signal-signal-power(ground)-ground(power)- signal-signal. figure 9. power supply and ground connections for the input and output signal connections of the ds3lim-sn module a board trace at high frequencies is not a zero-impedance metal interconnection. it is a distributed l/c network. the values of the l and c parasitic components are determined by trace geometry (width and height) and the surrounding material. component layout should be arranged to permit the use of short traces, especially for the analog inputs. these input traces should be restricted to one side of the motherboard, since vias have been found to cause degraded perfor- mance due to output signal coupling. a trace with a given geometry will have a different impedance if it is on an 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 ground 0.1 m f 10 m f + +5vdct tx_b3zs tx_b3zs tgnd tgnd tgnd tgnd tgnd txdis -5vdct -5vdct +5vdct +5vdct +5vdct equalize equalize rt tr asel0 asel1 txlev tc1 tc2 td1 td2 clk8 rx_b3zs rx_b3zs rgnd rgnd mon rgnd rgnd -5vdcr -5vdcr +5vdcr +5vdcr +5vdcr rxdis slct rxlos cv rc2 rc1 txloc rxais txais rd1 rd2 dck rxerr ground 0.1 m f 10 m f + +5vdcr bnc connector bnc connector
- 27 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g outside board layer from the same trace placed instead in an internal layer. large branches off a main trace will change the impedance at the branch point due to the effect of impedances in parallel, so branch lengths should be kept to a minimum (less than a quarter wavelength). this is very important for clock lines where load/source impedance mismatches can cause severe ringing, which leads to timing problems. use clock buff- ers to reduce the difficulty of distributing a clock with many loads. if relays are used to switch the transceivers in and out, use the 50 ohm shielded variety to minimize crosstalk, especially from the power used to energize the relay. match the impedance of the board traces of the transmit- ter outputs and receiver inputs to the transmission line impedance (75 ohms if a 1:1 transformer is used) to minimize reflections, and do not use vias in these signal paths. physically separate the analog signal lines from the digital lines. route the differential receiver lines side by side to make coupled noise common-mode. avoid ninety-degree corners in the board lands; keep lands as straight and short as possible. use terminating (i.e., 51 ohm series-damping) resistors in the digital signals lines where appropriate (i.e., if the line is longer than a quarter wavelength of the highest signal frequency of importance, reflections will start causing prob- lems). the above comments are guidelines only. high-frequency board layout is difficult and must be done with care. a bad board layout will reduce the snr of the transceiver and cause timing problems with the board logic, per- haps to the point of requiring a complete board redesign. functional differences between the ds3lim-sn and ds3lim modules the following nine functional differences between the ds3lim-sn and ds3lim modules affect the utilization of the pins of the module. the first two of these differences do not affect the ability of the ds3lim-sn to be used as a direct replacement for the ds3lim. the others represent performance differences which may require special accommodation by the user. 1. equalization (pins 14, 15) the ds3lim requires provision of a strap between the two equalize input pins (14, 15) for line input cable lengths less than 200 feet. due to incorporation of the art vlsi device, which has adaptive equal- ization, the ds3lim-sn can provide equalization for all line input cable lengths from zero to 900 feet auto- matically, without any such special settings based on cable length. the equalize pins are unused in the ds3lim-sn. 2. amplifier gain select (pins 18, 19) the ds3lim requires external pull-up resistors connected to the asel0 and asel1 input pins (18, 19) for line input amplifier gain selection. due to its use of the art device the ds3lim-sn has agc and does not use these two pins. 3. -5v power supply (pins 9, 10, 42, 43) the ds3lim-sn does not require the -5v power supply used by the ds3lim. the four -5v power input pins (9, 10, 42, 43) are unused. however, the +5v power supply current requirement of the module increases from 200 ma for the ds3lim to 290 ma for the ds3lim-sn. 4. txlev input (pin 20, transmit level select for ds3lim) the ds3lim can meet line output pulse mask requirements for all cable lengths from zero to 450 feet with the txlev input (pin 20) set low. with txlev set high or left floating a higher transmit level is provided, which may permit satisfactory performance with longer cables. for the ds3lim-sn the txlev input must be set according to cable length: low for cable lengths from 50 to 450 feet and high (10k w resistor to +5v) for cables shorter than 50 feet. there is no special provision for cables longer than 450 feet. for cable lengths from 50 to 450 feet (txlev low) the ds3lim-sn is compatible with the ds3lim. for cables shorter than 50 feet the low txlev setting provided for the ds3lim is not suitable, and txlev
- 28 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g must be changed to high. for cables longer than 450 feet the ds3lim-sn may not be able to match the ds3lim output pulse performance with txlev set high even if txlev is changed to low. unlike the ds3lim, the txlev pin has no pull-up resistor in the ds3lim-sn, so the pin does not pull high if it is left floating and the transmit output mode selection is indeterminate. it is necessary for the pin to be driven either high or low by an external connection. 5. rxerr output (pins 25 and 26, receive error rate for ds3lim) the ds3lim-sn indicates b3zs coding violations like the ds3lim, but it does not measure bit error rates using an 8 khz clock input (clk8, pin 25), and it cannot indicate error rates above 10 -6 , which the ds3lim does by setting the rxerr output (pin 26) high. (note: the edition 3 data sheet for the ds3lim incor- rectly describes this as an active low signal, rxerr .) the ds3lim-sn has the clk8 pin internally disconnected and the rxerr pin internally tied low to simu- late an error-free condition at all times, so that it can be used in place of the ds3lim, but it will not report bit error rates that exceed the 10 -6 threshold. the bit error rate may be calculated externally in the users application, based on monitoring of the coding violation pulses that are provided as the cv output (pin 35) of the ds3lim-sn. 6. loopback capability (pins 16, 17) the ds3lim module suffers data corruption at the terminal and line interfaces if the line (rt , pin 16) and terminal (tr , pin 17) loopback features are selected simultaneously. the ds3lim-sn exhibits the extended loopback capabilities of the art vlsi device, as described in the operation section of this data sheet, and is not subject to data corruption with simultaneous loopbacks. the implementation of extended loopback capabilities in the art vlsi device required the use of internal loopback path configurations different from those in the ds3rt vlsi device of the ds3lim. the different path used for terminal loopback results in a requirement for user application accommodations in treatment of the rxlos and cv output signals when the ds3lim-sn is substituted for the ds3lim, as described below. the ds3lim implements terminal loopback (transmit-to-receive (tr) loopback) close to the line side inputs and outputs within its ds3rt receiver/transmitter vlsi device. when tr loopback is active, the rxlos and cv output signals are driven by the looped-back transmit input signal and will usually indicate normal operation (i.e., no receive loss of signal or coding violations). the ds3lim-sn implements terminal loopback close to the terminal side inputs and outputs within its art receiver/transmitter vlsi device. when tr loopback is active, the receive input path connection through to the receive output is disabled, but the rxlos and cv output signals are still driven by the receive input signal. if there is no valid input signal, or the receive input is disconnected during tr loopback so that there is noise pickup, the rxlos and cv output signals will reflect this indeterminate receive input condi- tion rather than the looped-back transmit input signal. spurious receive loss of signal and coding violation indications may result. the user application should either disregard the rxlos and cv outputs during tr loopback or arrange to apply a valid signal to the receive input so that these outputs do not become active. 7. txloc output (pin 32, transmit loss of clock for ds3lim) the ds3lim-sn does not have the capability to detect and indicate when the transmit input clock (tc1, tc2) is stuck high or low, which the ds3lim does by setting the txloc output pin (32) low. the ds3lim-sn has the txloc pin internally pulled up to simulate an error-free condition at all times, so that it can be used in place of the ds3lim but will not report a loss of clock condition.
- 29 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g 8. receive loss of signal modified (rxlos , pin 36) the ds3lim detects and indicates receive loss of signal when a positive or negative data transition does not occur for 128 or more clock cycles. recovery occurs on the first positive or negative transition. the ds3lim-sn detects and indicates receive loss of signal when 175 75 zeroes appear in the incoming data stream. recovery occurs when the ones pulse density is in the range of 28% to 33% (or more than 33%) for 175 75 consecutive pulses. 9. receive signal monitor output (mon, pin 46) the txc-20153d version of the ds3lim-sn is more sensitive to external loading of this output pin than is the ds3lim module. the txc-20153g version does not have a monitor output connection to pin 46. 10. digital input and output parameter type changes (pins listed below) the pins listed below have different types of input or output parameter in the ds3lim-sn and the ds3lim. electrical parameter definitions for these types are provided in the input and output parameters section of this data sheet. notes: 1. a 10 k w pull-up resistor is provided in the txc-20153g module only. 2. no pull-up resistor is provided in the ds3lim-sn modules. circuit diagrams the circuit diagram for the txc-20153d and txc-20153g edition 1 versions of the ds3lim-sn module is pro- vided in figure 10. note 1 of this figure indicates the differences between the txc-20153d and txc-20153g versions. the resistors marked x are not installed, since the module has the nrz interface. figure 11 shows the corresponding circuit diagram for the txc-20153g edition 2, which provides 4 db attenuation at the receive line input. both circuit diagrams are reduced versions of larger drawings, so the annotation text is unavoidably small. enlarged versions of the diagrams may be viewed or printed from the pdf file version of this data sheet on the transwitch world wide web site (www.transwitch.com) using acrobat reader software. the reader can zoom portions of the diagram for viewing. a zoomed area may then be selected with tools/ select graphics and edit/copy to move it via the clipboard to any word processor (edit/paste) for printing. symbol pin no. i/o parameter type ds3lim-sn ds3lim txdis 8 i ttlp cmos or ttl rt 16 i ttlp cmosr tr 17 i ttlp cmosr dck 27 i cmos (1) ttl txais 30 i ttlp ttlr rxais 31 i ttlp cmosr cv 35 o cmos ttl2ma rxlos 36 o cmos ttl2ma txlev (2) 20 i ttl cmosr
- 30 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g rxd1 (rx_b3zs) rxd2 (rx_b3zs) rgnd (rgnd) rgnd (rgnd) mon (mon/nc) rgnd (rgnd) rgnd (rgnd) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 j1a m-hdr25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 j1b m-hdr25 txd1 (tx_b3zs) txd2 (tx_b3zs) tgnd (tgnd) tgnd (tgnd) tgnd (tgnd) tgnd (tgnd) tgnd (tgnd) c21 cap00-.1uf vcct c12 cap00-.1uf c13 cap00-.1uf c10 cap00-.1uf c11 cap00-.1uf gnd 33 29 vcct c9 cap01-10uf function vdd data rec 30 28 u1 power and ground pins clk rec (a) clk rec (d) rx out tx out cntl 25 17 6,5 rx/tx dig 10 24 12 4,3 11 vccr c16 cap01-10uf c14 cap00-.1uf c15 cap00-.1uf vccr zero vcc 14 gnd 7 1a 1 1y 2 2a 3 2y 4 3a 5 3y 6 4y 8 4a 9 5y 10 5a 11 6y 12 6a 13 u4 s74hct04 ind 1 c a p 2 ind 3 l2 50mhz_emi_fil vcct vcct txdis- (txdis_) +5vdct (+5vdct) +5vdct (+5vdct) +5vdct (+5vdct) "nc" (equalize) "nc" (equalize) tr- (tr_) zero (txlev) "nc" (-5vdct) "nc" (-5vdct) "nc" (asel0) "nc" (asel1) rt- (rt_) +5vdcr +5vdcr "nc" (-5vdcr) "nc" (-5vdcr) +5vdcr (+5vdcr) +5vdcr (+5vdcr) +5vdcr (+5vdcr) rxdis- (rxdis_) slct (slct) rxlos- (rxlos_) bpv (cv) rc2 (rc2) rc1 (rc1) txloc- (txloc_) rxais- (rxais_) ind 1 c a p 2 ind 3 l1 50mhz_emi_fil vccr txais- (txais_) rd1 (rd1) rd2 (rd2) dck (dck) rxerr (rxerr) vcct tc1 (tc1) tc2 (tc2) td1 (td1) td2 (td2) "nc" (clk8) pin symbols used in data sheet, but with suffix _ replacing symbol overline. rxerr tgnd txloc- rxdis- c23 cap00-.1uf note: symbols in parenthesis correspond to r18 res01-75 tgnd tgnd zero- tgnd vcct rgnd tgnd rgnd tgnd c17 cap00-.1uf c18 cap01-10uf 36 39 vccr 1 2 l4 s-ferrite 34 tx out 37 pll rxd1 rxd2 r1 res01-75 mon c1 cap00-.01uf 1 6 3 4 t1 s-wb1010 r g n d d c k r x l o s - r x a i s - b p v v c c r r19 res01-10k (see note 1) dck c7 cap00-.1uf rd2 r10 res01-51 r6 res01-51 rd1 vcct r9 res01-4.7k rc1 rc2 r11 res01-0 r7 res01-51 r8 res01-51 be 1 gnd 12 c0 2 a0 3 b0 4 d0 5 c1 6 a1 7 b1 8 d1 9 c2 10 a2 11 bx 13 vcc 24 b2 14 d2 15 c3 16 a3 17 b3 18 d3 19 c4 20 a4 21 b4 22 d4 23 u2 sqs3383q r14 res01-0 vcct tgnd rgnd rgnd vccr agndrx 29 n c 2 7 n c 2 6 a v d d r x 2 5 a g n d r x 2 4 b 3 z s d i s 2 3 b i s t 2 2 r e f c k 2 1 a v d d r x 2 8 d l o s 2 0 r a i s 1 9 c v 1 8 agndtx 39 dvdd 17 n c 4 0 d s x d i s 4 1 z e r o 4 2 r z t x i n 4 3 t a i s 4 4 l n l b k 1 t r l b k 2 a g n d t x 3 a v d d t x 5 a v d d t x 6 clki 7 avddrx 30 di1 31 di2 32 agndrx 33 avddtpll 34 tpllc 35 agndtpll 36 avddtx 37 dout 38 rp/rd 16 rn 15 clko 14 clko 13 dgnd 12 dgnd 11 dvdd 10 tp/td 9 tn 8 a g n d t x 4 u1 txc-02020-aipl c2 cap00-.01uf 1 2 l3 s-ferrite c22 cap01-10uf vccr txd2 c3 cap00-.1uf c20 cap01-10uf 1 6 3 4 t2 s-wb1010 rgnd c19 cap00-.01uf vcct tgnd tgnd tgnd vcct tgnd tc1 tc2 be 1 gnd 12 c0 2 a0 3 b0 4 d0 5 c1 6 a1 7 b1 8 d1 9 c2 10 a2 11 bx 13 vcc 24 b2 14 d2 15 c3 16 a3 17 b3 18 d3 19 c4 20 a4 21 b4 22 d4 23 u3 sqs3383q vcct c6 cap00-.1uf slct tgnd td1 td2 r17 res01-0 r15 res01-75 y r t - t r - t g n d t x a i s - t x d i s - v c c t t g n d v c c t z e r o - 44-pin art c4 cap00-.01uf c5 cap01-10uf txd1 note 1: txc-20153-gcmm do install: r19 (10k) TXC-20153-DCMM do not install: r19 (10k) disconnect mon pin mon pin connected nrz mode install: r15 do not install: r11,r14 y r17,r18 figure 10. ds3lim-sn circuit diagram (txc-20153d, txc-20153g edition 1)
- 31 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g figure 11. ds3lim-sn circuit diagram (txc-20153g edition 2)
- 32 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g package information the ds3/sts-1 line interface module consists of a 2.6 x 1.0 inch multi-layer printed circuit board with surface mounted components on both sides and 50 signal/power pins at 0.1 inch spacing on the two long edges to pro- vide a dip configuration. figure 12 is a simplified drawing that shows three views of the module. all dimen- sions are in inches and are nominal unless otherwise indicated. figure 12. ds3lim-sn simplified outline drawing top view 2.600 0.005 0.900 0.020 1.000 0.005 c5 c22 c20 c9 c16 c15 c14 c13 c11 c21 l3 l4 c18 c7 c6 c23 r9 r10 r15 r6 c10 0.120 max 0.062 0.005 0.100 0.010 0.300 0.210 t1 t2 j1 c2 u1 c4 l1 c17 c1 c3 l2 transwitch txc-02020-aipl r11 r17 c12 r14 r7 r21 c19 r8 u3 u2 u4 notes: 1. module is shown approximately twice full size. 2. all dimensions are in inches, and are nominal unless otherwise indicated. 3. r11, r14, r17 and r18 are not installed. r19 (10 k w ) is a coaxial-lead resistor. 4. the axis of each pin is located within 0.010 inch vertically and 0.005 inch horizontally from its nominal position. 5. this figure shows the component layout for txc-20153g edition 2 (also refer to figure 11). 6. the component layout for txc-20153d and txc-20153g edition 1 has c25 and r20 removed, and r21 replaced by r1 (refer to figure 10). r18 max r 1 9 (see note 4) r20 c25
- 33 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g the ds3lim-sn can be installed without or with a socket on the motherboard, as shown in figures 13 and 14, respectively. all dimensions are shown in inches and are nominal unless otherwise indicated. figure 13. installation without motherboard socket figure 14. installation with motherboard socket notes for figures 13 and 14: 1. all dimensions are in inches and are nominal unless otherwise indicated. 2. drawings not to scale. 3. samtec, inc. p.o. box 1147 new albany, indiana 47151-1147 usa phone: 812-944-6733 fax: 812-948-5047 twx: 810-540-4095 telex: 333-918 module pc board xfmr module 0.250 motherboard pc board indctr. module 0.120 max 0.070 0.125 0.108 connector (one pin of 25-pin strip) samtec, inc. #bbl-125-t-e, see note 3 0.060 0.060 pin 0.018 dia or indctr. module pc board xfmr module motherboard pc board indctr. module 0.120 max 0.083 0.165 samtec module connector #bbl-125-t-e mates with samtec micro-socket #sl-125-tt-19 or sl-125-tt-39 (lif) 0.153 #bbl-125-t-e (one pin of 25-pin strip) socket on motherboard (one of 25-socket strip) samtec. inc. #sl-125-tt-19 or sl-125-tt-39 (lif), see note 3 0.250 0.060 0.060 hollow leg 0.029 dia 0.070 flanges 0.07 dia
- 34 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g ordering information product number: txc-20153d part number: TXC-20153-DCMM ds3/sts-1 line interface module, nrz clock/data output 50-pin dual in-line package monitor pin provided for receive line signal input, no dck pull-up product number: txc-20153g part number: txc-20153-gcmm ds3/sts-1 line interface module, nrz clock/data output 50-pin dual in-line package no monitor pin, pull-up provided for dck external clock input) edition 1: 0 db attenuation provided for receive line input edition 2: 4 db attenuation provided for receive line input related products txc-20049d, ds3lim module (ds3 line interface module). a complete analog to digital converter which receives and transmits b3zs-encoded ds3 line signals and provides serial nrz clock and data interfaces on the terminal side. txc-21049, ds3lim evaluation board. a complete, ready-to-use test bed for the test and evaluation of the dslim-sn and ds3lim line interface modules. the module plugs into a socket on the evaluation board, input and output signals are terminated via bnc connectors, and all functions of the module are selectable via jumper insertion/extraction on the evaluation board. txc-20163, e3lim module (e3 line interface module). a complete and compact full duplex analog line to digital terminal interface that converts an hdb3-encoded line signal, in e3 asynchronous format, to and from nrz data and clock signals. the e3lim is packaged as a 2.6 inch x 1.0 inch 50-pin dual in-line package (dip) module. txc-02020, art vlsi device (advanced ds3/sts-1 receiver/transmitter). performs the receive and transmit line interface functions required for transmission of ds3 (44.736 mbit/s) or sts-1 (51.840 mbit/s) signals across a coaxial interface. the txc-02021 arte device has some extended features relative to the art and has a different package with more pins to support additional input and output signals. txc-03303, m13e vlsi device. this single-chip multiplex/demultiplex device provides the complete interfacing function between a single ds3 signal and 28 independent ds1 signals. txc-03401b, ds3f vlsi device (ds3 framer). maps broadband payloads into the ds3 frame format. operates in either the c-bit parity or m13 operating modes. txc-06125, xbert vlsi device (bit error rate generator receiver). programmable multi- rate test pattern generator and receiver in a single chip with serial, nibble, or byte interface capability.
- 35 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g standards documentation sources telecommunication technical standards and reference documentation ma y be obtained from the followin g or g anizations: ansi ( u.s.a. ) : american national standards institute ( ansi ) 11 west 42nd street new york, new york 10036 tel: 212-642-4900 fax: 212-302-1286 the atm forum ( u.s.a. ) : atm forum world head q uarters atm forum european office 303 vinta g e park drive 14 place marie - jeanne bassot foster cit y , ca 94404-1138 levallois perret cedex 92593 paris france tel: 415-578-6860 tel: 33 1 46 39 56 26 fax: 415-525-0182 fax: 33 1 46 39 56 99 bellcore ( u.s.a. ) : bellcore attention - customer service 8 corporate place piscatawa y , nj 08854 tel: 800-521-core ( in u.s.a. ) tel: 908-699-5800 fax: 908-336-2559 eia - electronic industries association ( u.s.a. ) : global en g ineerin g documents suite 407 7730 carondelet avenue cla y ton, mo 63105 tel: 800-854-7179 ( in u.s.a. ) fax: 314-726-6418 etsi ( europe ) : european telecommunications standards institute etsi, 06921 sophia - antipolis cedex france tel: 33 92 94 42 00 fax: 33 93 65 47 16 itu-t ( international ) : publication services of international telecommunication union ( itu ) telecommunication standardization sector ( t ) place des nations ch 1211 geneve 20, switzerland tel: 41-22-730-5285 fax: 41-22-730-5991
- 36 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g tc ( japan ) : ttc standard publishin g group of the telecommunications technolo gy committee 2nd floor, hamamatsucho - suzuki buildin g , 1 2-11, hamamatsu-cho, minato-ku, tok y o tel: 81-3-3432-1551 fax: 81-3-3432-1553
- 37 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g list of data sheet changes this change list identifies those areas within this updated ds3lim-sn data sheet that have significant differ- ences relative to the previous and now superseded ds3lim-sn data sheet: updated ds3lim-sn data sheet: ed. 2, august 1998 previous ds3lim-sn data sheet : ed. 1a, november 1996 the pa g e numbers indicated below of this updated data sheet include si g nificant chan g es relative to the pre- vious data sheet. please note that repa g ination chan g es and chan g es of fi g ure numbers are not listed. page number of updated data sheet summary of the change all changed edition number and date. 1, 40, 42 changed transwitch street address in shelton, ct. 1 in features list, changed features five and six. 2-3 updated table of contents and list of figures. 4 changed third paragraph. 5 in figure 1, added 4 db attenuator block after receive line input trans- former. changed second paragraph. 7 added c25, r20 and r21 to figure 2. 11 added edition 1 and edition 2 to name/function column for pin 46. 12 chan g ed first table and moved ambient operatin g temperature row from second table to first table. 14 deleted output parameters for ttl2ma table (no pins of this type). changed last table 15 changed first table. 16 changed first paragraph. 21 changed value column for input signal amplitude, cable length and input jitter tolerance in first table. changed maximum tone level column for both rows in second table. 22 changed values for pulse shape (ds3) and pulse shape (sts-1) in first table. changed parameter and value in last row of first table. 23 updated bellcore technical reference numbers in 6 locations. added references to category 1 equipment and associated new figure 7a. 24 added figure 7a. changed titles of figures 7b and 7c. 25 changed last column of table in figure 8. 26 changed second and third paragraphs of physical design of motherboard. changed rground and tground to ground in figure 9. 27 changed 450 feet to 900 feet in 1. equalization (pins 14,15) subsection.
- 38 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g 29 changed last paragraph. 30 changed title of figure 10. 31 added figure 11. 32 changed top view and added notes 5 and 6 of figure 12. 34 changed ordering information to describe the three versions of the ds3lim-sn module that can be ordered. updated related products. 35 updated standards documentation sources, adding eia. 37-38 substituted new list of data sheet changes. 41 updated documentation update registration form. page number of updated data sheet summary of the change
- 39 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g - notes- transwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. no liability is assumed as a result of their use or application. transwitch assumes no liability for transwitch applications assistance, customer product design, soft- ware performance, or infringement of patents or services described herein. nor does transwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of transwitch cov- ering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
- 40 - en g ines for global connectivit y transwitch corporation ? 3 enterprise drive ?? ?? shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453
- 41 - txc-20153-mb ed. 2, august 1998 ds3lim-sn txc-20153d, txc-20153g documentation update registration form if y ou would like be added to our database of customers who have re g istered to receive updated documentation for this device as it becomes available, please provide y our name and address below, and fax or mail this pa g e to mar y lombardo at transwitch. mar y will ensure that relevant product information sheets, data sheets, application notes, technical bulletins and other relevant publications are sent to y ou. this information will be made available in paper document form, on a windows/dos/macintosh/unix cd-rom disk, and on the internet world wide web at the transwitch site, http://www.transwitch.com. please print or t y pe the information re q uested below, or attach a business card. name: ________________________________________________________________________ title: _________________________________________________________________________ compan y : _____________________________________________________________________ dept./mailstop: ________________________________________________________________ street: _______________________________________________________________________ cit y /state/zip: _________________________________________________________________ if located outside u.s.a., please add - postal code: ___________ countr y : ______________ telephone:______________________________________________ ext.: _________________ fax: __________________________________ e-mail: _______________________________ purchasin g dept. location: _______________________________________________________ check a box if y our computer has a cd-rom drive: dos ? windows ? mac ? unix ? check box if y ou have internet web access: ? sun ? solaris ? hp ? other ? please describe briefl y y our intended application for this device, and indicate whether y ou would care to have a transwitch applications en g ineer contact y ou to provide assistance: ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ if y ou are also interested in receivin g updated documentation for other transwitch device t y pes, please list them below rather than submittin g separate re g istration forms: __________ __________ __________ __________ __________ __________ please fax this pa g e to mar y lombardo at ( 203 ) 926-9453 or fold, tape and mail it ( see other side ) .
en g ines for global connectivit y (fold back on this line first.) (fold back on this line second, then tape closed, stamp and mail.) first class posta g e re q uired transwitch cor p oration attention: mar y lombardo 3 enter p rise drive shelton, ct 06484 u.s.a. please complete the re g istration form on this back cover sheet, and fax or mail it, if y ou wish to receive updated documentation on this transwitch product as it becomes avail- able. transwitch corporation ? 3 enterprise drive ?? ?? shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453

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