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intensity ? hdsp-2131/2133 categor- ized for color ? excellent esd protection ? wave solderable ? x-y stackable description the hdsp-2131 (yellow), hdsp- 2179 (orange), hdsp-2132 (high efficiency red) and the hdsp- 2133 (green) are eight-digit, 5 x 7 dot matrix, alphanumeric displays. the 5.0 mm (0.2 inch) high characters are packaged in a standard 7.64 mm (0.30 inch) 32 pin dip. the on-board cmos ic has the ability to decode 128 ascii characters, which are permanently stored in rom. in addition, 16 programmable symbols may be stored in an on- board ram. seven brightness levels provide versatility in features ? wide operating tempera- ture range -55 c to +85 c ? smart alphanumeric display on-board cmos ic built-in ram ascii decoder led drive circuitry ? 128 ascii character set ? 16 user definable characters ? programmable features individual character flashing full display blinking multi-level dimming and blanking self test clear function ? read/write capability ? full ttl compatibility ? hdsp-2131/-2133/-2179 useable in night vision lighting applications ? categorized for luminous eight character 5.0 mm (0.2 inch) glass/ceramic intelligent 5 x 7 alphanumeric displays for military applications technical data hdsp-2131 hdsp-2132 HDSP-2133 hdsp-2179 devices yellow high efficiency red high performance green orange hdsp-2131 hdsp-2132 HDSP-2133 hdsp-2179 adjusting the display intensity and power consumption. the hdsp- 213x is designed for standard microprocessor interface tech- niques. the display and special features are accessed through a bidirectional eight-bit data bus. these features make the hdsp- 213x ideally suited for applica- tions where a hermetic, low power alphanumeric display is required.
2 package dimensions pin pin no. function no. function 1 cls 17 gnd (supply) 2 clk 18 gnd (logic) 3wr 19d4 4ce 20d5 5 rst 21 d6 6rd 22d7 7 no pin 23 no pin 8 no pin 24 no pin 9 no pin 25 no pin 10 no pin 26 no pin 11 d0 27 fl 12 d1 28 a0 13 d2 29 a1 14 d3 30 a2 15 nc 31 a3 16 v dd 32 a4 esd warning: standard cmos handling precautions should be observed with the hdsp-2131, hdsp-2132, HDSP-2133, and hdsp-2179. absolute maximum ratings supply voltage, v dd to ground [1] ........................................ -0.3 to 7.0 v operating voltage, v dd to ground [2] ............................................. 5.5 v input voltage, any pin to ground .............................. -0.3 to v dd +0.3 v free air operating temperature range, t a .................... -55 c to +85 c storage temperature, t s .............................................. -55 c to +100 c cmos ic junction temperature, t j (ic) .................................... +150 c maximum solder temperature at seating plane, t < 5 sec ......................................................... 260 c esd protection @ 1.5 k w , 100 pf ......................... v z = 4 kv (each pin) notes: 1. maximum voltage is with no leds illuminated. 2. 20 dots on in all locations at full brightness. note: 1. all dimensions are in mm (inches). 2. unless otherwse specified tolerance is 0.30 mm ( 0.015). 3. for green and yellow devices only. 4. leads are copper alloy, solder dipped. hdsp-213x/2179
3 character set
4 recommended operating conditions parameter symbol minimum nominal maximum units supply voltage v dd 4.5 5.0 5.5 v electrical characteristics over operating temperature range 4.5 < v dd < 5.5 v (unless otherwise specified) 25 c25 c parameter symbol min. typ. [1] max. [1] max. [2] units test conditions input leakage i i -10.0 +10.0 m av in = 0 to v dd , (input without pullup) pins clk, d 0 -d 7 , a 0 -a 4 input current i ip -30.0 11 18 30 m av in = 0 to v dd , (input with pullup) pins rst, cls, wr, rd, ce, fl i dd blank i dd (blk) 0.5 1.5 2.0 ma v in = v dd i dd 8 digits i dd (v) 200 255 330 ma "v" on in all 8 12 dots/character [3] locations i dd 8 digits i dd (#) 300 370 430 ma "#" on in all 8 20 dots/character [3] locations input voltage high v ih 2.0 v dd vv dd = 5.5 v +0.3 input voltage low v il gnd 0.8 v v dd = 4.5 v -0.3 v output voltage high v oh 2.4 v v dd = 4.5 v, i oh = -40 m a output voltage low v ol 0.4 v v dd = 4.5 v, d 0 -d 7 i ol = 1.6 ma output voltage low 0.4 v v dd = 4.5 v, clk i ol = 40 m a thermal resistance r q j-pin 11 c/w ic junction-to-pin notes: 1. v dd = 5.0 v. 2. maximum i dd occurs at -55 c. 3. average i dd measured at full brightness. see table 2 in control word section for i dd at lower brightness levels. peak i dd = 28/15 x average i dd (#).
5 optical characteristics at 25 c [4] v dd = 5.0 v at full brightness high efficiency red hdsp-2132 description symbol minimum typical units luminous intensity character average (#) i v 2.5 7.5 mcd peak wavelength l peak 635 nm dominant wavelength l d 626 nm orange hdsp-2179 description symbol minimum typical units luminous intensity character average (#) i v 2.5 7.5 mcd peak wavelength l peak 600 nm dominant wavelength l d 602 nm yellow hdsp-2131 description symbol minimum typical units luminous intensity character average (#) i v 2.5 7.5 mcd peak wavelength l peak 583 nm dominant wavelength l d 585 nm high performance green HDSP-2133 description symbol minimum typical units luminous intensity character average (#) i v 2.5 7.5 mcd peak wavelength l peak 568 nm dominant wavelength l d 574 nm note: 4. refers to the initial case temperature of the device immediately prior to the light measurement.
6 ac timing characteristics over temperature range v dd = 4.5 to 5.5 v unless otherwise specified. reference number symbol description min. [1] units 1t acc display access time write 210 read 230 ns 2t acs address setup time to chip enable 10 ns 3t ce chip enable active time [2, 3] write 140 read 160 ns 4t ach address hold time to chip enable 20 ns 5t cer chip enable recovery time 60 ns 6t ces chip enable active prior to rising edge of [1,2] write 140 read 160 ns 7t ceh chip enable hold time to rising edge of read/write signal [2, 3] 0ns 8t w write active time [2,3] 100 ns 9t wd data valid prior to rising edge of write signal 50 ns 10 t dh data write hold time 20 ns 11 t r chip enable active prior to valid data 160 ns 12 t rd read active prior to valid data 75 ns 13 t df read data float delay 10 ns t rc reset active time [4] 300 ns notes: 1. worst case values occur at an ic junction temperature of 150 c. 2. for designers who do not need to read from the display, the read line can be tied to v dd and the write and chip enable lines can be tied together. 3. changing the logic levels of the address lines when ce = 0 may cause erroneous data to be entered into the character ram, regardless of the logic levels of the wr and rd lines. 4. the display must not be accessed until after 3 clock pulses (110 m s min. using the internal refresh clock) after the rising edge of the reset line.
7 ac timing characteristics over temperature range v dd = 4.5 to 5.5 v unless otherwise specified. symbol description 25 c typical minimum [1] units f osc oscillator frequency 57 28 khz f rf [5] display refresh rate 256 128 hz f fl [6] character flash rate 2 1 hz t st [7] self test cycle time 4.6 9.2 sec notes: 5.f rf = f osc /224. 6.f fl = f osc /28,672. 7.t st = 262,144/f osc . write cycle timing diagram
8 read cycle timing diagram character font relative luminous intensity vs. temperature
9 electrical description pin function reset (rst, pin 5) reset initializes the display. flash (fl, pin 27) fl low indicates an access to the flash ram and is unaffected by the state of address lines a 3 -a 4 . address inputs each location in memory has a distinct address. address inputs (a 0 -a 2 ) (a 0 -a 4 , pins 28-32) select a specific location in the character ram, the flash ram or a particular row in the udc (user-defined character) ram. a 3 -a 4 are used to select which section of memory is accessed. table 1 shows the logic levels needed to access each section of memory. table 1. logic levels to access memory fl a 4 a 3 section of memory a 2 a 1 a 0 0 x x flash ram character address 1 0 0 udc address register don't care 1 0 1 udc ram row address 1 1 0 control word register don't care 1 1 1 character ram character address clock select this input is used to select either an internal (cls = 1) or external (cls = 0) (cls, pin 1) clock source. clock input/output outputs the master clock (cls = 1) or inputs a clock (cls = 0) for slave (clk, pin 2) displays. write (wr, pin 3) data is written into the display when the wr input is low and the ce input is low. chip enable (ce, pin 4) this input must be at a logic low to read or write data to the display and must go high between each read and write cycle. read (rd, pin 6) data is read from the display when the rd input is low and the ce input is low. data bus (d 0 -d 7 , the data bus is used to read from or write to the display. pins 11-14, 19-22) gnd (supply) (pin 17) this is the analog ground for the led drivers. gnd (logic) (pin 18) this is the digital ground for internal logic. v dd(power) (pin 16) this is the positive power supply input.
10 figure 1. hdsp-213x/-2179 internal block diagram.
11 driving of eight 5 x 7 dot matrix characters. the major user accessible portions of the display are listed below: flash ram, a 128 character ascii decoder, a 16 character udc ram, a udc address register, a control word register, and the refresh circuitry necessary to synchronize the decoding and character ram figure 2 shows the logic levels needed to access the hdsp-213x character ram. during a normal access the ce = "0" and either rd = "0" or wr = "0". however, erroneous data may be written into the character ram if the address lines are unstable when ce = "0" regardless of the logic levels of the rd or wr lines. address lines a 0 -a 2 are used to select the location in the charac- ter ram. two types of data can be stored in each character ram location: an ascii code or a udc ram address. data bit d 7 is used to differentiate between an ascii character and a udc ram address. d 7 = 0 enables the ascii decoder and d 7 = 1 enables the udc ram. d 0 -d 6 are used to input ascii data and d 0 -d 3 are used to input a udc address. figure 2. logic levels to access the character ram. character ram this ram stores either ascii character data or a udc ram address. flash ram this is a 1 x 8 ram which stores flash data. user-defined character this ram stores the dot pattern for custom characters. ram (udc ram) user-defined character this register is used to provide the address to the udc ram when address register the user is writing or reading a custom character. (udc address register) control word register this register allows the user to adjust the display brightness, flash individual characters, blink, self test or clear the display. display internal block diagram figure 1 shows the internal block diagram of the hdsp-213x/-2179 display. the cmos ic consists of an 8 byte character ram, an 8 bit
12 udc ram and udc address register figure 3 shows the logic levels needed to access the udc ram and the udc address register. the udc address register is eight bits wide. the lower four bits (d 0 -d 3 ) are used to select one of the 16 udc locations. the upper four bits (d 4 -d 7 ) are not used. once the udc address has been stored in the udc address register, the udc ram can be accessed. to completely specify a 5 x 7 character requires eight write cycles. one cycle is used to store the udc ram address in the udc address register. seven cycles are used to store dot data in the udc ram. data is entered by rows. one cycle is needed to access each row. figure 4 shows the organization of a udc character assuming the symbol to be stored is an f. a 0 -a 2 are used to select the row to be accessed and d 0 -d 4 are used to transmit the row dot data. the upper three bits (d 5 -d 7 ) are ignored. d 0 (least significant bit) corresponds to the right most column of the 5 x 7 matrix and d 4 (most significant bit) corresponds to the left most column of the 5 x 7 matrix. flash ram figure 5 shows the logic levels needed to access the flash ram. the flash ram has one bit associated with each location of the character ram. the flash input is used to select the flash ram. address lines a 3 -a 4 are ignored. address lines a 0 -a 2 are used to select the location in the flash ram to store the attribute. d 0 is used to store or remove the flash attribute. d 0 = 1 stores the attribute and d 0 = 0 removes the attribute. when the attribute is enabled through bit 3 of the control word and a "1" is stored in the flash ram, the corresponding character will flash at approximately 2 hz. the actual rate is dependent on the clock frequency. for an external clock the flash rate can be calculated by dividing the clock frequency by 28,672. figure 4. data to load f into the udc ram. figure 3. logic levels to access a udc character.
13 control word register figure 6 shows how to access the control word register. this is an eight bit register which performs five functions. they are bright- ness control, flash ram control, blinking, self test and clear. each function is independent of the others. however, all bits are updated during each control word write cycle. brightness (bits 0-2) bits 0-2 of the control word adjust the brightness of the display. bits 0-2 are interpreted as a three bit binary code with code (000) corresponding to maximum brightness and code (111) corresponding to a blanked display. in addition to varying the display brightness, bits 0-2 also vary the average value of i dd . i dd can be c alculated at any brightness level by multiplying the percent bright-ness level by the value of i dd at the 100% brightness level. these values of i dd are shown in table 2. flash function (bit 3) bit 3 determines whether the flashing character attribute is on or off. when bit 3 is a 1, the output of the flash ram is checked. if the content of a location in the flash ram is a 1, the associated digit will flash at approximately 2 hz. for an external clock, the blink rate can be calculated by driving the clock frequency by 28,672. if the flash enable bit of the control word is a 0, the content of the flash ram is ignored. to use this function with multiple display systems see the reset section. blink function (bit 4) bit 4 of the control word is used to synchronize blinking of all eight digits of the display. when this bit is a 1 all eight digits of the display will blink at approxi- mately 2 hz. the actual rate is dependent on the clock frequency. for an external clock, the blink rate can be calculated by dividing the clock frequency by 28,672. this function will override the flash function when it is active. to use this function with multiple display systems see the reset section. figure 5. logic levels to access the flash ram. table 2. current requirements at different brightness levels %25 c symbol d 2 d 1 d 0 brightness typical units i dd (v) 0 0 0 100 200 ma 001 80 160 ma 010 53 106 ma 0 1 1 40 80 ma 1 0 0 27 54 ma 1 0 1 20 40 ma 1 1 0 13 26 ma figure 6. logic levels to access the control word register
14 self test function (bits 5, 6) bit 6 of the control word register is used to initiate the self test function. results of the internal self test are stored in bit 5 of the control word. bit 5 is a read only bit where bit 5 = 1 indicates a passed self test and bit 5 = 0 indicates a failed self test. setting bit 6 to a logic 1 will start the self test function. the built-in self test function of the ic consists of two internal routines which exercises major portions of the ic and illuminates all of the leds. the first routine cycles the ascii decoder rom through all states and performs a checksum on the output. if the checksum agrees with the correct value, bit 5 is set to 1. the second routine provides a visual test of the leds using the drive circuitry. this is accomplished by writing checkered and inverse checkered patterns to the display. each pattern is displayed for approxi- mately 2 seconds. during the self test function the display must not be accessed. the time needed to execute the self test function is calculated by multiplying the clock period by 262,144. for example, assume a clock frequency of 58 khz, then the time to execute the self test function frequency is equal to (262,144/58,000) = 4.5 second duration. at the end of the self test function, the character ram is loaded with blanks, the control word register is set to zeros except for bit 5, and the flash ram is cleared and the udc address register is set to all ones. clear function (bit 7) bit 7 of the control word will clear the character ram and the flash ram. setting bit 7 to a "1" will start the clear function. three clock cycles (110 m s min. using the internal refresh clock) are required to complete the clear function. the display must not be accessed while the display is being cleared. when the clear function has been completed, bit 7 will be reset to a 0. the ascii character code for a space (20h) will be loaded into the character ram to blank the display and the flash ram will be loaded with 0s. the udc ram, udc address register, and the remainder of the control word are unaffected. display reset figure 7 shows the logic levels needed to reset the display. the display should be reset on power- up. the external reset clears the character ram, flash ram, control word and resets the internal counters. after the rising edge of the reset signal, three clock cycles (110 m s min. using the internal refresh clock) are required to complete the reset sequence. the display must not be accessed while the display is being reset. the ascii character code for a space (20h) will be loaded into the character ram to blank the display. the flash ram and control word register are loaded with all "0"s. the udc ram and udc address register are unaffected. all displays which operate with the same clock source must be simultaneously reset to synchronize the flashing and blinking functions. mechanical and electrical considerations the hdsp-213x/-2179 is a 32 pin dual-in-line package with 24 external pins, which can be stacked horizontally and vertically to create arrays of any size. the hdsp-213x/-2179 is designed to operate continuously from -55 c to +85 c with a maximum of 20 dots on per character. illuminat- ing all thirty-five dots at full brightness is not recommended. the hdsp-213x/-2179 is assembled by die attaching and wire bonding 280 led chips and a cmos ic to a ceramic substrate. a glass window is placed over the ceramic substrate creating an air gap over the led wire bonds. a second glass window creates an air gap over the cmos ic. this package construction makes the display highly tolerant to temperature cycling and allows wave soldering and visual inspection of the ic. figure 7. logic levels to reset the display. figure 8. maximum power dissipation vs. ambient temperature derating based on t j max = 125 c.
15 esd susceptibility these displays have esd sus- ceptibility ratings of class 3 per dod-std-1686 and class b per mil-std-883c. soldering and post solder cleaning instructions for the hdsp-213x/-2179 the hdsp-213x/-2179 may be hand soldered or wave soldered with sn63 solder. when hand soldering it is recommended that an electronically temperature con- trolled and securely grounded soldering iron be used. for best results, the iron tip temperature should be set at 315 c (600 f). for wave soldering, a rosin-based rma flux can be used. the solder wave temperature should be set at 245 c 5 c (473 f 9 f), and dwell in the wave should be set between 1 1 / 2 to 3 seconds for optimum soldering. the preheat temperature should not exceed 105 c (221 f) as measured on the solder side of the pc board. for further information on soldering and post solder cleaning, see application note 1027, soldering led components. contrast enhancement when used with the proper con- trast enhancement filters, the hcms-213x/-2179 series displays are readable daylight ambients. refer to application note 1029 luminous contrast and sun- light readability of the hdsp- 235x series alphanumeric displays for military applica- tions for information on contrast enhancement for daylight the inputs to the cmos ic are protected against static discharge and input current latchup. how- ever, for best results standard cmos handling precautions should be used. prior to use, the hdsp-213x should be stored in antistatic packages or conductive material. during assembly, a grounded conductive work area should be used, and assembly personnel should wear conductive wrist straps. lab coats made of synthetic material should be avoided since they are prone to static charge buildup. input current latchup is caused when the cmos inputs are subjected to either a voltage below ground (v in < ground) or to a voltage higher than v dd (v in > v dd ) and when a high current is forced into the input. to prevent input cur- rent latchup and esd damage, unused inputs should be connected either to ground or to v dd . voltages should not be applied to the inputs until v dd has been applied to the display. tran- sient input voltages should be eliminated. thermal considerations the hdsp-213x/-2179 has been designed to provide a low ther- mal resistance path from the cmos ic to the 24 package pins. this heat is then typically conducted through the traces of the users printed circuit board to free air. for most applications no additional heatsinking is required. the maximum operating ic junction temperature is 150 c. the maximum ic junction tem- perature can be calculated using the following equation: t j (ic) max = t a + (p d max) (r q j-pin + r q pin-a ) where p d max = (v dd max) (i dd max) i dd max = 370 ma with 20 dots on in eight character locations at 25 c ambient. this value is from the electrical characteristics table. p d max = (5.5 v) (0.370 a) = 2.04 w ground connections two ground pins are provided to keep the internal ic logic ground clean. the designer can, when necessary, route the analog ground for the led drivers sep- arately from the logic ground until an appropriate ground plane is available. on long interconnects between the display and the host system, the designer can keep voltage drops on the analog ground from affecting the display logic levels by isolating the two grounds. the logic ground should be con- nected to the same ground poten- tial as the logic interface circuitry. the analog ground and the logic ground should be connected at a common ground which can withstand the current introduced by the switching led drivers. when separate ground connec- tions are used, the analog ground can vary from -0.3 v to +0.3 v with respect to the logic ground. voltage below -0.3 v can cause all dots to be on. voltage above +0.3 v can cause dimming and dot mismatch.
ambients. refer to application note 1015 contrast enhance- ment techniques for led displays for information on con- trast enhancement in moderate ambients. night vision lighting when used with the proper nvg/ dv filters, the hdsp-2131, hdsp-2179 and HDSP-2133 may be used in night vision lighting applications. the hdsp-2131 (yellow), hdsp-2179 (orange) displays are used as master caution and warning indicators. the HDSP-2133 (high performance green) displays are used for general instrumentation. for a list of nvg/dv filters and a discussion on night vision lighting technology, refer to application note 1030 led displays and indicators and night vision imaging system lighting. an external dimming circuit must be used to dim these displays to night vision lighting levels to meet nvis radiance requirements. refer to an 1039 dimming hdsp-213x displays to meet night vision lighting levels. www.semiconductor.agilent.com data subject to change. copyright ? 1999 agilent technologies, inc. obsoletes 5952-0712 (3/90) 5964-6387e (11/99)

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