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revision 1.0 april 2005 K1B3216BDD - 1 - u t ram document title 2mx16 bit synchronous burst uni-transistor random access memory the attached datasheets are provided by samsu ng electronics. samsung electronics co., ltd. reserve the right to change the spe cifications and products. samsung electronics will answer to your questions about device. if you have any questio ns, please contact the samsung branch offices. revision history revision no. 0.0 0.1 1.0 remark preliminary preliminary final history initial draft - design target revised - corrected the name of 9th row of balls on the pakage to ?j? from ?i? on page.2 and page.42 finalize draft date september 02, 2004 november 01, 2004 april 06, 2005
revision 1.0 april 2005 K1B3216BDD - 2 - u t ram 2m x 16 bit synchronous bu rst uni-transi stor cmos ram features ? process technology: cmos ? organization: 2m x16 bit ? power supply voltage: 1.7~2.0v ? three state outputs ? supports mrs (mode register set) ? mrs control - software control ? supports driver strength optimization for system environment ? supports async. 4-page read / async. write mode ? supports sync. burst read / async. write mode (address latch type and low adv type) ? supports sync. burst read / sync. burst write mode - supports 4 word / 8 word / 16 word burst length - supports linear(wrap) burst type - latency support : latency 5 @ 66mhz(tcd 10ns) latency 4 @ 54mhz(tcd 10ns) - supports burst read suspend - supports burst write data masking by /ub & /lb control - supports wait function to indicate data availability. ? max. burst clock frequency : 66mhz ? package type : 54 fbga 6.00 x 8.00 samsung electronics co., ltd. reserves the right to change produc ts and specifications without notice . fig.1 pin description table 1. product family product family operating temp. vcc range clock freq. (max) async. speed (taa) power dissipation pkg type standby (i sb1 , max.) operating (i cc2 , max.) K1B3216BDD-i industrial(-40~85 c) 1.7~2.0v 66mhz 70ns 100ua 35ma 54 fbga 6.00 x 8.00 * ps must be tied to v cc. name function name function clk clock input v cc power supply adv address input valid v ccq i/o power supply ps * power save v ss ground cs chip select v ssq i/o ground oe output enable input ub upper byte(i/o 9 ~ 16 ) we write enable input lb lower byte(i/o 1 ~ 8 ) a 0 ~a 20 address inputs wait data availability i/o 1 ~i/o 16 data inputs/outputs dnu do not use table 2. pin description general description the world is moving into the mobile multi-media era and there- fore the mobile handsets need much bigger memory capacity to handle the multi-media data. samsung?s utram products are designed to meet all the request from the various customers who want to cope with the fast growing mobile market. utram is the perfect solution for the mobile market with its low cost, high density and high performance feature. K1B3216BDD is fabri- cated by samsung s advanced cmos technology using one transistor memory cell. the device supports the traditional sram like asynchronous bus operation (asynchronous page read and asynchronous write), the nor flash like synchronous bus operation (synchronous burst read and asynchronous write) and the fully synchronous bus operation (synchronous burst read and synchronous burst write). these three bus operation modes are defined through the mode register setting. the opti- mization of output driver strengt h is possible through the mode register setting to adjust for the different data loadings. through this driver strength optimizatio n, the device can minimize the noise generated on the data bus during read operation. lb oe a0 a1 a2 ps i/o9 ub a3 a4 cs i/o1 i/o10 i/o11 a5 a6 i/o2 i/o3 vssq i/o12 a17 a7 i/o4 vcc vccq i/o13 dnu a16 i/o5 vss i/o15 i/o14 a14 a15 i/o6 i/o7 i/o16 a19 a12 a13 we i/o8 a18 a8 a9 a10 a11 a20 wait clk adv dnu dnu dnu 54-fbga - 6.00 x 8.00 top view (ball down) 12 3 456 a b c d e f g h j
revision 1.0 april 2005 K1B3216BDD - 3 - u t ram contents revision history features and general description power up sequence functional description mode register setting operation mode register setting timing asynchronous operation asynchronous 4 page read operation asynchronous write operation asynchronous write operation in synchronous mode synchronous burst operation synchronous burst read operation synchronous burst write operation synchronous burst operat ion terminology clock latency count burst length burst stop wait control burst type product list absolute maximum ratings recommended dc operating conditions capacitance dc and operating characteristics asynchronous ac characteristics asynchronous timing waveforms synchronous ac characteristics synchronous timing waveforms transition timing waveforms package dimension 1 2 7 8 10 11 12 12 12 12 12 12 12 1 3 13 13 13 13 14 14 15 15 15 15 15 16 17 26 27 36 42 page
revision 1.0 april 2005 K1B3216BDD - 4 - u t ram list of tables table 1. product family table 2. pin description table 3. asynchronous 4 page read & asynchronous write mode truth table table 4. synchronous burst read & asynchronous write mode truth table table 5. synchronous burst read & sy nchronous burst write mode truth table table 6. mode register setti ng according to field of function table 7. mode register set. table 8. latency count support table 9. number of clocks for 1st data table 10. burst sequence table 11. product list table 12. absolute maximum ratings table 13. recommended dc operating conditions table 14. capacitance table 15. dc and operating characteristics table 16. asynchronous ac characteristics table 17. asynchronous read ac characteristics table 18. asynchronous page read ac characteristics table 19. asynchronous write ac characteristics(we controlled) table 20. asynchronous write ac characteristics(ub & lb controlled) table 21. asynch. write in synch. mode ac characteristics(address latch type, we controlled) table 22. asynch. write in synch. mode ac characteristics(address latch type, ub & lb controlled) table 23. asynch. write in synch. mode ac characteristics(low adv type, we controlled) table 24. asynch. write in synch. mode ac characteristics(low adv type, ub & lb controlled) table 25. asynch. write in synch. mode ac characteristics(low adv type multiple write, we controlled) table 26. synchronous ac characteristics table 27. burst operation ac characteristics table 28. burst read ac characteristics(cs toggling consecutive burst) table 29. burst read ac characteristics(cs low holding consecutive burst) table 30. burst read ac characteristics(last data sustaining) table 31. burst write ac characteristics(cs toggling consecutive burst) table 32. burst write ac characteristics(cs low holding consecutive burst) table 33. burst read stop ac characteristics table 34. burst write stop ac characteristics table 35. burst read suspend ac characteristics table 36. burst read to asynch. write( address latch type) ac characteristics table 37. burst read to asynch. write(low adv type) ac characteristics table 38. asynch. write(address latch type) to burst read ac characteristics table 39. asynch. write(low adv type) to burst read ac characteristics table 40. burst read to burst write ac characteristics table 41. burst write to burst read ac characteristics 2 2 8 8 9 10 10 13 13 15 15 15 15 15 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 32 33 35 36 37 38 39 40 41 page
revision 1.0 april 2005 K1B3216BDD - 5 - u t ram list of figures figure 1. pin description figure 2. functional block diagram figure 3. power up timing figure 4. standby mode state machine figure 5. mode register setting timing figure 6. asynchronous 4-page read figure 7. asynchronous write figure 8. synchronous burst read figure 9. synchronous burst write figure 10. latency configuration(read) figure 11. wait control and read/write latency control figure 12. ac output load circuit(asynchronous) figure 13. timing waveform of asynchronous read cycle figure 14. timing waveform of page read cycle figure 15. timing waveform of write cycle(asynchronous, we controlled) figure 16. timing waveform of write cycle(asynchronous, ub & lb controlled) figure 17. timing waveform of write cycle(asynchronous, address latch type, we controlled) figure 18. timing waveform of write cycle(asynchronous, address latch type, ub & lb controlled) figure 19. timing waveform of write cycle(asynchronous, low adv type, we controlled) figure 20. timing waveform of write cycle(asynchronous, low adv type, ub & lb controlled) figure 21. timing waveform of multiple write cycle(asynchronous, low adv type, we controlled ) figure 22. ac output load circuit(synchronous) figure 23. timing waveform of basic burst operation figure 24. timing waveform of burst read cycle(cs toggling consecutive burst read) figure 25. timing waveform of burst read cycle(cs low holding consecutive burst read) figure 26. timing waveform of burst read cycle(last data sustaining) figure 27. timing waveform of burst write cycle(cs toggling consecutive burst write) figure 28. timing waveform of burst write cycle(cs low holding consecutive burst write) figure 29. timing waveform of burst read stop by cs figure 30. timing waveform of burst write stop by cs figure 31. timing waveform of burst read suspend cycle figure 32. synch. burst read to asynch. write(address latch type) timing waveform figure 33. synch. burst read to asynch. write(low adv type) timing waveform figure 34. asynch. write(address latch type) to synch. burst read timing waveform figure 35. asynch. write(low adv type) to synch. burst read timing waveform figure 36. synch. burst read to synch. burst write timing waveform figure 37. synch. burst write to synch. burst read timing waveform 2 6 7 7 11 12 12 12 12 13 14 16 17 28 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 page
revision 1.0 april 2005 K1B3216BDD - 6 - u t ram fig.2 functional block diagram clk generator row select i/o 1 ~i/o 8 data controller i/o 9 ~i/o 16 vcc vss precharge circuit. memory array i/o circuit column select oe cs we adv ub control logic row addresses column addresses lb clk wait data controller data controller
revision 1.0 april 2005 K1B3216BDD - 7 - u t ram power up sequence after applying v cc upto minimum operating voltage(1.7v), drive cs high. then the device gets into the power up mode. wait for minimum 200 s to get into the normal operation mode. during the power up mode, the standby current can not be guaranteed. to get the stable standby current level, at least one cycle of ac tive operation should be implemented regardless of wait time dura tion. to get the appropriate device operation, be sure to keep the following power up sequence. 1. apply power. 2. maintain stable power(vcc min.=1.7v) for a minimum 200 s with cs high. min. 200 s ~ ~ v cc fig.3 power up timing v cc (min) min. 200 s cs normal operation power up mode min. 0ns fig.4 standby mode state machines default mode after power up is asynchronous mode (4 page read and asynchronous write). but this default mode is not 100% guaranteed so mrs setting sequence is highly recommended after power up. cs =v ih cs =v il , ub or lb =v il power on initial state (wait 200 s) active standby mode cs =v ih mrs setting cs =ub =lb =v il
revision 1.0 april 2005 K1B3216BDD - 8 - u t ram table 4. synchronous burst read & asynchro nous write mode(a15/a14=0/1) 1. x must be v il or v ih . 2. /wait is device output signal so does not have any affect to the mode definition. please refer to each timing diagram for /w ait pin function. cs oe we lb ub i/o 0~7 i/o 8~15 clk adv mode power h x 1) x 1) x 1) x 1) high-z high-z x 1) x 1) deselected standby lhh x 1) x 1) high-z high-z x 1) h output disabled active l x 1) x 1) h h high-z high-z x 1) h output disabled active l x 1) h x 1) x 1) high-z high-z read command active l l h l h dout high-z h lower byte read active l l h h l high-z dout h upper byte read active l l h l l dout dout h word read active l h l l h din high-z x 1) o r l o w e r b y t e w r i t e a c t i v e lhlhlhigh-zdin x 1) or upper byte write active lhllldindin x 1) or word write active table 3. asynchronous 4 page read & asynchro nous write mode (a15/a14=0/0) 1. x must be v il or v ih . 2. in asynchronous mode, clock and adv are ignored. 3. /wait pin is high-z in asynchronous mode. cs oe we lb ub i/o 0~7 i/o 8~15 mode power h x 1) x 1) x 1) x 1) high-z high-z deselected standby lhh x 1) x 1) high-z high-z output disabled active l x 1) x 1) h h high-z high-z output disabled active l l h l h dout high-z lower byte read active l l h h l high-z dout upper byte read active l l h l l dout dout word read active l h l l h din high-z lower byte write active l h l h l high-z din upper byte write active l h l l l din din word write active functional description
revision 1.0 april 2005 K1B3216BDD - 9 - u t ram table 5. synchronous burst read & synchro nous write mode(a15/a14=1/0) 1. x must be v il or v ih . 3. /wait is device output signal so does not have any affect to the mode definition. please refer to each timing diagram for /w ait pin function. 4. the last data written in the previous asynchronous write mode is not valid. to make the lastly written data valid, then impl ement at least one dummy write cycle before change mode into synchronous burst read and synchronous burst write mode. 5. the data written in synchronous burst write operation can be corrupted by the next asynchronous write operation. so the tran sition from synchronous burst write operation to asynchronous write operation is prohibited. cs oe we lb ub i/o 0~7 i/o 8~15 clk adv mode power h x 1) x 1) x 1) x 1) high-z high-z x 1) x 1) deselected standby lh h x 1) x 1) high-z high-z x 1) h output disabled active l x 1) x 1) h h high-z high-z x 1) h output disabled active l x 1) h x 1) x 1) high-z high-z read command active l l h l h dout high-z h lower byte read active l l h h l high-z dout h upper byte read active l l h l l dout dout h word read active l x 1) l or x 1) x 1) high-z high-z write command active lh x 1) l h din high-z h lower byte write active lh x 1) h l high-z din h upper byte write active lh x 1) l l din din h word write active
revision 1.0 april 2005 K1B3216BDD - 10 - u t ram mode register setting operation the device has several modes : asynchronous page read m ode, asynchronous write mode, synchronous burst read mode, syn- chronous burst write mode, standby mode. mode register set(mrs) op tion also defines burst length, burst type, wait polarity and latency count at synchronous burst read/write mode. mode register set (mrs) the mode register stores the data for controlling the various operation modes of utram. it programs burst length, burst type, latency count and various vendor spec ific options to make utram useful for a va riety of different applications. the default val ues of mode register are defined, therefore when the reserved address is input, the device runs at default modes. the mode register is writ- ten by driving cs , adv , we , ub , lb to v il and oe to v ih during valid address. the mode register is divided into various fields depend- ing on the fields of functions. burst length fi eld uses a5~a7, burst type uses a8, laten cy count uses a9~a11, wait polarity use s a13, operation mode uses a14~a15 and driver strength uses a16~a17. refer to the table below for detailed mode register setting . a18~a22 addresses are "don?t care" in mode register setting. table 6. mode register setting according to field of function note : ds(driver strength), ms(mode select ), wp(wait polarity), latency(latency count ), bt(burst type), bl(burst length), rfu(reserved for future use) table 7. mode register set * dnu: do not use. note : * the address bits other than those listed in the table above are reserved. for example, burst length address bits(a7:a6:a5) have 4 se ts of reserved bits like 0:0:0, 0:0:1, 1:0:1 and 1:1:0. if the reserved address bits are input, then the mode will be set into the default mode. each field has its own default mode and these default modes are written in blue-bold in the table above. * a12 is a reserved bit for future use. a12 must be set as "0". * not all the mode settings are tested . per the mode settings to be tested. * the last data written in the previous asynchronous write mode is not valid. to make the lastly written data valid, then imple ment at least one dummy write cycle before change mode into synchronous burst read and synchronous burst write mode. * the data written in synchronous burst write operation can be corrupted by the next asynchronous write operation. so the trans ition from synchronous burst write operation to asynchronous write operation is prohibited. address a17~a16 a15~a14 a13 a12 a11~a9 a8 a7~a5 a4~a0 function ds ms wp rfu latency bt bl rfu driver strength mode select a17 a16 ds a15 a14 ms 0 0 full drive 0 0 async. 4 page read / async. write 0 1 1/2 drive 0 1 sync. burst read / async. write 1 0 1/4 drive 1 0 sync. burst read / sync. burst write wait polarity rfu latency count burst type burst length a13 wp a12 rfu a11 a10 a9 latency a8 bt a7 a6 a5 bl 0 low enable 0 must 0 0 0 3 0 linear 0 1 0 4 word 1 high enable 1 dnu* 0 0 1 4 1 dnu* 0 1 1 8 word 0 1 0 5 1 0 0 16 word 0 1 1 6 1 1 1 dnu*
revision 1.0 april 2005 K1B3216BDD - 11 - u t ram mode register setting timing this device supports software access cont rol type mode register setting timing. this timing consists of 5 cycles of read operat ion. each cycle of read operation is normal asynchronous read operation. clock and adv are don?t care and wait signal is high-z. cs should be toggling between cycles. the address for 1st, 2nd and 3rd cycle should be 1fffff(h) and the address for 4th cycle sho uld be 1ffeff. the address for 5th cycle shoul d be mrs code(register setting values). (clock, adv , ub , lb are don?t care, wait =high-z) mrs timing waveform address t rcm t chm cs t clm 1fffff 1fffff 1fffff 1ffeff mrs code ac characteristics parameter sym- min max unit parameter sym- mi ma unit read cycle time t rcm 70 - ns cs low pulse width t clm 60 - ns cs high pulse width t chm 10 - ns oe we
revision 1.0 april 2005 K1B3216BDD - 12 - u t ram asynchronous operation asynchronous 4 page read operation asynchronous normal read operation starts when cs , oe and ub or lb are driven to v il under the valid address without tog- gling page addresses(a0, a1). if the page addresses(a0, a1) are toggled under the other valid address, the first data will be out with the normal read cycle time(trc) and the second, the third and the fourth data will be out with the page cycle time(tpc). ( we should be driven to v ih during the asynchro- nous (page) read operation) clock, adv , wait signals are ignored during the asynchronous (page) read operation. asynchronous write operation asynchronous write operation starts when cs , we and ub or lb are driven to v il under the valid address.(oe should be driven to v ih during the asynchronous write operation.) clock, adv , wait signals are ignored during the asynchronous (page) read operation. asynchronous write operation in syn- chronous mode a write operation starts when cs , we and ub or lb are driven to v il under the valid address. clock input does not have any affect to the write operation(oe should be driven to v ih during write operation. adv can be either toggling for address latch or held in v il ). clock, adv , wait signals are ignored during the asynchronous (page) read operation. synchronous burst operation burst mode operations enable the system to get high perfor- mance read and write operation. the address to be accessed is latched on the rising edge of clock or adv (whichever occurs first). cs should be setup before the address latch. during this first clock rising edge, we indicates whether the operation is going to be a read(we high) or a write(we low). for the optimized burst mode to each system, the system should determine how many clock cycles are required for the first data of each burst access(latency count), how many words the device outputs at an access(burst length) and which type of burst operation(burst type : linear ) is needed. the wait polarity should also be determined.(see table "mode register set") synchronous burst read operation the synchronous burst read command is implemented when the clock rising is detected during the adv low pulse. adv and cs should be set up before the clock rising. during read com- mand, we should be held in v ih . the multiple clock risings(dur- ing low adv period) are allowed but the burst operation starts from the first clock rising. the fi rst data will be out with latency count and tcd. synchronous burst write operation the synchronous burst write command is implemented when the clock rising is detected during the adv and we low pulse. adv , we and cs should be set up before the clock rising. the multiple clock risings(during low adv period) are allowed but the burst operation starts from the first clock rising. the first data will be written in the latency clock with tds. a22~a2 a1~a0 cs ub , lb oe data out high-z high-z high-z address cs ub , lb we data in data out fig.6 asynchronous 4-page read fig.7 asynchronous write clk adv addr. ub , lb oe data out cs wait 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 fig.8 synchronous burst read (latency 5, bl 4, wp : low enable) fig.9 synchronous burst write (latency 5, bl 4, wp : low enable) clk adv addr. ub , lb we data in cs wait 0 1 2 3 4 5 6 7 8 9 10 11 12 13
revision 1.0 april 2005 K1B3216BDD - 13 - u t ram address data out adv clock dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 data out dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 data out dq1 dq2 dq3 dq4 dq5 dq6 dq7 data out dq1 dq2 dq3 dq4 dq5 dq6 latency 3 latency 4 latency 5 latency 6 t synchronous burst o peration terminology clock(clk) the clock input is used as the reference for synchronous burst read and write operatio n of utram. the synchronous burst read an d write operation is synchronized to the rising edge of t he clock. the clock transitions must swing between v il and v ih . latency count the latency count configuration tells the dev ice how many clocks must elapse from the burst command before the first data shoul d be available on its data pins. this value depends on the input clock frequency. the supported latency count is as follows. table 8. latency count support : 3, 4, 5 table 9. number of clocks for 1st data fig.10 latency configuration(read) note : the first data will always keep the latency. from the second data, some per iod of wait time might be caused by wait pin. burst length burst length identifies how many data the device outputs at an ac cess. the device supports 4 word, 8 word and 16 word burst rea d or write. the first data will be out with the set latency + tcd. fr om the second data, the data will be out with tcd from each cl ock. burst stop burst stop is used when the system wants to stop bur st operation on special purpose. if driving cs to v ih during the burst read opera- tion, then the burst operation will be stopped. during the burst read operation, the new burst operation can not be issued. the new burst operation can be issued only after the previous burst operation is finished. the burst stop feature is very useful becaus e it enables the user to utilize the un-supported burst length such as 1 burst or 2 burst which accounts for big portion in usage for the mobile handset application environment. clock frequency upto 66mhz upto 54mhz upto 40mhz latency count 5 4 3 set latency latency 3 latency 4 latency 5 # of clocks for 1st data(read) 4 5 6 # of clocks for 1st data(write) 2 3 4
revision 1.0 april 2005 K1B3216BDD - 14 - u t ram synchronous burst operation terminology wait control(wait ) the wait signal is the device?s output signal whic h indicates to the host system when the device?s data-out or data-in is valid. to be compatible with the flash interfaces of various microprocessor types, the wait polarity(wp) can be configured. the polarity can be programmed to be either low enable or high enable. for the timing of wait signal, the wait signal should be set active one clock prior to the data regardless of read or write cycle. 12345678910111213 adv read clk dq0 dq1 0 dq2 fig.11 wait control and read/write latency control(late ncy : 5, burst length : 4, wp : low enable) write d0 d1 d2 dq3 d3 data out data in cs latency 5 latency 5 high-z wait high-z wait table 10. burst sequence start burst address sequence(decimal) length 4 word burst 8 word burst 16 word burst 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 4 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 5 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 6 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 7 7-0-1-2-3-4-5-6 7-8-9-10-11 -12-13-14-15-0-1-2-3-4-5-6 ~ ~ 14 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 15 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 burst type the device supports linear type burst sequence. linear type burst sequentially increments the burst address from the starting address. the detailed linear type burst address sequence is shown in burst sequence table.
revision 1.0 april 2005 K1B3216BDD - 15 - u t ram table 11. product list industrial temperature products (-40~85 c) part name function K1B3216BDD 1.8v, 70ns, 66mhz table 12. absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ra tings" may cause permanent damage to the device. functional ope ration should be restricted to be used under recommended operating condition. exposure to absolute maximum rating conditions longer than 1 secon d may affect reli- ability. item symbol ratings unit voltage on any pin relative to vss v in , v out -0.2 to v cc +0.3v v power supply voltage relative to vss v cc -0.2 to 2.5v v power dissipation p d 1.0 w storage temperature t stg -65 to 150 c operating temperature t a -40 to 85 c table 13. recommended dc operating conditions 1) 1. t a =-40 to 85 c, otherwise specified. 2. overshoot: v cc +1.0v in case of pulse width 3ns. 3. undershoot: -1.0v in case of pulse width 3ns. 4. overshoot and undershoot are sampled, not 100% tested. item symbol min typ max unit power supply voltage v cc 1.7 1.85 2.0 v ground vss 0 0 0 v input high voltage v ih 0.8 x v cc - v cc +0.2 2) v input low voltage v il -0.2 3) -0.3v table 14. capacitance 1) (f=1mhz, t a =25 c) 1. capacitance is sampled, not 100% tested. item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf table 15. dc and operating characteristics 1. standby mode is supposed to be set up after at least one active operation. i sb1 is measured after 60ms from the time when standby mode is set up. item symbol test conditions min typ max unit input leakage current i li v in =vss to v cc -1 - 1 a output leakage current i lo cs =v ih, oe =v ih or we =v il , v io =vss to v cc -1 - 1 a average operating current i cc2 cycle time=t rc +3t pc , i io =0ma, 100% duty, cs =v il , v in =v il or v ih --35ma output low voltage v ol i ol =0.1ma - - 0.2 v output high voltage v oh i oh =-0.1ma 1.4 - - v standby current(cmos) i sb1 1) cs v cc -0.2v, other inputs=vss to v cc - - 100 a
revision 1.0 april 2005 K1B3216BDD - 16 - u t ram ac operating conditions test conditions (test load and test input/output reference) input pulse level: 0.2 to v cc -0.2v input rising and falling time: 3ns input and output reference voltage: 0.5 x v cc output load: c l =30pf table 16. asynchronous ac characteristics (v cc =1.7~2.0v, t a =-40 to 85 c) 1. twc(min)=90ns or t wp (min)=70ns for continuous write operation over 50 times. parameter list symbol speed units min max async. (page) read cs high pulse width t cshp 10 - ns read cycle time t rc 70 - ns page read cycle time t pc 25 - ns address access time t aa -70ns page access time t pa -20ns chip select to output t co -70ns output enable to valid output t oe -35ns ub , lb access time t ba -35ns chip select to low-z output t lz 10 - ns ub , lb enable to low-z output t blz 5-ns output enable to low-z output t olz 5-ns chip disable to high-z output t chz 012ns ub , lb disable to high-z output t bhz 012ns output disable to high-z output t ohz 012ns output hold t oh 3-ns async. write write cycle time t wc 70 - ns chip select to end of write t cw 60 - ns adv minimum low pulse width t adv 7-ns address set-up time to beginning of write t as 0-ns address set-up time to adv falling t as(a) 0-ns address hold time from adv rising t ah(a) 7-ns cs setup time to adv rising t css(a) 10 - ns address valid to end of write t aw 60 - ns ub , lb valid to end of write t bw 60 - ns write pulse width t wp 55 1) -ns we high pulse width t whp 5 ns latency-1 clock - write recovery time t wr 0-ns we low to read latency t wlrl 1-clock data to write time overlap t dw 30 - ns data hold from write time t dh 0-ns figure 12. ac output load circuit vtt=0.5 x vddq 50 ? dout 30pf z0=50 ?
revision 1.0 april 2005 K1B3216BDD - 17 - u t ram asynchronous read timing waveform (asynchronous read cycle) 1. t chz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage leve ls. 2. at any given temperature and voltage condition, t chz (max.) is less than t lz (min.) both for a given devic e and from device to device interconnection. 3. in asynchronous read cycle, clock, adv and wait signals are ignored. fig.13 timing waveform of asynchronous read cycle ( we =v ih , wait =high-z) data valid high-z t rc t oh t aa t ba t oe t olz t blz t lz t ohz t bhz t chz t co address cs ub , lb oe data out table 17. asynchronous read ac characteristics symbol speed units symbol speed units min max min max t rc 70 - ns t olz 5-ns t aa -70nst blz 5-ns t co -70nst lz 10 - ns t ba -35nst chz 012ns t oe -35nst bhz 012ns t oh 3-nst ohz 012ns t cshp 10 - ns t chsp
revision 1.0 april 2005 K1B3216BDD - 18 - u t ram (asynchronous 4 page read cycle) 1. t chz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage leve ls. 2. at any given temperature and voltage condition, t chz (max.) is less than t lz (min.) both for a given devic e and from device to device interconnection. 3. in asynchronous 4 page read cycle, clock, adv and wait signals are ignored. fig.14 timing waveform of page read cycle ( we =v ih , wait =high-z) data valid data valid data valid data valid valid address valid address valid address valid address valid address t pc t pa a22~a2 a1~a0 cs oe t ohz t oe t co t aa data out t chz t oh ub , lb t bhz t ba t olz t blz high z t lz t rc asynchronous read timing waveform table 18. asynchronous page read ac characteristics symbol speed units symbol speed units min max min max t rc 70 - ns t oh 3-ns t aa -70nst olz 5-ns t pc 25 - ns t blz 5-ns t pa -20nst lz 10 - ns t co -70nst chz 012ns t ba -35nst bhz 012ns t oe -35nst ohz 012ns
revision 1.0 april 2005 K1B3216BDD - 19 - u t ram asynchronous write timing waveform table 19. asynchronous write ac characteristics (we controlled) 1. t wp (min)=70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t wc 70 - ns t as 0-ns t cw 60 - ns t wr 0-ns t aw 60 - ns t dw 30 - ns t bw 60 - ns t dh 0-ns t wp 55 1) -nst cshp 10 - ns address data valid ub , lb we data in t wc t cw t bw t wp t dh t dw t wr t aw t as cs data out high-z high-z t wc t as t wr data valid t dh t dw t whp t wp t cw t aw t bw fig.15 timing waveform of write cycle(1) ( oe =v ih , wait =high-z, we controlled) (asynchronous write cycle - we controlled) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest transition when cs goes high or we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs or we going high. 5. in asynchronous write cycle, clock, adv and wait signals are ignored. 6. condition for continuous write operation over 50 times : t wp (min)=70ns t cshp
revision 1.0 april 2005 K1B3216BDD - 20 - u t ram address data valid ub , lb we data in data out high-z high-z t wc t cw t bw t wp t dh t dw t wr t aw t as cs fig.16 timing waveform of write cycle(2) ( oe =v ih , wait =high-z, ub & lb controlled) (asynchronous write cycle - ub & lb controlled) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest transition when cs goes high or we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs or we going high. 5. in asynchronous write cycle, clock, adv and wait signals are ignored. asynchronous write timing waveform table 20. asynchronous write ac characteristics (ub & lb controlled) 1. twc(min)=90ns or t wp (min)=70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t wc 70 - ns t as 0-ns t cw 60 - ns t wr 0-ns t aw 60 - ns t dw 30 - ns t bw 60 - ns t dh 0-ns t wp 55 1) -ns
revision 1.0 april 2005 K1B3216BDD - 21 - u t ram fig.17 timing waveform of write cycle(address latch type) ( oe =v ih , wait =high-z, we controlled) ub , lb we data in t bw t wp t dh t dw data valid (address latch type asynchronous write cycle - we controlled) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for word operation. a write ends at the earliest transition when cs goes high or we goes high. the t wp is measured from the beginning of write to the end of write. 2. t aw is measured from the address valid to the end of write. in this address latch type write timing, t wc is same as t aw. 3. t cw is measured from the cs going low to the end of write. 4. t bw is measured from the ub and lb going low to the end of write. 5. clock input does not have any affect to the write operation if the parameter twlrl is met. asynchronous write timing waveform in synchronous mode adv address cs valid t as(a) t ah(a) t css(a) t cw data out high-z 12345678910111213 clk 0 t as read latency 5 high-z t wlrl 14 t aw table 21. asynch. write in synch. mode ac characteristics (address latch type, we controlled) 1. twc(min)=90ns or t wp (min)=70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t adv 7-nst bw 60 - ns t as(a) 0-nst wp 55 1) -ns t ah(a) 7-nst wlrl 1-clock t css(a) 10 - ns t as 0-ns t cw 60 - ns t dw 30 - ns t aw 60 - ns t dh 0-ns t adv
revision 1.0 april 2005 K1B3216BDD - 22 - u t ram (address latch type asynchronous write cycle - ub & lb controlled) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for word operation. a write ends at the earliest transition when cs goes or and we goes high. the t wp is measured from the beginning of write to the end of write. 2. t aw is measured from the address valid to the end of write. in this address latch type write timing, t wc is same as t aw. 3. t cw is measured from the cs going low to the end of write. 4. t bw is measured from the ub and lb going low to the end of write. 5. clock input does not have any affect to the write operation if the parameter twlrl is met. fig.18 timing waveform of wr ite cycle(address latch type) ( oe =v ih , wait =high-z, ub & lb controlled) ub , lb we data in t bw t wp t dh t dw data valid adv address cs valid t as(a) t ah(a) t css(a) t cw data out high-z 12345678910111213 clk 0 t as read latency 5 high-z t wlrl 14 t aw t adv asynchronous write timing waveform in synchronous mode table 22. asynch. write in synch. mode ac characteristics (address latch type, ub & lb controlled) 1. twc(min)=90ns or t wp (min)=70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t adv 7-nst bw 60 - ns t as(a) 0-nst wp 55 1) -ns t ah(a) 7-nst wlrl 1-clock t css(a) 10 - ns t as 0-ns t cw 60 - ns t dw 30 - ns t aw 60 - ns t dh 0-ns
revision 1.0 april 2005 K1B3216BDD - 23 - u t ram (low adv type write cycle - we controlled) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest transition when cs goes high or we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs or we going high. 5. clock input does not have any affect to the write operation if the parameter twlrl is met. fig.19 timing wavefor m of write cycle(low adv type) ( oe =v ih , wait =high-z, we controlled) asynchronous write timing waveform in synchronous mode address data valid ub , lb we data in t wc t cw t bw t wp t dh t dw t wr t aw t as cs adv data out high-z high-z 123456789 clk 0 read latency 5 10 11 12 13 14 t wlrl table 23. asynch. write in synch. mode ac characteristics (low adv type, we controlled) 1. twc(min)=90ns or t wp (min)=70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t wc 70 - ns t wlrl 1-clock t cw 60 - ns t as 0-ns t aw 60 - ns t wr 0-ns t bw 60 - ns t dw 30 - ns t wp 55 1) -nst dh 0-ns
revision 1.0 april 2005 K1B3216BDD - 24 - u t ram (low adv type write cycle - ub & lb controlled) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest transition when cs goes high or we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs or we going high. 5. clock input does not have any affect to the write operation if the parameter twlrl is met. fig.20 timing wavefor m of write cycle(low adv type) ( oe =v ih , wait =high-z, ub & lb controlled) address data valid ub , lb we data in t wc t cw t bw t wp t dh t dw t wr t aw t as cs adv data out high-z clk read latency 5 123456789 0 10 11 12 13 14 t wlrl high-z asynchronous write timing waveform in synchronous mode table 24. asynch. write in synch. mode ac characteristics (low adv type, ub & lb controlled) 1. twc(min)=90ns or t wp (min)=70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t wc 70 - ns t wlrl 1-clock t cw 60 - ns t as 0-ns t aw 60 - ns t wr 0-ns t bw 60 - ns t dw 30 - ns t wp 55 1) -nst dh 0-ns
revision 1.0 april 2005 K1B3216BDD - 25 - u t ram fig.21 timing waveform of multiple write cycle(low adv type) ( oe =v ih , wait =high-z, we controlled) asynchronous write timing waveform in synchronous mode address data valid ub , lb we data in t wc t cw t bw t wp t dh t dw t wr t aw t as cs adv data out high-z high-z 123456789 clk 0 10 11 12 13 t wc t as t wr data valid t dh t dw t whp t wp t cw t aw t bw (low adv type multiple write cycle) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest transition when cs goes high or we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs or we going high. 5. clock input does not have any affect to the asynchronous multiple write operation if t whp is shorter than (read latency - 1) clock duration. 6. t wp (min)=70ns for continuous wr ite operation over 50 times. 14 table 25. asynch. write in synch. mode ac characteristics (low adv type multiple write, we controlled) 1. twc(min)=90ns or t wp (min)=70ns for continuous write operation over 50 times. symbol speed units symbol speed units min max min max t wc 70 - ns t whp 5ns latency-1 clock - t cw 60 - ns t as 0-ns t aw 60 - ns t wr 0-ns t bw 60 - ns t dw 30 - ns t wp 55 1) -nst dh 0-ns
revision 1.0 april 2005 K1B3216BDD - 26 - u t ram table 26. synchronous ac characteristics (v cc =1.7~2.0v, t a =-40 to 85 c, maximum main clock fre- quency=66mhz) parameter list symbol speed units min max burst operation (common) clock cycle time t 15 200 ns burst cycle time t bc - 2500 ns address set-up time to adv falling(burst) t as(b) 0-ns address hold time from adv rising(burst) t ah(b) 7-ns adv setup time t advs 5-ns adv hold time t advh 7-ns cs setup time to clock rising(burst) t css(b) 5-ns burst end to new adv falling t beadv 7-ns burst stop to new adv falling t bsadv 12 - ns cs low hold time from clock t cslh 7-ns cs high pulse width t cshp 5-ns adv high pulse width t adhp 5-ns chip select to wait low t wl -10ns adv falling to wait low t awl -10ns clock to wait high t wh -12ns chip de-select to wait high-z t wz -12ns burst read operation ub , lb enable to end of latency clock t bel 1-clock output enable to end of latency clock t oel 1-clock ub , lb valid to low-z output t blz 5-ns output enable to low-z output t olz 5-ns latency clock rising edge to data output t cd -10ns output hold t oh 3-ns burst end clock to output high-z t hz -12ns chip de-select to output high-z t chz -12ns output disable to output high-z t ohz -12ns ub , lb disable to output high-z t bhz -12ns burst write operation we set-up time to command clock t wes 5-ns we hold time from command clock t weh 5-ns we high pulse width t whp 5-ns ub , lb set-up time to clock t bs 5-ns ub , lb hold time from clock t bh 5-ns byte masking set-up time to clock t bms 7-ns byte masking hold time from clock t bmh 7-ns data set-up time to clock t ds 5-ns data hold time from clock t dhc 3-ns ac operating conditions test conditions (test load and test input/output reference) input pulse level: 0.2 to v cc -0.2v input rising and falling time: 3ns input and output reference voltage: 0.5 x v cc output load: c l =30pf vtt=0.5 x vddq 50 ? dout 30pf z0=50 ? figure 22. ac output load circuit
revision 1.0 april 2005 K1B3216BDD - 27 - u t ram 123456789101112131415 adv address clk t advs t advh t as(b) t ah(b) t 0 t beadv don?t care valid valid burst command clock burst read end clock data out dq0 dq1 dq2 dq3 undefined data in d0 d1 d3 d0 d2 t beadv burst write end clock fig.23 timing waveform of basic burst operation [latency=5,burst length=4] synchronous burst operation timing waveform table 27. burst operation ac characteristics symbol speed units symbol speed units min max min max t 15 200 ns t as(b) 0-ns t bc - 2500 ns t ah(b) 7-ns t advs 5-nst css(b) 5-ns t advh 7-nst beadv 7-ns cs t css(b) t bc
revision 1.0 april 2005 K1B3216BDD - 28 - u t ram 123456789101112131415 adv address cs lb , ub data out oe clk dq0 dq1 dq2 dq3 undefined t cd valid latency 5 t hz valid t advs t advh t as(b) t ah(b) t css(b) t t oh don?t care fig.24 timing waveform of burst read cycle(1) [latency=5,burst length=4,wp=low enable] (we =v ih ) synchronous burst read timing waveform (synchronous burst read cycle - cs toggling consecutive burst read) 1. the new burst operation can be issued only after the previ ous burst operation is finished. for the new burst operation, tbea dv should be met. 2. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 4. burst cycle time(tbc) should not be over 2.5 s. wait t blz t bel t oel t olz high-z 0 t wh t wl t wz t chz t ohz t bhz t cshp t wl t wh - cs toggling consecutive burst read t beadv t bc table 28. burst read ac characteristics (cs toggling consecutive burst) symbol speed units symbol speed units min max min max t cshp 5-nst ohz -12ns t bel 1-clockt bhz -12ns t oel 1-clockt cd -10ns t blz 5-nst oh 3-ns t olz 5-nst wl -10ns t hz -12nst wh -12ns t chz -12nst wz -12ns
revision 1.0 april 2005 K1B3216BDD - 29 - u t ram 123456789101112131415 adv address cs lb , ub data out oe clk dq0 dq1 dq2 dq3 undefined t cd valid latency 5 t hz valid t advs t advh t as(b) t ah(b) t css(b) t t oh don?t care fig.25 timing waveform of burst read cycle(2) [latency=5,burst length=4,wp=low enable] (we =v ih ) synchronous burst read timing waveform (synchronous burst read cycle - cs low holding consecutive burst read) 1. the new burst operation can be issued only after the previ ous burst operation is finished. for the new burst operation, tbea dv should be met. 2. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 4. the consecutive multiple burst read operation with holding cs low is possible through issuing only new adv and address. 5. burst cycle time(tbc) should not be over 2.5 s. wait t blz t bel t oel t olz high-z 0 t wh t wl t awl t wh - cs low holding consecutive burst read t beadv t bc table 29. burst read ac characteristics (cs low holding consecutive burst) symbol speed units symbol speed units min max min max t bel 1-clockt cd -10ns t oel 1-clockt oh 3-ns t blz 5-nst wl -10ns t olz 5-nst awl -10ns t hz -12nst wh -12ns
revision 1.0 april 2005 K1B3216BDD - 30 - u t ram fig.26 timing waveform of burst read cycle(3) [latency=5,burst length=4,wp=low enable] (we =v ih ) adv address cs lb , ub data out oe clk dq0 dq1 dq2 undefined t cd valid latency 5 t advs t advh t as(b) t ah(b) t css(b) t t oh don?t care dq3 (synchronous burst read cycle - last data sustaining) 1. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 2. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 3. burst cycle time(tbc) should not be over 2.5 s. 1234567891011121314 synchronous burst read timing waveform t bel t oel t blz t olz wait high-z 0 t wl t wh t bc - last data sustaining table 30. burst read ac characteristics (last data sustaining) symbol speed units symbol speed units min max min max t bel 1-clockt cd -10ns t oel 1-clockt oh 3-ns t blz 5-nst wl -10ns t olz 5-nst wh -12ns
revision 1.0 april 2005 K1B3216BDD - 31 - u t ram 12345678910111213 adv address cs lb , ub data in we clk d0 d1 d2 d3 valid t advs t advh t as(b) t ah(b) t css(b) t t dhc fig.27 timing waveform of burst write cycle(1) [latency=5,burst length=4,wp=low enable] (oe =v ih ) synchronous burst write timing waveform (synchronous burst write cycle - cs toggling consecutive burst write) 1. the new burst operation can be issued only after the previ ous burst operation is finished. for the new burst operation, tbea dv should be met. 2. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 3. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 4. d2 is masked by ub and lb . 5. burst cycle time(tbc) should not be over 2.5 s. wait 0 t wes t weh t ds t dhc don?t care t bms t bmh latency 5 high-z t wl t wh valid t bs t bh d0 t whp t cshp t wz t wl latency 5 valid valid t wh - cs toggling consecutive burst write t beadv t bc table 31. burst write ac characteristics (cs toggling consecutive burst) symbol speed units symbol speed units min max min max t cshp 5-nst whp 5-ns t bs 5-nst ds 5-ns t bh 5-nst dhc 3-ns t bms 7-nst wl -10ns t bmh 7-nst wh -12ns t wes 5-nst wz -12ns t weh 5-ns
revision 1.0 april 2005 K1B3216BDD - 32 - u t ram 12345678910111213 adv address cs lb , ub data in we clk d0 d1 d2 d3 valid t advs t advh t as(b) t ah(b) t css(b) t t dhc fig.28 timing waveform of burst write cycle(2) [latency=5,burst length=4,wp=low enable] (oe =v ih ) synchronous burst write timing waveform (synchronous burst write cycle - cs low holding consecutive burst write) 1. the new burst operation can be issued only after the previ ous burst operation is finished. for the new burst operation, tbea dv should be met. 2. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 3. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 4. d2 is masked by ub and lb . 5. the consecutive multiple burst read operation with holding cs low is possible through issuing only new adv and address. 6. burst cycle time(tbc) should not be over 2.5 s. wait 0 t wes t weh t ds t dhc don?t care t bms t bmh latency 5 high-z t wl t wh valid t bs t bh d0 t whp t awl latency 5 valid valid t wh - cs low holding consecutive burst write t beadv t bc table 32. burst write ac characteristics (cs low holding consecutive burst) symbol speed units symbol speed units min max min max t bs 5-nst whp 5-ns t bh 5-nst ds 5-ns t bms 7-nst dhc 3-ns t bmh 7-nst wl -10ns t wes 5-nst awl -10ns t weh 5-nst wh -12ns
revision 1.0 april 2005 K1B3216BDD - 33 - u t ram fig.29 timing waveform of burst read stop by cs [latency=5,burst length=4,wp=low enable] (we =v ih ) 1234567891011121314 adv address cs lb , ub data oe clk dq0 undefined t cd don?t care valid latency 5 valid t advs t advh t as(b) t ah(b) t css(b) t t oh t chz synchronous burst read stop timing waveform wait t bel t oel t blz t olz t cslh (synchronous burst read stop timing) 1. the new burst operation can be issued only after the previous burst operation is finished. for the new burst operation, tbsa dv should be met 2. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 4. the burst stop operation should not be repeated for over 2.5 s. t cshp high-z 0 high-z t wl t wh t wz t wl dq1 t bsadv table 33. burst read stop ac characteristics symbol speed units symbol speed units min max min max t bsadv 12 - ns t cd -10ns t cslh 7-nst oh 3-ns t cshp 5-nst chz -12ns t bel 1-clockt wl -10ns t oel 1-clockt wh -12ns t blz 5-nst wz -12ns t olz 5-ns
revision 1.0 april 2005 K1B3216BDD - 34 - u t ram fig.30 timing waveform of burst write stop by cs [latency=5,burst length=4,wp=low enable] (oe =v ih ) synchronous burst write stop timing waveform 12345678910111213 adv address cs lb , ub data in we clk d0 d1 valid t advs t advh t as(b) t ah(b) t css(b) t t dhc (synchronous burst write stop timing) 1. the new burst operation can be issued only after the previous burst operation is finished. 2. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 4. the burst stop operation should not be repeated for over 2.5 s. wait 0 t wes t weh t ds valid d0 t cshp t cslh high-z high-z t wl t wh t wz t wl latency 5 latency 5 t wh d1 d2 don?t care t whp t bsadv table 34. burst write stop ac characteristics symbol speed units symbol speed units min max min max t bsadv 12 - ns t whp 5-ns t cslh 7-nst ds 5-ns t cshp 5-nst dhc 3-ns t bs 5-nst wl -10ns t bh 5-nst wh -12ns t wes 5-nst wz -12ns t weh 5-ns t bs t bh
revision 1.0 april 2005 K1B3216BDD - 35 - u t ram fig.31 timing waveform of burst read suspend cycle(1) [latency=5,burst length=4,wp=low enable] (we =v ih ) 123456 7891011 adv address cs lb , ub data out oe clk dq0 dq1 dq2 undefined t cd valid latency 5 t hz t advs t advh t as(b) t ah(b) t css(b) t don?t care synchronous burst read suspend timing waveform (synchronous burst read suspend cycle) 1. if clock input is halted during burst read operation, the data out will be suspended. during the burst read suspend period, oe high drives data out to high-z. if clock input is resumed, the suspended data will be out first. 2. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. during suspend period, oe high drives dq to high-z and oe low drives dq to low-z. if oe stays low during suspend period, the previous data will be sustained. 4. burst cycle time(tbc ) should not be over 2.5 s. wait t blz t bel t oel t olz high-z 0 t wh t wl dq1 t wz t ohz t olz dq3 high-z t bc table 35. burst read suspend ac characteristics symbol speed units symbol speed units min max min max t bel 1-clockt hz -12ns t oel 1-clockt ohz -12ns t blz 5-nst wl -10ns t olz 5-nst wh -12ns t cd -10nst wz -12ns t oh 3-ns t oh
revision 1.0 april 2005 K1B3216BDD - 36 - u t ram fig.32 synch. burst read to asynch. wr ite(address latch type) timing waveform 12345678910111213 1920 adv address cs lb , ub data out oe clk dq0 t cd valid latency 5 t hz valid t css(b) t t oh don?t care t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 21 dq1 dq3 dq2 we t css(a) data in t dh t dw data valid high-z high-z t as(a) t ah(a) [latency=5, burst length=4] t beadv (synchronous burst read cycle) 1. the new burst operation can be issued only after the previ ous burst operation is finished. for the new burst operation, tbea dv should be met. 2. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 4. burst cycle time(tbc) should not be over 2.5 s. (address latch type asynchronous write cycle - we controlled) 1. clock input does not have any affect to the write operation if we is driven to low before read late ncy-1 clock. read latency-1 clock in write timing is just a reference to we low going for proper write operation. t as read latency 5 0 t wp t wlrl t cw t aw t bw transition timing waveform between read and write t bc table 36. burst read to asynch. write( address latch type) ac characteristics symbol speed units symbol speed units min max min max t beadv 7-nst wlrl 1-clock wait high-z t wh t wl t wz high-z t adv
revision 1.0 april 2005 K1B3216BDD - 37 - u t ram 12345678910111213 1920 adv address cs lb , ub data out oe clk dq0 t cd valid latency 5 t hz t css(b) t t oh don?t care t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 21 dq1 dq2 we data in t dh t dw data valid high-z high-z t beadv t aw t cw t wp t bw fig.33 synch. burst read to asynch. write(low adv type) timing waveform [latency=5, burst length=4] t as t wr valid address (synchronous burst read cycle) 1. the new burst operation can be issued only after the previ ous burst operation is finished. for the new burst operation, tbea dv should be met. 2. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 4. burst cycle time(tbc) should not be over 2.5 s. (low adv type asynchronous write cycle - we controlled) 1. clock input does not have any affect to the write operation if we is driven to low before read latency-1 clock. read latency-1 clock in write timing is just a reference to we low going for proper write operation. read latency 5 transition timing waveform between read and write table 37. burst read to asynch. write(low adv type) ac characteristics symbol speed units symbol speed units min max min max t beadv 7-nst wlrl 1-clock t wlrl wait high-z t wh t wl t wz dq3 t bc high-z
revision 1.0 april 2005 K1B3216BDD - 38 - u t ram fig.34 asynch. write(address latch type ) to synch. burst read timing waveform [latency=5, burst length=4] 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv address cs lb , ub data out oe clk dq0 t cd valid latency 5 t hz valid t css(a) t t oh t bel t oel t advs t advh t as(a) t ah(a) 14 15 16 17 18 0 dq1 dq3 dq2 we t css(b) data in high-z t as(b) t ah(b) t wp t bw (synchronous burst read cycle) 1. the new burst operation can be issued only after the previ ous burst operation is finished. for the new burst operation, tbea dv should be met. 2. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 4. burst cycle time(tbc) should not be over 2.5 s. (address latch type asynchronous write cycle - we controlled) 1. clock input does not have any affect to the write operation if we is driven to low before read latency-1 clock. read latency-1 clock in write timing is just a reference to we low going for proper write operation. t as read latency 5 t dh t dw data valid don?t care don?t care t aw t cw transition timing waveform between read and write t adv t wlrl table 38. asynch. write(address latch type) to burst read ac characteristics symbol speed units symbol speed units min max min max t wlrl 1-clock wait high-z t wh t wl t wz t bc
revision 1.0 april 2005 K1B3216BDD - 39 - u t ram fig.35 asynch. write(low adv type) to synch. burst read timing waveform [latency=5, burst length=4] 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv address cs lb , ub data out oe clk dq0 t cd latency 5 t hz valid t t oh t bel t oel t advs t advh 14 15 16 17 18 0 dq1 dq3 dq2 we t css(b) data in high-z t as(b) t ah(b) t as t dh t dw data valid don?t care t aw t cw valid t wr t wp t bw t wc t adhp (synchronous burst read cycle) 1. the new burst operation can be issued only after the previ ous burst operation is finished. for the new burst operation, tbea dv should be met. 2. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 4. burst cycle time(tbc) should not be over 2.5 s. (low adv type asynchronous write cycle - we controlled) 1. clock input does not have any affect to the write operation if we is driven to low before read latency-1 clock. read latency-1 clock in write timing is just a reference to we low going for proper write operation. read latency 5 transition timing waveform between read and write table 39. asynch. write(low adv type) to burst read ac characteristics symbol speed units symbol speed units min max min max t wlrl 1-clockt adhp 5-ns t wlrl wait high-z t wh t wl t wz t bc
revision 1.0 april 2005 K1B3216BDD - 40 - u t ram high-z fig.36 synch. burst read to synch. burst write timing waveform [latency=5, burst length=4] transition timing waveform between read and write 12345678910111213 1920 adv address cs lb , ub data out oe clk dq0 t cd valid latency 5 t hz valid t css(b) t t oh don?t care t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 21 dq1 dq3 dq2 we t css(b) data in high-z high-z t beadv 0 t bc t as(b) t ah(b) d1 d3 d2 high-z d0 wait t wh t wl t wz latency 5 t bc t wes t weh t bs t bh t ds t dhc t wz t wl t wh table 40. burst read to burst write ac characteristics symbol speed units symbol speed units min max min max t beadv 7-ns (synchronous burst read & write cycle) 1. the new burst operation can be issued only after the previ ous burst operation is finished. for the new burst operation, tbea dv should be met. 2. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 4. burst cycle time(tbc) should not be over 2.5 s.
revision 1.0 april 2005 K1B3216BDD - 41 - u t ram high-z fig.37 synch. burst write to sy nch. burst read timing waveform [latency=5, burst length=4] transition timing waveform between read and write 12345678910111213 1920 adv address cs lb , ub data out oe clk t cd valid latency 5 t hz valid t css(b) t t oh don?t care t bel t oel t advs t advh t as(b) t ah(b) 14 15 16 17 18 21 we t css(b) data in high-z t beadv 0 t bc t as(b) t ah(b) d1 d2 wait t wh t wl latency 5 t bc t wes t weh t bs t bh t ds t dhc t wz t wl t wh table 41. burst write to burst read ac characteristics symbol speed units symbol speed units min max min max t beadv 7-ns (synchronous burst read & write cycle) 1. the new burst operation can be issued only after the previ ous burst operation is finished. for the new burst operation, tbea dv should be met. 2. /wait low(twl or tawl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the burst operation starts from the first clock rising. 4. burst cycle time(tbc) should not be over 2.5 s. d3 d0 dq0 dq1 dq3 dq2 high-z
revision 1.0 april 2005 K1B3216BDD - 42 - u t ram package dimension package dimension 654321 a b c d e f g h c b c1 b c bottom view top view d e1 e c side view a y detail a min typ max a - 0.75 - b 5.90 6.00 6.10 b1 - 3.75 - c 7.90 8.00 8.10 c1 - 6.00 - d 0.40 0.45 0.50 e- -1.00 e1 0.25 - - y- -0.10 b1 #a1 notes. 1. ball counts: 54(9 row x 6 column) 2. ball pitch: (x,y)=(0.75 x 0.75)(typ.) 3. all tolerence are 0.050 unless specified beside figure. 4. typ: typical 5. y is coplanarity unit: millimeters 54 ball fine pitch ball grid array(0.75mm ball pitch) e1 j

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