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SRC4192 (1) src4193 (1) 192khz stereo asynchronous sample rate converters description the SRC4192 and src4193 are asynchronous sample rate converters designed for professional and broadcast audio applications. the SRC4192 and src4193 combine a wide input-to-output sampling ratio with outstanding dynamic range and ultra low distortion. input and output serial ports support standard audio formats, as well as a time division multi- plexed (tdm) mode. flexible audio interfaces allow the SRC4192 and src4193 to connect to a wide range of audio data converters, digital audio receivers and transmitters, and digital signal processors. the SRC4192 is a standalone pin programmed device, with control pins for mode, data format, mute, bypass, and low group delay functions. the src4193 is a software-controlled device featuring a serial peripheral interface (spi) port, which is utilized to program all functions via internal control registers. the SRC4192 and src4193 may be operated from a single +3.3v power supply. a separate digital i/o supply (v io ) operates over the +1.65v to +3.6v supply range, allowing greater flexibility when interfacing to current and future gen- eration signal processors and logic devices. both the SRC4192 and src4193 are available in a 28-lead ssop package. features automatic sensing of the input-to- output sampling ratio wide input-to-output sampling range: 16:1 to 1:16 supports input & output sampling rates up to 212khz dynamic range: 144db (-60dbfs input, bw = 20hz to f s /2, a-weighted) thd+n: -140db (0dbfs input, bw = 20hz to f s /2) attenuates sampling and reference clock jitter high performance, linear phase digital filtering with better than 140db of stop band attenuation flexible audio serial ports: master or slave mode operation supports i 2 s, left justified, right justified, and tdm data formats supports 16, 18, 20, or 24-bit audio data tdm mode allows daisy chaining of up to eight devices supports 24-, 20-, 18-, or 16-bit input and output data all output data is dithered from the internal 28-bit data path low group delay option for interpo- lation filter direct downsampling option for decimation filter (src4193 only) spi port provides access to internal control registers (src4193 only) soft mute function bypass mode programmable digital output attenuation (src4193 only) 256 steps: 0db to C127.5db, 0.5db/step applications digital mixing consoles digital audio workstations audio distribution systems broadcast studio equipment high-end a/v receivers general digital audio processing www.ti.com production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. copyright ?2003, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. sbfs022a ?july 2003 all trademarks are the property of their respective owners. power down mode operates from a single +3.3 volt power supply small 28-lead ssop package pin compatible with the ad1896 (SRC4192 only) (2) (1) patents pending. (2) refer to the applications information section of this data sheet for details. s r c 4 1 9 2 s r c 4 1 9 3
SRC4192, src4193 sbfs022a 2 www.ti.com supply voltage, v dd .......................................................... ?.3v to +4.0v supply voltage, v io ........................................................... ?.3v to +4.0v digital input voltage .......................................................... ?.3v to +4.0v operating temperature range ........................................ ?5 c to +85 c storage temperature range ......................................... ?5 c to +150 c note: (1) stresses above these ratings may cause permanent damage. exposure to absolute maximum conditions for extended periods may de- grade device reliability. these are stress ratings only, and functional opera- tion of the device at these or any other conditions beyond those specified is not implied. pin configuration (SRC4192) specified package temperature package ordering transport product package-lead designator (1) range marking number media, quantity SRC4192 ssop-28 db ?5 c to +85 c SRC4192i SRC4192idb rails, 50 " """" SRC4192idbr tape and reel, 2000 src4193 ssop-28 db ?5 c to +85 c src4193i src4193idb rails, 50 " """" src4193idbr tape and reel, 2000 note: (1) for the most current specifications and package information, refer to our web site at www.ti.com. package/ordering information absolute maximum ratings (1) top view lgrp rcki nc sdin bcki lrcki vio dgnd bypas ifmt0 ifmt1 ifmt2 rst mute mode2 mode1 mode0 bcko lrcko sdout vdd dgnd tdmi ofmt0 ofmt1 owl0 owl1 rdy 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SRC4192 pin# name description 1 lgrp low group delay control input (active high) 2 rcki reference clock input 3 n.c. no connection 4 sdin audio serial data input 5 bcki input port bit clock i/o 6 lrcki input port left/right word clock i/o 7v io digital i/o supply, +1.65v to v dd 8 dgnd digital ground 9 bypas asrc bypass control input (active high) 10 ifmt0 input port data format control input 11 ifmt1 input port data format control input 12 ifmt2 input port data format control input 13 rst reset input (active low) 14 mute output mute control input (active high) 15 rdy asrc ready status output (active low) 16 owl1 output port data word length control input 17 owl0 output port data word length control input 18 ofmt1 output port data format control input 19 ofmt0 output port data format control input 20 tdmi tdm data input (connect to dgnd when not in use) 21 dgnd digital ground 22 v dd digital core supply, +3.3v 23 sdout audio serial data output 24 lrcko output port left/right word clock i/o 25 bcko output port bit clock i/o 26 mode0 serial port mode control input 27 mode1 serial port mode control input 28 mode2 serial port mode control input pin descriptions (SRC4192) electrostatic discharge sensitivity this integrated circuit can be damaged by esd. texas instru- ments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
SRC4192, src4193 sbfs022a 3 www.ti.com pin# name description 1 rcki reference clock input 2 n.c. no connection 3 n.c. no connection 4 sdin audio serial data input 5 bcki input port bit clock i/o 6 lrcki input port left/right word clock i/o 7v io digital i/o supply, +1.65v to v dd 8 dgnd digital ground 9 bypas asrc bypass control input (active high) 10 n.c. no connection 11 n.c. no connection 12 n.c. no connection 13 rst reset input (active low) 14 mute output mute control input (active high) 15 rdy asrc ready status output (active low) 16 ratio input-to-output ratio flag output low output denotes output rate lower than input rate. high output denotes output rate higher than input rate. 17 n.c. no connection 18 n.c. no connection 19 n.c. no connection 20 tdmi tdm data input (connect to dgnd when not in use) 21 dgnd digital ground 22 v dd digital core supply, +3.3v 23 sdout audio serial data output 24 lrcko output port left/right word clock i/o 25 bcko output port bit clock i/o 26 cs spi port chip select input (active low) 27 cclk spi port data clock input 28 cdata spi port serial data input pin configuration (src4193) top view rcki nc nc sdin bcki lrcki vio dgnd bypas nc nc nc rst mute cdata cclk cs bcko lrcko sdout v dd dgnd tdmi nc nc nc ratio rdy 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 src4193 pin descriptions (src4193)
SRC4192, src4193 sbfs022a 4 www.ti.com SRC4192, src4193 parameter condition min typ max units dynamic performance (1) resolution 24 bits input sampling frequency f sin 4 212 khz output sampling frequency f sout 4 212 khz input: output sampling ratio upsampling 1:16 downsampling 16:1 dynamic range bw = 20hz to f sout /2, 60dbfs input f in = 1khz, unweighted (add 3db to spec for a-weighted result) 44.1khz; 48khz 140 db 48khz; 44.1khz 140 db 48khz; 96khz 140 db 44.1khz; 192khz 138 db 96khz; 48khz 141 db 192khz; 12khz 141 db 192khz; 32khz 141 db 192khz; 48khz 141 db 32khz; 48khz 140 db 12khz; 192khz 138 db total harmonic distortion + noise bw = 20hz to f sout /2, 0dbfs input f in = 1khz, unweighted 44.1khz; 48khz 140 db 48khz; 44.1khz 140 db 48khz; 96khz 140 db 44.1khz; 192khz 137 db 96khz; 48khz 140 db 192khz; 12khz 140 db 192khz; 32khz 141 db 192khz; 48khz 141 db 32khz; 48khz 140 db 12khz; 192khz 137 db interchannel gain mismatch 0db interchannel phase deviation 0 degrees digital attenuation src4193 only minimum 0db maximum 127.5 db step size 0.5 db mute attenuation 24-bit word length, a-weighted 144 db digital interpolation filter characteristics passband 0.4535 x f sin hz passband ripple 0.007 db transition band 0.4535 x f sin 0.5465 x f sin hz stop band 0.5465 x f sin hz stop band attenuation 144 db normal group delay (lgrp = 0) decimation filter on (dflt = 0) 102.53125/f sin seconds normal group delay (lgrp = 0) decimation filter off (dflt = 1) 102/f sin seconds low group delay (lgrp = 1) decimation filter on (dflt = 0) 70.53125/f sin seconds low group delay (lgrp = 1) decimation filter off (dflt = 1) 70/f sin seconds digital decimation filter characteristics passband 0.4535 x f sout hz passband ripple 0.008 db transition band 0.4535 x f sout 0.5465 x f sout hz stop band 0.5465 x f sout hz stop band attenuation 143 db group delay decimation filter dflt = 0 for src4193 36.46875/f sout seconds direct down-sampling src4193 only, dflt = 1 0 seconds digital i/o characteristics high-level input voltage v ih 0.7 x v io v io v low level input voltage v il 0 0.3 x v io v high-level input current i ih 0.5 10 a low-level input current i il 0.5 10 a high-level output voltage v oh i o = 4ma 0.8 x v io v io v low-level output voltage v ol i o = +4ma 0 0.2 x v io v input capacitance c in 3pf electrical characteristics all parameters specified with t a = +25 c, v dd = +3.3v, and v io = +3.3v, unless otherwise noted.
SRC4192, src4193 sbfs022a 5 www.ti.com switching characteristics reference clock timing rcki frequency (2), (3) 128 x f smin 50 mhz rcki period t rckip 20 1/(128 x f smin )ns rcki pulsewidth high t rckih 0.4 x t rckip ns rcki pulsewidth low t rckil 0.4 x t rckip ns reset timing rst pulse width low t rstl 500 ns delay following rst rising edge src4193 only 500 s input serial port timing lrcki to bcki setup time t lris 10 ns bcki pulsewidth high t sih 10 ns bcki pulsewidth low t sil 10 ns sdin data setup time t ldis 10 ns sdin data hold time t ldih 10 ns output serial port timing sdout data delay time t dopd 10 ns sdout data hold time t doh 2ns bcko pulsewidth high t soh 10 ns bcko pulsewidth low t sol 5ns tdm mode timing lrcko setup time t lros 10 ns lrcko hold time t lroh 10 ns tdmi data setup time t tdms 10 ns tdmi data hold time t tdmh 10 ns spi timing cclk frequency 25 mhz cdata setup time t cds 12 ns cdata hold time t cdh 8ns cs falling to cclk rising t cscr 15 ns cclk falling to cs rising t cfcs 12 ns power supplies operating voltage v dd 3.0 +3.3 3.6 v v io 1.65 +3.3 3.6 v supply current v dd = +3.3v, v io = +3.3v i dd , power down rst = 0, no clocks 100 a i dd , power down (src4193 only) pdn bit = 0, no clocks 5 ma i dd , dynamic f sin = f sout = 192khz 66 ma i io , power down rst = 0, no clocks 100 a i io , power down (src4193 only) pdn bit = 0, no clocks 21 a i io , dynamic f sin = f sout = 192khz 2 ma total power dissipation v dd = +3.3v, v io = +3.3v p d , power down rst = 0, no clocks 660 w p d , power down (src4193) pdn bit = 0, no clocks 16.6 mw p d , dynamic f sin = f sout = 192khz 225 mw electrical characteristics (cont.) all parameters specified with t a = +25 c, v dd = +3.3v, and v io = +3.3v, unless otherwise noted. SRC4192, src4193 parameter condition min typ max units notes: (1) dynamic performance measured with an audio precision system two cascade or cascade plus. (2) f smin = min (f sin , f sout ). (3) f smax = max (f sin , f sout ).
SRC4192, src4193 sbfs022a 6 www.ti.com typical characteristics at t a = +25 c, v dd = +3.3v, and v io = +3.3v, unless otherwise noted. 0 20 40 60 80 100 120 140 160 180 dbfs fft with 1khz input tone at 0dbfs (12khz:192khz) 0 20k 40k 96k 80k 60k frequency (hz) 60 70 80 90 100 110 120 130 140 150 160 170 180 dbfs fft with 1khz input tone at 60dbfs (12khz:192khz) 0 20k 40k 96k 80k 60k frequency (hz) 0 20 40 60 80 100 120 140 160 180 dbfs fft with 1khz input tone at 0dbfs (32khz:48khz) 0 5k 10k 24k 20k 15k frequency (hz) 60 70 80 90 100 110 120 130 140 150 160 170 180 dbfs fft with 1khz input tone at 60dbfs (32khz:48khz) 0 5k 10k 24k 20k 15k frequency (hz) 0 20 40 60 80 100 120 140 160 180 dbfs fft with 1khz input tone at 0dbfs (44.1khz:48khz) 0 5k 10k 24k 20k 15k frequency (hz) 60 70 80 90 100 110 120 130 140 150 160 170 180 dbfs fft with 1khz input tone at 60dbfs (44.1khz:48khz) 0 5k 10k 24k 20k 15k frequency (hz)
SRC4192, src4193 sbfs022a 7 www.ti.com typical characteristics (cont.) at t a = +25 c, v dd = +3.3v, and v io = +3.3v, unless otherwise noted. 0 20 40 60 80 100 120 140 160 180 dbfs fft with 1khz input tone at 0dbfs (44.1khz:96khz) 0 10k 20k 48k 40k 30k frequency (hz) 60 70 80 90 100 110 120 130 140 150 160 170 180 dbfs fft with 1khz input tone at 60dbfs (44.1khz:96khz) 0 10k 20k 48k 40k 30k frequency (hz) 0 20 40 60 80 100 120 140 160 180 dbfs fft with 1khz input tone at 0dbfs (44.1khz:192khz) 0 20k 40k 96k 80k 60k frequency (hz) 60 70 80 90 100 110 120 130 140 150 160 170 180 dbfs fft with 1khz input tone at 60dbfs (44.1khz:192khz) 0 20k 40k 96k 80k 60k frequency (hz) 0 20 40 60 80 100 120 140 160 180 dbfs fft with 1khz input tone at 0dbfs (48khz:44.1khz) 0 5k 10k 22k 20k 15k frequency (hz) 60 70 80 90 100 110 120 130 140 150 160 170 180 dbfs fft with 1khz input tone at 60dbfs (48khz:44.1khz) 0 5k 10k 22k 20k 15k frequency (hz)
SRC4192, src4193 sbfs022a 8 www.ti.com typical characteristics (cont.) at t a = +25 c, v dd = +3.3v, and v io = +3.3v, unless otherwise noted. 0 20 40 60 80 100 120 140 160 180 dbfs fft with 1khz input tone at 0dbfs (48khz:96khz) 0 10k 20k 48k 40k 30k frequency (hz) 60 70 80 90 100 110 120 130 140 150 160 170 180 dbfs fft with 1khz input tone at 60dbfs (48khz:96khz) 0 10k 20k 48k 40k 30k frequency (hz) 0 20 40 60 80 100 120 140 160 180 dbfs fft with 1khz input tone at 0dbfs (48khz:192khz) 0 20k 40k 96k 80k 60k frequency (hz) 60 70 80 90 100 110 120 130 140 150 160 170 180 dbfs fft with 1khz input tone at 60dbfs (48khz:192khz) 0 20k 40k 96k 80k 60k frequency (hz) 0 20 40 60 80 100 120 140 160 180 dbfs fft with 1khz input tone at 0dbfs (96khz:44.1khz) 0 5k 10k 22k 20k 15k frequency (hz) 60 70 80 90 100 110 120 130 140 150 160 170 180 dbfs fft with 1khz input tone at 60dbfs (96khz:44.1khz) 0 5k 10k 22k 20k 15k frequency (hz)
SRC4192, src4193 sbfs022a 9 www.ti.com typical characteristics (cont.) at t a = +25 c, v dd = +3.3v, and v io = +3.3v, unless otherwise noted. 0 20 40 60 80 100 120 140 160 180 dbfs fft with 1khz input tone at 0dbfs (96khz:48khz) 0 5k 10k 24k 20k 15k frequency (hz) 60 70 80 90 100 110 120 130 140 150 160 170 180 dbfs fft with 1khz input tone at 60dbfs (96khz:48khz) 0 5k 10k 24k 20k 15k frequency (hz) 0 20 40 60 80 100 120 140 160 180 dbfs fft with 1khz input tone at 0dbfs (96khz:192khz) 0 20k 40k 96k 80k 60k frequency (hz) 60 70 80 90 100 110 120 130 140 150 160 170 180 dbfs fft with 1khz input tone at 60dbfs (96khz:192khz) 0 20k 40k 96k 80k 60k frequency (hz) 0 20 40 60 80 100 120 140 160 180 dbfs fft with 1khz input tone at 0dbfs (192khz:12khz) 01k2k3k4k 6k 5k frequency (hz) 60 70 80 90 100 110 120 130 140 150 160 170 180 dbfs fft with 1khz input tone at 60dbfs (192khz:12khz) 01k2k3k4k 6k 5k frequency (hz)
SRC4192, src4193 sbfs022a 10 www.ti.com typical characteristics (cont.) at t a = +25 c, v dd = +3.3v, and v io = +3.3v, unless otherwise noted. 0 20 40 60 80 100 120 140 160 180 dbfs fft with 1khz input tone at 0dbfs (192khz:32khz) 0 2.5 5k 7.5k 10k 16k 15k 12.5k frequency (hz) 60 70 80 90 100 110 120 130 140 150 160 170 180 dbfs fft with 1khz input tone at 60dbfs (192khz:32khz) 0 2.5k 5k 7.5k 10k 16k 15k 12.5k frequency (hz) 0 20 40 60 80 100 120 140 160 180 dbfs fft with 1khz input tone at 0dbfs (192khz:44.1khz) 0 5k 10k 22k 20k 15k frequency (hz) 60 70 80 90 100 110 120 130 140 150 160 170 180 dbfs fft with 1khz input tone at 60dbfs (192khz:44.1khz) 0 5k 10k 22k 20k 15k frequency (hz) 0 20 40 60 80 100 120 140 160 180 dbfs fft with 1khz input tone at 0dbfs (192khz:48khz) 0 5k 10k 24k 20k 15k frequency (hz) 60 70 80 90 100 110 120 130 140 150 160 170 180 dbfs fft with 1khz input tone at 60dbfs (192khz:48khz) 0 10k 20k 24k 40k 30k frequency (hz)
SRC4192, src4193 sbfs022a 11 www.ti.com typical characteristics (cont.) at t a = +25 c, v dd = +3.3v, and v io = +3.3v, unless otherwise noted. 0 20 40 60 80 100 120 140 160 180 dbfs fft with 1khz input tone at 0dbfs (192khz:96khz) 0 10k 20k 48k 40k 30k frequency (hz) 60 70 80 90 100 110 120 130 140 150 160 170 180 dbfs fft with 1khz input tone at 60dbfs (192khz:96khz) 0 10k 20k 48k 40k 30k frequency (hz) 0 20 40 60 80 100 120 140 160 180 dbfs fft with 20khz input tone at 0dbfs (44.1khz:48khz) 0 5k 10k 24k 20k 15k frequency (hz) 0 20 40 60 80 100 120 140 160 180 dbfs fft with 20khz input tone at 0dbfs (48khz:44.1khz) 0 5k 10k 22k 20k 15k frequency (hz) 0 20 40 60 80 100 120 140 160 180 dbfs fft with 20khz input tone at 0dbfs (48khz:48khz) 0 5k 10k 24k 20k 15k frequency (hz) 0 20 40 60 80 100 120 140 160 180 dbfs fft with 20khz input tone at 0dbfs (48khz:96khz) 0 10k 20k 48k 40k 30k frequency (hz)
SRC4192, src4193 sbfs022a 12 www.ti.com typical characteristics (cont.) at t a = +25 c, v dd = +3.3v, and v io = +3.3v, unless otherwise noted. 0 20 40 60 80 100 120 140 160 180 dbfs fft with 20khz input tone at 0dbfs (96khz:48khz) 0 5k 10k 24k 20k 15k frequency (hz) 0 20 40 60 80 100 120 140 160 180 dbfs fft with 80khz input tone at 0dbfs (192khz:192khz) 0 20k 40k 96k 80k 60k frequency (hz) 120 125 130 135 140 145 150 155 160 total harmonic distortion+noise (db) thd+n vs input amplitude f in = 1khz (44.1khz:48khz) 140 120 100 80 0 20 60 40 input amplitude (dbfs) 120 125 130 135 140 145 150 155 160 total harmonic distortion+noise (db) thd+n vs input amplitude f in = 1khz (48khz:44.1khz) 140 120 100 80 0 20 60 40 input amplitude (dbfs) 120 125 130 135 140 145 150 155 160 total harmonic distortion+noise (db) thd+n vs input amplitude f in = 1khz (48khz:96khz) 140 120 100 80 0 20 60 40 input amplitude (dbfs) 120 125 130 135 140 145 150 155 160 total harmonic distortion+noise (db) thd+n vs input amplitude f in = 1khz (96khz:48khz) 140 120 100 80 0 20 60 40 input amplitude (dbfs)
SRC4192, src4193 sbfs022a 13 www.ti.com typical characteristics (cont.) at t a = +25 c, v dd = +3.3v, and v io = +3.3v, unless otherwise noted. 120 125 130 135 140 145 150 155 160 total harmonic distortion+noise (db) thd+n vs input amplitude f in = 1khz (44.1khz:192khz) 140 120 100 80 0 20 60 40 input amplitude (dbfs) 120 125 130 135 140 145 150 155 160 total harmonic distortion+noise (db) thd+n vs input amplitude f in = 1khz (192khz:48khz) 140 120 100 80 0 20 60 40 input amplitude (dbfs) 120 125 130 135 140 145 150 155 160 total harmonic distortion+noise (db) thd+n vs input frequency, 0dbfs input (44.1khz:48khz) 0 5k 20k 15k 10k input frequency (hz) 120 125 130 135 140 145 150 155 160 total harmonic distortion+noise (db) thd+n vs input frequency, 0dbfs input (48khz:44.1khz) 0 5k 20k 15k 10k input frequency (hz) 120 125 130 135 140 145 150 155 160 total harmonic distortion+noise (db) thd+n vs input frequency, 0dbfs input (48khz:96khz) 0 5k 20k 15k 10k input frequency (hz) 120 125 130 135 140 145 150 155 160 total harmonic distortion+noise (db) thd+n vs input frequency, 0dbfs input (96khz:48khz) 0 5k 20k 15k 10k input frequency (hz)
SRC4192, src4193 sbfs022a 14 www.ti.com typical characteristics (cont.) at t a = +25 c, v dd = +3.3v, and v io = +3.3v, unless otherwise noted. 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 output amplitude (dbfs) linearity with f in = 200hz (44.1khz:48khz) 140 130 120 110 100 90 80 70 60 50 0 40 30 20 10 input amplitude (dbfs) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 output amplitude (dbfs) linearity with f in = 200hz (48khz:44.1khz) 140 130 120 110 100 90 80 70 60 50 0 40 30 20 10 input amplitude (dbfs) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 output amplitude (dbfs) linearity with f in = 200hz (48khz:48khz) 140 130 120 110 100 90 80 70 60 50 0 40 30 20 10 input amplitude (dbfs) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 output amplitude (dbfs) linearity with f in = 200hz (48khz:96khz) 140 130 120 110 100 90 80 70 60 50 0 40 30 20 10 input amplitude (dbfs) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 output amplitude (dbfs) linearity with f in = 200hz (96khz:48khz) 140 130 120 110 100 90 80 70 60 50 0 40 30 20 10 input amplitude (dbfs) 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 output amplitude (dbfs) linearity with f in = 200hz (44.1khz:192khz) 140 130 120 110 100 90 80 70 60 50 0 40 30 20 10 input amplitude (dbfs)
SRC4192, src4193 sbfs022a 15 www.ti.com typical characteristics (cont.) at t a = +25 c, v dd = +3.3v, and v io = +3.3v, unless otherwise noted. 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 dbfs frequency respone with 0dbfs input 0 10k 20k 30k 40k 60k 50k frequency (hz) 192khz:32khz 192khz:48khz 192khz:96khz 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 output amplitude (dbfs) linearity with f in = 200hz (192khz:44.1khz) 140 130 120 110 100 90 80 70 60 50 0 40 30 20 10 input amplitude (dbfs) 0 0.004 0.009 0.014 0.019 0.024 0.029 0.034 0.039 0.044 0.049 dbfs pass band ripple (48k:48k) 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 22k 20k frequency (hz) 0 0.01 0.02 0.03 0.04 0.05 (dbfs) pass band ripple (192k:48k) 0 5k 10k 15k 22k 20k input amplitude (dbfs)
SRC4192, src4193 sbfs022a 16 www.ti.com product overview the SRC4192 and src4193 are asynchronous sample rate converters (asrc) designed for professional audio applica- tions. operation at input and output sampling frequencies up to 212khz is supported, with an input/output sampling ratio range of 16:1 to 1:16. excellent dynamic range and total harmonic distortion + noise (thd+n) are achieved by em- ploying high performance, linear phase digital filtering with better than 140db of image rejection. digital filtering options allow for lower group delay processing. these include a low group delay option for the interpolation and re-sampler func- tion, as well as a direct down-sampling option for the decima- tion function (src4193 only). the audio input and output ports support standard audio data formats, as well as a tdm interface mode. word lengths of 24-, 20-, 18-, and 16-bits are supported. both ports may operate in slave mode, deriving their word and bit clocks from external input and output devices. alternatively, one port may operate in master mode while the other remains in slave mode. in master mode, the lrck and bck clocks are derived from the reference clock input, rcki. the flexible configuration of the input and output ports allows connection to a wide variety of audio data converters, interface devices, digital signal processors, and programmable logic. a bypass mode is included, which allows audio data to be passed directly from the input port to the output port, bypass- ing the asrc function. the bypass option is useful for passing through encoded or compressed audio data, or non- audio control or status data. a soft mute function is available on both the SRC4192 and src4193. digital output attenuation is available only for the src4193. both soft mute and digital attenuation functions provide artifact-free operation, while allowing muting or level adjustment of the audio output signal. the mute attenuation is typically 144db, while the digital attenuation control is adjustable from 0db to 127.5db in 0.5db steps. the src4193 includes a three-wire spi port, which is used to access on-chip control registers for configuration of inter- nal functions. the port can be easily interfaced to micropro- cessors or digital signal processors with synchronous serial port peripherals. functional block diagram figure 1 shows a functional block diagram of the SRC4192 and src4193. audio data is received at the input port, clocked by either the audio data source in slave mode, or by the SRC4192/4193 in master mode. the output port data is clocked by either the audio data source in slave mode, or by mode [2:0] ifmt [2:0 ofmt [1:0] owl [1:0] mute bypas lgrp rst control logic (SRC4192) rate estimator lrcki lrcko refclk rdy ratio (src4193 only) mute bypass rst cs cclk cdata spi and control logic (src4193) lrcko bcko sdout tdmi audio output port mux rcki refclk reference clock lrcki bcki sdin audio input port interpolation filters 16f sin f sin f sout v dd dgnd vio dgnd re-sampler 16f sout decimation filters f sout direct down-sampler (src4193 only) power figure 1. SRC4192/4193 functional block diagram.
SRC4192, src4193 sbfs022a 17 www.ti.com the SRC4192/4193 in master mode. the input data is passed through interpolation filters which up-sample the data, which is then passed on to the re-sampler. the rate estimator compares the input and output sampling frequencies by comparing lrcki, lrcko, and a reference clock. the results include an offset for the fifo pointer and the coeffi- cients needed for re-sampling function. the output of the re-sampler is passed on to either the decimation filter or direct down-sampler function. the deci- mation filter performs down-sampling and anti-alias filtering functions, and is required when the output sampling fre- quency is lower than the input sampling frequency. the direct down-sampler function does not provide any filtering, and may be used in cases when aliasing is not an issue. this includes the case when the output sampling frequency is equal to or greater than the input sampling frequency. the advantage of direct down-sampling is a significant reduction in the group delay associated with the decimation filter, allowing lower latency sample rate conversion. the direct down-sampler function is available only for the src4193. reference clock the SRC4192 and src4193 require a reference clock for operation. the reference clock is applied at the rcki input (pin 1 for the src4193, pin 2 for the SRC4192). figure 2 illustrates the reference clock connections and requirements for the SRC4192 and src4193. the reference clock may operate at 128f s , 256f s , or 512f s , where f s are the input or output sampling frequency. the maximum external reference clock input frequency is 50 mhz. reset and power down operation the SRC4192 and src4193 may be reset using the rst input (pin 13). there is no internal power on reset, so the user should force a reset sequence after power up in order to initialize the device. in order to force a reset, the reference clock input must be active, with an external clock source supplying a valid reference clock signal (refer to figure 2). the user must assert rst low for a minimum of 500 nanoseconds and then bring rst high again to force a reset. figure 3 shows the reset timing for the SRC4192 and src4193. for the src4193, there is an additional 500 microsecond delay after the rst rising edge, due to internal logic require- ments. the customer should wait at least 500 microseconds after the rst rising edge before attempting to write to the spi port of the src4193. the SRC4192 and src4193 also support a power-down mode. power-down mode may be set by either holding the rst input low (SRC4192 and src4193), or by setting the pdn bit in control register 1 to zero (src4193 only). the src4193 will be in power-down mode by default after an external reset has been issued. in order to enable normal operation for the src4193, the customer must disable power down mode by writing a 1 to the pdn bit in control register 1. finally, for the src4193, when using the pdn bit in control register 1 to enable power-down mode, the current state of the control registers is maintained through the power down /power up transition. rst rcki t rstl > 500ns figure 3. reset pulse width requirement. figure 2. reference clock input connections and timing requirements. t rckip t rckih t rckil rcki SRC4192 rcki from external clock source 50mhz max 2 src4193 rcki from external clock source 50mhz max t rckip > 20ns min t rckih > 0.4 t rckip t rckil > 0.4 t rckip 1
SRC4192, src4193 sbfs022a 18 www.ti.com mode2 mode1 mode0 serial port mode 0 0 0 both input and output ports are slave mode 0 0 1 output port is master mode with rcki = 128f s 0 1 0 output port is master mode with rcki = 512f s 0 1 1 output port is master mode with rcki = 256f s 1 0 0 both input and output ports are slave mode 1 0 1 input port is master mode with rcki = 128f s 1 1 0 input port is master mode with rcki = 512f s 1 1 1 input port is master mode with rcki = 256f s audio port modes the SRC4192 and src4193 both support seven serial port modes, which are shown in table 1. for the SRC4192, the audio port mode is selected using the mode0 (pin 26), mode1 (pin 27), and mode2 (pin 28) inputs. for the src4193, the mode is selected using the mode[2:0] bits in control register 1. the default mode setting for the src4193 is both input and output ports set to slave mode. in slave mode, the port lrck and bck clocks are config- ured as inputs, and receive their clocks from an external audio device. in master mode, the lrck and bck clocks are configured as outputs, being derived from the reference clock input (rcki). only one port can be set to master mode at any given time, as indicated in table 1. input port operation the audio input port is a three-wire synchronous serial interface that may operate in either slave or master mode. the sdin input (pin 4) is the serial audio data input. audio data is input at this pin in one of three standard audio data formats: philips i 2 s, left justified, or right justified. the audio data word length may be up to 24-bits for i 2 s and left justified formats, while the right justified format supports 16-, 18-, 20-, or 24-bit data. the data formats are shown in figure 4, while critical timing parameters are shown in figure 5 and listed in the electrical characteristics table. t lris t sih t ldis t sil t ldih lrcki bcki sdin table 1. setting the serial port modes. left channel (a) left justified data format (b) right justified data format right channel lrcko bcki sdin msb lsb lsb msb lrcki bcki sdin msb msb lsb lsb (c) i 2 s data format 1/f s lrcki bcki sdin msb lsb msb lsb figure 4. input data formats. figure 5. input port timing.
SRC4192, src4193 sbfs022a 19 www.ti.com the bit clock is either an input or output at bcki (pin 5). in slave mode, bcki is configured as an input pin, and may operate at rates from 32f s to 128f s ,with a minimum of one clock cycle per data bit. in master mode, bcki operates at a fixed rate of 64f s . the left/right word clock, lrcki (pin 6), may be configured as an input or output pin. in slave mode, lrcki is an input pin, while in master mode lrcki is an output pin. in either case, the clock rate is equal to f s , the input sampling frequency. the lrcki duty cycle is fixed to 50% for master mode operation. table 2 illustrates data format selection for the input port. for the SRC4192, the ifmt0 (pin 10), ifmt1 (pin 11), and ifmt2 (pin 12) inputs are utilized to set the input port data format. for the src4193, the ifmt[2:0] bits in control register 3 are used to select the data format. output port operation the audio output port is a four-wire synchronous serial interface that may operate in either slave or master mode. the sdout output (pin 23) is the serial audio data output. audio data is output at this pin in one of four data formats: philips i 2 s, left justified, right justified, or tdm. the audio data word length may be 16-, 18-, 20-, or 24-bits. for all word lengths, the data is triangular pdf dithered from the internal 28-bit data path. the data formats (with the exception of tdm mode) are shown in figure 6, while critical timing parameters are shown in figure 7 and listed in the electrical characteristics table. the tdm format and timing are shown in figures 14 and 15, respectively, while examples of stan- dard tdm configurations are shown in figures 16 and 17. left channel (a) left justified data format (b) right justified data format right channel lrcko bcko sdout msb lsb lsb msb lrcko bcko sdout msb msb lsb lsb (c) i 2 s data format 1/f s lrcko bcko sdout msb lsb msb lsb t soh t dopd t sol t doh lrcko bcko sdout ifmt2 ifmt1 ifmt0 input port data format 0 0 0 24-bit left justified 0 0 1 24-bit i2s 0 1 0 unused 0 1 1 unused 1 0 0 16-bit right justified 1 0 1 18-bit right justified 1 1 0 20-bit right justified 1 1 1 24-bit right justified table 2. input port data format selection. figure 6. output data formats. figure 7. output port timing.
SRC4192, src4193 sbfs022a 20 www.ti.com the bit clock is either input or output at bcko (pin 25). in slave mode, bcko is configured as an input pin, and may operate at rates from 32f s to 128f s , with a minimum of one clock cycle for each data bit. the exception is the tdm mode, where the bcko must operate at n x 64f s , where n is equal to the number of SRC4192 or src4193 devices included on the tdm interface. in master mode, bcko operates at a fixed rate of 64f s for all data formats except tdm, where bcko operates at the reference clock (rcki) frequency. additional information regarding tdm mode op- eration is included in the applications information section of this data sheet. the left/right word clock, lrcko (pin 24), may be configured as an input or output pin. in slave mode, lrcko is an input pin, while in master mode it is an output pin. in either case, the clock rate is equal to f s , the output sampling frequency. the clock duty cycle is fixed to 50% for i 2 s, left justified, and right justified formats in master mode. the lrcko pulse width is fixed to 32 bcko cycles for the tdm format in master mode. table 3 illustrates data format selection for the output port. for the SRC4192, the ofmt0 (pin 19), ofmt1 (pin 18), owl0 (pin 17), and owl1 (pin 16) inputs are utilized to set the output port data format and word length. for the src4193, the ofmt[1:0] and owl[1:0] bits in control register 3 are used to select the data format and word length. soft mute function the soft mute function of the SRC4192 and src4193 may be invoked by forcing the mute input (pin 14) high. for the src4193, the mute function may also be accessed using the mute bit in control register 1. the soft mute function slowly attenuates the output signal level down to all zeroes plus 1lsb of dither. this provides an artifact-free muting of the audio output port. digital attenuation (src4193 only) the src4193 includes independent digital attenuation for the left and right audio channels. the attenuation ranges from 0db (or unity) to -127.5db in 0.5db steps. the attenu- ation settings are programmed using control registers 4 and 5, corresponding to the left and right channels, respec- tively. the track bit in control register 1 is used to select independent or tracking attenuation modes. when track = 0, the left and right channels are controlled indepen- dently. when track = 1, the attenuation setting for the left channel is also used for the right channel, and the right channel is said to track the left channel attenuation setting. ready output the SRC4192 and src4193 include an active low ready output named rdy (pin 15). this is an output from the rate estimator block, which indicates that the input-to-output sam- pling frequency ratio has been determined. the ready signal can be used as a flag or indicator output. the ready signal can also be connected to the active high mute input (pin 14) to provide an auto-mute function, so that the output port is muted when the rate estimator is in transition. ratio output (src4193 only) the src4193 includes a simple ratio flag output named ratio (pin 16). when ratio is low, it indicates that the output sampling frequency is lower than the input sampling frequency. when ratio is high, it indicates that the output sampling frequency is higher than the input sampling fre- quency. the ratio output can be used as an indicator or flag output for an led or host device. serial peripheral interface (spi) port: src4193 only the spi port is a three-wire synchronous serial interface used to access the on-chip control registers of the src4193. the interface is comprised of a serial data clock input, cclk (pin 27), a serial data input, cdata (pin 28), and an active low chip-select input, cs (pin 26). figure 8 illustrates the protocol for writing control registers via the serial control port. figure 9 shows the critical timing parameters for the spi port interface, which are also listed in the electrical characteris- tics table. ofmt1 ofmt0 output port data format 0 0 left justified 01 i 2 s 1 0 tdm 1 1 right justified owl1 owl0 output port data word length 0 0 24-bits 0 1 20-bits 1 0 18-bits 1 1 16-bits table 2. output port data format selection. bypass mode the SRC4192 and src4193 include a bypass function, which routes the input port data directly to the output port, bypassing the asrc function. bypass mode may be invoked by forcing the bypas input (pin 9) high for either the SRC4192 or src4193. for the src4193, the bypass mode may also be accessed using the bypas bit in control register 1. for normal asrc operation, the bypas pin and control bit should be set to 0. no dithering is applied to the output data in bypass mode, and the digital attenuation and mute functions are also unavailable.
SRC4192, src4193 sbfs022a 21 www.ti.com byte 0 indicates the address of the control register to be written. the two most significant bits are set to 0, while the six least significant bits contain the control register address. byte 1 is a don t care byte. this byte is included in the protocol in order to maintain compatibility with current and future texas instruments digital audio products, including the dit4096 and dit4192 digital audio transmitters. byte 2 contains the 8-bit data for the control register addressed in byte 0. as shown in figure 8, a write sequence starts by bringing the cs input low. bytes 0, 1, and 2 are then written to program a single control register. bringing the cs input high after the third byte will write just one register. however, if cs remains low after writing the first control byte, the port will auto- increment the address by 1, allowing successive addresses byte 0 byte 1 byte n header set cs = 1 here to write one register or buffer location. keep cs = 0 to enable auto-increment mode. cs cdin cclk 00000a2a1a0 msb lsb byte 0: byte definition set to 0. register address set to 0. byte 1: all 8 bits are don t care. set to 0 or 1. bytes 2 through n: register data. all bytes are written msb first. byte 2 byte 3 register or buffer data t cscr t cdh t cds t cfcs cs cclk cdata figure 8. spi port protocol. figure 9. spi port timing. to be written. the address is automatically incremented by 1 after each byte is written as long as the cs input remains low. this is referred to as auto-increment operation, and is always enabled for the spi port. control register map (src4193 only) the control register map for the src4193 is shown in table 4. register 0 is reserved for factory use and defaults to all zeros upon reset. the user should avoid writing this register, as unexpected operation may result if register 0 is pro- grammed to an arbitrary value. registers 1 through 5 contain control bits, which are used to configure the internal functions of the src4193. all other register addresses are reserved and should not be used in customer applications. register address d7 d0 (dec/hex) (msb) d6 d5 d4 d3 d2 d1 (lsb) 0 00 000000 1 pdn track 0 mute bypas mode2 mode1 mode0 2 0 0 0 0 0 0 dflt lgrp 3 owl1 owl0 ofmt1 ofmt0 0 ifmt2 ifmt1 ifmt0 4 al7 al6 al5 al4 al3 al2 al1 al0 5 ar7 ar6 ar5 ar4 ar3 ar2 ar1 ar0 table 4. the src4193 control register map.
SRC4192, src4193 sbfs022a 22 www.ti.com bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) pdn track 0 mute bypas mode2 mode1 mode0 control register definitions (src4193 only) this section contains detailed descriptions for each control register. reset defaults are also defined for each register bit. register 1: system control register mode[2:0] audio serial port mode mode2 mode1 mode0 audio serial port mode 0 0 0 both serial ports are in slave mode (default) 0 0 1 output serial port is master with rcki = 128fs 0 1 0 output serial port is master with rcki = 512fs 0 1 1 output serial port is master with rcki = 256fs 1 0 0 both serial ports are in slave mode 1 0 1 input serial port is master with rcki = 128fs 1 1 0 input serial port is master with rcki = 512fs 1 1 1 input serial port is master with rcki = 256fs bypas bypass mode this bit is logically or d with the bypas input (pin 9) bypas function 0 bypass mode disabled with normal asrc operation. (default) 1 bypass mode enabled with data routed directly from the input port to the output port, bypassing the arsc function. mute output soft mute this bit is logically or d with the mute input (pin 14) mute output mute function 0 soft mute disabled (default) 1 soft mute enabled with data attenuated to all 0 s track digital attenuation tracking track attenuation tracking 0 tracking off: attenuation for the left and right channels is controlled independently. (default) 1 tracking on: left channel attenuation setting is used for both channels. pdn power down setting this bit to 0 will set the src4193 to the power-down state. all other register settings are preserved and the spi port remains active. (default) setting this bit to 1 will power up the src4193 using the current register settings.
SRC4192, src4193 sbfs022a 23 www.ti.com register 2: filter control register lgrp low group delay this bit is used to select the number of input audio samples to be stored in the data buffer before the asrc starts processing the audio data. lgrp group delay 0 normal delay, 64 samples. (default) 1 low delay, 32 samples. dflt decimation filtering / direct down-sampling the dflt bit is used to enable or disable the direct down-sampling function. dflt decimation filter operation 0 decimation filter enabled (default) (must be used when f sout is less than f sin ) 1 direct down-sampling enabled without filtering. (may be enabled when f sout is equal to or greater than f sin ) register 3: audio data format register bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) 0 0 0 0 0 0 dflt lgrp ifmt[2:0] input port data format ifmt2 ifmt1 ifmt0 input format 0 0 0 24-bit left justified (default) 0 0 1 24-bit i 2 s 0 1 0 - not used - 0 1 1 - not used - 1 0 0 right justified, 16-bit data 1 0 1 right justified, 18-bit data 1 1 0 right justified, 20-bit data 1 1 1 right justified, 24-bit data ofmt[1:0] output port data format ofmt1 ofmt0 output format 0 0 left justified (default) 01i 2 s 1 0 tdm 1 1 right justified owl[1:0] output port data word length owl1 owl0 output word length 0 0 24-bits (default) 0 1 20-bits 1 0 18-bits 1 1 16-bits bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) owl1 owl0 ofmt1 ofmt0 0 ifmt2 ifmt1 ifmt0
SRC4192, src4193 sbfs022a 24 www.ti.com applications information this section of the data sheet provides practical applications information for hardware and systems engineers who will be designing the SRC4192 and src4193 into their end equip- ment. recommended circuit configuration typical connection diagrams for the SRC4192 and src4193 are shown in figures 10 and 11, respectively. recom- mended values for power supply bypass capacitors are included. these capacitors should be placed as close to the ic package as possible. lgrp rcki nc sdin bcki lrcki vio dgnd bypas ifmt0 ifmt1 ifmt2 rst mute 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SRC4192 audio input device reference clock from/to control logic v dd = +3.3v 10 f mode2 mode1 mode0 bcko lrcko sdout v dd dgnd tdmi ofmt0 ofmt1 owl0 owl1 rdy 28 27 26 25 24 23 22 21 20 19 18 17 16 15 audio output device 0.1 f to pin 22 to pin 21 v io = +1.65v to v dd 0.1 f 10 f to pin 7 to pin 8 from control logic register 4: digital attenuation register C left channel register defaults to 00 hex , or 0db (unity gain). output attenuation (db) = ( n x 0.5), where n = al[7:0] dec register 5: digital attenuation register C right channel bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) al7 al6 al5 al4 al3 al2 al1 al0 register defaults to 00 hex , or 0db (unity gain). output attenuation (db) = ( n x 0.5), where n = ar[7:0] dec when the track bit in control register 1 is set to 1, the left channel attenuation setting will be used for the right channel attenuation. bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) ar7 ar6 ar5 ar4 ar3 ar2 ar1 ar0 figure 10. typical connection diagram for the SRC4192.
SRC4192, src4193 sbfs022a 25 www.ti.com rcki nc nc sdin bcki lrcki vio dgnd bypas nc nc nc rst mute 1 2 3 4 5 6 7 8 9 10 11 12 13 14 src4193 audio input device reference clock host (mcu, dsp) to/from host or control logic v dd = +3.3v 10 f cdata cclk cs bcko lrcko sdout v dd dgnd tdmi nc nc nc ratio rdy 28 27 26 25 24 23 22 21 20 19 18 17 16 15 audio output device 0.1 f to pin 22 to pin 21 v io = +1.65v to v dd 0.1 f 10 f to pin 7 to pin 8 interfacing to digital audio receivers and transmitters the SRC4192 and src4193 input and output ports are designed to interface to a variety of audio devices, including receivers and transmitters commonly used for aes/ebu, s/pdif, and cp1201 communications. texas instruments manufactures the dir1703 digital audio interface receiver and dit4096/4192 digital audio transmit- ters to address these applications. figure 12 illustrates interfacing the dir1703 to the SRC4192 or src4193 input port. the dir1703 operates from a single +3.3v supply, which requires the v io supply (pin 7) for the SRC4192 or src4193 to be set to +3.3v for interface compatibility. dir1703 lrcko bcko data scko lrcki bcki sdin SRC4192, src4193 rcli clock select assumes v io = +3.3v for SRC4192, src4293 clock generator rcv din aes3, s/pdif input figure 11. typical connection diagram for the src4193. figure 12. interfacing the src4193 to the dir1703 digital audio interface receiver.
SRC4192, src4193 sbfs022a 26 www.ti.com figure 13 shows the interface between the SRC4192 or src4193 output port and the dit4096 or dit4192 audio serial port. once again, the v io supplies for both the SRC4192/4193 and dit4096/4192 are set to +3.3v for compatibility. SRC4192, src4193 lrcko bcko sdout rcki sync sclk sdata dit4096, dit4192 mclk clock select assumes v io = +3.3v for SRC4192, src4293 and dit4096, dit4192 ref clock generator dit clock generator tx+ tx aes3, s/pdif output like the SRC4192 or src4193 output port, the dit4096 and dit4192 audio serial port may be configured as a master or slave. in cases where the SRC4192/4193 output port is set to master mode, it is recommended to use the reference clock source (rcki) as the master clock source (mclk) for the dit4096/4192, to ensure that the transmitter is synchro- nized to the SRC4192/4193 output port data. tdm applications the SRC4192 and src4193 support a tdm output mode, which allows multiple devices to be daisy-chained together to create a serial frame. each device occupies one sub- frame within a frame, and each sub-frame carries two chan- nels (left followed by right). each sub-frame is 64 bits long, with 32 bits allotted for each channel. the audio data for each channel is left justified within the allotted 32 bits. figure 14 illustrates the tdm frame format, while figure 15 shows tdm input timing parameters, which are listed in the electri- cal characteristics table of this data sheet. lrcko bcko sdout n = number of daisy-chained devices one sub-frame contains 64 bits, with 32 bits per channel. for each channel, the audio data is left justified, msb first format, with the word length determined by the owl[1:0] pins/bits . left right sub-frame 1 sub-frame 2 sub-frame n one frame = 1/f s left right left right t lros t tdms t lroh t tdmh lrcko bcko tdmi figure 15. input timing for tdm mode. figure 14. tdm frame format. figure 13. interfacing the src4193 to the dit4096/4192 digital audio interface transmitter.
SRC4192, src4193 sbfs022a 27 www.ti.com the frame rate is equal to the output sampling frequency, f s . the bcko frequency for the tdm interface is n*64f s , where n is the number of devices included in the daisy chain. for master mode, the output bcko frequency is fixed to the reference clock (rcki) input frequency. the number of devices that can be daisy-chained in tdm mode is depen- dent upon the output sampling frequency and the bcko frequency, leading to the following numerical relationship: number of daisy-chained devices = (f bcko / f s ) / 64 where: f bcko = output port bit clock (bcko), 27.648 mhz maximum f s = output port sampling (or lrcko) frequency, 216khz maximum. this relationship holds true for both slave and master modes. tdmi SRC4192, src4193 slave #n sdout lrcko bcko rcki tdmi SRC4192, src4193 slave #2 sdout lrcko bcko rcki tdmi SRC4192, src4193 slave #1 sdout lrcko bcko rcki drn fsrn clkrn clkin or clksn tms320c671x mcbsp clock generator n = 0 or 1 tdmi SRC4192, src4193 master sdout lrcko bcko rcki tdmi SRC4192, src4193 slave #2 sdout lrcko bcko rcki tdmi SRC4192, src4193 slave #1 sdout lrcko bcko rcki drn fsrn clkrn clkin or clksn tms320c671x mcbsp clock generator n = 0 or 1 figures 16 and 17 show typical connection schemes for tdm mode. although the tms320c671x dsp family is shown as the audio processing engine in these figures, other ti digital signal processors with a multi-channel buffered serial port (mcbsp tm ) may also function with this arrangement. inter- facing to processors from other manufacturers is also pos- sible. refer to figure 7 in this data sheet, along with the equivalent serial port timing diagrams shown in the dsp data sheet, to determine compatibility. figure 16. tdm interface where all devices are slaves. figure 17. tdm interface where one device is master to multiple slaves.
SRC4192, src4193 sbfs022a 28 www.ti.com pin compatibility with the analog devices ad1896 (SRC4192 only) the SRC4192 is pin-and function-compatible with the ad1896 when observing the guidelines indicated in the following paragraphs. power supplies. to ensure compatibility, the vdd_io and vdd_core supplies of the ad1896 must be set to +3.3v, while the v io and v dd supplies of the SRC4192 must be set to +3.3v. crystal oscillator. the SRC4192 does not have an on-chip crystal oscillator. an external reference clock is required at the rcki input (pin 2). reference clock frequency. the reference clock input frequency for the SRC4192 must be no higher than 30 mhz, in order to match the master clock frequency specification of the ad1896. in addition, the SRC4192 does not support the 768f s reference clock rate. master mode maximum sampling frequency. when the input or output ports are set to master mode, the maximum sampling frequency must be limited to 96khz in order to support the ad1896 specification. this is despite the fact that the SRC4192 supports a maximum sampling frequency of 212khz in master mode. the user should consider building an option into his or her design to support the higher sampling frequency of the SRC4192. matched phase mode. due to the internal architecture of the SRC4192, it does not require or support the matched phase mode of the ad1896. given multiple SRC4192 de- vices, if all reference clock (rcki) inputs are driven from the same clock source, the devices will be phase matched.
SRC4192, src4193 sbfs022a 29 www.ti.com db (r-pdso-g**) plastic small-outline 4040065 /e 12/01 28 pins shown gage plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 seating plane 9,90 7,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 a 28 1 20 16 6,50 6,50 14 0,05 min 5,90 5,90 dim a max a min pins ** 2,00 max 6,90 7,50 0,65 m 0,15 0 C 8 0,10 0,09 0,25 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-150 package drawing
packaging information orderable device status(1) package type package drawing pins package qty SRC4192idb active ssop db 28 50 SRC4192idbr active ssop db 28 2000 src4193idb active ssop db 28 50 src4193idbr active ssop db 28 2000 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. package option addendum www.ti.com 3-oct-2003
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2003, texas instruments incorporated

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