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data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 1 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| features ? provides up to 32 full-duplex hdlc/sdlc channels compatible with 1.544 mb/s t1 and 2.048mb/s cept pcm-30 carrier format provides on-board buffer memory management supports standard hyperchannel configuration and fully programmable hyperchannel configuration provides on-board crc-16, automatic flag and zero insertion and deletion functions in hdlc format provides programmable tri-state outputs to t1/e1 serial interface and fill/mask, thus enabling up to 8 devices connecting to a tdm bus provides data rate adaptation functions compatible with hdlc, sna sdlc, x.25, x.75, lapb, and lapd protocols support non-hdlc signaling channels single +5v power supply package: 68-pin plcc introduction the PT7A6632 hdlc controller operates at layer 2 (data link protocol level) of the open systems inter- connection (osi) reference model. it supports hdlc and isdn implementations. the PT7A6632 processes data transmitting and re- ceiving on a t1 or e1 communication link. it con- nects between the t1/e1 serial bus and an external memory shared with cpu(s), multiplexing / demultiplexing up to 32 fully-duplex high-speed data channels. it provides additional functions that support x.30 and x.31 rate adaptation and fully flexible hyperchannels. applications primary rate interfaces basic-rate d-channel controller multi-channel hdlc interfaces cpu external shared memory hdlc PT7A6632 d0-d7 a0-a15 e1/t1 trunk interface t1/cept pcm-30 line figure 1. application diagram of PT7A6632
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 2 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| contents features ............................................................................................................................... ........................ 1 applications ............................................................................................................................... ................. 1 introduction ............................................................................................................................... .................. 1 block diagram .................................................................................................................. .......................... 4 pin information ................................................................................................................ ........................... 4 pin assignment ................................................................................................................. ................. 4 pin configuration .............................................................................................................. ................ 5 pin description ................................................................................................................ .................. 6 functional description ......................................................................................................... ....................... 9 general description ............................................................................................................ ............... 9 transmit bit-level processor ................................................................................................... ........ 10 timing ............................................................................................................................... ..... 10 data rate adaptation ........................................................................................................... .. 10 hyperchannel ................................................................................................................... ...... 13 tri-state serial data output tser ........................................................................................ 14 channel operation modes...................................................................................................... 14 data transmission order ........................................................................................................ 14 receive bit-level processor .................................................................................................... ........ 15 timing ............................................................................................................................... ..... 15 data rate adaptation ........................................................................................................... .. 15 hdlc frame validity ............................................................................................................ 15 hyperchannel ................................................................................................................... ...... 15 channel operation modes...................................................................................................... 15 data reception order........................................................................................................... .. 18 memory manager ................................................................................................................. ........... 18 state / control machine ........................................................................................................ ........... 19
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 3 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| external memory organization and definition .................................................................................... ..... 20 general structure .............................................................................................................. ............... 20 activation memory .............................................................................................................. ............ 21 channel activation byte ........................................................................................................ 21 channel buffer pointers ........................................................................................................ .21 data processing memory ......................................................................................................... ........ 24 general ........................................................................................................................ ........... 24 transmit data buffer ........................................................................................................... ... 24 transmit command buffer ..................................................................................................... 26 minimum number of data bytes in a tx buffer.................................................................... 30 receive data buffer ............................................................................................................ ... 31 receive command buffer ...................................................................................................... 33 minimum buffer size ............................................................................................................ .37 device operation ............................................................................................................... ....................... 38 device initialization .......................................................................................................... ............... 38 channel initialization ......................................................................................................... .............. 38 data transmission and reception operation ................................................................................... 39 channel period ................................................................................................................. ............... 41 memory address ................................................................................................................. ............ 42 memory address extension ................................................................................................... 42 activation memory address................................................................................................... 42 memory address restrictions................................................................................................. 43 interrupt indication ........................................................................................................... ............... 43 detailed specifications ........................................................................................................ ...................... 48 absolute maximum ratings ....................................................................................................... ..... 48 recommended operating conditions .............................................................................................. 4 8 dc electrical, power supply and capacitance characteristics ........................................................ 49 ac characteristics ............................................................................................................. .............. 50 serial interface............................................................................................................... ......... 50 external memory interface ..................................................................................................... 5 4 channel activation/deactivation ............................................................................................ 56 input characteristics .......................................................................................................... ..... 57 output characteristics ......................................................................................................... ... 58 mechanical specifications ...................................................................................................... ......... 59 ordering information ........................................................................................................... ..................... 60 notes .......................................................................................................................... ............................... 61
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 4 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| block diagram figure 2. block diagram of PT7A6632 pin information pin assignment table 1. pin assignment p u o r gp u o r g p u o r g p u o r gp u o r gl o b m y sl o b m y s l o b m y s l o b m y sl o b m y sn o i t c n u fn o i t c n u f n o i t c n u f n o i t c n u fn o i t c n u f e c a f r e t n i y r o m e m , s a , e t i r w , d a e r , 5 1 a - 0 a , 7 d - 0 d d n m d d e r a h s h t i w s l a n g i s & s e s s e r d d a , a t a d y r o m e m e c a f r e t n i l a i r e s , x a m t , r e s t , d e r r , c n y s r , r e s r n e r e s t , k l c r , k l c t , k l c s y s e c a f r e t n i l a i r e s h t i w g n i m i t & a t a d e c a f r e t n i u p cr t n i , c c a s y s , k c a t a , n t t au p c h t i w s l a n g i s l o r t n o c & e t a t s , s f d m , 1 s c h , 0 s c h , t p e c / 1 t , s i s x t / x r , 4 h c - 0 h c , t e s e r , n e a u s l a n g i s l o r t n o c & s u t a t s e c i v e d r e w o pv c c d n g ,d n u o r g & r e w o p receive bit-level processor transmit bit-level processor memory manager a0-a15 d0-d7 read write as dmnd rser rsync rred rclk tclk attn atack sysacc intr sysclk ch0-ch4 rx/tx reset hcs0-hcs1 t1/cept sis uaen mdfs tseren tser tmax state / control machine 16 8 5 2
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 5 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| pin configuration figure 3. pin configuration 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 nc ch0 hcs1 hcs0 t1/cept reset sis tmax nc tseren rclk rsync rred rser nc gnd gnd d6 d7 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 nc ch1 ch2 ch3 ch4 rx/tx tclk sysclk tser v cc gnd gnd d0 d1 d2 d3 d4 d5 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 nc intr as attn sysacc gnd gnd gnd v cc write read atack dmnd mdfs uaen a15 a14 68-pin plcc top view
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 6 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| pin description table 2. pin description n i pn i p n i p n i pn i pe m a ne m a n e m a n e m a ne m a ne p y te p y t e p y t e p y te p y tn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d , 0 6 , 3 4 , 9 , 1 3 6 c n n o i t c e n n o c o nn o i t c e n n o c o n n o i t c e n n o c o n n o i t c e n n o c o nn o i t c e n n o c o n 2x a m ti : c n y s e m a r f i t l u m t i m s n a r t: c n y s e m a r f i t l u m t i m s n a r t : c n y s e m a r f i t l u m t i m s n a r t : c n y s e m a r f i t l u m t i m s n a r t: c n y s e m a r f i t l u m t i m s n a r t . h g i h e v i t c a , e c a f r e t n i k n u r t 1 e / 1 t m o r f t u p n i e s l u p . e m a r f i t l u m a f o g n i n i g e b e h t s e t a c i d n i h g i h o t g n i t t e g 3s i si : t c e l e s e c a f r e t n i l a i r e s: t c e l e s e c a f r e t n i l a i r e s : t c e l e s e c a f r e t n i l a i r e s : t c e l e s e c a f r e t n i l a i r e s: t c e l e s e c a f r e t n i l a i r e s . 5 2 e l b a t e e s . k l c r d n a k l c t f o e g d e e v i t c e f f e e h t s e d i c e d . e v i t c e f f e k l c r d n a k l c t f o e g d e g n i l l a f , 1 = s i s . e v i t c e f f e e g d e g n i s i r , 0 = s i s 4t e s e ri : t e s e r: t e s e r : t e s e r : t e s e r: t e s e r e b l l i w n o i t a z i l a i t i n i e h t . h g i h e v i t c a , 2 3 6 6 a 7 t p e h t g n i z i l a i t i n i r o f t u p n i s t e s t e s e r e h t . w o l o t s e g n a h c t e s e r r e t f a s d o i r e p k l c s y s 0 9 n i h t i w d e t e l p m o c : e t a t s g n i w o l l o f e h t n i e c i v e d e h t , e d o m c l d h - , s o r e z e r a s t i b k s a m / l l i f e h t l l a - , d e t a v i t c a e d s l e n n a h c l l a - . s e n o l l a t u p t u o s l e n n a h c t i m s n a r t - 5t p e c / 1 ti a : e d o m t p e c r o 1 t t c e l e sa : e d o m t p e c r o 1 t t c e l e s a : e d o m t p e c r o 1 t t c e l e s a : e d o m t p e c r o 1 t t c e l e sa : e d o m t p e c r o 1 t t c e l e s n i s t e s w o l a , e d o m g n i m a r f 1 t n i e c i v e d e h t s t e s h g i h . e d o m g n i m a r f 0 3 - m c p t p e c 6 7 0 s c h 1 s c h i : t c e l e s l e n n a h c r e p y h: t c e l e s l e n n a h c r e p y h : t c e l e s l e n n a h c r e p y h : t c e l e s l e n n a h c r e p y h: t c e l e s l e n n a h c r e p y h: e d o m t p e c r o 1 t n i s n r e t t a p l e n n a h c r e p y h d r a d n a t s t e s , ) 1 = t p e c / 1 t ( e d o m 1 t n i - , ) 0 h ( s / b k 4 8 3 f o s l e n n a h c r u o f , 1 0 = 1 s c h 0 s c h . ) 1 1 h ( s / b m 6 3 5 . 1 f o l e n n a h c e l g n i s , 0 1 = : ) 0 = t p e c / 1 t ( e d o m 0 3 - m c p t p e c n i - , ) 2 1 h ( s / b k 4 6 e r a 6 1 d n a 0 t o l s - e m i t , s / b m 2 9 . 1 f o l e n n a h c e l g n i s , 1 0 = 1 s c h 0 s c h . d e v r e s e r , 0 1 = , e d o m 0 3 - m c p t p e c r o 1 t f o y n a n i - , s / b k 4 6 e r a s l e n n a h c l l a , 0 0 = 1 s c h 0 s c h . d e v r e s e r , 1 1 = 8 0 1 1 1 2 1 3 1 0 h c 1 h c 2 h c 3 h c 4 h c o : r e b m u n l e n n a h c: r e b m u n l e n n a h c : r e b m u n l e n n a h c : r e b m u n l e n n a h c: r e b m u n l e n n a h c b s l e h t s i 0 h c . ) y r a n i b ( r e b m u n s ? l e n n a h c e v i t c a t n e r r u c s e t a c i d n i . b s m e h t s i 4 h c d n a 4 1x t / x ro : l e n n a h c t i m s n a r t / e v i e c e r: l e n n a h c t i m s n a r t / e v i e c e r : l e n n a h c t i m s n a r t / e v i e c e r : l e n n a h c t i m s n a r t / e v i e c e r: l e n n a h c t i m s n a r t / e v i e c e r s n a e m h g i h . l e n n a h c e v i t c a t n e r r u c f o n o i t c e r i d s e t a c i d n i . t i m s n a r t s n a e m w o l d n a e v i e c e r 5 1k l c ti : k c o l c t i m s n a r t: k c o l c t i m s n a r t : k c o l c t i m s n a r t : k c o l c t i m s n a r t: k c o l c t i m s n a r t 2 3 6 6 a 7 t p r o f d e s u . e c a f r e t n i k n u r t 1 e / 1 t m o r f t u p n i e v a w e r a u q s y c n e u q e r f d n a k l c s y s f o t a h t h t i w d e n g i l a e b t s u m e s a h p s t i . k c o l c e c a f r e t n i t i m s n a r t . k l c s y s f o f l a h e n o s i
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 7 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| n i pn i p n i p n i pn i pe m a ne m a n e m a n e m a ne m a ne p y te p y t e p y t e p y te p y tn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d 6 1k l c s y si : k c o l c m e t s y s: k c o l c m e t s y s : k c o l c m e t s y s : k c o l c m e t s y s: k c o l c m e t s y s = y c n e u q e r f . e c a f r e t n i y r o m e m l a n r e t x e l l a r o f e c n e r e f e r g n i m i t s e d i v o r p . 0 3 - m c p t p e c r o f z h m 6 9 0 . 4 r o 1 t r o f z h m 8 8 0 . 3 7 1r e s to : a t a d l a i r e s d e t t i m s n a r t: a t a d l a i r e s d e t t i m s n a r t : a t a d l a i r e s d e t t i m s n a r t : a t a d l a i r e s d e t t i m s n a r t: a t a d l a i r e s d e t t i m s n a r t s e i r r a c , e c a f r e t n i 1 e / 1 t o t t u p t u o e t a t s - i r t , e n i l t u p t u o a t a d l a i r e s . m a e r t s t i b a t a d r e t t i m s n a r t 2 5 , 8 1v c c i ) v 5 + ( y l p p u s r e w o p) v 5 + ( y l p p u s r e w o p ) v 5 + ( y l p p u s r e w o p ) v 5 + ( y l p p u s r e w o p) v 5 + ( y l p p u s r e w o p , 3 5 , 0 2 , 9 1 , 1 6 , 5 5 , 4 5 2 6 d n gi d n u o r gd n u o r g d n u o r g d n u o r gd n u o r g 8 2 - 1 27 d - 0 do / i : s e n i l a t a d y r o m e m: s e n i l a t a d y r o m e m : s e n i l a t a d y r o m e m : s e n i l a t a d y r o m e m: s e n i l a t a d y r o m e m d e r a h s e h t d n a 2 3 6 6 a 7 t p e h t n e e w t e b s u b a t a d l a n o i t c e r i d i b . b s m e h t s i 7 d d n a b s l e h t s i 0 d . y r o m e m 5 4 - 4 4 , 2 4 - 9 25 1 a - 0 ao : s e n i l s s e r d d a y r o m e m: s e n i l s s e r d d a y r o m e m : s e n i l s s e r d d a y r o m e m : s e n i l s s e r d d a y r o m e m: s e n i l s s e r d d a y r o m e m d n a b s l e h t s i 0 a . y r o m e m l a n r e t x e e h t o t s e n i l s s e r d d a t u p t u o . b s m e h t s i 5 1 a 6 4n e a ui e l b a n e s s e r d d a r e p p ue l b a n e s s e r d d a r e p p u e l b a n e s s e r d d a r e p p u e l b a n e s s e r d d a r e p p ue l b a n e s s e r d d a r e p p u: e t a t s ) 5 1 a - 8 a ( s e n i l s u b s s e r d d a r e p p u e h t s t e s : s s e c c a y r o m e m n o i t a v i t c a g n i r u d e c n a d e p m i h g i h n i 5 1 a - 8 a s t e s 2 3 6 6 a 7 t p : 1 = n e a u . d e t r e s s a c c a s y s h t i w . d e t r e s s a c c a s y s n e h w w o l 5 1 a - 8 a s t e s 2 3 6 6 a 7 t p : 0 = n e a u 7 4s f d mi : t c e l e s t a m r o f a t a d y r o m e m: t c e l e s t a m r o f a t a d y r o m e m : t c e l e s t a m r o f a t a d y r o m e m : t c e l e s t a m r o f a t a d y r o m e m: t c e l e s t a m r o f a t a d y r o m e m : 1 = s f d m a t a d d n a e z i s r e f f u b , s s e r d d a t r a t s r e f f u b t x e n f o s e t y b t n a c i f i n g i s t s o m e h t r i e h t d n a , y r o m e m l a n r e t x e e h t n i y l e v i t c e p s e r s e s s e r d d a n e v e t a e r a h t g n e l . ) u p m 0 0 0 8 6 ( s e s s e r d d a d d o t a s e t y b t n a c i f i n g i s t s a e l : 0 = s f d m t r a t s r e f f u b t x e n f o s e t y b t n a c i f i n g i s t s o m e h t , . e . i , e v o b a e h t h t i w e s r e v n i e h t n i y l e v i t c e p s e r s e s s e r d d a d d o t a e r a h t g n e l a t a d d n a e z i s r e f f u b , s s e r d d a 0 8 0 8 ( s e s s e r d d a n e v e t a s e t y b t n a c i f i n g i s t s a e l r i e h t d n a , y r o m e m l a n r e t x e . ) u p m 8 4d n m do : d n a m e d y r o m e m: d n a m e d y r o m e m : d n a m e d y r o m e m : d n a m e d y r o m e m: d n a m e d y r o m e m 2 3 6 6 a 7 t p e h t t a h t s u b y r o m e m e h t n o s e c i v e d r e h t o s m r o f n i h g i h a . ) e g d e g n i s i r ( n o i t r e s s a d n m d r e t f a d o i r e p k l c t e n o y r o m e m l a n r e t x e e h t s s e c c a l l i w . s s e c c a y r o m e m e h t f o n o i t e l p m o c t a d e t r e s s a e d e b l l i w d n m d e h t 9 4k c a t ao : e g d e l w o n k c a n o i t n e t t a: e g d e l w o n k c a n o i t n e t t a : e g d e l w o n k c a n o i t n e t t a : e g d e l w o n k c a n o i t n e t t a: e g d e l w o n k c a n o i t n e t t a n o i t a v i t c a s s e c c a o t n t t a e h t o t s d n o p s e r 2 3 6 6 . h g i h e v i t c a n i d e t r e s s a e d s i k c a t a . k c a t a s t r e s s a 2 3 6 6 , s s e c c a e h t f o n o i t e l p m o c r e t f a . y r o m e m . ) e g d e g n i l l a f ( n t t a f o n o i t r e s s a e d o t e s n o p s e r 0 5d a e ro : d a e r y r o m e m: d a e r y r o m e m : d a e r y r o m e m : d a e r y r o m e m: d a e r y r o m e m t i n e h w . g n i d a e r a t a d r o f y r o m e m l a n r e t x e e h t o t t u p t u o . w o l e v i t c a . k l c s y s f o e g d e g n i s i r e h t n o 2 3 6 6 a 7 t p e h t o t d e h c t a l s i y r o m e m m o r f a t a d , w o l s i 1 5e t i r wo : e t i r w y r o m e m: e t i r w y r o m e m : e t i r w y r o m e m : e t i r w y r o m e m: e t i r w y r o m e m. g n i t i r w a t a d r o f y r o m e m l a n r e t x e e h t o t t u p t u o . w o l e v i t c a 6 5c c a s y so : s s e c c a m e t s y s: s s e c c a m e t s y s : s s e c c a m e t s y s : s s e c c a m e t s y s: s s e c c a m e t s y s n o i t a v i t c a g n i s s e c c a s i 2 3 6 6 a 7 t p e h t s e t a c i d n i h g i h a . h g i h e v i t c a . s r e t n i o p r e f f u b l e n n a h c r o e t y b n o i t a v i t c a l e n n a h c r o f s n o i t a c o l y r o m e m table 2. pin descripti o n (continued)
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 8 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| n i pn i p n i p n i pn i pe m a ne m a n e m a n e m a ne m a ne p y te p y t e p y t e p y te p y tn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d 7 5n t t ai n o i t n e t t an o i t n e t t a n o i t n e t t a n o i t n e t t an o i t n e t t a n o i t a v i t c a l e n n a h c e h t s s e c o r p o t 2 3 6 6 a 7 t p s e r i u q e r h g i h a . h g i h e v i t c a : e b l l i w n t t a . y r o m e m d e r a h s e h t n i h 0 0 x x n o i t a c o l y r o m e m n o i t a v i t c a t a ) b a c ( e t y b . k c a t a f o n o i t r e s s a o t e s n o p s e r n i d e t r e s s a e d 8 5s ao : e b o r t s s s e r d d a y r o m e m: e b o r t s s s e r d d a y r o m e m : e b o r t s s s e r d d a y r o m e m : e b o r t s s s e r d d a y r o m e m: e b o r t s s s e r d d a y r o m e m s s e r d d a y r o m e m d i l a v a e k a m l l i w e g d e g n i l l a f s t i . w o l e v i t c a . s e n i l s s e r d d a y r o m e m e h t n o e b 9 5r t n io : t p u r r e t n i: t p u r r e t n i : t p u r r e t n i : t p u r r e t n i: t p u r r e t n i s t i . e t a d p u r e d n u s i e t y b s u t a t s r e f f u b e h t t a h t s e t a c i d n i w o l a . w o l e v i t c a . d o i r e p k l c s y s e n o o t l a u q e s i n o i t a r u d e s l u p 4 6r e s ri : a t a d l a i r e s d e v i e c e r: a t a d l a i r e s d e v i e c e r : a t a d l a i r e s d e v i e c e r : a t a d l a i r e s d e v i e c e r: a t a d l a i r e s d e v i e c e r 1 e / 1 t e h t m o r f m a e r t s t i b a t a d g n i v i e c e r , e n i l t u p n i a t a d l a i r e s . e c a f r e t n i 5 6d e r ri : m r a l a d e r e v i e c e r: m r a l a d e r e v i e c e r : m r a l a d e r e v i e c e r : m r a l a d e r e v i e c e r: m r a l a d e r e v i e c e rf o s s o l o t e u d d i l a v n i s i a t a d d e v i e c e r e h t s e t a c i d n i h g i h a e v i e c e r l l a n i g n i s s e c o r p s p o t s 2 3 6 6 a 7 t p , o s f i . n o s a e r r a l i m i s r o t n e m n g i l a e m a r f . d e r o t s e r n o i t a z i n o r h c n y s n o i t p e c e r e h t l i t n u s l e n n a h c 6 6c n y s ri : n o i t a z i n o r h c n y s e v i e c e r: n o i t a z i n o r h c n y s e v i e c e r : n o i t a z i n o r h c n y s e v i e c e r : n o i t a z i n o r h c n y s e v i e c e r: n o i t a z i n o r h c n y s e v i e c e re m a r f e v i e c e r r o f t u p n i e s l u p r o l e v e l . h g i h e v i t c a . n o i t a z i n o r h c n y s 7 6k l c ri : k c o l c e v i e c e r: k c o l c e v i e c e r : k c o l c e v i e c e r : k c o l c e v i e c e r: k c o l c e v i e c e r k c o l c / e c a f r e t n i 1 e / 1 t e h t m o r f t u p n i . g n i v i e c e r a t a d l a i r e s r o f k c o l c . 0 3 - m c p t p e c r o f z h m 8 4 0 . 2 r o 1 t r o f z h m 4 4 5 . 1 s i y c n e u q e r f . t i u c r i c y r e v o c e r 8 6n e r e s ti : e l b a n e r e s t: e l b a n e r e s t : e l b a n e r e s t : e l b a n e r e s t: e l b a n e r e s t n i t i b k s a m / l l i f h t i w g n o l a s u t a t s e n i l r e s t s e d i c e d , h g i h e v i t c a . r o t p i r c s e d , r e s t n o a t a d d n e s , 1 = k s a m / l l i f , 1 = n e r e s t n e h w . r e s t n o 1 a d n e s , 0 = k s a m / l l i f , r e s t n o a t a d d n e s , 1 = k s a m / l l i f , 0 = n e r e s t n e h w . r e s t n o e c n a d e p m i h g i h , 0 = k s a m / l l i f table 2. pin description (continued)
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 9 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| functional description general description the PT7A6632 hdlc controller is applied between an exter- nal memory and t1/e1 trunk interface to perform data trans- mission and reception. see figure 1. its signal attributes are shown in figure 4. PT7A6632 reads the data to be transmitted from the external memory in 8-bit parallel way, formats them and adapts data rate, then transmits the data to the t1/e1 trunk interface. PT7A6632 receives serial data from the t1/e1 trunk interface, figure 4. PT7A6632 interface signals a0-a15 d0-d7 read write as dmnd rser rsync rred rclk tclk attn atack sysacc intr sysclk ch0-ch4 rx/tx reset hcs0-hcs1 t1/cept sis uaen mdfs tseren tser tmax PT7A6632 external memory cpu t1/e1 trunk interface channel status out p ut device mode 16 8 5 2 deformats them and adapts data rate, then stores the data into the external memory. the channel operation modes are set up in the external memory by cpu. PT7A6632 reads the commands from the external memory and process data channel by channel, totally 64 chan- nels (32 for transmission and 32 for receive). each channel mode can be set up in external memory independently by cpu. PT7A6632 consists of 4 functional blocks as shown in figure 2. there are: transmit bit-level processor, receive bit-level processor, memory manager, and state/control machine.
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 10 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| transmit bit-level processor the block diagram of the transmit bit-level processor is shown in figure 5. the external memory stores data to be trans- mitted and the channel operation modes in a set of linked buffers (referred as transmit data/command buffers) in the external memory. refer to figure 23 and 24 in the external memory organization and definition. for transmit, the PT7A6632 reads the data from external memory, formats it in hdlc format (generates flags, abort and idle code, inserts zero-bit, counts the frame check sequences), non-hdlc signaling format or non-hdlc data format, adapts data rate, and sends the processed data to tser output via the transmit interface. timing tclk clocks data bit stream out at its falling edge. tmax is multiframe synchronization signal from the t1/e1 trunk inter- face. sis decides the tmax is sampled in rising or falling edge of tclk . PT7A6632 processes data channel by channel for the data transmission under control of channel counter in the transmit interface. see figure 7-10. data rate adaptation the PT7A6632 can adapt the data rate of sub-64kb/s (n x 8kb/ s, n = 1 - 8) to the standard 64kb/s bearer rate. a fill/mask byte in the transmit command buffer is applied to the data bit by bit to perform data rate adaptation. an example is shown in the figure 6. transmit interface format & rate adapt (32 channels) to/from memory manager tclk tser tseren tmax state/control signals figure 5. block diagram of transmit bit-level processor a b c d e f g h j k l m n o p q msb lsb data bytes to be transmitted 1 0 1 1 1 0 0 0 fill/mask pattern fill/mask 0 = a fill bit of 1 or high z (see tseren) 1 = insert bit of data byte starting with lsb 1 1 1 h g f 1 e 1 1 1 d c b 1 a 1 1 1 q p o . . . t1/cept pcm-30 serial output ts m in frame n ts m in frame n+1 ts m in frame n+2 lsb transmitted data figure 6. 32kb/s subrate operation - single transmit channel
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 11 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| figure 7. transmit frame synchronization timing - t1 mode, sis = 1 figure 8. transmit frame synchronization timing - cept pcm-30 mode, sis = 1 bit 7 bit 8 bit f bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 channel 24 channel 1 tclk tmax fill/mask* tseren (low) tser tseren (high) tser high z high z high z data data data data data data data data data data time fill 111 * the f-bit time is processed as if the fill/mask = 0. however, this actual fill/mask does not apply to the f-bit. 1 time fill bit 7 bit 8 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 time-slot 31 time-slot 0 tclk tmax fill/mask tseren (low) tser tseren (high) tser high z high z high z data data data data data data data data data data time fill 111 1 time fill
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 12 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| figure 9. transmit frame synchronization timing - t1 mode, sis = 0 figure 10. transmit frame synchronization timing - cept pcm-30 mode, sis = 0 bit 7 bit 8 bit f bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 channel 24 channel 1 tclk tmax fill/mask* tseren (low) tser tseren (high) tser high z high z high z * the f-bit time is processed as if the fill/mask = 0. however, this actual fill/mask does not apply to the f-bit. data data data data data data data data data data time fill 111 1 time fill bit 8 bit 7 bit 8 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 time-slot 31 time-slot 0 tclk tmax fill/mask tseren (low) tser tseren (high) tser high z high z high z data data data data data data data data data data time fill 111 1 time fill bit 1
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 13 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| figure 11. standard hyperchannel provisory f 123456789101112131415s171819202122232425262728293031 framing time-slot (8 bits) signaling channel (8 bits) 64kb/s f 1 s 1 cept pcm-30 mode ts 0, ch 00000 data channel (8 bits) (typ.) ts 1, ch 00001 ts 17, ch 10001 ts 31, ch 11111 ts 16, ch 10000 1920 kb/s ts 1, ch 00001 h12 h0 f123456789101112131415161718192021222324 64kb/s f 1 2 3 4 ch 00001 ch 00010 ch 11000 384 kb/s f 1 1536 kb/s h11 note : grouping of 64kb/s channels into standard hyperchannels is fixed as shown. time-slot assignments can be changed (when hcs1 hcs0 = 00) to create flexible hyperchannels by programming command buffers. t1 mode table 3. hyperchannel selection t p e c / 1 tt p e c / 1 t t p e c / 1 t t p e c / 1 tt p e c / 1 t1 s c h1 s c h 1 s c h 1 s c h1 s c h0 s c h0 s c h 0 s c h 0 s c h0 s c hn o i t c e l e s l e n n a h cn o i t c e l e s l e n n a h c n o i t c e l e s l e n n a h c n o i t c e l e s l e n n a h cn o i t c e l e s l e n n a h c x00 ) d e m m a r g o r p e b n a c l e n n a h c r e p y h e l b i x e l f ( . s / b k 4 6 e r a s l e n n a h c l l a 110 . y l n o 1 t r o f d i l a v . ) 0 h ( s / b k 4 8 3 f o s l e n n a h c r u o f 10 1 . y l n o 1 t r o f d i l a v . ) 1 1 h ( s / b m 8 3 5 . 1 f o l e n n a h c e l g n i s 010 t p e c r o f d i l a v . s / b k 4 6 e r a 6 1 d n a 0 s t o l s - e m i t . ) 2 1 h ( s / b m 2 9 . 1 f o l e n n a h c e l g n i s . y l n o x11 . d e v r e s e r 001 . d e v r e s e r hyperchannel three standard isdn hyperchannel options (two for t1, one for cept pcm-30) are available by setting hcs0 and hcs1 as well as t1/cept pins. see table 3 and figure 11. all channels can also be randomly grouped into flexible hyperchannel (with hcs0 hcs1 = 00). a hyperchannel can contains any number of 64kb/s channels. details is illustrated in ?external memory organization and definition? and table 10.
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 14 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| tri-state serial data output tser the tser can be set to different state by setting tseren pin and fill/mask byte in the transmit command buffer. see table 4. table 4. output selection on tser when tseren = 0, and fill/mask bit = 0, the tser output line is in high impedance. this feature allows to connect up to eight PT7A6632 devices together to realize subrate tdm trans- mission. channel operation modes the transmit channels can be set in the following operation modes by cpu in transmit command buffer. see mode byte in the transmit command buffer for details (figure 24). hdlc mode in hdlc mode, the transmit processor generates flags, abort and idle code, inserts zero-bit, count the frame check se- quences (fcs) for the data. in hdlc mode, it is programmable to attach a number of flags to the end of hdlc frame as time-fill sequence. the number of flags is specified in the transmit data buffer. the PT7A6632 counts the intentionally inserted zeroes based on hdlc format. these intentionally inserted zeroes may be counted as intraframe time-fill bits. in this case, the programmed flag number will be adjusted according to the counting result. reset the device will make all channels in hdlc mode. non-hdlc data mode in non-hdlc data mode, the data from memory directly trans- mit on tser. in non-hdlc data channel mode (dmi mode 0 or 1), cf/p bit of status byte of allocated data buffer should be reset to ensure uninterrupted data transmit. n e r e s tn e r e s t n e r e s t n e r e s tn e r e s tk s a m / l l i fk s a m / l l i f k s a m / l l i f k s a m / l l i fk s a m / l l i fr e s t n o t u p t u or e s t n o t u p t u o r e s t n o t u p t u o r e s t n o t u p t u or e s t n o t u p t u o 10 1 a d n e s 00 t u p t u o e c n a d e p m i - h g i h 11 a t a d d n e s 01 a t a d d n e s non-hdlc signaling mode the non-hdlc signaling requires no special consideration in transmit data processing. in non-hdlc signaling mode, cf/p bit of status byte of allocated data buffer should be reset to ensure uninterrupted data transmit. the PT7A6632 assumes that no more than 2 linked data buffers are allocated to the signaling channel by the cpu. details are shown in section ?external memory or- ganization and definition? and tables 8 and 14. loop mode when a transmit channel is specified in loop mode, the PT7A6632 will send the data of this channel into an interme- diate buffer in PT7A6632 in channel period while sends the data to tser output. the data then will be sent back to the external memory via a receive channel in loop mode. each time only one transmit and one receive channel can be speci- fied in loop mode. the transmit loop channel number and receive loop channel number are not necessarily identical. the loop mode does not support hyperchannel. if only a transmit loop channel is defined without a receive loop channel defined, the loop operation can not be performed. reset the device will delete all loop mode. logical inversion if a transmit channel is set in inversion mode, data including flag, abort and fcs bits will be inverted bit by bit when transmit processing. device reset sets all channel in inversion mode. data transmission order the PT7A6632 transmits data bytes in the same time sequence as they are arranged in ascending addresses in the external buffers. for a certain channel, the data at byte address m is transmitted first, the data at address m+1 is transmitted next, and so on while the data bytes are in the same buffer. after the data in a data buffer is exhausted, the PT7A6632 starts to trans- mit the next byte from the next buffer whose address is speci- fied in the current buffer. the transition to the next buffer is transparent to the cpu while the flow of actual data is main- tained. this natural sequence of data flow is maintained for flexible hyperchannels, as well. the PT7A6632 transmits the lsb (d0) of a data byte first; then the next lsb second; and the msb (d7) last. the only exception is that the msb of the hdlc fcs (crc-ccitt) is transmitted first; the lsb transmitted last.
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 15 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| figure 12. block diagram of receive bit-level processor receive interface deformat & fill/mask filter (32 channels) tclk state/control signal rred rser rsync rclk elastic buffer to/from memory manager receive bit-level processor the block diagram of the receive bit-level processor is shown in figure 12. the receive bit-level processor accept serial data from the t1/e1 trunk interface, perform hdlc deformat (pro- cesses flags, abort, deletes zeroes, checks fcs, filters time-fill bits), or other non-hdlc functions and assemble the processed bit, including hdlc header, into bytes and sends them into the external memory. the cpu sets up the channel operation in a set of linked buffers (referred as receive command/data buffer) in the external memory. refer to figure 26 and 27 in the section ?external memory organization and definition?. timing generally, the starting of a data frame received from the t1/e1 trunk interface is not correlated with that of a transmit frame. as PT7A6632 uses same 8-bit memory bus for data writing and reading, an elastic buffer is adopted to coordinate the data access on the bus. the received data stream is clocked into the elastic buffer by the rclk and then clocked out to the deformat and rate adapt circuit by the tclk. in this way, the data flow on the memory bus is simple and coordinated. the data is sampled and processed in rising edge (sis = 0) or falling edge (sis = 1) of the rclk. see figure 14-17. the rsync is used for receive frame synchronization. data rate adaptation reverse process of data rate adaptation of transmission. illus- trated in figure 13. receive mornitor the PT7A6632 monitors the receive red alarm (rred) in- put. once the PT7A6632 detects rred high, it will stop data processing in all receive channels and reports by writing the status byte. the synchronization will be restored by tmax and rsync signals. the PT7A6632 performs data validity check (checks crc) for the received data. once the PT7A6632 finds any errors in the crc, the receive interface will stop data processing in current channel until detects a new hdlc flag byte. the situation is reported to the external memory. details are shown in table 11 for status byte, abrt, fcer and sher bits in section ?ex- ternal memory organization and definition?. hyperchannel three standard isdn hyperchannel options (two for t1, one for cept pcm-30) are available by setting hcs0 and hcs1 as well as t1/cept pins. see table 3 and figure 11. the channels can also be randomly grouped into flexible hyperchannel (with hcs0 hcs1 = 00). a hyperchannel can contains any number of 32 64kb/s channels. details is illus- trated in section ?external memory organization and defini- tion? and table 10. channel operation modes see receive command buffer in section ?external memory or- ganization and definition? for details (figure 27).
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 16 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| a b c d e f g h msb lsb received data 1 0 1 1 1 0 0 0 fill/mask a 1 b c d 1 1 1 e 1 f g h 1 1 1 t1/cept pcm-30 serial input ts m in frame n+1 ts m in frame n assembled data byte figure 13. 32kb/s subrate operation - single receive channel figure 14. receive frame synchronization timing - t1 mode, sis = 1 ~ ~ ~ ~ ~ ~ ~ ~ proving period 1 ( one full multiframe) proving period 2 (one full multiframe) proving period 3 (one full multiframe) (one full multiframe) from this point, fully multiframe synchronized until rred goes high channel 1, first frame of the next multiframe channel 24, last frame of a multiframe bit 7 bit 8 bit f bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 rred rsync rclk rser rred rsync ~ ~ ~ ~ ~ ~ ~ ~ hdlc mode in hdlc mode, the receive processor detects flags, abort, delete zero-bit, check the frame check sequences (fcs), and filters the time-fill bits by applying fill/mask byte to the received data. reset the device will make all channels in hdlc mode. non-hdlc data mode in this mode, received data are directly written into external memory without deformating. non-hdlc signaling mode in non-hdlc signaling mode, PT7A6632 detects the multiframe alignment sequence. if the alignment sequence is valid, the received data will be sent to the external memory; if not, the data will not be sent to external memory until a valid alignment sequence is detected. the loss of the multiframe alignment will be reported to external memory. any channel(s) can be specified to receive bit-oriented signaling. this feature is very useful in central office switching applications.
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 17 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| figure 15. receive frame synchronization timing - cept pcm-30 mode, sis = 1 figure 16. receive frame synchronization timing - t1 mode, sis = 0 ~ ~ ~ ~ ~ ~ ~ ~ proving period 1 ( one full multiframe) proving period 2 (one full multiframe) proving period 3 (one full multiframe) (one full multiframe) from this point, fully multiframe synchronized until rred goes high time-slot 0, first frame of the next multiframe time-slot 31, last frame of a multiframe bit 7 bit 8 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 rred rsync rclk rser rred rsync ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ proving period 1 ( one full multiframe) proving period 2 (one full multiframe) proving period 3 (one full multiframe) (one full multiframe) from this point, fully multiframe synchronized until rred goes high channel 1, first frame of the next multiframe channel 24, last frame of a multiframe bit 7 bit 8 bit f bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 rred rsync rclk rser rred rsync ~ ~ ~ ~ ~ ~ ~ ~
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 18 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| figure 17. receive frame synchronization timing - cept pcm-30 mode, sis = 0 loop mode when a receive channel is specified in loop mode, data to be sent to the external memory is not from the external t1/e1 trunk interface, instead, it is fetched internally from an inter- mediate buffer in the PT7A6632, in which the data was from a loop mode transmit channel. thus the data from the external memory is feedback to external memory. each time only one transmit and one receive channel can be specified in loop mode to guarantee normal operation. the transmit loop chan- nel no. and receive loop channel no. are not necessarily iden- tical. the loop mode does not support hyperchannel. reset the device will delete all loop mode. logical inversion if a receive channel is set in inversion mode, the received data will be inverted bit by bit when being processed, including flag, abort and fcs bits. reset the device will make all channel in inversion mode. data reception order the PT7A6632 writes received data bytes in the external memory in the same order in which they are received in time. for a certain channel, the first received byte is written at byte address m, the second received at byte address m+1, and so on as long as the buffer is not completely filled or an end-of-frame is not reached. after the end of the frame or the end of the buffer (whichever occurs first) is detected, the PT7A6632 writes the next received data byte at the first allocated address of the next available buffer. the PT7A6632 writes the first received data bit of an octet at the lsb (d0) position of the external buffer byte, the second received data bit at the next to lsb position, and so on. the last (8th) received data bit of an octet is written at the msb (d7) position of the data byte. ~ ~ ~ ~ ~ ~ ~ ~ proving period 1 ( one full multiframe) proving period 2 (one full multiframe) proving period 3 (one full multiframe) (one full multiframe) from this point, fully multiframe synchronized until rred goes high time-slot 0, first frame of the next multiframe time-slot 31, last frame of a multiframe bit 6 bit 7 bit 8 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 rred rsync rclk rser rred rsync ~ ~ ~ ~ ~ ~ ~ ~
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 19 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| memory manager the memory manager controls data flow between transmit processor/receive processor and the external memory as shown in figure 18. cpu assigns the external memory into several parts for activation information (activation memory) and data processing information (data processing memory) as shown in figure 20 in section ?external memory organization and definition?. the data processing memory is allocated to each transmit and receive channel for data, command and status storage. the cpu allocated enough memory in the buffers for the real-time operation of transmit and receive with no data underrun or overrun. the external memory is managed with minimal inter- vention from the cpu. the cpu sends out an attn signal to command PT7A6632 to access the activation memory that contains channel number and channel starting address. the sysacc signal is asserted by PT7A6632 during accessing the activation memory. after the access, the atack will be asserted. the data processing memory contains such information as next buffer address, operation mode, buffer size, data length, buffer status and hdlc frame completion status. they are set up by cpu. PT7A6632 accesses the buffers and processes data and update the status in the buffers after processing. dmnd is asserted by the PT7A6632 to inform other devices using the memory bus that PT7A6632 will access the external memory one tclk period after rising edge of the dmnd. intr as- serted when PT7A6632 updates the status byte in buffers. the memory manager responds to cpu-initiated changes in the operational modes of a channel or relocation of the allocated buffers without affecting the operation of the other channels. the timing for the memory access is generated from sysclk. from rx bit-level processor / to tx bit-level processors memory manager a0-a15 d0-d7 read write as dmnd attn atack, sysacc, intr external memory sysclk cpu PT7A6632 3 figure 18. diagram of memory manager with external memory and cpu state/control machine the state/control machine processes the device mode and status. mdfs sets the memory location pattern, i.e., the even addresses in external memory are for higher bytes (mdfs = 1) or for lower bytes (mdfs = 0) of the next buffer starting ad- dress, buffer size and data length respectively. figure 19 uaen sets the upper address lines (a8 - a15) in high imped- ance (uaen = 1) or in low state (uaen = 0) when accessing activation memory. when the upper address lines in high im- pedance, the cpu can drive them to any state during accessing activation memory. hcs0, hcs1 and t1/cept select t1 or cept pcm-30 mode and hyperchannel (table 3). sis selects trigger edge of rclk and tclk. tseren sets tser output line state, i.e., sending data, sending ?1? or in high impedance (table 4). ch0 to ch4 and rx/tx are status outputs indicating the cur- rent active channel number and direction. ch0 is lsb, ch4 is msb. the main clock for PT7A6632 is generated by the state/con- trol machine from sysclk. ch0- ch4 rx/tx reset hcs0-hcs1 t1/cept sis uaen mdfs state / control machine 5 2 to rx and tx processors & memory manager
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 20 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| external memory organization and definition general structure the external memory is divided by the cpu into two func- tional blocks for channel activation and data processing, re- ferred as activation memory and data processing memory. the activation memory contains channel activation byte and channel buffer pointers, providing PT7A6632 such in- formation as channel activation/deactivation, channel direc- tion (transmit or receive) and channel starting addresses. cpu allocates the channel starting pointer for each receive and transmit channel. the data processing memory contains data/command buffers storing descriptors, user?s data received or to be transmitted, channel operation mode and status. cpu allocates a set of linked data/command buffers for each receive and transmit channel. details are shown in figures 20-22. (address) external memory (contents) channel activation b y te 128 bytes of system memory for channel buffer pointers data processing memory 0 1 2 j j + 128 to j + 255 p p + 1 to p + n 1 x x + 1 to x + n - 1 n-byte data buffer for rx channel #k n-byte data buffer for tx channel #m ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ activation memor y figure 20. external memory map - top level
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 21 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| activation memory the activation memory map is shown in the figure 21. channel activation byte the channel activation byte are illustrated in the following table 5. the PT7A6632 reads this byte so that gets the channel number, the channel state (active or inactive) and the channel direction (transmit or receive). the PT7A6632 asserts sysacc when it accesses the activation memory. channel buffer pointers channel buffer pointers provide PT7A6632 the channel start- ing address (16-bit) for each channel, 64 channels totally, guid- ing to a link of buffers containing data and command. the relative location of the upper and lower bytes of the 16-bit start address word is determined by the mdfs input (see fig- ure 17). the upper address lines (a8-a15) are placed in the high-impedance state or low by the PT7A6632 during the activation memory accesses. figure 21a. activation memory map locations ( mdfs = high) channel activation byte channel buffer pointers 7 6 5 4 3 2 1 0 xx00 active x rx/tx channel number xx01 xx7f byte addresses xx01 through xx7f are not used by PT7A6632 xx80 transmit channel 0 start address (high-order byte) xx81 transmit channel 0 start address (low-order byte) xx82 transmit channel 1 start address (high-order byte) xx83 transmit channel 1 start address (low-order byte) transmit channels 2 to 30 start addresses xxbe transmit channel 31 start address (high-order byte) xxbf transmit channel 31 start address (low-order byte) xxc0 receive channel 0 start address (high-order byte) xxc1 receive channel 0 start address (low-order byte) receive channels 1 to 30 start address xxfe receive channel 31 start address (high-order byte) xxff receive channel 31 start address (low-order byte) ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ a. mdfs = high (68000 based) (address) (hex) (contents) 7 t i b7 t i b 7 t i b 7 t i b7 t i b6 t i b6 t i b 6 t i b 6 t i b6 t i b5 t i b5 t i b 5 t i b 5 t i b5 t i b4 t i b4 t i b 4 t i b 4 t i b4 t i b3 t i b3 t i b 3 t i b 3 t i b3 t i b2 t i b2 t i b 2 t i b 2 t i b2 t i b1 t i b1 t i b 1 t i b 1 t i b1 t i b0 t i b0 t i b 0 t i b 0 t i b0 t i b t i b e v i t c at i b e v i t c a t i b e v i t c a t i b e v i t c at i b e v i t c at i b x t / x rt i b x t / x r t i b x t / x r t i b x t / x rt i b x t / x r) y r a n i b ( 1 3 ~ 0 r e b m u n l e n n a h c) y r a n i b ( 1 3 ~ 0 r e b m u n l e n n a h c ) y r a n i b ( 1 3 ~ 0 r e b m u n l e n n a h c ) y r a n i b ( 1 3 ~ 0 r e b m u n l e n n a h c) y r a n i b ( 1 3 ~ 0 r e b m u n l e n n a h c 10 d e s u n u 10 , 0 l e n n a h c - 0 0 0 0 0 , 1 l e n n a h c - 1 0 0 0 0 , 2 l e n n a h c - 0 1 0 0 0 . c t e l e n n a h c e h t d e t a v i t c a l e n n a h c e h t d e t a v i t c a e d e v i e c e rt i m s n a r t table 5. channel activation byte
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 22 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| figure 21b. activation memory map locations ( mdfs = low) 7 6 5 4 3 2 1 0 xx00 active x rx/tx channel number xx01 xx7f byte addresses xx01 through xx7f are not used by PT7A6632 xx80 transmit channel 0 start address (low-order byte) xx81 transmit channel 0 start address (high-order byte) xx82 transmit channel 1 start address (low-order byte) xx83 transmit channel 1 start address (high-order byte) transmit channels 2 to 30 start addresses xxbe transmit channel 31 start address (low-order byte) xxbf transmit channel 31 start address (high-order byte) xxc0 receive channel 0 start address (low-order byte) xxc1 receive channel 0 start address (high-order byte) receive channels 1 to 30 start address xxfe receive channel 31 start address (low-order byte) xxff receive channel 31 start address (high-order byte) ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ b. mdfs = low (iapx 86 based) (address) (hex) (contents) channel activation byte channel buffer pointers
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 23 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| next buffer start address buffer size data length status byte ~ ~ m m+7 m+7+1 m+7+n buffer 2 8 bytes of buffer descriptor* 70 next buffer start address buffer size data length status byte ~ ~ address i i+7 i+7+1 i+7+k buffer 1 8 bytes of buffer descriptor* data or command 70 next buffer start address buffer size data length status byte ~ ~ p p+7 p+7+1 p+7+r buffer n 8 bytes of buffer descriptor* 70 * formats are different for data buffer and command buffer, and differs with mdfs ~ ~ ~ ~ ~ ~ k bytes of user s data or 2 bytes of channel mode & rate definition data r bytes of user s data or 2 bytes of channel mode & rate definition data n bytes of user s data or 2 bytes of channel mode & rate definition data data or command data or command figure 22. organization and linking of data or command buffers
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 24 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| i i+1 i+2 not used i+3 i+4 fc fo not used i+5 i+6 not used by PT7A6632 i+7 undr ivba not used cf/p cmnd mpty (i+7)+1 (i+7)+2 (i+7)+j (i+7)+j+1 (i+7)+k a. mdfs = 1 ~ ~ ~ ~ (address) next buffer address buffer size (k) msb lsb data length (j) lsb lsb msb status (0) first date b y te second date byte last date byte flag count (optional) last location in buffer ~ ~ ~ ~ - descripto rs i i+1 i+2 i+3 not used i+4 i+5 fc fo not used i+6 undr ivba not used cf/p cmnd mpty i+7 not used by PT7A6632 (i+7)+1 (i+7)+2 (i+7)+j (i+7)+j+1 (i+7)+k b. mdfs = 0 ~ ~ ~ ~ (address) 7 (contents) 0 next buffer address buffer size (k) msb lsb data length (j) lsb lsb msb status (0) first date b y te second date byte last date byte flag count (optional) last location in buffer ~ ~ ~ ~ - descriptor s data data 7 (contents) 0 msb msb figure 23. transmit data buffer data processing memory general the data processing memory refers to data or command buff- ers which are linked each other. the PT7A6632 accesses the data processing memory for transmit/receive data and opera- tion commands. each buffer has following configuration (see figure 22): 8-byte descriptors data bytes to be transmitted or received or command there are 4 kinds of buffers, transmit data buffer and trans- mit command buffer for transmit channels, and receive data buffer and receive command buffer for receive channels. transmit data buffer the transmit data buffer contains 8 bytes of descriptors and j bytes of user?s data as shown in figure 23. the mdfs pin decides the most significant byte and least significant byte locations (in even and odd addresses). descriptors the first 8 bytes in the transmit data buffer is descriptors that specifies next buffer address, buffer size, data length and status respectively. see table 6 for the definition. data bytes following the descriptors are the data to be transmitted. the number of bytes are specified by data length (for complete data buffer) or buffer size (for partial data buffer). the buffer may contains last byte of a frame (cf/p = 1) or partial data of a frame (cf/p = 0) in hdlc mode. the cf/p should be reset for other modes. flag count byte (optional) specifies the additional flags to be added after ?crc + one flag? of a frame. it will be read only when flag control bit in the ms byte of data length is set (fc = 1).
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 25 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| e m a ne m a n e m a n e m a ne m a nn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d r e f f u b t x e nr e f f u b t x e n r e f f u b t x e n r e f f u b t x e nr e f f u b t x e n s s e r d d a s s e c c a o t 2 3 6 6 r o f r e f f u b t x e n o t g n i t n i o p , d r o w s s e r d d a t i b - 6 1 e z i s r e f f u be z i s r e f f u b e z i s r e f f u b e z i s r e f f u be z i s r e f f u b s d a e r 2 3 6 6 e h t . r e f f u b t n e r r u c r o f u p c e h t y b d e t a c o l l a s n o i t a c o l y r o m e m f o r e b m u n e t y b s e i f i c e p s , t i b - 2 1 2 3 6 6 e h t . a t a d l a i t r a p s n i a t n o c r e f f u b a t a d e h t t a h t s w o h s ) 0 = p / f c ( s u t a t s e h t n e h w y l n o e z i s r e f f u b e h t . r e f f u b s i h t n i s e t y b a t a d f o r e b m u n l a u t c a e h t o t e z i s r e f f u b e h t t r e v n o c l l i w c fc f c f c fc f l o r t n o c g a l fl o r t n o c g a l f l o r t n o c g a l f l o r t n o c g a l fl o r t n o c g a l f r o f c r c d e w o l l o f g a l f e n o m u m i n i m e h t t p e c x e ( s g a l f l a n o i t i d d a y n a f i s e t a c i d n i , t i b - 1 : , u p c e h t y b t e s e r s i c f f i . a t a d c l d h e h t f o ) g a l f 1 + c r c ( e h t r e t f a d e x i d n e p p a e b o t ) t a m r o f c l d h e b o t ) s ( g a l f l a n o i t i d d a e b l l i w e r e h t s n a e m t i , u p c e h t y b t e s f i . d e d d a e b o t g a l f l a n o i t i d d a o n s n a e m t i n i e t y b t n u o c g a l f l a n o i t p o e h t n i d e i f i c e p s s i ) s ( g a l f l a n o i t i d d a e h t f o r e b m u n e h t . a t a d e h t o t d e d d a . r e f f u b a t a d x t e h t o fo f o f o fo f t n u o c t e s f f o g a l ft n u o c t e s f f o g a l f t n u o c t e s f f o g a l f t n u o c t e s f f o g a l ft n u o c t e s f f o g a l f s t n u o c l e n n a h c x t e h t , u p c e h t y b t e s s i o f f i . 1 = c f n e h w y l n o l u f g n i n a e m , t i b - 1 : s t l u s e r d e t n u o c e h t s e d i v i d n e h t , l o c o t o r p c l d h n o d e s a b s o r e z d e t r e s n i y l l a n o i t n e t n i f o r e b m u n l a t o t e h t e h t . a t a d e h t n i d e t r e s n i e t y b a t a d - n o n f o r e b m u n e h t s t n e s e r p e r ) " t e s f f o g a l f " d e l l a c ( t n e i t o u q e h t . 8 y b d e t r e s n i e h t f o e g d e l w o n k t u o h t i w t e s s a w h c i h w , t n u o c g a l f e h t m o r f t e s f f o g a l f e h t s t c a r t b u s 2 3 6 6 . a t a d e h t o t d e d d a e b o t s g a l f l a n o i t i d d a f o r e b m u n l a u t c a e h t s i t n a t l u s e r e h t . s o r e z h t g n e l a t a dh t g n e l a t a d h t g n e l a t a d h t g n e l a t a dh t g n e l a t a d s d a e r 2 3 6 6 e h t . r e f f u b a t a d x t e h t n i d e t t i m s n a r t e b o t s e t y b a t a d f o r e b m u n l a u t c a e h t s e i f i c e p s , t i b - 2 1 . ) 1 = p / f c ( e m a r f a f o e t y b t s a l e h t s n i a t n o c r e f f u b e h t t a h t s w o h s s u t a t s e h t f i y l n o h t g n e l a t a d e h t y t p my t p m y t p m y t p my t p m y t p m ey t p m e y t p m e y t p m ey t p m e e h t . n o i s s i m s n a r t r o f y d a e r t o n s i a t a d , . e . i , y t p m e s i r e f f u b e h t s n a e m t i , u p c e h t y b t e s f i , t i b - 1 : s t e s 2 3 6 6 . y d a e r s i a t a d e h t n e h w t i b s i h t s t e s e r u p c e h t . t e s e r s i t i l i t n u t i b s i h t g n i l l o p p e e k l l i w 2 3 6 6 . s n o i t a c o l y t p m e e h t s e s u e r n a c u p c e h t d n a , r e f f u b e h t n i n o i s s i m s n a r t a t a d s e t e l p m o c t i e c n o 1 o t t i b e h t d n m cd n m c d n m c d n m cd n m c d n a m m o cd n a m m o c d n a m m o c d n a m m o cd n a m m o c t i , u p c e h t y b t e s e r f i . r e f f u b d n a m m o c a s i r e f f u b e h t s n a e m t i , u p c e h t y b t e s n e h w , t i b - 1 : . r e f f u b a t a d a s i p / f cp / f c p / f c p / f cp / f c : r e f f u b a t a d l a i t r a p / e m a r f e t e l p m o c: r e f f u b a t a d l a i t r a p / e m a r f e t e l p m o c : r e f f u b a t a d l a i t r a p / e m a r f e t e l p m o c : r e f f u b a t a d l a i t r a p / e m a r f e t e l p m o c: r e f f u b a t a d l a i t r a p / e m a r f e t e l p m o c t s a l e h t s n i a t n o c r e f f u b a t a d e h t t a h t w o h s o t u p c e h t y b t e s , t i b - 1 a t a d . x a m ( h t g n e l a t a d e h t y b d e i f i c e p s s i s e t y b a t a d f o r e b m u n l a u t c a . a t a d d e m a r f c l d h n a f o e t y b . ) 5 9 0 4 : h t g n e l g n i d e e c c u s n i s i a t a d t s e r e h t d n a , e m a r f a f o a t a d l a i t r a p s n i a t n o c r e f f u b e h t s n a e m t i , u p c e h t y b t e s e r s i t i f i s i s e t y b a t a d f o r e b m u n l a u t c a . r e f f u b g n i d s s e c c u s t x e n e h t o t s n r u t y l l a c i t a m o t u a 2 3 6 6 e h t . ) s ( r e f f u b . ) 5 9 0 4 : e z i s r e f f u b . x a m ( e z i s r e f f u b e h t y b d e i f i c e p s n o i s s i m s n a r t a t a d e s i w r e h t o , n o i s s i m s n a r t a t a d y l s u o u n i t n o c r o f 0 e b d l u o h s t i b e h t , a t a d c l d h - n o n r o f . d e t p u r r e t n i e b l l i w a b v ia b v i a b v i a b v ia b v i s s e r d d a r e f f u b d i l a v n is s e r d d a r e f f u b d i l a v n i s s e r d d a r e f f u b d i l a v n i s s e r d d a r e f f u b d i l a v n is s e r d d a r e f f u b d i l a v n i s a h c u s , . e . i , s s e r d d a r e f f u b t x e n d i l a v n i n a s d n i f t i f i t i b e h t s t e s 2 3 6 6 e h t , t i b - 1 : s e t y b e n o - l l a d n a d e t a v i t c a e d e b l l i w l e n n a h c x t e h t , e s a c s i h t n i . x f f f f o m r o f n i r o s o r e z 6 1 f o s s e r d d a . u p c e h t y b d e t a v i t c a - e r s i l e n n a h c e h t l i t n u d e t t i m s n a r t e b r d n ur d n u r d n u r d n ur d n u n u r r e d n un u r r e d n u n u r r e d n u n u r r e d n un u r r e d n u s d n i f 2 3 6 6 e h t n e h w , . g . e , a t a d f o t u o s n u r l e n n a h c x t t n e r r u c e h t f i t i b e h t s t e s 2 3 6 6 e h t , t i b - 1 : e h t , o s f i . r e f f u b a t a d l a i t r a p a g n i w o l l o f r e f f u b d n a m m o c a r o , r e f f u b y t p m e n a , s s e r d d a r e f f u b d i l a v n i n a , ) e d o m c l d h n i f i ( d e r a e l c s i n o i t i d n o c e h t l i t n u s g a l f y b d e w o l l o f e d o c t r o b a n a t u o d n e s l l i w 2 3 6 6 f i ( r e f f u b a t a d y t p m e - n o n d i l a v a p u s t e s u p c e h t l i t n u y l d e t a e p e r s e t y b s e n o - l l a t u o d n e s l l i w 2 3 6 6 e h t r o . ) e d o m c l d h - n o n n i table 6. descriptors in transmit data buffer
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 26 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| transmit command buffer the transmit command buffer contains 8 bytes of descriptors and 2 bytes of channel mode & rate definition data (and maybe the hyperchannel configuring bytes) as shown in figure 24. the mdfs pin decides the ms byte and ls byte locations (in even and odd addresses). figure 24. transmit command buffer i i+1 i+2 not used i+3 not used i+4 not used i+5 i+6 not used i+7 x ivba not used cf/p cmnd mpty (i+7)+1 0 0 0 0 inv loop sig hdlc (i+7)+2 (i+7)+3 e a x channel number (i+7)+j e a x channel number a. mdfs = 1 ~ ~ (address) next buffer address data length (j) lsb lsb msb status (1) mode fill/mask ~ ~ - descriptor s 7 (contents) 0 i i+1 i+2 not used i+3 not used i+4 i+5 not used i+6 x ivba not used cf/p cmnd mpty i+7 not used (i+7)+1 0 0 0 0 inv loop sig hdlc (i+7)+2 (i+7)+3 e a x channel number (i+7)+j e a x channel number b. mdfs = 0 ~ ~ (address) next buffer address data length (j) lsb lsb msb status (1) mode fill/mask ~ ~ - descriptor s 7 (contents) 0 hyperchannel configuring hyperchannel configuring msb msb
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 27 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| table 7. descriptors in transmit command buffer e m a ne m a n e m a n e m a ne m a nn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d r e f f u b t x e nr e f f u b t x e n r e f f u b t x e n r e f f u b t x e nr e f f u b t x e n s s e r d d a s s e c c a o t 2 3 6 6 r o f r e f f u b t x e n o t g n i t n i o p , d r o w s s e r d d a t i b - 6 1 h t g n e l a t a dh t g n e l a t a d h t g n e l a t a d h t g n e l a t a dh t g n e l a t a d . s s e c o r p l e n n a h c r e p y h e l b i x e l f r o s s e c o r p l e n n a h c r e p y h - e l b i x e l f - n o n e h t s e d i c e d , t i b - 8 , s s e c o r p l e n n a h c r e p y h - n o n y l n o , 2 r o 1 , 0 = h t g n e l a t a d . s s e c o r p l e n n a h c r e p y h s i e r e h t , 2 > h t g n e l a t a d y t p my t p m y t p m y t p my t p m y t p m ey t p m e y t p m e y t p m ey t p m e e s a c s i h t n i . y d a e r t o n s i a t a d d n a m m o c , . e . i , y t p m e s i r e f f u b e h t t a h t w o h s o t t i s t e s u p c e h t , t i b - 1 : . y d a e r s i a t a d d n a m m o c e h t n e h w t i b s i h t s t e s e r u p c e h t . t e s e r s i t i l i t n u t i b s i h t g n i l l o p p e e k l l i w 2 3 6 6 e h t . r e f f u b e h t n i g n i s s e c o r p d n a m m o c f o n o i t e l p m o c u p c e h t m r o f n i o t t i b e h t s t e s 2 3 6 6 d n m cd n m c d n m c d n m cd n m cd n a m m o cd n a m m o c d n a m m o c d n a m m o cd n a m m o c. r e f f u b d n a m m o c a s i r e f f u b e h t e t a c i d n i o t u p c e h t y b t e s , t i b - 1 : p / f cp / f c p / f c p / f cp / f c : r e f f u b d n a m m o c l a i t r a p / r e f f u b d n a m m o c e t e l p m o c: r e f f u b d n a m m o c l a i t r a p / r e f f u b d n a m m o c e t e l p m o c : r e f f u b d n a m m o c l a i t r a p / r e f f u b d n a m m o c e t e l p m o c : r e f f u b d n a m m o c l a i t r a p / r e f f u b d n a m m o c e t e l p m o c: r e f f u b d n a m m o c l a i t r a p / r e f f u b d n a m m o c e t e l p m o c e h t t a h t e t a c i d n i o t u p c e h t y b t e s , t i b - 1 e h t , g n i s s e c o r p r e f f u b d n a m m o c e t e l p m o c e h t g n i r u d . r e f f u b d n a m m o c e t e l p m o c a s i r e f f u b d n a m m o c . e d o m c l d h n i s i t i f i t r o b a c l d h n a t i m s n a r t l l i w 2 3 6 6 e h t e s a c s i h t n i . ) 1 = d n m c , 0 = p / f c ( r e f f u b d n a m m o c l a i t r a p a e t a c i d n i o t t i b p / f c e h t s t e s e r u p c e h t . r e f f u b t x e n s s e c o r p o t e u n i t n o c n e h t , ) s ( e t y b s e n o - l l a c l d h - n o n r o g a l f c l d h d n e s l l i w 2 3 6 6 a b v ia b v i a b v i a b v ia b v i s s e r d d a r e f f u b d i l a v n is s e r d d a r e f f u b d i l a v n i s s e r d d a r e f f u b d i l a v n i s s e r d d a r e f f u b d i l a v n is s e r d d a r e f f u b d i l a v n i s a h c u s , s s e r d d a r e f f u b t x e n d i l a v n i n a s d n i f t i f i t i b e h t s t e s 2 3 6 6 e h t , t i b - 1 : e b s t i b e n o - l l a d n a d e t a v i t c a e d e b l l i w l e n n a h c x t e h t , e s a c s i h t n i . x f f f f o m r o f n i r o s o r e z 6 1 f o s s e r d d a . u p c e h t y b d e t a v i t c a - e r s i l e n n a h c e h t l i t n u d e t t i m s n a r t descriptors the first 8 bytes in the transmit command buffer are descriptors that specify next buffer address, data length and status respectively. see table 7 for the definition.
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 28 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| table 8. mode byte in transmit command buffer e d o me d o m e d o m e d o me d o me m a ne m a n e m a n e m a ne m a nn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d 4 - 7 s t i bd e s u t o n 3 t i b v n iv n i v n i v n iv n i 1n o i t r e v n i 0n o i t r e v n i - n o n 2 t i b p o o lp o o l p o o l p o o lp o o l 1l e n n a h c p o o l 0l e n n a h c p o o l - n o n 0 t i b , 1 t i b c l d h , g i sc l d h , g i s c l d h , g i s c l d h , g i sc l d h , g i s 0 0 e d o m l e n n a h c a t a d c l d h - n o ne d o m l e n n a h c a t a d c l d h - n o n e d o m l e n n a h c a t a d c l d h - n o n e d o m l e n n a h c a t a d c l d h - n o ne d o m l e n n a h c a t a d c l d h - n o n t e s e r e b d l u o h s p / f c . n o i t a c i l p p a i m d f o 1 d n a 0 s e d o m n i d e s u : y l d e t a e p e r e t y b e n o - l l a t i m s n a r t l l i w 2 3 6 6 e h t e s i w r e h t o , n o i s s i m s n a r t a t a d d e t p u r r e t n i n u t e g o t . e m a s e h t e r a s e d o c e l d i e h t d n a l l i f e m i t l e n n a h c e h t . r e f f u b e h t n i e t y b t s a l e h t g n i w o l l o f 1 0 : e d o m l e n n a h c a t a d c l d h: e d o m l e n n a h c a t a d c l d h : e d o m l e n n a h c a t a d c l d h : e d o m l e n n a h c a t a d c l d h: e d o m l e n n a h c a t a d c l d h d e t n e i r o - e g a s s e m d p a l n a r o l e n n a h c c l d h n a s i l e n n a h c e h t e t a l u c l a c o t d e s u s i l a i m o n y l o p t t i c c - c r c t i b - 6 1 , s e t y b l a r g e t n i n i s i d l e i f n o i t a m r o f n i . l e n n a h c . s t n e m e r i u q e r c l d h d n a c l d s s e i f s i t a s e c n e u q e s t r o b a d n a , s c f 0 1 : e d o m l e n n a h c g n i l a n g i s c l d h - n o n: e d o m l e n n a h c g n i l a n g i s c l d h - n o n : e d o m l e n n a h c g n i l a n g i s c l d h - n o n : e d o m l e n n a h c g n i l a n g i s c l d h - n o n: e d o m l e n n a h c g n i l a n g i s c l d h - n o n 2 3 6 6 . a t a d g n i l a n g i s d e t n e i r o - t i b s e i r r a c l e n n a h c e h t . u p c e h t y b l e n n a h c g n i l a n g i s e h t o t d e t a c o l l a e r a s r e f f u b a t a d d e k n i l 2 n a h t e r o m o n t a h t s e m u s s a . r e f f u b g n i t a l u c r i c e r a e b o t d e m u s s a s i ) r e f f u b y l n o e h t s i t i f i n e v e ( r e f f u b a t a d t s a l e h t 1 1d e v r e s e r mode byte (channel mode) the mode byte is set up by the cpu to specify channel modes of hdlc, non-hdlc signaling, non-hdlc data, loop, non- loop, inversion or non-inversion. the details are shown in table 8.
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 29 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| n o i t p on o i t p o n o i t p o n o i t p on o i t p o r e b m u n a t a da t a d a t a d a t a da t a d e t a r t i bt i b t i b t i bt i b s k r a m e rs k r a m e r s k r a m e r s k r a m e rs k r a m e r 7 7 7 7 7 ) b s m () b s m ( ) b s m ( ) b s m () b s m ( 6 6 6 6 65 5 5 5 54 4 4 4 43 3 3 3 32 2 2 2 21 1 1 1 10 0 0 0 0 ) b s l () b s l ( ) b s l ( ) b s l () b s l ( * 0s / b k 0 0 0000000 l l i w l l i f e m i t r o f s 1 t h g i e . t n e s e b l l i w a t a d o n . 1 = n e r e s t f i t n e s e b 1s / b k 8 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 t i b e n o y n a n i 1 a ; d e n i f e d r e s u - y r a r t i b r a . 1 e n o y l n o t u b , n o i t i s o p 2s / b k 6 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 t i b o w t y n a n i 1 a ; n r e t t a p d e n i f e d r e s u . s 1 o w t y l n o t u b , s n o i t i s o p 3s / b k 4 2 0 0 0 1 0 0 0 1 0 0 1 1 1 0 1 0 . r e s u y b d e n i f e d s a e r e h w y n a s 1 e e r h t f o l a t o t a 4s / b k 2 3 0 1 1 0 1 0 0 1 1 0 1 0 1 0 1 1 0 0 1 0 1 1 0 0 . r e s u y b d e n i f e d s a e r e h w y n a s 1 r u o f f o l a t o t a 5s / b k 0 4 0 0011111 . r e s u y b d e n i f e d s a e r e h w y n a s 1 e v i f f o l a t o t a 6s / b k 8 4 0 0111111 . r e s u y b d e n i f e d s a e r e h w y n a s 1 x i s f o l a t o t a 7s / b k 6 5 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 d e t c i r t s e r , e c i v r e s a t a d l a t i g i d n i e t a r d r a d n a t s . s / b k 4 6 f o n o i s r e v . r e s u y b d e n i f e d s a e r e h w y n a s 1 n e v e s f o l a t o t a 8s / b k 4 6 1 1111111 m o r f a t a d g n i h c t e f s i t i n e h w g n i d u l c n i , s / b k 4 6 t a s i t i f i s a s e t a r e p o r e t t i m s n a r t e h t h c i h w n i e d o m e s o p r u p l a i c e p s a * . d e t t i m s n a r t s i a t a d o n h g u o h t n e v e , y r o m e m l a n r e t x e e h t table 9. examples of fill/mask options fill/mask byte (rate definition) the fill/mask byte is used as a masking pattern on the hdlc-formatted (including flag, header, data, crc, and abort code) or non-hdlc-formatted data in order to adapt subrates that are multiples of 8kb/s to the 64kb/s rate. the 8- bit sequence is applied to data on a bit by bit basis to insert 1 (fill/mask bit = 0) for time fill, or insert data bit (fill/ mask = 1). see an example in figure 6 in section ?transmit bit-level processor? and table 9. for bit-oriented signaling mode, the fill/mask should be set as 1111 1111. if not, the PT7A6632 will not override any other fill/mask pattern.
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 30 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| ) e ( 7 t i b) e ( 7 t i b ) e ( 7 t i b ) e ( 7 t i b) e ( 7 t i b) a ( 6 t i b) a ( 6 t i b ) a ( 6 t i b ) a ( 6 t i b) a ( 6 t i bn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d 0x s n i a m e r t n e m n g i s s a l e n n a h c r e p y h . d e g n a h c n u 10 4 - 0 s t i b n i r e b m u n l e n n a h c e t e l e d . l e n n a h c r e p y h m o r f 11 o t 4 - 0 s t i b n i r e b m u n l e n n a h c d d a . l e n n a h c r e p y h flexible hyperchannel configuring byte (optional) the byte follows the fill/mask byte if any. it is used to configure flexible hyperchannel. bits 0 - 4 specify number of a channel to be grouped into or removed from a hyperchannel. bits 6 and 7 is for hyperchannel enable and add/delete respec- tively. see table 10 for details. table 10 data length is used to specify flexible hyperchannel. when data length = 0, 1 or 2, only normal channel process. when data length > 2, there is hyperchannel process. flexible hyperchannel the flexible hyperchannel mode allows the PT7A6632 to group any number of 32 64kb/s channels into a hyperchannel. the data length (>2) is read to decide the number of addi- tional channels to be added to a hyperchannel. if a previously activated channel is assigned to a flexible hyperchannel, it will suspend the original buffer process, and the process will be restored once the channel is released from the hyperchannel. it may take one frame time. a channel can be assigned to one hyperchannel only. the channel map may be updated in one cycle of channel counting. in flexible hyperchannel mode, the hcs0 and hcs1 should be set as ?0 0?, otherwise the standard hyperchannel will override the flexible hyperchannel. partial command buffer if the cpu can not make next buffer ready before the PT7A6632 completes data transmission of a channel, the cpu will reset the cf/p bit to indicate that it is a partial command buffer (cf/p=0, cmnd=1). in this case the PT7A6632 will read next buffer address and send a hdlc flag(s) or a non-hdlc octet all-ones to fill the gap, then the PT7A6632 turns to a new buffer chain as if it complete a normal buffer process by setting the mpty and cf/p bits. the PT7A6632 sends out flags or all-ones until it is informed to resume data transmission by the cpu again. one partial command buffer sends one flag or one all-ones byte, a chain of partial command buffer sends multiple flags or ones. the partial command buffer processing will not change the mode and fill/mask. if a partial command buffer is processed after a partial data buffer, the hdlc abort or non-hdlc all-ones will be sent. minimum number of data bytes in a tx buffer for transmit data buffers and transmit command buffers, minimum number of data bytes is required for buffer mainte- nance and buffer transition. the minimum numbers depend on the current buffer type and next buffer type. refer to figure 25. command buffer (10x)* complete data buffer (001)* 3 bytes complete data buffer (001)* partial data buffer (000)* partial data buffer (000)* 6 bytes complete data buffer (001)* 2 bytes partial data buffer (000)* 5 bytes complete data buffer (001)* 2 bytes partial data buffer (000)* 5 bytes current buffer next buffer * status bits: cmnd, mpty, cf/p any buffer (xxx)* command buffer (10x)* 2 bytes figure 25. minimum data bytes for transmit buffer current buffer next buffer current buffer next buffer current buffer next buffer min. data bytes
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 31 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| i i+1 i+2 not used i+3 i+4 not used i+5 i+6 not used by PT7A6632 i+7 over ivba abrt fcer sher cf/p cmnd mpty (i+7)+1 (i+7)+2 (i+7)+j (i+7)+k a. mdfs = 1 ~ ~ ~ ~ (address) next buffer address buffer size (k) msb lsb data length (j) lsb lsb msb status (0) first date b y te second date byte last date byte last location in buffer ~ ~ ~ ~ - descriptor s i i+1 i+2 i+3 not used i+4 i+5 not used i+6 over ivba abrt fcer sher cf/p cmnd mpty i+7 not used by PT7A6632 (i+7)+1 (i+7)+2 (i+7)+j (i+7)+k b. mdfs = 0 ~ ~ ~ ~ (address) 7 (contents) 0 next buffer address buffer size (k) msb lsb data length (j) lsb lsb msb status (0) first date b y te second date byte last date byte last location in buffer ~ ~ ~ ~ - descriptor s data data 7 (contents) 0 msb msb figure 26. receive data buffer receive data buffer the receive data buffer contains 8 bytes of descriptors and j bytes of user?s data as shown in figure 26. the mdfs pin decides the ms byte and ls byte locations (in even and odd addresses). descriptors the first 8 bytes in the receive data buffer are descriptors that specify next buffer address, buffer size, data length and status respectively. see table 11 for the definition. data bytes following the descriptors are received data. the number of data bytes are indicated by data length which is written by the PT7A6632 after it receives the last byte of an hdlc frame or the hdlc abort code, upon the loss of multiframe align- ment error from a non-hdlc signaling channel, or when re- ceiver bit-level processor detects receive synchronization error caused by rsyn, elastic buffer error or rred. when it is a partial data buffer, the number of data bytes is indicated by the buffer size.
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 32 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| e m a ne m a n e m a n e m a ne m a nn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d r e f f u b t x e nr e f f u b t x e n r e f f u b t x e n r e f f u b t x e nr e f f u b t x e n s s e r d d a s s e c c a o t 2 3 6 6 r o f r e f f u b t x e n o t g n i t n i o p , d r o w s s e r d d a t i b - 6 1 e z i s r e f f u be z i s r e f f u b e z i s r e f f u b e z i s r e f f u be z i s r e f f u b s d a e r 2 3 6 6 e h t . r e f f u b t n e r r u c r o f u p c e h t y b d e t a c o l l a s n o i t a c o l y r o m e m f o r e b m u n e t y b s e i f i c e p s , t i b - 2 1 . r e f f u b e h t o t n i a t a d s e t i r w n e h w e z i s r e f f u b e h t h t g n e l a t a dh t g n e l a t a d h t g n e l a t a d h t g n e l a t a dh t g n e l a t a d e t y b t s a l e h t s e v i e c e r t i r e t f a 2 3 6 6 e h t y b n e t t i r w , 2 3 6 6 y b d e v i e c e r s e t y b a t a d f o r e b m u n l a u t c a e h t , t i b - 2 1 a m o r f r o r r e t n e m n g i l a e m a r f i t l u m f o s s o l e h t n o p u r o , e d o c t r o b a c l d h e h t r o e m a r f c l d h n a f o d e h c a e r s i r e f f u b d e t a c o l l a e h t f o d n e e h t f i n e t t i r w t o n s i h t g n e l a t a d . l e n n a h c g n i l a n g i s c l d h - n o n e h t , e s a c a h c u s n i . ) e z i s r e f f u b n a h t r e t a e r g s i h t g n e l e m a r f a t a d f i , . e . i ( d e v i e c e r s i e t y b t s a l e h t e r o f e b t u p n i n t t a e h t f i n e t t i r w e b t o n y a m h t g n e l a t a d , o s l a . e z i s r e f f u b n e v i g e h t o t l a u q e s i h t g n e l a t a d l a u t c a . l e n n a h c e v i t c a n a f o n o i t a v i t c a e r r o n o i t a v i t c a e d e h t n i g n i t l u s e r , d e t r e s s a s i . e z i s r e f f u b d e m m a r g o r p e h t d e e c x e t o n l l i w h t g n e l a t a d y t p my t p m y t p m y t p my t p m y t p m ey t p m e y t p m e y t p m ey t p m e d e v i e c e r g n i r o t s r o f y d a e r s i r e f f u b e h t , . e . i , y t p m e s i r e f f u b e h t s n a e m t i , u p c e h t y b t e s f i , t i b - 1 : t i b s i h t g n i l l o p p e e k l l i w 2 3 6 6 a 7 t p e h t . y t p m e t o n s i r e f f u b e h t n e h w t i b s i h t s t e s e r 2 3 6 6 a 7 t p e h t . a t a d . s u t a t s e h t s e t a d p u t i r e v e n e h w t i b e h t s t e s e r 2 3 6 6 e h t . t e s s i t i l i t n u d n m cd n m c d n m c d n m cd n m c d n a m m o cd n a m m o c d n a m m o c d n a m m o cd n a m m o c t i , u p c e h t y b t e s e r f i . r e f f u b d n a m m o c a s i r e f f u b e h t s n a e m t i , u p c e h t y b t e s n e h w , t i b - 1 : . r e f f u b a t a d a s i p / f cp / f c p / f c p / f cp / f c : r e f f u b a t a d l a i t r a p / e m a r f e t e l p m o c: r e f f u b a t a d l a i t r a p / e m a r f e t e l p m o c : r e f f u b a t a d l a i t r a p / e m a r f e t e l p m o c : r e f f u b a t a d l a i t r a p / e m a r f e t e l p m o c: r e f f u b a t a d l a i t r a p / e m a r f e t e l p m o c t s a l e h t s n i a t n o c r e f f u b a t a d e h t t a h t w o h s o t 2 3 6 6 e h t y b t e s , t i b - 1 c l d h e h t f i 2 3 6 6 e h t y b t e s e b o s l a l l i w t i . g n o r w s i n o i t a z i n o r h c n y s t a h t r o a t a d d e m a r f c l d h n a f o e t y b . x a m t r o c n y s r , d e r r , t r o b a f o n o i t i d n o c o r h c n y s - e r y b d e t r o b a s i g n i v i e c e r a t a d c l d h - n o n r o a t a d e r o m e r o t s l l i w 2 3 6 6 d n a r e f f u b s i h t n i t o n s i e m a r f c l d h n a f o e t y b t s a l e h t n e h w t i b s i h t s t e s e r 2 3 6 6 e h t . e d o m g n i l a n g i s r o e d o m c l d h - n o n r o f t e s e r e b s y a w l a l l i w t i b s i h t . r e f f u b g n i d e e c c u s e h t o t a t a d t r b at r b a t r b a t r b at r b a r e c f r e h s : r o r r e e m a r f c l d h t r o h s , r o r r e k c e h c e m a r f , t r o b a: r o r r e e m a r f c l d h t r o h s , r o r r e k c e h c e m a r f , t r o b a : r o r r e e m a r f c l d h t r o h s , r o r r e k c e h c e m a r f , t r o b a : r o r r e e m a r f c l d h t r o h s , r o r r e k c e h c e m a r f , t r o b a: r o r r e e m a r f c l d h t r o h s , r o r r e k c e h c e m a r f , t r o b a l a m r o n b a t r o p e r o t d e s u e r a s t i b 3 e s e h t . 2 3 6 6 y b d e t c e t e d s n o i t i d n o c = r e h s r e c f t r b a, d e t c e t e d s r o r r e o n : 0 0 0 , r o r r e e m a r f c l d h r e g e t n i - n o n r o t r o h s : 1 0 0 , r o r r e c r c : 0 1 0 , r o r r e r e g e t n i - n o n & r o r r e c r c : 1 1 0 , d e v i e c e r e d o c t r o b a c l d h : 0 0 1 , t s o l t n e m n g i l a e m a r f i t l u m c l d h - n o n : 1 0 1 , r o r r e c n y s r & r o r r e r e f f u b c i t s a l e : 0 1 1 . m r a l a d e r r : 1 1 1 a b v ia b v i a b v i a b v ia b v i s s e r d d a r e f f u b d i l a v n is s e r d d a r e f f u b d i l a v n i s s e r d d a r e f f u b d i l a v n i s s e r d d a r e f f u b d i l a v n is s e r d d a r e f f u b d i l a v n i s a h c u s , s s e r d d a r e f f u b t x e n d i l a v n i n a s d n i f t i f i t i b e h t s t e s 2 3 6 6 e h t , t i b - 1 : e v i e c e r t o n d n a e t a t s e l d i n i e b l l i w l e n n a h c x r e h t , e s a c s i h t n i . x f f f f o m r o f n i r o s o r e z 6 1 f o s s e r d d a . u p c e h t y b d e t a v i t c a - e r s i l e n n a h c e h t l i t n u a t a d e r o m r e v or e v o r e v o r e v or e v o n u r r e v on u r r e v o n u r r e v o n u r r e v on u r r e v o a t a d d e v i e c e r r o f e l b a l i a v a t o n s i r e f f u b a t a d y t p m e t x e n e h t n e h w t i b s i h t s t e s 2 3 6 6 e h t , t i b - 1 : e l b a l i a v a t o n s i r e f f u b a t a d y t p m e t x e n e h t n e h w r o , g n i v i e c e r a t a d c l d h n i d e t e l p m o c s i e m a r f a e r o f e b . g n i v i e c e r a t a d c l d h - n o n r o f g n i l a n g i s d e v i e c e r r e i l r a e f o e c a l p n i n e t t i r w e b l l i w a t a d w e n . l e n n a h c g n i l a n g i s r o f d e t r o p e r n u r r e v o o n . a t a d table 11. descriptors in receive data buffer
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 33 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| receive command buffer the receive command buffer contains 8 bytes of descriptors and 2 bytes of channel mode & rate definition data (and maybe hyperchannel configuring bytes) as shown in figure 27. the mdfs pin decides the ms byte and ls byte locations (in even and odd addresses). figure 27. receive command buffer i i+1 i+2 not used i+3 not used i+4 not used i+5 i+6 not used i+7 x ivba not used cmnd mpty (i+7)+1 0 0 0 0 inv loop sig hdlc (i+7)+2 (i+7)+3 e a x channel number (i+7)+j e a x channel number a. mdfs = 1 ~ ~ (address) next buffer address data length (j) lsb lsb msb status (1) mode fill/mask ~ ~ descriptor s 7 (contents) 0 i i+1 i+2 not used i+3 not used i+4 i+5 not used i+6 x ivba not used cmnd mpty i+7 not used (i+7)+1 0 0 0 0 inv loop sig hdlc (i+7)+2 (i+7)+3 e a x channel number (i+7)+j e a x channel number b. mdfs = 0 ~ ~ (address) next buffer address data length (j) lsb lsb msb status (1) mode fill/mask ~ ~ descriptor s 7 (contents) 0 hyperchannel configuring hyperchannel configuring msb msb
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 34 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| table 12. descriptors in receive command buffer e m a ne m a n e m a n e m a ne m a nn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d r e f f u b t x e nr e f f u b t x e n r e f f u b t x e n r e f f u b t x e nr e f f u b t x e n s s e r d d a s s e c c a o t 2 3 6 6 r o f r e f f u b t x e n o t g n i t n i o p d r o w s s e r d d a t i b - 6 1 h t g n e l a t a dh t g n e l a t a d h t g n e l a t a d h t g n e l a t a dh t g n e l a t a d . s s e c o r p l e n n a h c r e p y h e l b i x e l f r o s s e c o r p l e n n a h c r e p y h - e l b i x e l f - n o n e h t s e d i c e d , t i b - 8 , s s e c o r p l e n n a h c l a m r o n y l n o , 2 r o 1 , 0 = h t g n e l a t a d . s s e c o r p l e n n a h c r e p y h s i e r e h t , 2 > h t g n e l a t a d d e d d a e b o t s l e n n a h c l a n o i t i d d a y n a m w o h e d i c e d o t d a e r s i h t g n e l a t a d e h t , e d o m l e n n a h c r e p y h e l b i x e l f n i o t d a e r e r a s r e b m u n l e n n a h c l a n o i t i d d a e h t n i a t n o c s e t y b e h t d n a , l e n n a h c r e p y h e h t m o r f e v o m e r / o t . s l e n n a h c g n i d n o p s e r r o c e h t e v o m e r / d d a y t p my t p m y t p m y t p my t p m , t i b - 1 : y t p m e, t i b - 1 : y t p m e , t i b - 1 : y t p m e , t i b - 1 : y t p m e, t i b - 1 : y t p m e e s a c s i h t n i . y d a e r t o n s i a t a d d n a m m o c , . e . i , y t p m e s i r e f f u b e h t t a h t w o h s o t t i s t e s u p c e h t . y d a e r s i a t a d d n a m m o c e h t n e h w t i b s i h t s t e s e r u p c e h t . t e s e r s i t i l i t n u t i b s i h t g n i l l o p p e e k l l i w 2 3 6 6 e h t . r e f f u b e h t n i g n i s s e c o r p d n a m m o c s e t e l p m o c t i t a h t u p c e h t m r o f n i o t t i b e h t s t e s 2 3 6 6 d n m cd n m c d n m c d n m cd n m cd n a m m o cd n a m m o c d n a m m o c d n a m m o cd n a m m o c. r e f f u b d n a m m o c a s i r e f f u b e h t e t a c i d n i o t u p c e h t y b t e s , t i b - 1 : a b v ia b v i a b v i a b v ia b v i s s e r d d a r e f f u b d i l a v n is s e r d d a r e f f u b d i l a v n i s s e r d d a r e f f u b d i l a v n i s s e r d d a r e f f u b d i l a v n is s e r d d a r e f f u b d i l a v n i s a h c u s , s s e r d d a r e f f u b t x e n d i l a v n i n a s d n i f t i f i t i b e h t s t e s 2 3 6 6 e h t , t i b - 1 : l e n n a h c e h t l i t n u d e t a v i t c a e d e b l l i w l e n n a h c x r e h t , e s a c s i h t n i . x f f f f o m r o f n i r o s o r e z 6 1 f o s s e r d d a . u p c e h t y b d e t a v i t c a - e r s i descriptors the first 8 bytes in the receive command buffer is descriptors that specifies next buffer address, data length and status respectively. see table 12 for the definition.
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 35 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| table 13. mode byte in receive command buffer e d o me d o m e d o m e d o me d o me m a ne m a n e m a n e m a ne m a nn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e d 4 - 7 s t i bd e s u t o n 3 t i b v n iv n i v n i v n iv n i 1n o i t r e v n i 0n o i t r e v n i - n o n 2 t i b p o o lp o o l p o o l p o o lp o o l 1l e n n a h c p o o l 0l e n n a h c p o o l - n o n 0 t i b , 1 t i b , g i s, g i s , g i s , g i s, g i s c l d h 0 0 e d o m l e n n a h c a t a d c l d h - n o ne d o m l e n n a h c a t a d c l d h - n o n e d o m l e n n a h c a t a d c l d h - n o n e d o m l e n n a h c a t a d c l d h - n o ne d o m l e n n a h c a t a d c l d h - n o n e h t k c e h c 2 3 6 6 e h t . n o i t a c i l p p a i m d f o 1 d n a 0 s e d o m n i d e s u : d e l l i f e h t s e t a d p u 2 3 6 6 e h t . r e f f u b e h t o t a t a d d e v i e c e r s e t i r w d n a r e f f u b d e t a c o l l a e h t f o y t i l i b a l i a v a g n i t i r w d n a g n i v i e c e r a t a d e h t . r e f f u b a t a d t x e n e h t o t s e v o m n e h t , r t n i s t r e s s a d n a s u t a t s r e f f u b . e l b a l i a v a r e f f u b e r o m o n r o l a n g i s n t t a n a y b d e t p u r r e t n i s i t i l i t n u e u n i t n o c l l i w 1 0 : e d o m l e n n a h c a t a d c l d h: e d o m l e n n a h c a t a d c l d h : e d o m l e n n a h c a t a d c l d h : e d o m l e n n a h c a t a d c l d h: e d o m l e n n a h c a t a d c l d h d e t n e i r o - e g a s s e m d p a l n a r o l e n n a h c c l d h n a s i l e n n a h c e h t e t a l u c l a c o t d e s u s i l a i m o n y l o p t t i c c - c r c t i b - 6 1 - - a t a d c l d h e h t s t a m r o f e d 2 3 6 6 e h t . l e n n a h c r e d a e h e h t r o f g n i s s e c o r p l a i c e p s o n , d e z i n g o c e r e r a s o r e z d e t r e s n i d n a s g a l f , t r o b a d n a , s c f . ) s d l e i f l o r t n o c d n a s s e r d d a ( 0 1 : e d o m l e n n a h c g n i l a n g i s c l d h - n o n: e d o m l e n n a h c g n i l a n g i s c l d h - n o n : e d o m l e n n a h c g n i l a n g i s c l d h - n o n : e d o m l e n n a h c g n i l a n g i s c l d h - n o n: e d o m l e n n a h c g n i l a n g i s c l d h - n o n d e t n e i r o - t i b e h t e v i e c e r o t n o i t a c i l p p a 2 3 7 . g r o i m d n i d e s u y a w e h t n i s r e f f u b a t a d o t n i d e r o t s e r a a t a d d e v i e c e r e h t . t a m r o f c l d h t u o h t i w a t a d g n i l a n g i s . d n u o f s i r o r r e y n a f i s t r o p e r d n a t n e m n g i l a e m a r f i t l u m e h t s t c e t e d 2 3 6 6 e h t . 4 1 e l b a t n i n w o h s 1 1d e v r e s e r mode byte (channel mode) the channel mode byte is set up by the cpu to specify channel modes of hdlc, non-hdlc signaling, non-hdlc data, loop, non-loop, inversion or non-inversion. the details are shown in table 13.
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 36 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| ) s s e r d d a (7 ) s t n e t n o c (0 i j r o i = s s e r d d a r e f f u b t x e n 1 + i 2 + i s r o t p i r c s e d g n i n i a m e r 7 + i 1 + ) 7 + i (x1xxx1 b1 a3 1 a 2 + ) 7 + i (x1xxx2 b2 a4 1 a 3 + ) 7 + i (x1xxx3 b3 a5 1 a 1 1 + ) 7 + i (x1xxx1 1 b1 1 a3 2 a 2 1 + ) 7 + i (x1xxx2 1 b2 1 a1 a 3 1 + ) 7 + i (x1xxx3 1 b3 1 a1 a 4 1 + ) 7 + i (x1xxx4 1 b4 1 a2 a 5 1 + ) 7 + i (x1xxx5 1 b5 1 a3 a 6 1 + ) 7 + i (x1xxx6 1 b6 1 a4 a 7 1 + ) 7 + i (x1xxx7 1 b7 1 a5 a 3 2 + ) 7 + i (x1xxx3 2 b3 2 a1 1 a 4 2 + ) 7 + i (10s y0111 2 1 a table 14. receive buffer data arrangement for non-hdlc bit-oriented signaling channel ) s s e r d d a (7 ) s t n e t n o c (0 i j r o i = s s e r d d a r e f f u b t x e n 1 + i 2 + i s r o t p i r c s e d g n i n i a m e r 7 + i 1 + ) 7 + i (7 1 d7 1 c7 1 b7 1 a1 d1 c1 b1 a 2 + ) 7 + i (8 1 d8 1 c8 1 b8 1 a2 d2 c2 b2 a 3 + ) 7 + i (9 1 d9 1 c9 1 b9 1 a3 d3 c3 b3 a 1 1 + ) 7 + i (7 2 d7 2 c7 2 b7 2 a1 1 d1 1 c1 1 b1 1 a 2 1 + ) 7 + i (8 2 d8 2 c8 2 b8 2 a2 1 d2 1 c2 1 b2 1 a 3 1 + ) 7 + i (9 2 d9 2 c9 2 b9 2 a3 1 d3 1 c3 1 b3 1 a 4 1 + ) 7 + i (0 3 c0 3 c0 3 b0 3 a4 1 d4 1 c4 1 b4 1 a 5 1 + ) 7 + i (1 3 d1 3 c1 3 b1 3 a5 1 d5 1 c5 1 b5 1 a 6 1 + ) 7 + i (11ys10000 a. t1 mode b. cept pcm-30 mode
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 37 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| fill/mask byte (rate definition) the PT7A6632 fill/mask byte is used as a masking pattern on the hdlc-formatted (including flag, header, data, crc, and abort code) or non-hdlc-formatted data in order to adapt subrates that are multiples of 8kb/s to the 64kb/s rate. the 8-bit sequence is applied to data on a bit by bit basis to remove time-fill (fill/mask bit = 0) bits. see an example in figure 13 in section ?receive bit-level processor? and table 9. for bit-oriented signaling mode, the fill/mask should be set as 1111 1111, otherwise the PT7A6632 will not override any other fill/mask pattern. flexible hyperchannel configuring byte (optional) the byte follows the fill/mask byte if any. it is used to configure flexible hyperchannel. bits 0 - 4 specify number of a channel to be grouped into or removed from a hyperchannel. bits 6 and 7 is for hyperchannel enable and add/delete respec- tively. see table 10 for details. r e f f u b a t a d e v i e c e rr e f f u b a t a d e v i e c e r r e f f u b a t a d e v i e c e r r e f f u b a t a d e v i e c e rr e f f u b a t a d e v i e c e r d n a m m o c e v i e c e rd n a m m o c e v i e c e r d n a m m o c e v i e c e r d n a m m o c e v i e c e rd n a m m o c e v i e c e r r e f f u b . n i m. n i m . n i m . n i m. n i m r e f f u b e z i s ) s r o t p i r c s e d ( s e t y b 8 ) a t a d ( s e t y b 6 + ) s r o t p i r c s e d ( s e t y b 8 ) d n a m m o c ( s e t y b 2 + data length is used to specify flexible hyperchannel. when data length = 0, 1 or 2, only non-hyperchannel process. when data length > 2, there is hyperchannel process, while the data length indicates how many additional channels to be added to the hyperchannel. see section ?flexible hyperchannel? in transmit command buffer. minimum buffer size the size of receive data buffer must ensure normal buffer main- tenance and buffer transition without losing data. table 15
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 38 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| device operation device initialization the device is initialized by reset signal. upon reset, all the channels are set in the following states: - the operation mode is hdlc, inversion, non-loop, - fill/mask byte: 0000 0000, - all channels are inactive, - flexible hyperchannels are disabled, - no data transferred from the external memory or written to the external memory. the PT7A6632 monitors the tmax, rsync and rred sig- nals and correspondingly reset the transmit channel counter and the receive channel counter to ascertain the framing syn- chronization. channel initialization the channels are initialized for preparing data transmission and reception by cpu asserting the attn signal. before asserting the attn, the cpu first allocates memory in the external memory for a command buffer containing 8 bytes of descriptors including next buffer starting address, data length, status, and 2 bytes of mode and fill/mask. and a chain of linked data buffers are set up by the cpu following the command buffer, containing next buffer start address, buffer size, data length, status and data bytes. then the cpu set up the activation memory containing channel no. to be activated and channel direction, and channel starting ad- dress (pointers) in the external memory. then the cpu sends out the attn signal. the PT7A6632 receives the attn, starting to access the acti- vation memory (asserting sysacc) for the channel number and the channel start address, which will be stored internally in the PT7A6632. PT7A6632 asserts the atack after comple- tion the access, cpu negates the attn in response to the atack, and PT7A6632 negates the atack in response to negation of attn. the channel initialization is completed. the process is illustrated in figure 28. this process can be repeated for each channel to be initial- ized. the PT7A6632 must make three activation memory ac- cesses to complete the channel attn processing. the worst case of time delay from attn assertion to atack assertion is three t1/cept pcm-30 channel periods. the earliest is 1.5 channel period. cpu PT7A6632 channel activation byte for channel #m channel #m start address atack ! " # $ % ! cpu prepares data buffer and writes to activation byte for a channel. " cpu asserts attn. % PT7A6632 responds to attn, reads channel number, rx/tx, active/inactive in channel activation byte. $ PT7A6632 find out the corresponding channel start address and read the start address of the first buffer allocated for the channel. # PT7A6632 informs task completion by asserting atack. external memory attn figure 28. channel initialization
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 39 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| data transmission and reception operation in transmission, the PT7A6632 reads the first command buffer according to the channel start address, judges status of buffer, fetches the mode and fill/mask information for the chan- nel, then it reads the next buffer start address in the current buffer. it goes to the next buffer to get data length/buffer size, and data bytes to send the data out in according to mode specified and update the status if necessary. the PT7A6632 figure 29. typical linked buffer transmit sequence tx ch31 tx ch0 tx ch1 next bf addr. command modes fill/mask next bf addr. data length mpty=0 cf/p=1 next bf addr. buffer size mpty=0 cf/p=0 next bf addr. data length mpty=0 cf/p=1 next bf addr. data length mpty=0 cf/p=1 next bf addr. buffer size mpty=0 cf/p=0 command buffer data buffer #1 data buffer #2 data buffer #3 data buffer #4 data buffer #5 1: attn goes high. 2: PT7A6632 reads activation byte (xx00). 3: PT7A6632 reads the first buffer s starting address (command or data), then sets atack, & starts processing that buffer. 4: PT7A6632 resets atack after attn goes low. 5: PT7A6632 continues processing command or data buffers as controlled by the status of each. xx00 xx80 xx81 xx82 xx83 xxbe xxbf activation memory data processing memory processes channel by channel in this way. see figure 29 for example. in receiving, the PT7A6632 reads the command buffer of a channel to locates the cpu-allocated buffers for received data storage, and stores the processed data into the data buffer and write the data length. it updates the status of the completed buffer if necessary. see figure 30 for example.
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 40 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| figure 30. typical linked buffer receive activity rx ch31 rx ch0 rx ch1 next bf addr. command modes fill/mask next bf addr. size length mpty=1 next bf addr. size length mpty=1 command buffer data buffer #1 data buffer #2 1: attn goes high. 2: PT7A6632 accesses activation memory (xx00). 3: PT7A6632 reads the first buffer s starting address (command or data), then sets atack, & starts processing that buffer. 4: PT7A6632 resets atack after attn goes low. 5: PT7A6632 continues processing command or data buffers as controlled by the status of each. xx00 xxc0 xxc1 xxc2 xxc3 xxfe xxff activation memory data processing memory
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 41 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| channel period for memory access the PT7A6632 accesses the external memory for buffer man- agement and data processing. normally, the t1/cept pcm-30 data flow requires that a byte of data should be supplied for transmission and a byte of data be taken from the receiving source within a single channel period. so the PT7A6632 divides a channel period into 2 halves, the first half is tx memory access period and the sec- ond is rx memory access period, 4 tclk periods for each. in the first half of channel period, the PT7A6632 reads command information, descriptors information and transmission data from the external memory for tx channels, and in second half of channel period, it reads command information, descriptors information from external memory and write the received data to the memory for rx channels. typically, the PT7A6632 fetches a data byte from the memory during tx channel period m for transmission of the data byte over channel m in the next appropriate tx channel m, and the PT7A6632 takes a data byte from the receiving circuit of chan- nel j and will store the data into the external memory in the next appropriate rx channel period j. then the PT7A6632 moves to process the next tx channel (m+1) and rx channel (j+1). see figure 31. in each tx or rx memory access period, the PT7A6632 can 8 tclk periods one channel period for memory access rx memory access tx memory access access external memory for data byte for once, or twice if the descriptor reading is necessary, even more, three times if an attn signal asserted by the cpu. at the start of each half-channel period, the PT7A6632 first outputs the channel number ch0 - ch4, and the channel di- rection rx/tx of the current channel. after around half tclk period, the PT7A6632 asserts dmnd to inform the external memory that it will access it after 1 tclk period from the rising edge of dmnd. then the PT7A6632 asserts the as strobe, whose falling edge will make the address valid on the address bus. the PT7A6632 sends out read or write strobe to read data from the memory or write data into the memory during low of the read or write. after finish memory access (1, 2 or 3 times access as applicable) and sets the dmnd low to inform end of memory access of this half-channel period. dur- ing the process, if the attn is asserted and the PT7A6632 accesses the activation memory, it will assert sysacc and negate it after activation memory access completed. address setup time, address hold time, data setup time and data hold time are specified such that a wide variety of off-the- shelf ram devices may be used. the read output from the PT7A6632 may be used as an output enable (oe) input to the ram devices. since the PT7A6632 uses its sysclk input to generate various strobes for memory access, the access time requirements are automatically scaled depending on the t1/ cept pcm-30 application. one channel period for memory access for tx for rx for tx for rx channel no. m j m+1 j+1 channel period served figure 31. channel period
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 42 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| memory address memory address extension the output of ch0 - ch4 and rx/tx of the PT7A6632 can be used as upper address bits to extend the 16-bit addresses to 22- bit addresses. see an example in figure 32. or these six bits can be mapped by an external lookup table to another set of n bits (where n is specified by the cpu). since the channel num- ber and rx/tx are output by the PT7A6632 well in advance of the 16-bit address, address translation time is not a concern. external memory PT7A6632 16 1 5 a15-a0 ch0 - ch4 rx/tx a15-a0 a20-a16 a21 figure 32. address extension activat byte not used tx ch31 rx ch31 rx ch0 rx ch1 (addresses xx80, xx81 and xxb2 through xxbf are not used in t1 modes.) (addresses xxc0, xxc1 and xxf2 through xxff are not used in t1 mode.) xx00 xx80 xx81 xx82 xx83 xxbe xxbf xxc0 xxc1 xxc2 xxc3 xxfe xxff activation memory tx ch0 tx ch1 upper address lines xx (a8-a15): when uaen = 0, xx = 00. when uaen = 1, a8 a15 output of PT7A6632 is set in high impedance, xx are decided by the cpu. activation memory address the activation memory has 256 byte locations as shown in figure 33. the addresses can be decided by the cpu by setting uaen and sysacc output of the PT7A6632. when uaen = 0, the address output lines a8-a15 of the PT7A6632 is set low, so the address of the activation memory is in 00xx(h). when uaen = 1, PT7A6632 sets its outputs of a8-a15 in high im- pedance and the cpu can drive the addresses a8-a15. figure 33. activation memory address
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 43 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| memory address restrictions activation memory address -- the PT7A6632 judges the channel start address for its invalidity immediately after it reads the activation memory for the address in response to the attn assertion. if the 16-bit address is found invalid, the channel will be deactivated. the channel start address is thought in- valid by the PT7A6632 when it is all zero or in form of fffx. data/command buffer address -- the PT7A6632 checks next buffer address in each buffer. if found a next buffer address is invalid, the PT7A6632 will set the channel inactive and set the ivba bit of the current buffer. the channel can be reacti- vated only when cpu asserts the attn signal. the 16-bit next buffer address is thought invalid by the PT7A6632 if it is all zero or in form of fffx, namely, the address is valid when it is within 0001 to ffef. the PT7A6632 locates a descriptor byte or a data byte by adding offset to a next buffer address read from last buffer. the maximum address in a buffer is the address of the last byte. as for 16-bit address lines, the addresses are restricted in the range of 2 16 - 1 (65,535), the last byte address in a buffer should meet the following condition: 1/2 tclk period intr channel no. and status are valid on the bus 6632 updates status last byte address in a buffer = buffer start address + 7 (decimal) of descriptor bytes + 12-bit data length or buffer size <= 65,535. if the last byte address exceeds the restriction, the PT7A6632 will access memory locations not intended for the channel. all the external memory addresses should be within one 64k byte bank. interrupt indication at the rising edge of intr, channel no. and status contents can be shifted into the external fifo. the intr is asserted by the PT7A6632 when PT7A6632 updates the status of a buffer. after update, the PT7A6632 negates the intr and at its rising edge the channel no. and status are guaranteed to be valid on the bus so that external fifo can take the information, and the actual address of the status byte is also be placed on the bus. the PT7A6632 removes the interruption channel no. and buffer status without waiting for acknowledge from the cpu. see figure 34. the cpu can take the actual status byte address and it can relocate the completed buffers within the 64k byte bank and also cross-check against its own list of linked buffer addresses. if all the buffer start addresses are divisible exactly by 8, they can be derived from the status byte addresses by setting the three lsb addresses to zero. figure 34. interrupt indication
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 44 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| sysclk dmnd as a0-a15 write intr* d0-d7 rx/tx ch0-ch4 * activated by status write only. figure 35. PT7A6632 external memory example interface waveforms - single write memory access sysclk dmnd as a0-a15 write intr* d0-d7 rx/tx ch0-ch4 * activated by status write only. figure 36. PT7A6632 external memory example interface waveforms - double write memory access
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 45 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| sysclk dmnd as a0-a15 read d0-d7 rx/tx ch0-ch4 figure 37. PT7A6632 external memory example interface waveforms - single read memory access sysclk dmnd as a0-a15 read write d0-d7 intr* rx/tx ch0-ch4 * activated by status write only. figure 38. PT7A6632 external memory example interface waveforms - read write double memory access
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 46 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| sysclk dmnd as a0-a15 read write d0-d7 intr* rx/tx ch0-ch4 figure 39. PT7A6632 external memory example interface waveforms - write read double memory access sysclk dmnd as a0-a15 read d0-d7 rx/tx ch0-ch4 sysacc figure 40. PT7A6632 external memory example interface waveforms - single activation read memory access
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 47 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| sysclk dmnd as a0-a15 write intr* d0-d7 rx/tx ch0-ch4 read sysacc * activated by status write only. figure 41. PT7A6632 external memory example interface waveforms - single write memory access plus a single activation read access sysclk dmnd as a0-a15 write intr* d0-d7 rx/tx ch0-ch4 read sysacc * activated by status write only. figure 42. PT7A6632 external memory example interface waveforms - single write memory access plus a double activation read access
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 48 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| sysclk dmnd as a0-a15 read write d0-d7 intr* rx/tx ch0-ch4 sysacc * activated by status write only. figure 43. PT7A6632 external memory example interface waveforms - write/read double memory access plus a single activation read access detailed specifications absolute maximum ratings recommended operating conditions table 16. recommended operating conditions m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e ds n o i t i d n o c t s e ts n o i t i d n o c t s e t s n o i t i d n o c t s e t s n o i t i d n o c t s e ts n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u v c c e g a t l o v y l p p u s d e d n e m m o c e r r e v o s n o i t i d n o c g n i t a r e p o 5 . 40 . 55 . 5v t a e r u t a r e p m e t g n i t a r e p o0 4 -5 25 8 o c storage temperature ...................................................... -65 o c to +150 o c ambient temperature with power applied ...................... -40 o c to +85 o c supply voltage to ground potential (inputs & v cc only) ...... -0.3 to 7.0v supply voltage to ground potential (outputs & d/o only) .. -0.3 to 7.0v dc input voltage .................................................................. -0.3 to 7.0v dc output current ...................................................................... 120ma power dissipation .............................................................................. 2w note: operation at levels greater than those listed under ?absolute maximum ratings? may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operation condition tables is not implied. expo- sure to absolute maximum rating conditions for extended periods may affect reliability. note: typical figures are at 25 o c and are for design aid only; not production tested.
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 49 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| dc electrical, power supply and capacitance characteristics table 17. dc electrical, power supply and capacitance characteristics note: typical figures are at 25 o c and are for design aid only; not production tested. * i ol and i oh are obsolute values. m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e ds n o i t i d n o c t s e ts n o i t i d n o c t s e t s n o i t i d n o c t s e t s n o i t i d n o c t s e ts n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u i c c t n e r r u c y l p p u s v c c s e c r u o s k c o l c l l a , v 5 = o t d e t c e n n o c e r a s n i p g n i d n o p s e r r o c 42 1a m v h i e g a t l o v h g i h t u p n in i g r a m e s i o n v m 0 0 54 . 2v v l i e g a t l o v w o l t u p n in i g r a m e s i o n v m 0 0 58 . 0v v l o e g a t l o v w o l t u p t u oi l o * a m 0 1 =5 . 01v v h o ) s o m c ( e g a t l o v h g i h t u p t u oi h o * a m 0 1 =5 . 35 . 4v i l o t n e r r u c w o l t u p t u ov l o v 5 . 0 =42 1a m i h o t n e r r u c h g i h t u p t u ov h o v 5 . 4 =40 1a m c n i e c n a t i c a p a c n i p t u p n i 0 1f p c t u o e c n a t i c a p a c n i p t u p t u o 0 1f p
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 50 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| ac characteristics (note: all output ac timing measurements are referenced to the 0.4v for low level and 2.4v for high level, and all input ac timing measurements are referenced to the 0.8v for low level and 2.0v for high level.) serial interface transmit frame synchronization timing table 18. transmit frame synchronization timing m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e ds n o i t i d n o c t s e ts n o i t i d n o c t s e t s n o i t i d n o c t s e t s n o i t i d n o c t s e ts n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u t s m e m i t p u t e s x a m t0 5s n t h m e m i t d l o h x a m t0 5s n bit 8, ch24 f bit bit 1, ch1 t ms t mh tclk tmax (from t1/e1 controller) tser (from PT7A6632) tclk tmax (from t1/e1 controller) tser (from PT7A6632) a. transmit serial output - t1 mode, tseren=1 bit 8, ch24 bit 1, ch1 b. transmit serial output - t1 mode, tseren=0 tcl k tmax (from t1/e1 controller) tser (from PT7A6632) c. transmit serial output - cept pcm-30 mode, tseren=0 or 1 bit 7, ts31 bit 8, ts31 bit 1, ts0 bit 2, ts0 t ms t mh t ms t mh f bit figure 44. diagram of transmit frame synchronization timing (sis = 1)
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 51 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e ds n o i t i d n o c t s e ts n o i t i d n o c t s e t s n o i t i d n o c t s e t s n o i t i d n o c t s e ts n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u t d c t y a l e d k l c t00 5s n t w p c s h t d i w e s l u p k l c s y s0 1 12 2 1s n t w p c t h t d i w e s l u p k l c t0 0 24 4 2s n t p c s d o i r e p k l c s y s0 4 24 4 20 0 0 1s n t r t / f ) k l c s y s ( e m i t l l a f / e m i t e s i r 5s n ? clock timing table 19. clock timing figure 45. clock timing t scp t scpw t scpw t tcpw t r t f t tcd t tcd sysclk tclk
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 52 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e ds n o i t i d n o c t s e ts n o i t i d n o c t s e t s n o i t i d n o c t s e t s n o i t i d n o c t s e ts n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u t w p c r h t d i w e s l u p k l c r0 0 24 4 2s n t d c r t e c n e r e f f i d k l c r , k l c t *s n t r t / f ) k l c t , k l c r ( e m i t l l a f / e m i t e s i r 0 1s n f o n o i t a r u d y n a r e v o s e c n e r e f f i d c i d o i r e p k l c t d n a k l c r f o n o i t a m m u s e h t . k l c t d n u o r a d e r e t n e c e b o t s i k l c r * . s d o i r e p k l c t 4 1 d e e c x e r e v e n t s u m e m i t tclk - rclk timing table 20. tclk - rclk timing figure 46. tclk - rclk timing t rcpw t r t f t rcpw tclk rclk t r t f t trcd
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 53 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| PT7A6632 receive frame synchronization timing table 29. receive frame synchronization timing m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e ds n o i t i d n o c t s e ts n o i t i d n o c t s e t s n o i t i d n o c t s e t s n o i t i d n o c t s e ts n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u t s r e m i t p u t e s c n y s r0 5s n t h r e m i t d l o h c n y s r0 5s n f bit bit 1, ch1 t rs t rh rclk rsync (from t1/e1 controller) rser (from PT7A6632) rclk rsync (from t1/e1 controller) rser (from PT7A6632) a. receive serial output - t1 mode bit 1, ts0 bit 2, ts0 b. receive serial output - cept pcm-30 mode t rs t rh figure 47. diagram of receive frame synchronization timing (sis=1)
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 54 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e ds n o i t i d n o c t s e ts n o i t i d n o c t s e t s n o i t i d n o c t s e t s n o i t i d n o c t s e ts n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u t d s a y a l e d e b o r t s s s e r d d a0 15 7s n t d a y a l e d s s e r d d a0 18 7s n t f a y a l e d t a o l f s s e r d d a0 15 7s n t d r y a l e d e l b a n e d a e r0 18 7s n t a d r e m i t s s e c c a a t a d d a e r *s n t h d r e m i t d l o h a t a d d a e r0* *s n t = y r o m e m d e r a h s r o f e m i t s s e c c a a t a d d a e r * p c s . s n 5 2 1 - t = t a o l f s u b a t a d o t e v i r d a t a d * * w p c s . s n 5 6 - external memory interface read cycle timing table 22. read cycle timing sysclk as address read d0-d7 t asd t af t ad t af t rd t rd t rda t rdh 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v figure 48. read cycle timing
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 55 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e ds n o i t i d n o c t s e ts n o i t i d n o c t s e t s n o i t i d n o c t s e t s n o i t i d n o c t s e ts n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u t d s a y a l e d e b o r t s s s e r d d a0 18 7s n t d a y a l e d s s e r d d a0 10 0 1s n t f a y a l e d t a o l f s s e r d d a0 10 9s n t d w y a l e d e t i r w0 15 7s n t p w h t d i w e s l u p e t i r w0 87 1 1s n t d i y a l e d t p u r r e t n i0 1s n t d d w y a l e d a t a d e t i r w0 10 2 1s n t h d w * e m i t d l o h a t a d e t i r w0 10 9s n e m i t t a o l f s u b a t a d o t e v i r d a t a d * write cycle timing table 23. write cycle timing sysclk as address write intr d0-d7 t asd t asd t ad t af t wd t wd t id t wdh 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v t id t wp t wdd figure 49. write cycle timing
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 56 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| m y sm y s m y s m y sm y sn o i t p i r c s e dn o i t p i r c s e d n o i t p i r c s e d n o i t p i r c s e dn o i t p i r c s e ds n o i t i d n o c t s e ts n o i t i d n o c t s e t s n o i t i d n o c t s e t s n o i t i d n o c t s e ts n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u t s n t a e m i t e s n o p s e r k c a t a o t n t t a0 28 4s k l c s y s t h n t a e m i t d l o h n t t a0s n t r k t a y a l e d t e s e r k c a t a24s k l c s y s channel activation/deactivation table 24. channel activation/deactivation timing figure 50. channel activation/deactivationtiming t atns t atnh t atkr t atnh syscl k attn atack
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 57 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| input characteristics table 25. input characteristics e m a n l a n g i se m a n l a n g i s e m a n l a n g i s e m a n l a n g i se m a n l a n g i sl a n g i s e c n e r e f e rl a n g i s e c n e r e f e r l a n g i s e c n e r e f e r l a n g i s e c n e r e f e rl a n g i s e c n e r e f e re g d e e v i t c e f f ee g d e e v i t c e f f e e g d e e v i t c e f f e e g d e e v i t c e f f ee g d e e v i t c e f f e) . n i m ( p u t e s) . n i m ( p u t e s ) . n i m ( p u t e s ) . n i m ( p u t e s) . n i m ( p u t e s) . n i m ( d l o h) . n i m ( d l o h ) . n i m ( d l o h ) . n i m ( d l o h) . n i m ( d l o hs t i n us t i n u s t i n u s t i n us t i n u n t t ak l c s y sg n i s i r0 50 5s n t e s e rk l c tg n i s i r0 60 6s n 7 d - 0 dk l c s y sg n i s i r0 50s n ) 1 = s i s ( x a m tk l c tg n i l l a f0 50 5s n ) 0 = s i s ( x a m tk l c tg n i s i r0 50 5s n ) 1 = s i s ( r e s rk l c rg n i l l a f0 50 5s n ) 0 = s i s ( r e s rk l c rg n i s i r0 50 5s n ) 1 = s i s ( d e r rk l c rg n i l l a f0 50 5s n ) 0 = s i s ( d e r rk l c rg n i s i r0 50 5s n ) 1 = s i s ( c n y s rk l c rg n i l l a f0 50 5s n ) 0 = s i s ( c n y s rk l c rg n i s i r0 50 5s n
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 58 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| output characteristics table 26. output characteristics e m a n l a n g i se m a n l a n g i s e m a n l a n g i s e m a n l a n g i se m a n l a n g i sl a n g i s e c n e r e f e rl a n g i s e c n e r e f e r l a n g i s e c n e r e f e r l a n g i s e c n e r e f e rl a n g i s e c n e r e f e re g d e e v i t c e f f ee g d e e v i t c e f f e e g d e e v i t c e f f e e g d e e v i t c e f f ee g d e e v i t c e f f e) . x a m ( y a l e d) . x a m ( y a l e d ) . x a m ( y a l e d ) . x a m ( y a l e d) . x a m ( y a l e d) . n i m ( d l o h) . n i m ( d l o h ) . n i m ( d l o h ) . n i m ( d l o h) . n i m ( d l o hs t i n us t i n u s t i n u s t i n us t i n u d n m dk l c s y sg n i s i r0 90 1s n s ak l c s y sg n i l l a f / g n i s i r8 70 1s n 5 1 a - 0 ak l c s y sg n i s i r0 0 10 1s n c c a s y sk l c s y sg n i s i r0 70 1s n d a e rk l c s y sg n i s i r8 70 1s n e t i r wk l c s y sg n i l l a f / g n i s i r0 2 10 1s n 7 d - 0 dk l c s y sg n i l l a f0 2 10 1s n r t n ik l c s y sg n i l l a f0 2 10 1s n 4 h c - 0 h ck l c s y sg n i s i r0 70 1s n x t / x rk l c s y sg n i s i r0 70 1s n k c a t ak l c s y sg n i s i r5 70 1s n r e s tk l c tg n i l l a f5 60 1s n
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 59 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| mechanical specifications figure 51. 68-pin plcc
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 60 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||| ordering information table 27. ordering information r e b m u n t r a pr e b m u n t r a p r e b m u n t r a p r e b m u n t r a pr e b m u n t r a pe g a k c a pe g a k c a p e g a k c a p e g a k c a pe g a k c a p j 2 3 6 6 a 7 t pc c l p n i p - 8 6
data sheet PT7A6632 32-channel hdlc controller pt019(05/02) ver:2 61 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| pericom technology inc. email: support@pti.com.cn web-site: www.pti.com.cn, www.pti-ic.com china : no. 20 building, 3/f, 481 guiping road, shanghai, 200233, china tel: (86)-21-6485 0576 fax: (86)-21-6485 2181 asia pacific : unit 1517, 15/f, chevalier commercial centre, 8 wang hoi rd, kowloon bay, hongkong tel: (852)-2243 3660 fax: (852)- 2243 3667 u.s.a. : 2380 bering drive, san jose, california 95131, usa tel: (1)-408-435 0800 fax: (1)-408-435 1100 pericom technology incorporation reserves the right to make changes to its products or specifications at any time, without noti ce, in order to improve design or performance and to supply the best possible product. pericom technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in pericom technology product. the company makes no representations that circuitry described herein is free from patent infringement or other rights, of pericom technology incorporation. notes

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