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ibm13m16734jcb 16m x 72 one-bank registered / buffered sdram module 06k7739.h03380 4/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 1 of 22 features ? 168-pin registered 8-byte dual in-line memory module ? 16mx72 synchronous dram dimm ? performance: ? intended for 133mhz applications ? inputs and outputs are lvttl (3.3v) compatible ? single 3.3v 0.3v power supply ? single pulsed ras interface ? sdrams have four internal banks ? module has one physical bank ? fully synchronous to positive clock edge ? programmable operation: - dimm cas latency:4 (registered mode) - burst type: sequential or interleave - burst length: 1, 2, 4, 8, full-page - operation: burst read and write or multiple burst read with single write ? data mask for byte read/write control ? auto refresh (cbr) and self refresh ? automatic and controlled precharge commands ? suspend mode and power down mode ? 12/10/2 addressing (row/column/bank) ? 4096 refresh cycles distributed across 64ms ? card size: 5.25" x 1.5" x 0.157" ? gold contacts ? sdram s in tsop - type ii package ? serial presence detect with write protect feature description ibm13m16734jcb is a registered 168-pin synchro- nous dram dual in-line memory module (dimm) organized as a 16mx72 high-speed memory array. the dimm uses nine 16mx8 sdrams in 400 mil tsop packages. the dimm achieves high-speed data-transfer rates of 133mhz by employing a prefetch/pipeline hybrid architecture that synchro- nizes the output data to a system clock. the dimm is intended for use in applications oper- ating at 133mhz memory bus speed. all control and address signals are re-driven through registers/buff- ers to the sdram devices. operating in registered mode (rege pin tied high), the control/address input signals are latched in the register on one rising clock edge and sent to the sdram devices on the following rising clock edge (data access is delayed by one clock). a phase-lock loop (pll) on the dimm is used to re- drive the clock signals to the sdram devices to minimize system clock loading. (ck0 is connected to the pll, and ck1, ck2, and ck3 are terminated on the dimm.) a single clock enable (cke0) con- trols all devices on the dimm, enabling the use of sdram power-down modes. prior to any access operation, the device cas latency and burst type/length/operation type must be programmed into the dimm by address inputs a0-a9, i/o addresses ba0 and ba1 using the mode register set cycle. the dimm cas latency, when operated in registered mode, is one clock later than the device cas latency due to the address and con- trol signals being clocked to the sdram devices. the dimm uses serial presence detects imple- mented via a serial eeprom using the two-pin iic protocol. the first 128 bytes of serial pd data are programmed and locked by the dimm manufac- turer. the last 128 bytes are available to the cus- tomer and may be write protected by providing a high level to pin 81 on the dimm. an on-board pull- down resistor keeps this in the write-enable mode. all ibm 168-pin dimms provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. -75a reg. units dimm cas latency 4 f ck clock frequency 133 mhz t ck clock cycle 7.5 ns t ac clock access time 5.65 ns .
ibm13m16734jcb 16m x 72 one-bank registered / buffered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 2 of 22 06k7739.h03380 4/00 card outline ordering information part number organization clock cycle (cl, t rcd , t rp ) cas latency access time leads dimension power IBM13M16734JCB-75AT 16mx72 7.5ns (333) 3 5.4ns gold 5.25" x 1.5" x 0.157" 3.3v 1 85 10 94 11 95 40 124 41 125 84 168 (front) (back)
ibm13m16734jcb 16m x 72 one-bank registered / buffered sdram module 06k7739.h03380 4/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 3 of 22 pin description ck0 - ck3 clock inputs dq0 - dq63 data input/output cke0 clock enable cb0 - cb7 check bit data input/output ras row address strobe dqmb0 - dqmb7 data mask cas column address strobe v dd power (3.3v) we write enable v ss ground s0, s2 chip selects nc no connect a0 - a9, a11 address inputs scl serial presence detect clock input a10/ap address input/autoprecharge sda serial presence detect data input/output ba0, ba1 sdram bank address inputs sa0-2 serial presence detect address inputs wp spd write protect rege register enable pinout pin# front side pin# back side pin# front side pin# back side pin# front side pin# back side pin# front side pin# back side 1 v ss 85 v ss 22 cb1 106 cb5 43 v ss 127 v ss 64 v ss 148 v ss 2 dq0 86 dq32 23 v ss 107 v ss 44 nc 128 cke0 65 dq21 149 dq53 3 dq1 87 dq33 24 nc 108 nc 45 s2 129 nc 66 dq22 150 dq54 4 dq2 88 dq34 25 nc 109 nc 46 dqmb2 130 dqmb6 67 dq23 151 dq55 5 dq3 89 dq35 26 v dd 110 v dd 47 dqmb3 131 dqmb7 68 v ss 152 v ss 6 v dd 90 v dd 27 we 111 cas 48 nc 132 nc 69 dq24 153 dq56 7 dq4 91 dq36 28 dqmb0 112 dqmb4 49 v dd 133 v dd 70 dq25 154 dq57 8 dq5 92 dq37 29 dqmb1 113 dqmb5 50 nc 134 nc 71 dq26 155 dq58 9 dq6 93 dq38 30 s0 114 nc 51 nc 135 nc 72 dq27 156 dq59 10 dq7 94 dq39 31 nc 115 ras 52 cb2 136 cb6 73 v dd 157 v dd 11 dq8 95 dq40 32 v ss 116 v ss 53 cb3 137 cb7 74 dq28 158 dq60 12 v ss 96 v ss 33 a0 117 a1 54 v ss 138 v ss 75 dq29 159 dq61 13 dq9 97 dq41 34 a2 118 a3 55 dq16 139 dq48 76 dq30 160 dq62 14 dq10 98 dq42 35 a4 119 a5 56 dq17 140 dq49 77 dq31 161 dq63 15 dq11 99 dq43 36 a6 120 a7 57 dq18 141 dq50 78 v ss 162 v ss 16 dq12 100 dq44 37 a8 121 a9 58 dq19 142 dq51 79 ck2 163 ck3 17 dq13 101 dq45 38 a10/ap 122 ba0 59 v dd 143 v dd 80 nc 164 nc 18 v dd 102 v dd 39 ba1 123 a11 60 dq20 144 dq52 81 wp 165 sa0 19 dq14 103 dq46 40 v dd 124 v dd 61 nc 145 nc 82 sda 166 sa1 20 dq15 104 dq47 41 v dd 125 ck1 62 nc nc nc 83 scl 167 sa2 21 cb0 105 cb4 42 ck0 126 nc 63 nc 147 rege 84 v dd 168 v dd note: all pin assignments are consistent with all 8-byte unbuffered versions.
ibm13m16734jcb 16m x 72 one-bank registered / buffered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 4 of 22 06k7739.h03380 4/00 x72 ecc sdram dimm block diagram (1 bank, x8 sdrams) rege pck rdqmb3 rdqmb2 dq0 dq1 dq2 dq3 dqm i/o 0 i/o 1 i/o 2 i/o 3 d0 rdqmb0 dq4 dq5 dq6 dq7 i/o 4 i/o 5 i/o 6 i/o 7 dq8 dq9 dq10 dq11 dqm i/o 0 i/o 1 i/o 2 i/o 3 d1 dq12 dq13 dq14 dq15 i/o 4 i/o 5 i/o 6 i/o 7 dq16 dq17 dq18 dq19 dqm i/o 0 i/o 1 i/o 2 i/o 3 d3 dq20 dq21 dq22 dq23 i/o 4 i/o 5 i/o 6 i/o 7 dq24 dq25 dq26 dq27 dqm i/o 0 i/o 1 i/o 2 i/o 3 d4 dq28 dq29 dq30 dq31 i/o 4 i/o 5 i/o 6 i/o 7 dq40 dq41 dq42 dq43 dqm i/o 0 i/o 1 i/o 2 i/o 3 d6 rdqmb4 dq44 dq45 dq46 dq47 i/o 4 i/o 5 i/o 6 i/o 7 dq48 dq49 dq50 dq51 dqm i/o 0 i/o 1 i/o 2 i/o 3 d7 dq52 dq53 dq54 dq55 i/o 4 i/o 5 i/o 6 i/o 7 dq56 dq57 dq58 dq59 dqm i/o 0 i/o 1 i/o 2 i/o 3 d8 dq60 dq61 dq62 dq63 i/o 4 i/o 5 i/o 6 i/o 7 cb0 cb1 cb2 cb3 dqm i/o 0 i/o 1 i/o 2 i/o 3 d2 cb4 cb5 cb6 cb7 i/o 4 i/o 5 i/o 6 i/o 7 rdqmb1 dq32 dq33 dq34 dq35 dqm i/o 0 i/o 1 i/o 2 i/o 3 d5 dq36 dq37 dq38 dq39 i/o 4 i/o 5 i/o 6 i/o 7 rdqmb5 rdqmb6 rdqmb7 # r s0 cs cs cs cs cs cs cs cs cs r s2 a0 serial presence detect a1 a2 sa0 sa1 sa2 scl sda v dd v ss d0 - d8 d0 - d8 ck0 pll ck1, ck2, ck3 terminated ras: sdrams d0 - d8 cas: sdrams d0 - d8 cke: sdrams d0 - d8 we: sdrams d0 - d8 s0/ s2 dqmb0 to dqmb7 ba0-ba1 a0-a11 ras cas cke0 we r s0/r s2 rdqmb0 - rdqmb7 r ras r cas rcke0 r we r e g i s t e r rba0 - rba1 ra0-ra11 ba0-ba1: sdrams d0-d8 a0-a11: sdrams d0-d8 note: dq wiring may differ from that described in this drawing; however dq/dqmb relationships are maintained as shown. v dd 10k # unless otherwise noted, resistor values are 22 ohms. wp 47k
ibm13m16734jcb 16m x 72 one-bank registered / buffered sdram module 06k7739.h03380 4/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 5 of 22 clock wiring 10 ohm ck0 clock net wiring (ck0): in sdram sdram all pll clock sdram loads are equal-- fdbk (pll out to feedback input) 10 0hms ck1, ck2, and ck3 terminated clock nets (ck1, ck2, ck3): pck out1 in 12pf to out3 out10 12pf phase lock loop achieved in part through equal-length wiring. notes: sdram out4 pck register (1:1) 1. the pll is programmed via a combination of the feedback path and on-dimm loading. pll feedback produces zero phase shift from the delayed ck0 input. 2. card wiring and capacitance loading variation: 100 ps. 3. timing is based on a driver with a 1 volt/ns rise time. 4. feedback capacitor value determined by pll phase characteristics. one of three sdram outputs is shown. register (1:1) 5.1pf
ibm13m16734jcb 16m x 72 one-bank registered / buffered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 6 of 22 06k7739.h03380 4/00 input/output functional description symbol type signal polarity function ck0 - ck3 input pulse positive edge the system clock inputs. all the sdram inputs are sampled on the rising edge of their associ- ated clock. ck0 drives the pll. ck1, ck2, and ck3 are terminated. cke0 input level active high activates the sdram ck signal when high and deactivates the ck signal when low. by deacti- vating the clocks, cke low initiates the power down mode, the suspend mode, or the self refresh mode. s0, s2 input pulse active low enables the associated sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras, cas , we input pulse active low when sampled at the positive rising edge of the clock, cas, ras, and we define the operation to be executed by the sdram. ba0, 1 input level selects which sdram bank of four is activated. a0 - a9, a11, a10/ap input level during a bank activate command cycle, a0-a11 defines the row address (ra0-ra11) when sampled at the rising clock edge. during a read or write command cycle, a0-a9 defines the column address (ca0-ca9) when sampled at the rising clock edge. in addition to the column address, ap is used to invoke auto- precharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0, ba1 defines the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction with ba0, ba1 to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0 or ba1. if ap is low, then ba0 and ba1 are used to define which bank to precharge. dq0 - dq63, cb0 - cb7 input output level data and check bit input/output pins. dqmb0 - dqmb7 input pulse active high the data input/output masks, associated with one data byte, place the dq buffers in a high impedance state when sampled high. in read mode, dqmb has a latency of three clock cycles in registered mode, and controls the output buffers like an output enable. in write mode, dqmb has a latency of one clock cycle in registered mode. in this case, dqmb operates as a byte mask by allowing input data to be written if it is low but blocks the write oper- ation if it is high. v dd , v ss supply power and ground for the module. rege input level active high (regis- ter mode enable) the register enable pin is used to permit the dimm to operate in buffered mode (inputs re- driven asynchronously) or registered mode (signals re-driven to sdrams when clock rises, and held valid until next rising clock). sa0 - 2 input level these signals are tied at the system planar to either v ss or v dd to configure the spd eeprom. sda input output level this is a bidirectional pin used to transfer data into or out of the spd eeprom. a resistor must be connected from the sda bus line to v dd to act as a pullup. scl input pulse this signal is used to clock data into and out of the spd eeprom. a resistor may be connected from the scl bus line to v dd to act as a pullup. wp input level active high this signal is pulled low on the dimm to enable data to be written into the last 128 bytes of the spd eeprom.
ibm13m16734jcb 16m x 72 one-bank registered / buffered sdram module 06k7739.h03380 4/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 7 of 22 serial presence detect (part 1 of 2) byte # description spd entry value serial pd data entry (hexadecimal) notes 0 number of serial pd bytes written during production 128 80 1 total number of bytes in serial pd device 256 08 2 fundamental memory type sdram 04 3 number of row addresses on assembly 12 0c 4 number of column addresses on assembly 10 0a 5 number of dimm banks 1 01 6 - 7 data width of assembly x72 4800 8 assembly voltage interface levels lvttl 01 9 sdram device cycle time (cl = 3) 7.5ns 75 1, 2 10 sdram device access time from clock at cl=3 5.4ns 54 11 assembly error detection/correction scheme ecc 02 12 assembly refresh rate/type sr/1x(15.625 m s) 80 13 sdram device width x8 08 14 error checking sdram device width x8 08 15 sdram device attr: min clk delay, random col access 1 clock 01 16 sdram device attributes: burst lengths supported 1, 2, 4, 8, full page 8f 17 sdram device attributes: number of device banks 4 04 18 sdram device attributes: cas latency 2, 3 06 19 sdram device attributes: cs latency 0 01 20 sdram device attributes: we latency 0 01 21 sdram module attributes registered/buffered with pll if 22 sdram device attributes: general write-1/read burst, precharge all, auto-precharge 0e 23 minimum clock cycle at clx-1 (cl = 2) 15.0ns f0 1, 2 24 maximum data access time (t ac ) from clock at clx-1 (cl = 2) 9.0ns 90 25 minimum clock cycle time at clx-2 (cl = 1) n/a 00 26 maximum data access time (t ac ) from clock at clx-2 (cl = 1) n/a 00 27 minimum row precharge time (t rp ) -260, -360 20.0ns 14 28 minimum row active to row active delay (t rrd ) 15.0ns 0f 29 minimum ras to cas delay (t rcd ) 20.0ns 14 1. in a registered dimm, data is delayed an additional clock cycle due to the on-dimm pipeline register (that is, device cl [clo ck cycles] + 1 = dimm cas latency). 2. minimum application clock cycle time is 7.5ns (133mhz). 3. cc = checksum data byte, 00-ff (hex). 4. r = alphanumeric revision code, a-z, 0-9. 5. rr = ascii coded revision code byte r. 6. ww = binary coded decimal week code, 01-53 (decimal) ? 01-35 (hex). 7. yy = binary coded decimal year code, 00-99 (decimal) ? 00-63 (hex). 8. ss = serial number data byte, 00-ff (hex). 9. these values apply to pc100 applications only.
ibm13m16734jcb 16m x 72 one-bank registered / buffered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 8 of 22 06k7739.h03380 4/00 30 minimum ras pulse width (t ras ) 50.0ns 32 31 module bank density 128mb 20 32 address and command setup time before clock 1.5ns 15 33 address and command hold time after clock 0.8ns 8 34 data input setup time before clock 1.5ns 15 35 data input hold time after clock 0.8ns 8 36 - 61 reserved undefined 00 62 spd revision 02 02 63 checksum for bytes 0 - 62 checksum data cc 3 64 - 71 manufacturers jedec id code ibm a400000000000000 72 assembly manufacturing location toronto, canada 91 vimercate, italy 53 73 - 90 assembly part number ascii 13m16734jc r -75at 31334d31363733344a43 rr2d37354154 4, 5 91 - 92 assembly revision code r plus ascii blank rr20 5 93 - 94 assembly manufacturing date year/week code yyww 6, 7 95 - 98 assembly serial number serial number ssssssss 8 99 - 125 reserved undefined not specified 126 module supports this clock frequency 100mhz 64 9 127 attributes for clock frequency defined in byte 126 clk0, cl=3, conap 85 9 128 - 255 open for customer use undefined 00 serial presence detect (part 2 of 2) byte # description spd entry value serial pd data entry (hexadecimal) notes 1. in a registered dimm, data is delayed an additional clock cycle due to the on-dimm pipeline register (that is, device cl [clo ck cycles] + 1 = dimm cas latency). 2. minimum application clock cycle time is 7.5ns (133mhz). 3. cc = checksum data byte, 00-ff (hex). 4. r = alphanumeric revision code, a-z, 0-9. 5. rr = ascii coded revision code byte r. 6. ww = binary coded decimal week code, 01-53 (decimal) ? 01-35 (hex). 7. yy = binary coded decimal year code, 00-99 (decimal) ? 00-63 (hex). 8. ss = serial number data byte, 00-ff (hex). 9. these values apply to pc100 applications only.
ibm13m16734jcb 16m x 72 one-bank registered / buffered sdram module 06k7739.h03380 4/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 9 of 22 absolute maximum ratings symbol parameter rating units notes v dd power supply voltage -0.3 to +4.6 v1 v in input voltage sdram devices -1.0 to +4.6 serial pd device -0.3 to +6.5 register 0 - v dd pll 0 - v dd v out output voltage sdram devices -1.0 to +4.6 serial pd device -0.3 to +6.5 t a operating temperature (ambient) 0 to +70 c 1 t stg storage temperature -55 to +125 c 1 p d power dissipation 6.55 w 1, 2 i out short circuit output current 50 ma 1 f 0p operating frequency min. 66 mhz max. 133 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect r eli- ability. 2. maximum power is calculated assuming the physical bank is in auto refresh mode. recommended dc operating conditions (t a = 0 to 70?c) symbol parameter rating units notes min. typ. max. v dd supply voltage 3.0 3.3 3.6 v 1 v ih input high voltage 2.0 v dd + 0.3 v1 v il input low voltage -0.3 0.8 v 1 1. all voltages referenced to v ss .
ibm13m16734jcb 16m x 72 one-bank registered / buffered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 10 of 22 06k7739.h03380 4/00 capacitance (t a = 25 c, f=1mhz, v dd = 3.3v 0.3v) symbol parameter organization units x72 max c i1 input capacitance (a0 - a9, a10/ap, a11, ba0, ba1, we, cas, ras, cke0) 11.5 pf c i2 input capacitance ( s0, s2) 9 pf c i3 input capacitance (dqmb0 - dqmb7) 9.5 pf c i4 input capacitance (rege) 10 pf c i5 input capacitance (ck0) 28 pf c i6 input capacitance (ck1 - ck3) 24 pf c i7 input capacitance (sa0 - sa2, scl, wp) 9 pf c io1 input/output capacitance (dq0 - dq63, cb0 - cb7) 16 pf c io2 input/output capacitance (sda) 11 pf
ibm13m16734jcb 16m x 72 one-bank registered / buffered sdram module 06k7739.h03380 4/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 11 of 22 device dc output load circuit input/output characteristics (t a = 0 to +70?c, v dd = 3.3v 0.3v) symbol parameter x72 units notes min. max. i i(l) input leakage current, any input (0.0v v in 3.6v), all other pins not under test = 0v address and control inputs 10 10 m a dq0-63, cb0 - 7 -2 +2 i o(l) output leakage current (d out is disabled, 0.0v v out 3.6v) dq0-63, cb0 - 7 -2 +2 m a sda -1 +1 v oh output level output h level voltage (i out = -2.0ma) 2.4 v dd v1 v ol output level output l level voltage (i out = +2.0ma) 0.0 0.4 1. see dc output load circuit. output 1200 w 50pf 3.3v 870 w v oh (dc) = 2.4v, i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma
ibm13m16734jcb 16m x 72 one-bank registered / buffered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 12 of 22 06k7739.h03380 4/00 operating, standby, and refresh currents (t a = 0 to +70?c, v dd = 3.3v 0.3v) parameter symbol test condition speed -75a units notes operating current 1 bank operation i cc1 t rc = t rc (min), t ck = min active-precharge command cycling without burst operation 875 ma 1 precharge standby current in power down mode i cc2p cke0 v il (max), t ck = min, cs =v ih (min) 119 ma 1 i cc2ps cke0 v il (max), t ck = infinity, s0, s2 =v ih (min) 24 ma precharge standby current in non- power down mode i cc2n cke0 3 v ih (min), t ck = min, s0, s2 =v ih (min) 516 ma 1 i cc2ns cke0 3 v ih (min), t ck = infinity, s0, s2 =v ih (min) 105 ma no operating current (active state: 4bank) i cc3n cke0 3 v ih (min), t ck = min, s0, s2 =v ih (min) 626 ma 1 i cc3p cke0 v il (max), t ck = min, s0, s2 =v ih (min) (power down mode) 201 ma 1 burst operating current (active state: 4bank) i cc4 t ck = min, read command cycling 1190 ma 1, 2 auto (cbr) refresh current i cc5 t ck = min, cbr command cycling 1821 ma 1 self refresh current i cc6 cke0 0.2v 33 ma 1. these parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t ck and t rc . input signals are changed once during t ck (min). t ck (min) = 7.5ns. 2. the specified values are obtained with the dimm data outputs open.
ibm13m16734jcb 16m x 72 one-bank registered / buffered sdram module 06k7739.h03380 4/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 13 of 22 ac characteristics (t a = 0 to +70?c, v dd = 3.3v 0.3v) 1. an initial pause of 200 m s, with cke0 held high, is required after power-up. a precharge all banks com- mand must be given followed by a minimum of eight auto (cbr) refresh cycles before or after the mode register set operation. 2. ac timing tests have v il = 0.8v and v ih = 2.0v with the timing referenced to the 1.40v crossover point. 3. the transition time is measured between v ih and v il (or between v il and v ih ). 4. ac measurements assume t t =1.2ns (1 volt/ns rise). 5. in addition to meeting the transition rate speci?cation, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner 6. a 1 ms stabilization time is required for the integrated pll circuit to obtain phase lock of its feedback sig- nal to its reference signal. 7. all timings are speci?ed at the input receiver of the signal. this allows times to be speci?ed at the end of the transmission line versus at the dimm connector which may display signi?cant re?ections. ac characteristics diagram output input clock t oh t setup t hold t ac t lz 1.4v 0.8v 1.4v 1.4v 2.0v t t t ckh t ckl output 50pf z o = 50 w ac output load circuit
ibm13m16734jcb 16m x 72 one-bank registered / buffered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 14 of 22 06k7739.h03380 4/00 . clock and clock enable parameters symbol parameter -75a max. (device cl t rcd , t rp = 3, 3, 3) units notes min. max. t ck4 clock cycle time, dimm cas latency = 4 7.5 1000 ns 1 t ac4 clock access time, dimm cas latency = 4 5.65 ns 1, 2 t ckh clock high pulse width 2.5 ns 3 t ckl clock low pulse width 2.5 ns 3 t ces clock enable setup time 1.65 ns 1 t ceh clock enable hold time 0.35 ns 1 t sb power down mode entry time 0 7.5 ns t t transition time (rise and fall) 0.5 10 ns 1. dimm cas latency = device cl [clock cycles] + 1 for the register mode. 2. access time is measured at 1.4v. see ac output load circuit. 3. t ckh is the pulse width of clk measured from the positive edge to the negative edge referenced to v ih (min). t ckl is the pulse width of clk measured from the negative edge to the positive edge referenced to v il (max). common parameters symbol parameter -75a units notes min. max. t cs command setup time 1.65 ns 1 t ch command hold time 0.35 ns 1 t as address and bank select setup time 1.65 ns 1 t ah address and bank select hold time 0.35 ns 1 t rcd ras to cas delay 20.0 ns 1 t rc bank cycle time 67.5 ns 1 t ras active command period 50 100000 ns 1 t rp precharge time 20.0 ns 1 t rrd bank to bank delay time 15 ns 1 t ccd cas to cas delay time (same bank) 1 clk 1. these parameters account for the number of clock cycles and depend on the operating frequency of the clock as follows: the num- ber of clock cycles = specified value of timing/clock period (count fractions as a whole number).
ibm13m16734jcb 16m x 72 one-bank registered / buffered sdram module 06k7739.h03380 4/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 15 of 22 mode register set cycle symbol parameter -75a units min. max. t rsc mode register set cycle time 2 clk refresh cycle symbol parameter -75a units notes min. max. t ref refresh period 64 ms 1, 2 t refi average refresh interval time 15.625 m s t refc row refresh cycle time 75 ns t srex self refresh exit time 10 ns 3 1. 4096 cycles. 2. any time that the refresh period has been exceeded, a minimum of two auto (cbr) refresh commands must be given to wake up the device. 3. self refresh exit is asynchronous, requiring 10ns to ensure initiation. self refresh exit is complete in 10ns + t rc . read cycle symbol parameter -75a units notes min. max. t oh data out hold time 2.45 ns t lz data out to low impedance time 0.6 ns t hz3 data out to high impedance time 3.6 6.6 ns 1 t dqz dqm data out disable latency 3 clk 1. referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. write cycle symbol parameter -75a units min. max. t ds data in setup time 1.75 ns t dh data in hold time 1.05 ns t dpl data input to precharge 15 ns t dal3 data in to active delay ( cas latency = 3) 5 clk t dqw dqm write mask latency 1 clk
ibm13m16734jcb 16m x 72 one-bank registered / buffered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 16 of 22 06k7739.h03380 4/00 wiring and topology this section contains the information needed to understand the timing relationships presented in ac charac- teristics. each timing parameter is measured at the first receiving device (sdram dq pin for input data, reg- ister input pin for address and control, and pll clk input pin for clock). this section will enable the user to understand the pin numbers on the dimm, the net structures, and the loading associated with these devices. for detailed timing analysis, contact the ibm marketing representative for simulation models. modeling is strongly recommended to determine delay adders of the entire net structure. presence detect read and write cycle symbol parameter min. max. units notes f scl scl clock frequency 100 khz t i noise suppression time constant at scl, sda inputs 100 ns t aa scl low to sda data out valid 0.3 3.5 m s t buf time the bus must be free before a new transmission can start 4.7 m s t hd:sta start condition hold time 4.0 m s t low clock low period 4.7 m s t high clock high period 4.0 m s t su:sta start condition setup time (for a repeated start condition) 4.7 m s t hd:dat data in hold time 0 m s t su:dat data in setup time 250 ns t r sda and scl rise time 1 m s t f sda and scl fall time 300 ns t su:sto stop condition setup time 4.7 m s t dh data out hold time 300 ns t wr write cycle time 15 ms 1 1. the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address.
ibm13m16734jcb 16m x 72 one-bank registered / buffered sdram module 06k7739.h03380 4/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 17 of 22 pin assignments for the 128mb sdram planar component (top view) 54-pin plastic tsop(ii) 400 mil 1 2 3 4 5 6 9 10 11 12 13 14 7 8 15 16 17 18 19 20 21 22 54 53 52 51 50 49 46 45 44 43 42 41 48 47 40 39 38 37 36 35 34 33 23 24 25 32 31 30 26 27 29 28 v dd dq0 v ddq nc dq1 v ssq v ddq nc dq3 v ssq nc v dd nc dq2 nc we cas ras cs a13/bs0 a12/bs1 a10/ap a0 a1 a2 a3 v dd v ss dq7 v ssq nc dq6 v ddq v ssq nc dq4 v ddq nc v ss nc dq5 nc dqm clk cke nc a11 a9 a8 a7 a6 a5 a4 v ss 4mbit x 8 i/o x 4 bank
ibm13m16734jcb 16m x 72 one-bank registered / buffered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 18 of 22 06k7739.h03380 4/00 the table below describes the dq wiring information for each sdram on the dimm. note that the dq wiring is different from that described in the block diagram on page 4; the dqs are scrambled within the same device for wiring optimization. the table below describes the input wiring for each clock on the dimm. data wiring cross reference dq sdram designator dq sdram pin num- ber device position to dimm tab data i/o 1 d0 d1 d2 d3 d4 d5 d6 d7 d8 dq0 2 7 15 cb1 23 31 32 40 48 56 dq1 5 6 14 cb5 22 30 33 41 49 57 dq2 8 5 13 cb0 21 29 34 42 50 58 dq3 11 4 12 cb4 20 28 35 43 51 59 dq4 44 3 11 cb7 19 27 36 44 52 60 dq5 47 2 10 cb3 18 26 37 45 53 61 dq6 50 1 9 cb6 17 25 38 46 54 62 dq7 53 0 8 cb2 16 24 39 47 55 63 1. these numbers can be associated with the corresponding dimm tab pin by referencing the dimm connector pinout on page 3 of this specification. example: dq14 at the dimm tab (pin 19) is wired to sdram device position d1, pin 5. data topology clock input wiring ck0 ck1 ck2 ck3 pll clk input pin 24 termination rc termination rc termination rc clock topology tl0 tl1 total unit min max min max min max 0.134 0.312 0.787 1.018 0.838 1.285 in. sdram note: transmission lines (tl) are represented as cylinders and labeled with length designators. these are the only lines which represent physical trace segments. for more detailed topology information please refer to the cur- rent pc133 sdram registered dimm specification. 22 w 5% dimm connector tl1 tl0 ck0 10 w ck1, ck2, and ck3 12pf tl0 tl1 unit 0.127 2.647 in. 10 w dimm connector tl1 tl0 12pf phase lock loop (pll)
ibm13m16734jcb 16m x 72 one-bank registered / buffered sdram module 06k7739.h03380 4/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 19 of 22 the table below describes the address and control information for each signal on the dimm. note that several signals are double loaded at the input of the register. functional description and timing diagrams refer to the ibm 128mb synchronous dram data sheet (document 33l8019.) for the functional description and timing diagrams for buffered-mode operation. refer to the ibm application notes serial presence detect on memory dimms and sdram presence detect definitions for the serial presence detect functional description and timings. register input wiring register pin number register 1 signal register 2 signal 30 clk clk 31 we ba0 33 cas a10 34 dqmb0 a11 36 dqmb4 ba1 37 dqmb1 nc 38 dqmb5 cke0 40 s0 s2 41 ras dqmb6 42 a0 dqmb2 43 a1 dqmb7 44 a2 dqmb3 45 a3 nc 47 a4 nc 48 a5 nc 49 a6 nc 51 a7 nc 52 a9 nc 54 a8 nc address/control signal topology note: each signal has two register input loads with the exception of dqmbs and chip selects ( s0 and s2) which have one. for more detailed topology information please refer to the current pc133 sdram registered dimm specification. register input register input tl0 unit min max 0.293 0.686 in. dimm connector tl0
ibm13m16734jcb 16m x 72 one-bank registered / buffered sdram module ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 20 of 22 06k7739.h03380 4/00 layout drawing 3.99 .157 max. side 1.27 0.10 .050 .004 4.24 .167 4.24 .167 (front) (back) r 1.00 .0393 note: all dimensions are typical unless otherwise stated. 2.0 .078 3.0 .118 detail a scale: 4/1 millimeters inches 6.35 .250 1.27 pitch .050 1.00 width .039 see detail a 1.50 38.1 (2) 0 3.18 .1255 131.35 5.171 .118 3.0 (2x) 4.00 .157 .700 17.80 front 127.35 5.014 133.35 5.25 42.18 1.661 66.68 2.63 d0 d1 d3 d4 register 1 register 2 pll d5 d6 d7 d8 d2 back
ibm13m16734jcb 16m x 72 one-bank registered / buffered sdram module 06k7739.h03380 4/00 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 21 of 22 revision log rev contents of modi?cation 4/00 initial release
copyright and disclaimer copyright international business machines corporation 1999, 2000 all rights reserved printed in the united states of america april 2000 the following are trademarks of international business machines corporation in the united states, or other coun- tries, or both. ibm ibm logo other company, product and service names may be trademarks or service marks of others. all information contained in this document is subject to change without notice. the products described in this docu- ment are not intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. the information contained in this document does not affect or change ibm product specifications or warranties. nothing in this document shall operate as an express or implied license or indemnity under the intellec- tual property rights of ibm or third parties. all information contained in this document was obtained in specific environ- ments, and is presented as an illustration. the results obtained in other operating environments may vary. the information contained in this document is provided on an "as is" basis. in no event will ibm be liable for damages arising directly or indirectly from any use of the information contained in this document. ibm microelectronics division 1580 route 52, bldg. 504 hopewell junction, ny 12533-6351 the ibm home page can be found at http://www.ibm.com the ibm microelectronics division home page can be found at http://www.chips.ibm.com 06k7739.h03380 4/00 a

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