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features single chip synthesised tuner solution for quadrature down conversion, l-band to zero if. dvb compliant, operating dynamic range -70 to -20dbm. compatible with dss and dvb variable symbol rate applications. selectable baseband path, programmable through i 2 c bus. excellent quadrature balance up to 30mhz baseband excellent immunity to spurious second harmonic (rf and lo) mixing effects. low oscillator phase noise and reradiation. high output referred linearity for low distortion and multi channel application. integral fast mode compliant i 2 c bus controlled pll frequency synthesiser, designed for high comparison frequencies and low phase noise performance. buffered crystal output for clocking qpsk demodulator. esd protection (normal esd handling procedures should be observed). applications satellite receiver systems. data communications systems. figure 1. pin connections 36 1 18 19 xtalcap xtal sda scl bufref vccd vcc rf rfb vcc ifia ifib vcc ofia ofib vee iout add pump drive port p0 vee tanks tanksb vee tankv tankvb vee ifqa ifqb vcc ofqa ofqb vee qout agccont description the sl1935 is a complete single chip bus controlled zero if tuner and operates from 950 to 2150mhz. it includes an on-board low phase noise pll frequency synthesiser and low noise lna/agc. the sl1935 is intended primarily for application in digital satellite network interface modules and performs the complete tuner function. the device contains all elements necessary, with the exception of local oscillator tuning network and crystal reference, to produce a high performance i(n-phase) & q(uadrature) downconversion tuner function. due to the high signal handling design the device does not require any front end tracking filters. the sl1935 includes selectable baseband signal paths, allowing application with two externally definable filter bandwidths, facilitating application in variable symbol rate and simulcast systems. the sl1935 is optimised to interface with the vp310 (adc/qpsk/fec) satellite channel decoder, available from zar link semiconductor and offers a full front end solution. i 2 c sl1935 single chip synthesized zero if tuner april 2004 ordering information sl1935d/kg/np1p (tubes) 36 pin ssop sl1935d/kg/np1q (tape and reel) 36 pin ssop 1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003 - 2004, zarlink semiconductor inc. all rights reserved.
2 sl1935 figure 2. block diagram frequency agile phase splitter ag c sender divide by 2 15 bit programmab le divider i 2 c bus interface charge pump reference divider vcc 7,10,13,24 vccd vee 16,21,27,30,33 agccont rf 8 rfb 9 6 tanks 32 tanksb 31 tankv 29 tankvb 28 sda 3 scl 4 add 18 xtal 2 xtalcap 1 5 bufref 34 por t p0 35 drive 36 pump 15 ofib 14 ofia 12 ifib 11 ifia 17 iout 20 qout 26 ifqa 25 ifqb 23 ofqa 22 ofqb fpd/2 fcomp fpd ref osc vcov vcos vs bs rf section pll section pll section bs rf section 90deg 0deg 19
3 sl1935 table 1. quick reference data functional description general the sl1935 is a complete wideband direct conversion tuner incorporating an on board frequency synthesiser and lna/agc, optimised for application in digital satellite receiver systems. the device offers a highly integrated solution to a satellite tuner function, incorporating an i 2 c bus interface controller, a low phase noise pll frequency synthesiser and all tuner analogue functionality. the analogue blocks include the reference oscillator, consisting of two independent oscillators, a phase splitter, rf preamplifier with agc facility, channel mixers and baseband amplifiers incorporating two selectable baseband paths, allowing for two externally definable bandwidths. in this application two varactor tuned tanks, a reference crystal and baseband filtering components are required to complete the tuner system. a buffered crystal frequency output is available to clock the qpsk demodulator and powers up in the active state. the i 2 c bus interface controls the frequency synthesiser, the local oscillator, the baseband path selection, the buffered reference frequency output and an external switching port. figure 2 shows the device block diagram and pin allocations are shown in figure 1. quadrature downconverter section in normal application the tuner if frequency of typically 950 to 2150mhz is fed direct to the sl1935 rf input through an appropriate impedance match (fig.16) and lnb switching. the input stage is optimised for both nf and signal handling. the signal handling of the front end is designed to offer immunity to input composite overload without the requirement of a tracking filter. rf input impedance is shown in fig.3. the rf input amplifier feeds an agc stage and provides system gain control. the system agc gain range will guarantee an operating dynamic range of -70 to -20dbm. the agc is controlled by the agc sender and is optimised for s/n and s/i performance across the full dynamic range. details of the agc characteristics, variations in iip3, iip2, p1db and nf are illustrated in figs.4, 5, 6, 7, and 8 respectively. the required i and q local oscillator frequencies for quadrature downconversion are generated by the on- board reference oscillators designated ? vcos ? and ? vcov ? . vcos operates nominally from 1900 to 3000mhz and is then divided by two to provide 950 to 1500mhz. vcov operates nominally from 1400 to 2200mhz. only the oscillator selected via bit vs in the i 2 c data transmission is powered. characteristic v alue units operating range input dynamic range vswr with input match input nf @ -70dbm operating sensitivity @ -60dbm operating sensitivity ipip3 @ -20dbm operating sensitivity ipip2@ -20dbm operating sensitivity ipp1db@ -20dbm operating sensitivity baseband output limit voltage gain match up to 22mhz phase match up to 22mhz gain flatness up to 30mhz local oscillator phase noise ssb at 10khz offset in band lo reradiation from rf input lo second harmonic interference level at input level of -20dbm per carrier lna second harmonic interference level at input level of -25dbm per carrier pll maximum comparison frequency pll phase noise at phase detector 950 to 2150 -75 to -15 10 10 15 +5 +20 -5 2.0 0.2 0.7 1 -80 <-70 -55 -35 4 -152 mhz dbm db db db dbm dbm dbm v db deg db dbc/hz dbm dbc dbc mhz dbc/hz note: 6db interstage filter loss assumed in external base band paths. dbm assumes 75 ? ` `
4 sl1935 quadrature downconverter section - continued the oscillators share a common varactor line drive and both require an external varactor tuned resonator optimised for low phase noise performance. the recommended application circuit for the local oscillators is detailed in fig.9 and the typical phase noise performance is detailed in fig.10. the local oscillator frequency is coupled internally to the pll frequency synthesiser programmable divider input. the mixer outputs are coupled to the baseband buffer amplifiers, providing for one of two selectable baseband outputs in each channel. the required output is selected by bit bs in the i 2 c bus transmission (table 6). these outputs are fed off chip via ports ? opia ? and ? opib ? ( ? opqa ? and ? opqb ? ), then back on chip through ports ? ipia ? and ? ipib ? ( ? ipqa ? and ? ipqb ? ), allowing for the insertion of two independent user definable filter bandwidths. each output provides a low impedance drive (fig.11) and each input provides a high impedance load . an example filter for 30ms/s is detailed in fig.13. both path gains are nominally equal. nb 6db insertion loss is assumed in each channel, however a different pot down ratio may be applied. each baseband path is then multiplexed to the final baseband amplifier stage, providing further gain and a low impedance output drive. the nominal output load test condition is detailed in fig.14. pll frequency synthesiser section the pll frequency synthesiser section contains all the elements necessary, with the exception of a reference frequency source and a loop filter to control the selected oscillator to produce a complete pll frequency synthesised source. the device, produced using high speed logic, allows for operation with a high comparison frequency and enables the generation of a loop with excellent phase noise performance. the lo signal from the selected oscillator drives from the phase splitter into an internal preamplifier, providing gain and reverse isolation from the divider signals. the output of the preamplifier interfaces directly with the 15-bit fully programmable divider. the programmable divider has mn+a architecture, the dual modulus prescaler is 16/17, the a counter is 4-bits and the m counter is 11-bits. the output of the programmable divider is fed to the phase comparator and compared in both phase and frequency domains to the comparison frequency. this frequency is derived from either the on board crystal controlled oscillator or from an external reference source. in both cases the reference frequency is divided down to the comparison frequency by the reference divider, programmable into 1 of 29 ratios and detailed in table 3. the typical application for the crystal oscillator is shown in fig.15. the output of the phase detector feeds a charge pump and a loop amplifier. when used with an external loop filter and a high voltage transistor it integrates the current pulses into the varactor line voltage used to control the selected oscillator. the programmable divider output fpd divided by two and the reference divider output fcomp are switched to port p0 by programming the device into test mode. test modes are detailed in table 4. the crystal reference frequency can be switched to the bufref output by bit re as detailed in table 7. programming the sl1935 is controlled by an i 2 c data bus and is compatible with both standard and fast mode formats. data and clock are fed on the sda and scl lines respectively as defined by the i 2 c bus format. the device can either accept data (write mode) or send data (read mode). the lsb of the address byte (r/w) sets the device into write mode if it is low and read mode if it is high. tables 9a and 9b detail the format of the data. the sl1935 may be programmed to respond to several addresses and enables the use of more than one device in an i 2 c bus system. table 9c details the how the address is selected by applying a voltage to the ? add ? input. when the device receives a valid address byte, it pulls the sda line low during the acknowledge period and during following acknowledge periods after further data bytes are received. when the device is programmed into read mode, the controller accepting the data must pull the sda line low during all status byte acknowledge periods to read another status byte. if the controller fails to pull the sda line low during this period, the device generates an internal ? stop ? condition which inhibits further reading. write mode bytes 2 and 3 contain frequency information bits 2 14 to 2 0 inclusive (table 9). byte 4 controls the synthesiser reference divider ratio (table 3) and the charge pump setting (table 5). byte 5 controls test modes (table 4), baseband filter path select bs (table 6), local oscillator select vs (table 8), buffered crystal reference output select re (table 7) and the output port p0. after reception and acknowledgment of a correct address (byte 1), the first bit of the following byte determines whether the byte is interpreted as byte 2 or 4, a logic ? 0 ? indicates byte 2 and a logic ? 1 ? indicates byte 4. having interpreted this byte as either byte 2 or 4, the following byte will be interpreted as byte 3 or 5 respectively. after receiving two complete data bytes, additional data bytes may be entered and byte interpretation follows the same procedure without re- addressing the device. the procedure continues until a ? stop ? condition is received.
5 sl1935 the stop condition can be generated after any data byte, if however it occurs during a byte transmission, the previous byte data is retained. to facilitate smooth fine tuning, the frequency data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the generation of a stop condition. read mode when the device is in read mode, the status byte read from the device takes the form shown in table 9b. synthesiser programmable divider reference programmable divider baseband filter path select local oscillator select charge pump current test mode general purpose port, p0 buffered crystal reference output, bufref programmable features function as described above function as described above. function as described above. function as described above. the charge pump current can be programmed by bits c1 & c0 (table 5). the test modes are defined by bits t2 - t0 as described in table 4. the general purpose port can be programmed by bit p0; logic ? 1 ? = on logic ? 0 ? = off (high impedance) the buffered crystal reference frequency can be switched to the bufref output by bit re as described in table 7. the bufref output defaults to the ? on ? condition at device power up. bit 1 (por) is the power-on reset indicator, and this is set to a logic ? 1 ? if the vccd supply to the device has dropped below 3v (at 25 o c), e.g. when the device is initially turned on. the por is reset to ? 0 ? when the read sequence is terminated by a stop command. when por is set high this indicates that the programmed information may have been corrupted and the device reset to the power up condition. bit 2 (fl) indicates whether the synthesiser is phase locked, a logic ? 1 ? is present if the device is locked, and a logic ? 0 ? if the device is unlocked. the typical key performance data at vcc = 5v and +25 o c ambient are detailed in table 1. function table 2. programmable features r4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 r3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 r2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 r1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 r0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ratio 2 4 8 16 32 64 128 256 illegal state 5 10 20 40 80 160 320 illegal state 6 12 24 48 96 192 384 illegal state 7 14 28 56 112 224 448 table 3. reference division ratios
6 sl1935 table 5. charge pump current table 6. baseband path select table 4. test modes note: * clocks need to be present on crystal and rf inputs to enable charge pump test modes and to toggle status byte bit fl. table 7. buffered crystal reference output select table 8. local oscillator select t2 0 0 0 0 1 1 1 1 t1 0 0 1 1 0 0 1 1 t0 0 1 0 1 0 1 0 1 test mode description normal operation charge pump sink* (status byte fl set to logic '0') charge pump source* (status byte fl set to logic '0') charge pump disabled* (status byte fl set to logic '1') normal operation and port p0 = fpd/2 charge pump sink* (status byte fl set to logic '0'. port p0 = fcomp) charge pump source* (status byte fl set to logic '0'. port p0 = fcomp) charge pump disabled* (status byte fl set to logic '1'. port p0 = fcomp) 0 0 1 1 0 1 0 1 min +-116 +-247 +-517 +-1087 current in
7 sl1935 table 9a. write data format (msb is transmitted first) table 9b. read data format (msb is transmitted first) table 9c. address selection key to tables 9a to 9c a ......................................... acknowledge bit ma1, ma0 ........................... variable address bits (table 9c) 2 14 to 2 0 ................................ programmable division ratio control bits c1 to c0 .............................. charge pump current select (table 5) r4 to r0 .............................. reference division ratio select (table 3) t2 to t0 .............................. test modes control bits (table 4) bs ....................................... baseband path select (table 6) vs ....................................... local oscillator select (table 8) re ....................................... buffered crystal reference output enable (table 7) p0 ....................................... p0 port output state por .................................... power on reset indicator fl ........................................ phase lock flag note: * programmed by connecting a 30k ? ? ? ?
8 sl1935 0 10 20 30 40 50 60 70 80 90 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 70db minimum, agc < 0.75v 20db maximum, agc > 4.25v agccont voltage (v) system gain (db) assuming 6db interstage filter loss 60 70 80 90 100 110 120 20 25 30 35 40 45 50 55 60 65 70 system gain (db) assuming 6db interstage filter loss system input referred ip3 (dbuv) 100 110 120 130 140 150 160 170 20 25 30 35 40 45 50 55 60 65 70 baseband dominated ip2 lna dominated ip2 system gain (db) assuming 6db interstage filter loss system input referred ip2 (dbuv) figure 4. agc characteristic (typical) figure 5. variation in iip3 with system gain (typical) figure 6. variation in iip2 with system gain (typical)
9 sl1935 bb837 bb837 bb831 bb831 1k ? ? ? ?
10 sl1935 0.5 0.2 1 0 +j0.2 +j0.5 +j1 +j2 +j5 2 ? j5 ? j2 ? j1 ? j0.5 ? j0.2 stop 30mhz start 1mhz normalised to 50 ? ? ? ? ? ?
11 sl1935 100nf 1k ? ? ? ?
12 sl1935 figure 16. input matching network table 10. electrical characteristics test conditions (unless otherwise stated); tamb = -20 o to +80 o c, vee= 0v, vcc =vccd = 5v+-5%. these characteristics are guaranteed by either production test or design. they apply within the specified ambient temperature and supply voltage unless otherwise stated. characteristic pin value min max typ units conditions supply current rf input operating frequency system system noise figure dsb variation in system nf with gain adjust system input referred ip2 variation in system input referred ip2 with operating sensitivity system input referred ip3 variation in system input referred ip3 with operating sensitivity continued 6,7,10 13,24 8,9 950 121 112 130 10 15 140 175 2150 12 17 -1 ma mhz db db db/db db ?
13 sl1935 characteristic pin value min max typ units conditions system dynamic range system i q gain match system i q phase balance system i and q channel in band ripple system baseband path gain match lo second harmonic interference level lna second harmonic interference level synthesiser and other spurii on i and q outputs in band leakage to rf input converter converter input impedance converter input return loss system input referred p1db converter output impedance, ofia, ofib, opqa and opqb. converter output leakage to unselected output, ofia, ofib, opqa and opqb. oscillator vcos operating range oscillator vcov operating range local oscillator ssb phase noise baseband amplifiers baseband input impedance, ifia, ifib, ifqa and ifqb. resistance capacitance baseband unselected input leakage to output baseband amplifier output impedance baseband output limiting baseband bandwidth 1db baseband output roll-off 17,20 17,20 17,20 17,20 8,9 8,9 8,9 14,15 22,23 31,32 28,29 11,12 25,26 17,20 17,20 17,20 17,20 -70 -1 -3 -1 8 102 1900 1450 10 2.0 40 6 -50 -35 -60 75 25 -26 -78 +1 +3 1 +1 76 50 3000 2150 5 -40 20 dbm dbm db deg db db dbc dbc db ? ? ? ?
14 sl1935 characteristic pin value min max typ units conditions leakage current hysterysis sda output voltage scl clock rate charge pump output current charge pump output leakage charge pump drive output current crystal frequency recommended crystal series resistance external reference input frequency external reference drive level phase detector comparison frequency equivalent phase noise at phase detector local oscillator programmable divider division ratio reference division ratio output port p0 sink current leakage current bufref output output amplitude output impedance address select input high curent input low current 3 4 36 36 35 1,2 2 2 34 5 18 0.5 2 10 2 0.2 240 2 10 0.4 0.6 400 +-10 20 200 20 0.5 4 32767 10 1 -0.5 ? ? ?
15 sl1935 figure 17. input and output interface circuits (rf section) rf inputs oscillator inputs (pins 28, 29 and 31, 32) baseband amplifier inputs (pins 11, 12, 25 and 23) bias 1k 1k v ref2 tank tankb ifia ifib ifqa ifqb rf rfb 8 9 agc input converter outputs (pins 14, 15, 22 and 23) baseband outputs (pins 17 and 20) v ref agccont 30k 5k ofia ofib ofqa ofqb 19 v cc iout and qout
16 sl1935 v ccd scl/sda xtal v ccd 300 35 drive pump 36 ] v ccd 47k on sda only 3k 60k 20k add v ccd p0 34 enable/ disable bufref v ccd ack xtalcap 18 2 1 5 reference oscillator loop amplifier sda/scl (pins 3 and 4) add input output port bufref output figure 18. input and output interface circuits (pll section) ]
17 sl1935 sl1935 demo board the demo board contains an sl1935 i 2 c bus controlled zero if tuner ic, plus all components necessary to demonstrate operation of the sl1935. the schematic and pcb layout of the board are shown in figures 19, 20 and 21. supplies the board must be provided with the following supplies: 5v for the synthesiser section (5vd) 5v for the converter and baseband sections (5v) 30v for the varactor line (30v) the supply connector is a 5 pin 0.1 pin header. the order of connections is 5v e gnd e 30v e gnd e 5v. i 2 c bus connections the board is provided with a rj11 i 2 c bus connector which feeds directly to the synthesiser. this connects to a standard 4 way cable. operating instructions 1. software. use the zar link semiconductor synthesiser software. pull down the ? device ? menu, then select the ? sl1935 ? . it is suggested that the charge pump is set to 130ua with a reference divider ratio of 32. these settings give a small loop bandwidth (i.e. 100 ? s hz), which allows detailed phase noise measurements of the oscillators to be taken if desired. 2. vco control . the two vco ? s are selected by toggling the oscillator switch below the two oscillators on the main software block diagram. this switch programs bit vs of the i 2 c data (see tables 8 and 9a to 9c). vcos oscillates at twice the lo frequency (lower band) and is then divided by two to provide the required lo frequency in the range 950mhz to 1500mhz (approximately). vcov oscillates at the lo frequency (upper band) in the range 1500mhz to 2150mhz (approximately). 3. baseband path select. the sl1935 has two filter paths selected by programming bit bs of the i 2 c data (see tables 6 and 9a to 9c). the value of bs is changed by toggling the switch position to the left of ? filter a ? and ? filter b ? on the main software block diagram. 4. agc control . the conversion gain of the sl1935 is set by the voltage applied to the agccont input. on the demo board this is controlled by the potential divider labelled ? agc adj ? which varies the agccont input from 0v to vcc. caution : care should be taken to ensure the chip is powered on if the board is modified to accept an external agc input voltage. damage to the device may result if this is not complied with as a result of the ic powering itself up via the agccont input esd protection diode. it is recommended that a low current limit is set on any external agc voltage source used. 5. free running the vco ? s. select the required vco as detailed in (2) above. program an lo frequency which is above the maximum capability of the oscillator. 3ghz is suggested. under this condition the varactor control voltage is pumped to its maximum value, ie to the top of the band. the oscillator frequency can now be manually tuned by varying the 30v supply. characteristic min max units conditions supply voltage sd a, scl dc offsets all i/o port dc offsets por t p0 current storage temperature j unction temperature pac kage thermal resistance, chip to case pac kage thermal resistance, chip to ambient po wer consumption at 5.25v esd protection -0.3 -0.3 -0.3 -55 3.5 7 6 vcc+0.3 10 150 150 20 77 919 v v v ma o c o c o c/w o c/w mw kv vcc = vee to 5.25v mil-std 883 method 3015 cat1 table 11. absolute maximum ratings (all voltages referred to vee at 0v and vcc = vccd)
18 sl1935 19. view figure 19. top view
19 sl1935 figure 20. bottom view
20 sl1935 figure 21. of xtalcap 1 xtal 2 sda 3 scl 4 bufref 5 vccd 6 vcc 7 rfin 8 rfinb 9 vcc 10 ifia 11 ifib 12 vcc 13 ofia 14 ofib 15 ve e 16 iout 17 add 18 a gc cont 19 qout 20 ve e 21 ofqb 22 ofqa 23 vcc 24 ifqb 25 ifqa 26 ve e 27 tankvb 28 tankva 29 ve e 30 tanksb 31 tanksa 32 ve e 33 port p0 34 drive 35 pump 36 ic1 sl1935 tr1 bcw31 c27 15nf c26 68pf r19 13k r20 22k r18 13k 30v l1 l2 l3 l4 d1 bb837 d2 bb837 d3 bb831 d4 bb831 c25 2n2 r16 1k r17 1k gnd xl1 4mhz c3 150pf c2 82pf sda 3 5v0 4 gnd 5 scl 6 cn7 i2c 5vd 5vd 5v c5 1nf c6 1nf rfina 5v c7 100nf c8 100nf c9 100nf c10 100nf r1 1k r2 1k r3 1k r4 1k c11 3p9 c12 3p9 c24 100nf c23 100nf c22 100nf c21 100nf r14 1k r13 1k r11 1k r12 1k c19 3p9 c20 3p9 p0 sk2 i out sk3 q out sk1 rf in rfina c13 220nf r5 100r r6 1k c14 15pf iout iout c18 220nf r10 100r r9 1k c17 15pf qout qout ofqb c16 10nf agc + c30 22uf c29 100pf c28 100nf c32 100pf c31 100nf c36 100nf c37 100pf + c38 22uf 5vd 30v 5v c35 100pf c34 100pf c33 100pf d5 port 0 r15 2k7 p0 rv 1 5k r21 620r r22 620r 5vd agc 1 2 3 4 5 cn8 dc power c39 100pf c40 100pf tp8 ag c 5v 5v r7 75r r23 2k r24 2k tp1 tp2 tp3 tp4 tp5 tp6 tp7 1 2 jp1 5v
21 sl1935 purchase of zarlink semiconductor i 2 c components conveys a licence under the phillips i 2 c patent rights to use these components in an i 2 c system,provided that the system conforms to the i 2 c standard specification as defined by phillips.

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