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hm628127hbi series 131072-word 8-bit high speed cmos static ram ade-203-785a (z) rev. 1.0 may. 19, 1997 description the hm628127hbi is an asynchronous high speed static ram organized as 128-k word 8-bit. it realize high speed access time (20 ns) with employing 0.8 m m shrink cmos process and high speed circuit designing technology. it is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. the hm628127hbi is packaged in 400-mil 32-pin soj for high density surface mounting. features single 5 v supply access time 20 ns (max) completely static memory ? no clock or timing strobe required equal access and cycle times directly ttl compatible ? all inputs and outputs 400-mil 32-pin soj package center v cc and v ss type pinout operating temperature C 40 to + 85 c ordering information type no. access time package HM628127HBLJPI-20 20 ns 400-mil 32-pin plastic soj (cp-32db)
hm628127hbi series 2 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a3 a2 a1 a0 cs i/o1 i/o2 v v i/o3 i/o4 we a16 a15 a14 a13 ss a4 a5 a6 a7 oe i/o8 i/o7 v v i/o6 i/o5 a8 a9 a10 a11 a12 cc (top view) hm628127hbljpi series cc ss pin description pin name function a0 to a16 address input i/o1 to i/o8 data input/output cs chip select oe output enable we write enable v cc power supply v ss ground
hm628127hbi series 3 block diagram i/o1 . . . i/o8 we input data control column i/o column decoder memory matrix 256 rows 512 columns 8 bit (1,048,576 bits) row decoder oe cs cs cs v cc v ss cs a3 a2 a1 a0 a7 a6 a5 a4 a13 a12 a11 a14 a15 a16 a10 a9 a8 (lsb) (msb) (lsb) (msb) function table cs oe we mode v cc current i/o ref. cycle h standby i sb , i sb1 high-z l h h output disable i cc high-z l l h read i cc dout read cycle (1) to (3) l h l write i cc din write cycle (1) l l l write i cc din write cycle (2) note: : h or l
hm628127hbi series 4 absolute maximum ratings parameter symbol value unit supply voltage relative to v ss v cc C0.5 to +7.0 v voltage on any pin relative to v ss v t C0.5* 1 to v cc +0.5 v power dissipation p t 1.0* 2 /1.5* 3 w operating temperature topr C 40 to + 85 c storage temperature tstg C 55 to + 125 c storage temperature under bias tbias C 40 to + 85 c notes: 1. v t min = C2.5 v for pulse width (under shoot) 10 ns 2. at still air condition 3. at air flow 3 1.0 m/s recommended dc operating conditions (ta = C 40 to + 85 c) parameter symbol min typ max unit supply voltage v cc * 2 4.5 5.0 5.5 v v ss * 3 000v input voltage v ih 2.4 v cc + 0.5 v v il C0.5* 1 0.6 v notes: 1. v il min = C2.0 v for pulse width (under shoot) 10 ns 2. the supply voltage with all v cc pins must be on the same level. 3. the supply voltage with all v ss pins must be on the same level.
hm628127hbi series 5 dc characteristics (ta = C 40 to + 85 c, v cc = 5v 10%, v ss = 0v) parameter symbol min typ* 1 max unit test conditions input leakage current ii li i2 m a vin = v ss to v cc output leakage current ii lo i2 m a vin = v ss to v cc operation power supply current i cc 100 150 ma cs = v il , lout = 0 ma other inputs = v ih /v il standby power supply current i sb 4580ma cs = v ih , other inputs = v ih /v il i sb1 0.5 ma v cc 3 cs 3 v cc - 0.2 v, (1) 0 v vin 0.2 v or (2) v cc 3 vin 3 v cc - 0.2 v output voltage v ol 0.4 v i ol = 8 ma v oh 2.4 v i oh = C4 ma notes: 1. typical values are at v cc = 5.0 v, ta = +25 c and not guaranteed. capacitance (ta = 25 c, f = 1.0 mhz) parameter symbol min typ max unit test conditions input capacitance* 1 cin 6 pf vin = 0 v input/output capacitance* 1 c i/o 8 pfv i/o = 0 v note: 1. this parameter is sampled and not 100% tested.
hm628127hbi series 6 ac characteristics (ta = C 40 to + 85 c, v cc = 5 v 10%, unless otherwise noted.) test conditions input pulse levels: 0 v to 3.5 v input rise and fall time: 3 ns input and output timing reference levels: 1.5v output load: see figures (including scope and jig) dout 255 w 480 w 5 v 30 pf dout 255 w 480 w 5 v 5 pf output load (b) (for t clz , t olz , t chz , t ohz , t whz , and t ow ) output load (a) read cycle hm628127hbi-20 parameter symbol min max unit notes read cycle time t rc 20 ns address access time t aa 20ns chip select access time t acs 20ns output enable to output valid t oe 10ns output hold from address change t oh 5ns chip select to output in low-z t clz 3 ns 1 output enable to output in low-z t olz 1 ns 1 chip deselect to output in high-z t chz 7 ns 1 output disable to output in high-z t ohz 7 ns 1 chip selection to power up time t pu 0ns chip selection to power down time t pd 20ns
hm628127hbi series 7 write cycle hm628127hbi-20 parameter symbol min max unit notes write cycle time t wc 20ns address valid to end of write t aw 15ns chip select to end of write t cw 12ns9 write pulse width t wp 12ns8 address setup time t as 0 ns 6 write recovery time t wr 2 ns 7 data to write time overlap t dw 10ns data hold from write time t dh 1ns write disable to output in low-z t ow 3 ns 1 output disable to output in high-z t ohz 7 ns 1 write enable to output in high-z t whz 7 ns 1 note: 1. transition is measured 200 mv from steady voltage with load (b). this parameter is sampled and not 100% tested. 2. address should be valid prior to or coincident with cs transition low. 3. we and/or cs must be high during address transition time. 4. if cs and oe are low during this period, i/o pins are in the output state. then, the data input signals of opposite phase to the outputs must not be applied to them. 5. if the cs low transition occurs simultaneously with the we low transition or after the we transition, output remains a high impedance state. 6. t as is measured from the latest address transition to the later of cs or we going low. 7. t wr is measured from the earlier of cs or we going high to the first address transition. 8. a write occurs during the overlap of a low cs and a low we . a write begins at the latest transition among cs going low and we going low. a write ends at the earliest transition among cs going high and we going high. t wp is measured from the beginning of write to the end of write. 9. t cw is measured from the later of cs going low to the end of write.
hm628127hbi series 8 timing waveforms read timing waveform (1) ( we = v ih ) t t t t t rc aa acs oe clz valid data address cs dout valid address high impedance t ohz oe t oh t chz t olz read timing waveform (2) ( we = v ih , cs = v il , oe = v il ) t t rc aa valid data address dout valid address t oh t oh
hm628127hbi series 9 read timing waveform (3) ( we = v ih , cs = v il , oe = v il )* 2 valid data cs dout high impedance high impedance v cc supply current i cc i sb 50% 50% t pu t clz t acs t rc t chz t pd write timing waveform (1) ( we controlled) address we * 3 dout din t wc t wp t wr t cw t dw t dh valid address t aw valid data t as cs * 3 t ohz * 4 * 4 oe high impedance* 5
hm628127hbi series 10 write timing waveform (2) ( cs controlled) address we * 3 dout din t wc t wp t wr t cw t dw t dh valid address t aw valid data t as cs * 3 t whz t ow * 4 * 4 high impedance* 5
hm628127hbi series 11 low v cc data retention characteristics (ta = C 40 to + 85 c) parameter symbol min typ* 1 max unit test conditions v cc for data retention v dr 2.0 v v cc 3 cs 3 v cc C 0.2 v (1) 0 v vin 0.2 v or (2) v cc 3 vin 3 v cc C 0.2 v data retention current i ccdr 2 200 m av cc = 3 v, v cc 3 cs 3 v cc C 0.2 v (1) 0 v vin 0.2 v or (2) v cc 3 vin 3 v cc C 0.2 v chip deselect to data retention time t cdr 0 ns see retention waveform operation recovery time t r 50ms note: 1. typical values are at v cc = 3.0 v, ta = 25 c, and not guaranteed. low v cc data retention timing waveform cc v 4.5 v 2.4 v 0 v cs t cdr t r v 3 cs 3 v ?0.2 v cc cc dr v data retention mode
hm628127hbi series 12 package dimensions hm628127hbljpi series (cp-32db) unit: mm 20.71 21.08 max 32 17 116 0.74 10.16 ?0.13 11.18 ?0.13 3.50 ?0.26 0.43 ?0.10 9.40 ?0.25 2.85 ?0.12 1.30 max 0.10 1.27 0.80 +0.25 ?.17 hitachi code jedec code eiaj code weight cp-32db mo-061-ab sc-638 1.2 g 0.41 ?0.08
hm628127hbi series 13 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi america, ltd. semiconductor & ic div. 2000 sierra point parkway brisbane, ca. 94005-1835 u s a tel: 415-589-8300 fax: 415-583-4207 hitachi europe gmbh electronic components group continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30 00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 0628-585000 fax: 0628-778322 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 0104 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071 copyright ?hitachi, ltd., 1997. all rights reserved. printed in japan.
hm628127hbi series 14 revision record rev. date contents of modification drawn by approved by 1.0 may. 19. 1997 initial issue

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