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hm5264165 series hm5264805 series hm5264405 series 64m lvttl interface sdram 125 mhz/100 mhz 1-mword 16-bit 4-bank/2-mword 8-bit 4-bank/ 4-mword 4-bit 4-bank ade-203-497c(z) rev. 1.0 july 1, 1998 description the hitachi hm5264165 is a 64-mbit sdram organized as 1048576-word 16-bit 4 bank. the hitachi hm5264805 is a 64-mbit sdram organized as 2097512-word 8-bit 4 bank. the hitachi hm5264405 is a 64-mbit sdram organized as 4194304-word 4-bit 4 bank. all inputs and outputs are referred to the rising edge of the clock input. it is packaged in standard 54-pin plastic tsop ii. features 3.3 v power supply clock frequency: 125 mhz/100 mhz (max) lvttl interface single pulsed ras 4 banks can operate simultaneously and independently burst read/write operation and burst read/single write operation capability programmable burst length: 1/2/4/8/full page 2 variations of burst sequence ? sequential (bl = 1/2/4/8/full page) ? interleave (bl = 1/2/4/8) programmable cas latency : 2/3 byte control by dqm : dqm (hm5264805/hm5264405) : dqmu/dqml (hm5264165) refresh cycles: 4096 refresh cycles/64 ms 2 variations of refresh ? auto refresh ? self refresh
hm5264165 series, hm5264805 series, hm5264405 series 2 full page burst length capability ? sequential burst ? burst stop capability ordering information type no. frequency package hm5264165tt-80 hm5264165tt-10 125 mhz 100 mhz 400-mill 54-pin plastic tsop ii (ttp-54d) hm5264165ltt-80 hm5264165ltt-10 125 mhz 100 mhz HM5264805TT-80 hm5264805tt-10 125 mhz 100 mhz hm5264805ltt-80 hm5264805ltt-10 125 mhz 100 mhz hm5264405tt-80 hm5264405tt-10 125 mhz 100 mhz hm5264405ltt-80 hm5264405ltt-10 125 mhz 100 mhz
hm5264165 series, hm5264805 series, hm5264405 series 3 pin arrangement (hm5264165) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v ss dq15 v ss q dq14 dq13 v cc q dq12 dq11 v ss q dq10 dq9 v cc q dq8 v ss nc dqmu clk cke nc a11 a9 a8 a7 a6 a5 a4 v ss v cc dq0 v cc q dq1 dq2 v ss q dq3 dq4 v cc q dq5 dq6 v ss q dq7 v cc dqml we cas ras cs a13 a12 a10 a0 a1 a2 a3 v cc 54-pin tsop (top view) pin description pin name function pin name function a0 to a13 address input dqmu/dqml input/output mask row address a0 to a11 clk clock input column address a0 to a7 cke clock enable bank select address a12/a13 (bs) v cc power for internal circuit dq0 to dq15 data-input/output v ss ground for internal circuit cs chip select v cc q power for dq circuit ras row address strobe command v ss q ground for dq circuit cas column address strobe command nc no connection we write enable
hm5264165 series, hm5264805 series, hm5264405 series 4 pin arrangement (hm5264805) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v ss dq7 v ss q nc dq6 v cc q nc dq5 v ss q nc dq4 v cc q nc v ss nc dqm clk cke nc a11 a9 a8 a7 a6 a5 a4 v ss v cc dq0 v cc q nc dq1 v ss q nc dq2 v cc q nc dq3 v ss q nc v cc nc we cas ras cs a13 a12 a10 a0 a1 a2 a3 v cc 54-pin tsop (top view) pin description pin name function pin name function a0 to a13 address input dqm input/output mask row address a0 to a11 clk clock input column address a0 to a8 cke clock enable bank select address a12/a13 (bs) v cc power for internal circuit dq0 to dq7 data-input/output v ss ground for internal circuit cs chip select v cc q power for dq circuit ras row address strobe command v ss q ground for dq circuit cas column address strobe command nc no connection we write enable
hm5264165 series, hm5264805 series, hm5264405 series 5 pin arrangement (hm5264405) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v ss nc v ss q nc dq3 v cc q nc nc v ss q nc dq2 v cc q nc v ss nc dqm clk cke nc a11 a9 a8 a7 a6 a5 a4 v ss v cc nc v cc q nc dq0 v ss q nc nc v cc q nc dq1 v ss q nc v cc nc we cas ras cs a13 a12 a10 a0 a1 a2 a3 v cc 54-pin tsop (top view) pin description pin name function pin name function a0 to a13 address input dqm input/output mask row address a0 to a11 clk clock input column address a0 to a9 cke clock enable bank select address a12/a13 (bs) v cc power for internal circuit dq0 to dq3 data-input/output v ss ground for internal circuit cs chip select v cc q power for dq circuit ras row address strobe command v ss q ground for dq circuit cas column address strobe command nc no connection we write enable
hm5264165 series, hm5264805 series, hm5264405 series 6 block diagram (hm5264165) column address counter column address buffer row address buffer refresh counter a0 to a13 a0 to a13 dq0 to dq15 input buffer output buffer control logic & timing generator row decoder sense amplifier & i/o bus column decoder memory array clk cke cs ras cas we dqmu /dqml a0 to a7 bank 0 4096 row x 256 column x 16 bit row decoder sense amplifier & i/o bus column decoder memory array bank 1 4096 row x 256 column x 16 bit row decoder sense amplifier & i/o bus column decoder memory array bank 2 4096 row x 256 column x 16 bit row decoder sense amplifier & i/o bus column decoder memory array bank 3 4096 row x 256 column x 16 bit
hm5264165 series, hm5264805 series, hm5264405 series 7 block diagram (hm5264805) column address counter column address buffer row address buffer refresh counter a0 to a13 a0 to a13 input buffer output buffer control logic & timing generator row decoder sense amplifier & i/o bus column decoder memory array clk cke cs ras cas we dqm a0 to a8 bank 0 4096 row x 512 column x 8 bit row decoder sense amplifier & i/o bus column decoder memory array 4096 row x 512 column x 8 bit row decoder sense amplifier & i/o bus column decoder memory array 4096 row x 512 column x 8 bit row decoder sense amplifier & i/o bus column decoder memory array 4096 row x 512 column x 8 bit bank 1 bank 2 bank 3 dq0 to dq7
hm5264165 series, hm5264805 series, hm5264405 series 8 block diagram (hm5264405) column address counter column address buffer row address buffer refresh counter a0 to a13 a0 to a13 dq0 to dq3 input buffer output buffer control logic & timing generator row decoder sense amplifier & i/o bus column decoder memory array clk cke cs ras cas we dqm a0 to a9 bank 0 4096 row x 1024 column x 4 bit row decoder sense amplifier & i/o bus column decoder memory array bank 1 4096 row x 1024 column x 4 bit row decoder sense amplifier & i/o bus column decoder memory array bank 2 4096 row x 1024 column x 4 bit row decoder sense amplifier & i/o bus column decoder memory array bank 3 4096 row x 1024 column x 4 bit
hm5264165 series, hm5264805 series, hm5264405 series 9 pin functions clk (input pin): clk is the master clock input to this pin. the other input signals are referred at clk rising edge. cs (input pin): when cs is low, the command input cycle becomes valid. when cs is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. ras , cas , and we (input pins): although these pin names are the same as those of conventional drams, they function in a different way. these pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. for details, refer to the command operation section. a0 to a11 (input pins): row address (ax0 to ax11) is determined by a0 to a11 level at the bank active command cycle clk rising edge. column address (ay0 to ay7; hm5264165, ay0 to ay8; hm5264805, ay0 to ay9; hm5264405) is determined by a0 to a7, a8 or a9 (a7; hm5264165, a8; hm5264805, a9; hm5264405) level at the read or write command cycle clk rising edge. and this column address becomes burst access start address. a10 defines the precharge mode. when a10 = high at the precharge command cycle, all banks are precharged. but when a10 = low at the precharge command cycle, only the bank that is selected by a12/a13 (bs) is precharged. for details refer to the command operation section. a12/a13 (input pin): a12/a13 are bank select signal (bs). the memory array of the hm5264165, hm5264805, the hm5264405 is divided into bank 0, bank 1, bank 2 and bank 3. hm5264165 contain 4096-row 256-column 16-bit. hm5264805 contain 4096-row 512-column 8-bit. hm5264405 contain 4096-row 1024-column 4-bit. if a12 is low and a13 is low, bank 0 is selected. if a12 is high and a13 is low, bank 1 is selected. if a12 is low and a13 is high, bank 2 is selected. if a12 is high and a13 is high, bank 3 is selected. cke (input pin): this pin determines whether or not the next clk is valid. if cke is high, the next clk rising edge is valid. if cke is low, the next clk rising edge is invalid. this pin is used for power- down mode, clock suspend mode and self refresh mode. dqm, dqmu/dqml (input pins): dqm, dqmu/dqml controls input/output buffers. read operation: if dqm, dqmu/dqml is high, the output buffer becomes high-z. if the dqm, dqmu/dqml is low, the output buffer becomes low-z. (the latency of dqm, dqmu/dqml during reading is 2 clocks.) write operation: if dqm, dqmu/dqml is high, the previous data is held (the new data is not written). if dqm, dqmu/dqml is low, the data is written. (the latency of dqm, dqmu/dqml during writing is 0 clock.) dq0 to dq15 (dq pins): data is input to and output from these pins (dq0 to dq15; hm5264165, dq0 to dq7; hm5264805, dq0 to dq3; hm5264405). v cc and v cc q (power supply pins): 3.3 v is applied. (v cc is for the internal circuit and v cc q is for the output buffer.)
hm5264165 series, hm5264805 series, hm5264405 series 10 v ss and v ss q (power supply pins): ground is connected. (v ss is for the internal circuit and v ss q is for the output buffer.) command operation command truth table the sdram recognizes the following commands specified by the cs , ras , cas , we and address pins. cke command symbol n - 1 n cs ras cas we a12/a13 a 1 0 a0 to a11 ignore command desl h h no operation nop h lhhh burst stop in full page bst h lhhl column address and read command read h lhl hv l v read with auto-precharge read a h lhl hv hv column address and write command writ h lhl lv l v write with auto-precharge writ a h lhl lv hv row address strobe and bank active actv h ll hhv vv precharge select bank pre h ll hlv l precharge all bank pall h ll hl h refresh ref/self h v l l l h mode register set mrs h llllv vv note: h: v ih . l: v il . : v ih or v il . v: valid address input ignore command [desl]: when this command is set ( cs is high), the sdram ignore command input at the clock. however, the internal status is held. no operation [nop]: this command is not an execution command. however, the internal operations continue. burst stop in full-page [bst]: this command stops a full-page burst operation (burst length = full-page (256; hm5264165, 512; hm5264805, 1024; hm5264405)), and is illegal otherwise. when data input/output is completed for a full page of data, it automatically returns to the start address, and input/output is performed repeatedly. column address strobe and read command [read]: this command starts a read operation. in addition, the start address of burst read is determined by the column address (ay0 to ay7; hm5264165, ay0 to ay8; hm5264805, ay0 to ay9; hm5264405) and the bank select address (bs). after the read operation, the output buffer becomes high-z.
hm5264165 series, hm5264805 series, hm5264405 series 11 read with auto-precharge [read a]: this command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4 or 8. when the burst length is full-page, this command is illegal. column address strobe and write command [writ]: this command starts a write operation. when the burst write mode is selected, the column address (ay0 to ay7; hm5264165, ay0 to ay8; hm5264805, ay0 to ay9; hm5264405) and the bank select address (a12/a13) become the burst write start address. when the single write mode is selected, data is only written to the location specified by the column address (ay0 to ay7; hm5264165, ay0 to ay8; hm5264805, ay0 to ay9; hm5264405) and the bank select address (a12/a13). write with auto-precharge [writ a]: this command automatically performs a precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a single write operation. when the burst length is full-page, this command is illegal. row address strobe and bank activate [actv]: this command activates the bank that is selected by a12/a13 (bs) and determines the row address (ax0 to ax11). when a12 and a13 are low, bank 0 is activated. when a12 is high and a13 is low, bank 1 is activated. when a12 is low and a13 is high, bank 2 is activated. when a12 and a13 are high, bank 3 is activated. precharge selected bank [pre]: this command starts precharge operation for the bank selected by a12/a13. if a12 and a13 are low, bank 0 is selected. if a12 is high and a13 is low, bank 1 is selected. if a12 is low and a13 is high, bank 2 is selected. if a12 and a13 are high, bank 3 is selected. precharge all banks [pall]: this command starts a precharge operation for all banks. refresh [ref/self]: this command starts the refresh operation. there are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. for details, refer to the cke truth table section. mode register set [mrs]: the sdram has a mode register that defines how it operates. the mode register is specified by the address pins (a0 to a13) at the mode register set cycle. for details, refer to the mode register configuration. after power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register.
hm5264165 series, hm5264805 series, hm5264405 series 12 dqm truth table (hm5264165) cke command symbol n - 1 n dqmu dqml upper byte (dq8 to dq15) write enable/output enable enbu h l lower byte (dq0 to dq7) write enable/output enable enbl h l upper byte (dq8 to dq15) write inhibit/output disable masku h h lower byte (dq0 to dq7) write inhibit/output disable maskl h h note: h: v ih . l: v il . : v ih or v il . write: i did is needed. read: i dod is needed. dqm truth table (hm5264805/hm5264405) cke command symbol n - 1 n dqm write enable/output enable enb h l write inhibit/output disable mask h h note: h: v ih . l: v il . : v ih or v il . write: i did is needed. read: i dod is needed. the sdram can mask input/output data by means of dqm, dqmu/dqml. dqmu masks the upper byte and dqml masks the lower byte (hm5264165). during reading, the output buffer is set to low-z by setting dqm, dqmu/dqml to low, enabling data output. on the other hand, when dqm, dqmu/dqml is set to high, the output buffer becomes high-z, disabling data output. during writing, data is written by setting dqm, dqmu/dqml to low. when dqm, dqmu/dqml is set to high, the previous data is held (the new data is not written). desired data can be masked during burst read or burst write by setting dqmu/dqml. for details, refer to the dqm, dqmu/dqml control section of the sdram operating instructions.
hm5264165 series, hm5264805 series, hm5264405 series 13 cke truth table cke current state command n - 1 n cs ras cas we address active clock suspend mode entry h l h any clock suspend l l clock suspend clock suspend mode exit l h idle auto-refresh command (ref) h h lllh idle self-refresh entry (self) h llllh idle power down entry h l l h h h hl h self refresh self refresh exit (selfx) l h l h h h lhh power down power down exit l h l h h h lhh note: h: v ih . l: v il . : v ih or v il . clock suspend mode entry: the sdram enters clock suspend mode from active mode by setting cke to low. the clock suspend mode changes depending on the current status (1 clock before) as shown below. active clock suspend: this suspend mode ignores inputs after the next clock by internally maintaining the bank active status. read suspend and read with auto-precharge suspend: the data being output is held (and continues to be output). write suspend and writ with auto-precharge suspend: in this mode, external signals are not accepted. however, the internal state is held. clock suspend: during clock suspend mode, keep the cke to low. clock suspend mode exit: the sdram exits from clock suspend mode by setting cke to high during the clock suspend state. idle: in this state, all banks are not selected, and completed precharge operation. auto-refresh command [ref]: when this command is input from the idle state, the sdram starts auto-refresh operation. (the auto-refresh is the same as the cbr refresh of conventional drams.) during the auto-refresh operation, refresh address and bank select address are generated inside the sdram. for every auto-refresh cycle, the internal address counter is updated. accordingly, 4096 times are required to refresh the entire memory. before executing the auto-refresh command, all the banks must be in the idle state. in addition, since the precharge for all banks is automatically performed after auto-refresh, no precharge command is required after auto-refresh.
hm5264165 series, hm5264805 series, hm5264405 series 14 self-refresh entry [self]: when this command is input during the idle state, the sdram starts self- refresh operation. after the execution of this command, self-refresh continues while cke is low. since self-refresh is performed internally and automatically, external refresh operations are unnecessary. power down mode entry: when this command is executed during the idle state, the sdram enters power down mode. in power down mode, power consumption is suppressed by cutting off the initial input circuit. self-refresh exit: when this command is executed during self-refresh mode, the sdram can exit from self-refresh mode. after exiting from self-refresh mode, the sdram enters the idle state. power down exit: when this command is executed at the power down mode, the sdram can exit from power down mode. after exiting from power down mode, the sdram enters the idle state. function truth table the following table shows the operations that are performed when each command is issued in each mode of the sdram. the following table assumes that cke is high. current state cs ras cas we address command operation precharge h desl enter idle after trp lhhh nop enter idle after trp lhhl bst nop l h l h ba, ca, a10 read/read a illegal l h l l ba, ca, a10 writ/writ a illegal l l h h ba, ra actv illegal l l h l ba, a10 pre, pall nop ll lh ref, self illegal l l l l mode mrs illegal idle h desl nop lhhh nop nop lhhl bst nop l h l h ba, ca, a10 read/read a illegal l h l l ba, ca, a10 writ/writ a illegal l l h h ba, ra actv bank and row active l l h l ba, a10 pre, pall nop ll lh ref, self refresh l l l l mode mrs mode register set
hm5264165 series, hm5264805 series, hm5264405 series 15 current state cs ras cas we address command operation row active h desl nop lhhh nop nop lhhl bst nop l h l h ba, ca, a10 read/read a begin read l h l l ba, ca, a10 writ/writ a begin write l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall precharge ll lh ref, self illegal l l l l mode mrs illegal read h desl continue burst to end lhhh nop continue burst to end lhhl bst burst stop to full page l h l h ba, ca, a10 read/read a continue burst read to cas latency and new read l h l l ba, ca, a10 writ/writ a term burst read/start write l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall term burst read and precharge ll lh ref, self illegal l l l l mode mrs illegal read with auto- precharge h desl continue burst to end and precharge lhhh nop continue burst to end and precharge lhhl bst illegal l h l h ba, ca, a10 read/read a illegal l h l l ba, ca, a10 writ/writ a illegal l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall illegal ll lh ref, self illegal l l l l mode mrs illegal
hm5264165 series, hm5264805 series, hm5264405 series 16 current state cs ras cas we address command operation write h desl continue burst to end lhhh nop continue burst to end lhhl bst burst stop on full page l h l h ba, ca, a10 read/read a term burst and new read l h l l ba, ca, a10 writ/writ a term burst and new write l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall term burst write and precharge* 2 ll lh ref, self illegal l l l l mode mrs illegal write with auto- precharge h desl continue burst to end and precharge lhhh nop continue burst to end and precharge lhhl bst illegal l h l h ba, ca, a10 read/read a illegal l h l l ba, ca, a10 writ/writ a illegal l l h h ba, ra actv other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall illegal ll lh ref, self illegal l l l l mode mrs illegal refresh (auto- refresh) h desl enter idle after t rc lhhh nop enter idle after t rc lhhl bst enter idle after t rc l h l h ba, ca, a10 read/read a illegal l h l l ba, ca, a10 writ/writ a illegal l l h h ba, ra actv illegal l l h l ba, a10 pre, pall illegal ll lh ref, self illegal l l l l mode mrs illegal notes: 1. h: v ih . l: v il . : v ih or v il . the other combinations are inhibit. 2. an interval of t dpl is required between the final valid data input and the precharge command. 3. if t rrd is not satisfied, this operation is illegal.
hm5264165 series, hm5264805 series, hm5264405 series 17 from precharge state, command operation to [desl], [nop] or [bst]: when these commands are executed, the sdram enters the idle state after t rp has elapsed from the completion of precharge. from idle state, command operation to [desl], [nop], [bst], [pre] or [pall]: these commands result in no operation. to [actv]: the bank specified by the address pins and the row address is activated. to [ref], [self]: the sdram enters refresh mode (auto-refresh or self-refresh). to [mrs]: the sdram enters the mode register set cycle. from row active state, command operation to [desl], [nop] or [bst]: these commands result in no operation. to [read], [read a]: a read operation starts. (however, an interval of t rcd is required.) to [writ], [writ a]: a write operation starts. (however, an interval of t rcd is required.) to [actv]: this command makes the other bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. to [pre], [pall]: these commands set the sdram to precharge mode. (however, an interval of t ras is required.) from read state, command operation to [desl], [nop]: these commands continue read operations until the burst operation is completed. to [bst]: this command stops a full-page burst. to [read], [read a]: data output by the previous read command continues to be output. after cas latency, the data output resulting from the next command will start. to [writ], [writ a]: these commands stop a burst read, and start a write cycle. to [actv]: this command makes other banks bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. to [pre], [pall]: these commands stop a burst read, and the sdram enters precharge mode.
hm5264165 series, hm5264805 series, hm5264405 series 18 from read with auto-precharge state, command operation to [desl], [nop]: these commands continue read operations until the burst operation is completed, and the sdram then enters precharge mode. to [actv]: this command makes other banks bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. from write state, command operation to [desl], [nop]: these commands continue write operations until the burst operation is completed. to [bst]: this command stops a full-page burst. to [read], [read a]: these commands stop a burst and start a read cycle. to [writ], [writ a]: these commands stop a burst and start the next write cycle. to [actv]: this command makes the other bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. to [pre], [pall]: these commands stop burst write and the sdram then enters precharge mode. from write with auto-precharge state, command operation to [desl], [nop]: these commands continue write operations until the burst is completed, and the sdram enters precharge mode. to [actv]: this command makes the other bank active. (however, an interval of t rrd is required.) attempting to make the currently active bank active results in an illegal command. from refresh state, command operation to [desl], [nop], [bst]: after an auto-refresh cycle (after t rc ), the sdram automatically enters the idle state.
hm5264165 series, hm5264805 series, hm5264405 series 19 simplified state diagram precharge write suspend read suspend row active idle idle power down auto refresh self refresh mode register set power on writea writea suspend reada reada suspend active clock suspend sr entry sr exit mrs refresh cke cke_ active write read write with ap read with ap power applied cke cke_ cke cke_ cke cke_ cke cke_ cke cke_ precharge ap read write write with ap read with read with ap write with ap precharge precharge precharge bst (on full page) bst (on full page) *1 read read write write automatic transition after completion of command. transition resulting from command input. note: 1. after the auto-refresh operation, precharge operation is performed automatically and enter the idle state.
hm5264165 series, hm5264805 series, hm5264405 series 20 mode register configuration the mode register is set by the input to the address pins (a0 to a13) during mode register set cycles. the mode register consists of five sections, each of which is assigned to address pins. a13, a12, a11, a10, a9 a8: (opcode): the sdram has two types of write modes. one is the burst write mode, and the other is the single write mode. these bits specify write mode. burst read and burst write: burst write is performed for the specified burst length starting from the column address specified in the write cycle. burst read and single write: data is only written to the column address specified during the write cycle, regardless of the burst length. a7: keep this bit low at the mode register set cycle. if this pin is high, the vender test mode is set. a6, a5, a4: (lmode): these pins specify the cas latency. a3: (bt): a burst type is specified. when full-page burst is performed, only "sequential" can be selected. a2, a1, a0: (bl): these pins specify the burst length. a2 a1 a0 burst length 00 0 1 00 1 2 01 0 4 01 1 8 1 1 1 f.p. bt=0 bt=1 10 0 r 11 0 r 1 2 4 8 r r r a3 0 sequential 1 interleave burst type a6 a5 a4 cas latency 00 0 r 00 1 r 01 0 2 01 1 3 1xx r a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 opcode 0 lmode bt bl a9 0 0r write mode a8 0 1 burst read and burst write 1 burst read and single write 0 1r 1 10 1 r r f.p. = full page (256: hm5264165) (512: hm5264805) (1024: hm5264405) r is reserved (inhibit) x: 0 or 1 a11 a10 a10 x x x a11 x x x 00 a12 a13 a13 x x x 0 a12 x x x 0
hm5264165 series, hm5264805 series, hm5264405 series 21 burst sequence a2 a1 a0 addressing(decimal) 00 0 00 1 01 0 01 1 11 1 interleave sequential 10 0 11 0 10 1 starting ad. 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 2, 3, 4, 5, 6, 7, 3, 4, 5, 6, 7, 4, 5, 6, 7, 5, 6, 7, 6, 7, 7, 0, 0, 1, 0, 1, 2, 0, 1, 2, 3, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4, 5, 0, 1, 2, 3, 4, 5, 6, 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 2, 3, 0, 1, 6, 7, 3, 2, 1, 0, 7, 4, 5, 6, 7, 5, 4, 7, 6, 7, 7, 6, 4, 5, 6, 5, 4, 0, 1, 2, 3, 6, 1, 0, 3, 2, 4, 5, 2, 3, 0, 1, 6, 5, 4, 3, 2, 1, 0, burst length = 8 a1 a0 addressing(decimal) 00 01 10 11 interleave sequential starting ad. 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0, burst length = 4 a0 addressing(decimal) 0 1 interleave sequential starting ad. 0, 1, 1, 0, 0, 1, 1, 0, burst length = 2
hm5264165 series, hm5264805 series, hm5264405 series 22 operation of the sdram read/write operations bank active: before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (actv) command. bank 0, bank 1, bank 2 or bank 3 is activated according to the status of the a12/a13 pin, and the row address (ax0 to ax11) is activated by the a0 to a11 pins at the bank active command cycle. an interval of t rcd is required between the bank active command input and the following read/write command input. read operation: a read operation starts when a read command is input. output buffer becomes low-z in the ( cas latency - 1) cycle after read command set. hm5264165, hm5264805 series, hm5264405 can perform a burst read operation. the burst length can be set to 1, 2, 4, 8 or full-page (256; hm5264165, 512; hm5264805, 1024; hm5264405). the start address for a burst read is specified by the column address (ay0 to ay7; hm5264165, ay0 to ay8; hm5264805, ay0 to ay9; hm5264405) and the bank select address (a12/a13) at the read command set cycle. in a read operation, data output starts after the number of clocks specified by the cas latency. the cas latency can be set to 2 or 3. when the burst length is 1, 2, 4, 8, the dout buffer automatically becomes high-z at the next clock after the successive burst-length data has been output. the cas latency and burst length must be specified at the mode register. cas latency read clk command dout actv row column address cl = 2 cl = 3 out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 t rcd cl = cas latency burst length = 4
hm5264165 series, hm5264805 series, hm5264405 series 23 burst length read clk command dout actv row column out 0 out 6 out 7 out 8 address out 0 out 1 out 4 out 5 out 0 out 1 out 2 out 3 bl = 1 out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 out 6 out 7 out 4 out 5 out 0-1 out 0 out 1 bl = 2 bl = 4 bl = 8 bl = full page t rcd bl : burst length cas latency = 2 write operation: burst write or single write mode is selected by the opcode (a13, a12, a11, a10, a9, a8) of the mode register. 1. burst write: a burst write operation is enabled by setting opcode (a9, a8) to (0, 0). a burst write starts in the same clock as a write command set. (the latency of data input is 0 clock.) the burst length can be set to 1, 2, 4, 8, and full-page, like burst read operations. the write start address is specified by the column address (ay0 to ay7; hm5264165, ay0 to ay8; hm5264805, ay0 to ay9; hm5264405) and the bank select address (a12/a13) at the write command set cycle. writ clk command din actv row column in 0 in 6 in 7 in 8 address in 1 in 4 in 5 in 3 bl = 1 in 6 in 7 in 4 in 5 in 0-1 in 0 in 1 bl = 2 bl = 4 bl = 8 bl = full page t rcd in 0 in 0 in 0 in 0 in 1 in 1 in 1 in 2 in 2 in 2 in 3 in 3 cas latency = 2, 3
hm5264165 series, hm5264805 series, hm5264405 series 24 2. single write: a single write operation is enabled by setting opcode (a9, a8) to (1, 0). in a single write operation, data is only written to the column address (ay0 to ay7; hm5264165, ay0 to ay8; hm5264805, ay0 to ay9; hm5264405) and the bank select address (a12/a13) specified by the write command set cycle without regard to the burst length setting. (the latency of data input is 0 clock). writ clk command din actv row column in 0 address t rcd auto precharge read with auto-precharge: in this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. the command executed for the same bank after the execution of this command must be the bank active (actv) command. in addition, an interval defined by l apr is required before execution of the next command. cas latency precharge start cycle 3 2 cycle before the final data is output 2 1 cycle before the final data is output burst read (burst length = 4) clk l apr l ras l apr cl=2 command cl=3 command dq (input) dq (input) note: internal auto-precharge starts at the timing indicated by " ". and an interval of t ras (l ras ) is required between previous active (actv) command and internal precharge " ". actv read a actv out3 out2 out1 out0 l ras actv read a actv out3 out2 out1 out0
hm5264165 series, hm5264805 series, hm5264405 series 25 write with auto-precharge: in this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. the command executed for the same bank after the execution of this command must be the bank active (actv) command. in addition, an interval of l apw is required between the final valid data input and input of next command. burst write (burst length = 4) clk command dq (input) l apw i ras actv writ a in0 in1 in2 in3 actv note: internal auto-precharge starts at the timing indicated by " ". and an interval of t ras (l ras ) is required between previous active (actv) command and internal precharge " ". single write clk command dq (input) l apw i ras actv writ a in actv note: internal auto-precharge starts at the timing indicated by " ". and an interval of t ras (l ras ) is required between previous active (actv) command and internal precharge " ".
hm5264165 series, hm5264805 series, hm5264405 series 26 full-page burst stop burst stop command during burst read: the burst stop (bst) command is used to stop data output during a full-page burst. the bst command sets the output buffer to high-z and stops the full-page burst read. the timing from command input to the last data changes depending on the cas latency setting. in addition, the bst command is valid only during full-page burst mode, and is illegal with burst lengths 1, 2, 4 and 8. cas latency bst to valid data bst to high impedance 212 323 cas latency = 2, burst length = full page l = 1 clock bsr clk command dq (output) out out out out l = 2 clocks bsh bst out out cas latency = 3, burst length = full page l = 2 clocks bsr clk command dq (output) out out out out l = 3 clocks bsh bst out out out
hm5264165 series, hm5264805 series, hm5264405 series 27 burst stop command at burst write: the burst stop command (bst command) is used to stop data input during a full-page burst write. no data is written in the same clock as the bst command, and in subsequent clocks. in addition, the bst command is only valid during full-page burst mode, and is illegal with burst lengths of 1, 2, 4 and 8. and an interval of t dpl is required between last data-in and the next precharge command. burst length = full page t clk command dq (input) in dpl in pre/pall bst i = 0 clock bsw
hm5264165 series, hm5264805 series, hm5264405 series 28 command intervals read command to read command interval: 1. same bank, same row address: when another read command is executed at the same row address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 clock. even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. read to read command interval (same row address in same bank) clk command dout out b3 address out b1 out b2 bs actv row column a read read column b out a0 out b0 bank0 active column =a read column =b read column =a dout column =b dout cas latency = 3 burst length = 4 bank 0 2. same bank, different row address: when the row address changes on same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank-active command. 3. different bank: when the bank changes, the second read can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. read to read command interval (different bank) clk command dout out b3 address out b1 out b2 bs actv row 0 row 1 actv read column a out a0 out b0 bank0 active bank3 active bank0 read bank3 read read column b bank0 dout bank3 dout cas latency = 3 burst length = 4
hm5264165 series, hm5264805 series, hm5264405 series 29 write command to write command interval: 1. same bank, same row address: when another write command is executed at the same row address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 clock. in the case of burst writes, the second write command has priority. write to write command interval (same row address in same bank) clk command din in b3 address in b1 in b2 bs actv row column a writ writ column b in a0 in b0 bank0 active column =a write column =b write burst write mode burst length = 4 bank 0 2. same bank, different row address: when the row address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank-active command. 3. different bank: when the bank changes, the second write can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. in the case of burst write, the second write command has priority. write to write command interval (different bank) clk command din in b3 address in b1 in b2 bs actv row 0 row 1 actv writ column a in a0 in b0 bank0 active bank3 active bank0 write bank3 write writ column b burst write mode burst length = 4
hm5264165 series, hm5264805 series, hm5264405 series 30 read command to write command interval: 1. same bank, same row address: when the write command is executed at the same row address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 clock. however, dqm, dqmu/dqml must be set high so that the output buffer becomes high-z before data input. read to write command interval (1) clk command dout in b2 in b3 read writ in b0 in b1 high-z din cl=2 cl=3 dqm, dqmu /dqml burst length = 4 burst write read to write command interval (2) clk command dout read writ din cl=2 cl=3 dqm, dqmu/dqml high-z 2 clock high-z 2. same bank, different row address: when the row address changes, consecutive write commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank- active command. 3. different bank: when the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. however, dqm, dqmu/dqml must be set high so that the output buffer becomes high-z before data input.
hm5264165 series, hm5264805 series, hm5264405 series 31 write command to read command interval: 1. same bank, same row address: when the read command is executed at the same row address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 clock. however, in the case of a burst write, data will continue to be written until one clock before the read command is executed. write to read command interval (1) clk command din writ read in a0 out b1 out b2 out b3 out b0 dout column = a write column = b read column = b dout cas latency dqm, dqmu/dqml burst write mode cas latency = 2 burst length = 4 bank 0 write to read command interval (2) clk command din writ read in a0 out b1 out b2 out b3 out b0 dout column = a write column = b read column = b dout cas latency in a1 dqm, dqmu/dqml burst write mode cas latency = 2 burst length = 4 bank 0 2. same bank, different row address: when the row address changes, consecutive read commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank- active command. 3. different bank: when the bank changes, the read command can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. however, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address).
hm5264165 series, hm5264805 series, hm5264405 series 32 read command to precharge command interval (same bank): when the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one clock. however, since the output buffer then becomes high-z after the clocks defined by l hzp , there is a case of interruption to burst read data output will be interrupted, if the precharge command is input during burst read. to read all data by burst read, the clocks defined by l ep must be assured as an interval from the final data output to precharge command execution. read to precharge command interval (same bank): to output all data cas latency = 2, burst length = 4 clk command dout read pre/pall out a0 out a1 out a2 out a3 cl=2 l = -1 cycle ep cas latency = 3, burst length = 4 clk command dout read pre/pall out a0 out a1 out a2 out a3 cl=3 l = -2 cycle ep
hm5264165 series, hm5264805 series, hm5264405 series 33 read to precharge command interval (same bank): to stop output data cas latency = 2, burst length = 1, 2, 4, 8, full page burst clk command dout read pre/pall out a0 l hzp =2 high-z cas latency = 3, burst length = 1, 2, 4, 8, full page burst clk command dout read pre/pall out a0 l hzp =3 high-z
hm5264165 series, hm5264805 series, hm5264405 series 34 write command to precharge command interval (same bank): when the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 clock. however, if the burst write operation is unfinished, the input data must be masked by means of dqm, dqmu/dqml for assurance of the clock defined by t dpl . write to precharge command interval (same bank) burst length = 4 (to stop write operation) clk command din writ pre/pall t dpl dqm, dqmu/dqml clk in a0 in a1 command din writ pre/pall dqm, dqmu/dqml t dpl burst length = 4 (to write all data) clk in a0 in a1 in a2 command din writ pre/pall in a3 dqm, dqmu/dqml t dpl
hm5264165 series, hm5264805 series, hm5264405 series 35 bank active command interval: 1. same bank: the interval between the two bank-active commands must be no less than t rc . 2. in the case of different bank-active commands: the interval between the two bank-active commands must be no less than t rrd . bank active to bank active for same bank clk command address bs bank 0 active actv row actv row bank 0 active t rc bank active to bank active for different bank clk command address bs bank 0 active bank 3 active actv row:0 actv row:1 t rrd
hm5264165 series, hm5264805 series, hm5264405 series 36 mode register set to bank-active command interval: the interval between setting the mode register and executing a bank-active command must be no less than l rsa . clk command address mode register set bank active mrs actv i rsa bs & row code dqm control the dqmu and dqml mask the upper and lower bytes of the dq data, respectively. the timing of dqmu/dqml is different during reading and writing. reading: when data is read, the output buffer can be controlled by dqm, dqmu/dqml. by setting dqmu/dqml to low, the output buffer becomes low-z, enabling data output. by setting dqm, dqmu/dqml to high, the output buffer becomes high-z, and the corresponding data is not output. however, internal reading operations continue. the latency of dqm, dqmu/dqml during reading is 2 clocks. writing: input data can be masked by dqm, dqmu/dqml. by setting dqm, dqmu/dqml to low, data can be written. in addition, when dqm, dqmu/dqml is set to high, the corresponding data is not written, and the previous data is held. the latency of dqm, dqmu/dqml during writing is 0 clock.
hm5264165 series, hm5264805 series, hm5264405 series 37 reading clk dq (output) out 0 out 1 l = 2 latency out 3 dod dqm, dqmu/dqml high-z writing clk dq (input) in 0 in 1 l = 0 latency in 3 did dqm, dqmu/dqml
hm5264165 series, hm5264805 series, hm5264405 series 38 refresh auto-refresh: all the banks must be precharged before executing an auto-refresh command. since the auto-refresh command updates the internal counter every time it is executed and determines the banks and the row addresses to be refreshed, external address specification is not required. the refresh cycle is 4096 cycles/64 ms. (4096 cycles are required to refresh all the row addresses.) the output buffer becomes high-z after auto-refresh start. in addition, since a precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by the precharge command is not required. self-refresh: after executing a self-refresh command, the self-refresh operation continues while cke is held low. during self-refresh operation, all row addresses are refreshed by the internal refresh timer. a self-refresh is terminated by a self-refresh exit command. before and after self-refresh mode, execute auto- refresh to all refresh addresses in or within 64 ms period on the condition (1) and (2) below. (1) enter self-refresh mode within 15.6 m s after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. (2) start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6 m s after exiting from self-refresh mode. others power-down mode: the sdram enters power-down mode when cke goes low in the idle state. in power down mode, power consumption is suppressed by deactivating the input initial circuit. power down mode continues while cke is held low. in addition, by setting cke to high, the sdram exits from the power down mode, and command input is enabled from the next clock. in this mode, internal refresh is not performed. clock suspend mode: by driving cke to low during a bank-active or read/write operation, the sdram enters clock suspend mode. during clock suspend mode, external input signals are ignored and the internal state is maintained. when cke is driven high, the sdram terminates clock suspend mode, and command input is enabled from the next clock. for details, refer to the "cke truth table". power-up sequence: the sdram should be gone on the following sequence with power up. the clk, cke, cs , dqm, dqmu/dqml and dq pins keep low till power stabilizes. the clk pin is stabilized within 100 m s after power stabilizes before the following initialization sequence. the cke and dqm, dqmu/dqml is driven to high between power stabilizes and the initialization sequence. this sdram has v cc clamp diodes for clk, cke, cs , dqm, dqmu/dqml and dq pins. if these pins go high before power up, the large current flows from these pins to v cc through the diodes. initialization sequence: when 200 m s has past after the above power-up sequence, all banks must be precharged using the precharge command (pall). after t rp delay, set 8 or more auto refresh commands (ref). set the mode register set command (mrs) to initialize the mode register. we recommend that by keeping dqm, dqmu/dqml to high, the output buffer becomes high-z during initialization sequence, to avoid dq bus contention on memory system formed with a number of device.
hm5264165 series, hm5264805 series, hm5264405 series 39 v cc , v cc q power up sequence initialization sequence 100 s 0 v low low low cke, dqm, dqmu/dqml clk cs , dq 200 s power stabilize absolute maximum ratings parameter symbol value unit note voltage on any pin relative to v ss v t C0.5 to v cc + 0.5 ( 4.6 (max)) v1 supply voltage relative to v ss v cc C0.5 to +4.6 v 1 short circuit output current iout 50 ma power dissipation p t 1.0 w operating temperature topr 0 to +70 c storage temperature tstg C55 to +125 c note: 1. respect to v ss dc operating conditions (ta = 0 to +70 c) parameter symbol min max unit notes supply voltage v cc , v cc q 3.0 3.6 v 1, 2 v ss , v ss q0 0v3 input high voltage v ih 2.0 v cc + 0.3 v 1, 4, 5 input low voltage v il C0.3 0.8 v 1, 6 notes: 1. all voltage referred to v ss 2. the supply voltage with all v cc and v cc q pins must be on the same level. 3. the supply voltage with all v ss and v ss q pins must be on the same level. 4. clk, cke, cs , dqm, dqmu/dqml, dq pins: v ih (max) = v cc + 0.5 v for pulse width 5 ns at v cc . 5. others: v ih (max) = 4.6 v for pulse width 5 ns at v cc . 6. v il (min) = C1.0 v for pulse width 5 ns at v ss .
hm5264165 series, hm5264805 series, hm5264405 series 40 dc characteristics (ta = 0 to 70 c, v cc , v cc q = 3.3 v 0.3 v, v ss , v ss q = 0 v) (hm5264165) hm5264165 -80 -10 parameter symbol min max min max unit test conditions notes operating current ( cas latency = 2) i cc1 90 75 ma burst length = 1 t rc = min 1, 2, 3 ( cas latency = 3) i cc1 95 80 ma standby current in power down i cc2p 3 3 ma cke = v il , t ck = 12 ns 6 standby current in power down (input signal stable) i cc2ps 2 2 ma cke = v il , t ck = 7 standby current in non power down i cc2n 20 20 ma cke, cs = v ih , t ck = 12 ns 4 standby current in non power down (input signal stable) i cc2ns 9 9 ma cke = v ih , t ck = 9 active standby current in power down i cc3p 6 6 ma cke = v il , t ck = 12 ns 1, 2, 6 active standby current in power down (input signal stable) i cc3ps 5 5 ma cke = v il , t ck = 2, 7 active standby current in non power down i cc3n 30 30 ma cke, cs = v ih , t ck = 12 ns 1, 2, 4 active standby current in non power down (input signal stable) i cc3ns 20 20 ma cke = v ih , t ck = 2, 9 burst operating current ( cas latency = 2) i cc4 145 120 ma t ck = min, bl = 4 1, 2, 5 ( cas latency = 3) i cc4 205 170 ma refresh current i cc5 140 110 ma t rc = min 3 self refresh current i cc6 2 2 mav ih 3 v cc C 0.2 v v il 0.2 v 8 self refresh current (l-version) i cc6 400 400 m a input leakage current i li C1 1 C1 1 m a0 vin v cc output leakage current i lo C1.5 1.5 C1.5 1.5 m a0 vout v cc dq = disable output high voltage v oh 2.4 2.4 v i oh = C2 ma output low voltage v ol 0.4 0.4 v i ol = 2 ma
hm5264165 series, hm5264805 series, hm5264405 series 41 dc characteristics (ta = 0 to 70 c, v cc , v cc q = 3.3 v 0.3 v, v ss , v ss q = 0 v) (hm5264805) hm5264805 -80 -10 parameter symbol min max min max unit test conditions notes operating current ( cas latency = 2) i cc1 80 65 ma burst length = 1 t rc = min 1, 2, 3 ( cas latency = 3) i cc1 85 70 ma standby current in power down i cc2p 3 3 ma cke = v il , t ck = 12 ns 6 standby current in power down (input signal stable) i cc2ps 2 2 ma cke = v il , t ck = 7 standby current in non power down i cc2n 20 20 ma cke, cs = v ih , t ck = 12 ns 4 standby current in non power down (input signal stable) i cc2ns 9 9 ma cke = v ih , t ck = 9 active standby current in power down i cc3p 6 6 ma cke = v il , t ck = 12 ns 1, 2, 6 active standby current in power down (input signal stable) i cc3ps 5 5 ma cke = v il , t ck = 2, 7 active standby current in non power down i cc3n 30 30 ma cke, cs = v ih , t ck = 12 ns 1, 2, 4 active standby current in non power down (input signal stable) i cc3ns 20 20 ma cke = v ih , t ck = 2, 9 burst operating current ( cas latency = 2) i cc4 115 90 ma t ck = min, bl = 4 1, 2, 5 ( cas latency = 3) i cc4 155 120 ma refresh current i cc5 140 110 ma t rc = min 3 self refresh current i cc6 2 2 mav ih 3 v cc C 0.2 v v il 0.2 v 8 self refresh current (l-version) i cc6 400 400 m a input leakage current i li C1 1 C1 1 m a0 vin v cc output leakage current i lo C1.5 1.5 C1.5 1.5 m a0 vout v cc dq = disable output high voltage v oh 2.4 2.4 v i oh = C2 ma output low voltage v ol 0.4 0.4 v i ol = 2 ma
hm5264165 series, hm5264805 series, hm5264405 series 42 dc characteristics (ta = 0 to 70 c, v cc , v cc q = 3.3 v 0.3 v, v ss , v ss q = 0 v) (hm5264405) hm5264405 -80 -10 parameter symbol min max min max unit test conditions notes operating current ( cas latency = 2) i cc1 75 65 ma burst length = 1 t rc = min 1, 2, 3 ( cas latency = 3) i cc1 80 70 ma standby current in power down i cc2p 3 3 ma cke = v il , t ck = 12 ns 6 standby current in power down (input signal stable) i cc2ps 2 2 ma cke = v il , t ck = 7 standby current in non power down i cc2n 20 20 ma cke, cs = v ih , t ck = 12 ns 4 standby current in non power down (input signal stable) i cc2ns 9 9 ma cke = v ih , t ck = 9 active standby current in power down i cc3p 6 6 ma cke = v il , t ck = 12 ns 1, 2, 6 active standby current in power down (input signal stable) i cc3ps 5 5 ma cke = v il , t ck = 2, 7 active standby current in non power down i cc3n 30 30 ma cke, cs = v ih , t ck = 12 ns 1, 2, 4 active standby current in non power down (input signal stable) i cc3ns 20 20 ma cke = v ih , t ck = 2, 9 burst operating current ( cas latency = 2) i cc4 105 80 ma t ck = min, bl = 4 1, 2, 5 ( cas latency = 3) i cc4 145 110 ma refresh current i cc5 140 110 ma t rc = min 3 self refresh current i cc6 2 2 mav ih 3 v cc C 0.2 v v il 0.2 v 8 self refresh current (l-version) i cc6 400 400 m a input leakage current i li C1 1 C1 1 m a0 vin v cc output leakage current i lo C1.5 1.5 C1.5 1.5 m a0 vout v cc dq = disable output high voltage v oh 2.4 2.4 v i oh = C2 ma output low voltage v ol 0.4 0.4 v i ol = 2 ma
hm5264165 series, hm5264805 series, hm5264405 series 43 notes: 1. i cc depends on output load condition when the device is selected. i cc (max) is specified at the output open condition. 2. one bank operation. 3. input signals are changed once per one clock. 4. input signals are changed once per two clocks. 5. input signals are changed once per four clocks. 6. after power down mode, clk operating current. 7. after power down mode, no clk operating current. 8. after self refresh mode set, self refresh current. 9. input signals are v ih or v il fixed. capacitance (ta = 25 c, v cc , v cc q = 3.3 v 0.3 v) parameter symbol typ max unit notes input capacitance (address) c i1 5 pf 1, 2, 4 input capacitance (signals) c i2 5 pf 1, 2, 4 output capacitance (dq) c o 7 pf 1, 2, 3, 4 notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. measurement condition: f = 1 mhz, 1.4 v bias, 200 mv swing. 3. dqm, dqmu/dqml = v ih to disable dout. 4. this parameter is sampled and not 100% tested.
hm5264165 series, hm5264805 series, hm5264405 series 44 ac characteristics (ta = 0 to 70 c, v cc , v cc q = 3.3 v 0.3 v, v ss , v ss q = 0 v) hm5264165/hm5264805/hm5264405 -80 -10 parameter symbol min max min max unit notes system clock cycle time ( cas latency = 2) t ck 12 15 ns 1 ( cas latency = 3) t ck 8 10 ns clk high pulse width t ckh 33ns1 clk low pulse width t ckl 33ns1 access time from clk ( cas latency = 2) t ac 8 8 ns 1, 2 ( cas latency = 3) t ac 6 8 ns data-out hold time t oh 2.5 2.5 ns 1, 2 clk to data-out low impedance t lz 2 2 ns 1, 2, 3 clk to data-out high impedance t hz 6 7 ns 1, 4 data-in setup time t ds 22ns1 data in hold time t dh 11ns1 address setup time t as 22ns1 address hold time t ah 11ns1 cke setup time t ces 2 2 ns 1, 5 cke setup time for power down exit t cesp 22ns1 cke hold time t ceh 11ns1 command ( cs , ras , cas , we , dqm) setup time t cs 22ns1 command ( cs , ras , cas , we , dqm) hold time t ch 11ns1 ref/active to ref/active command period t rc 72 90 ns 1 active to precharge command period t ras 48 120000 60 120000 ns 1 active command to column command (same bank) t rcd 24 30 ns 1 precharge to active command period t rp 24 30 ns 1 write recovery or data-in to precharge lead time t dpl 10 15 ns 1 active (a) to active (b) command period t rrd 16 20 ns 1 transition time (rise to fall) t t 1515ns refresh period t ref 64 64 ms
hm5264165 series, hm5264805 series, hm5264405 series 45 notes: 1. ac measurement assumes t t = 1 ns. reference level for timing of input signals is 1.4 v. 2. access time is measured at 1.4 v. load condition is cl = 50 pf with current source. 3. t lz (max) defines the time at which the outputs achieves the low impedance state. 4. t hz (max) defines the time at which the outputs achieves the high impedance state. 5. t ces define cke setup time to clk rising edge except power down exit command. test conditions input and output timing reference levels: 1.4 v input waveform and output load: see following figures t t 2.8 v v ss input 80% 20% t t 50 w +1.4 v i/o cl
hm5264165 series, hm5264805 series, hm5264405 series 46 relationship between frequency and minimum latency hm5264165/hm5264805/hm5264405 parameter -80 -10 frequency (mhz) 125 83 100 66 t ck (ns) symbol 8 12 10 15 notes active command to column command (same bank) l rcd 32321 active command to active command (same bank) l rc 9696= [l ras + l rp ] 1 active command to precharge command (same bank) l ras 64641 precharge command to active command (same bank) l rp 32321 write recovery or data-in to precharge command (same bank) l dpl 21211 active command to active command (different bank) l rrd 22221 self refresh exit time l srex 22222 last data in to active command (auto precharge, same bank) l apw 5353= [l dpl + l rp ] self refresh exit to command input l sec 9696= [l rc ] 3 precharge command to high impedance ( cas latency = 2) l hzp 2 2 ( cas latency = 3) l hzp 3333 last data out to active command (auto precharge) (same bank) l apr 1111 last data out to precharge (early precharge) ( cas latency = 2) l ep C1C1 ( cas latency = 3) l ep C2 C2 C2 C2 column command to column command l ccd 1111 write command to data in latency l wcd 0000 dqm to data in l did 0000 dqm to data out l dod 2222 cke to clk disable l cle 1111 register set to active command l rsa 1111 cs to command disable l cdd 0000 power down exit to command input l pec 1111
hm5264165 series, hm5264805 series, hm5264405 series 47 hm5264165/hm5264805/hm5264405 parameter -80 -10 frequency (mhz) 125 83 100 66 t ck (ns) symbol 8 12 10 15 notes burst stop to output valid data hold ( cas latency = 2) l bsr 1 1 ( cas latency = 3) l bsr 2222 burst stop to output high impedance ( cas latency = 2) l bsh 2 2 ( cas latency = 3) l bsh 3333 burst stop to write data ignore l bsw 0000 notes: 1. l rcd to l rrd are recommended value. 2. be valid [dsel] or [nop] at next command of self refresh exit. 3. except [dsel] and [nop]
hm5264165 series, hm5264805 series, hm5264405 series 48 timing waveforms read cycle bank 0 active bank 0 read bank 0 precharge clk cke cs t ras t rcd t ch t cs ras cas we bs a10 address dqm, dqmu/dqml dq (input) dq (output) t ch t cs t ckh t t ck t ac t ac ckl t ac t oh t oh t oh t oh t rp t rc cas latency = 2 burst length = 4 bank 0 access = v or v t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as t ch t cs t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as t ac t lz v ih ih il t hz
hm5264165 series, hm5264805 series, hm5264405 series 49 write cycle clk cke cs t ras t rcd ras cas we bs a10 address dq (input) dq (output) t ch t cs t ckh t t ck t dh t dh ckl t dh t dh t ds t ds t ds t ds t rp t rc t dpl bank 0 write t ch t cs bank 0 active bank 0 precharge t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ch t cs t ah t as t ah t as t ah t as t ah t as t ah t as t ah t as t ch t cs t ah t as t ch t cs t ch t cs t ch t cs t ah t as t ch t cs t ah t as t ch t cs t ch t cs t ch t cs t ah t as t ah t as v ih cas latency = 2 burst length = 4 bank 0 access = v or v ih il dqm, dqmu/dqml
hm5264165 series, hm5264805 series, hm5264405 series 50 mode register set cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 clk cke cs ras cas we bs address dqm, dqmu/dqml dq (input) dq (output) high-z b b+3 b b?1 b?2 b?3 l valid c: b rsa code l rcd l rp precharge if needed mode register set bank 3 active bank 3 read r: b c: b output mask v ih l = 3 cas latency = 3 burst length = 4 = v or v ih il rcd read cycle/write cycle 0 1 2 3 4 5 6 7 8 9 1011121314151617181920 r:a c:a r:b c:b c:b' c:b" a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3 cke ras cs cas we address dqm, dqmu/dqml dq (output) dq (input) clk bs r:a c:a r:b c:b c:b' c:b" a a+1 a+2 a+3 b b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3 bank 0 active bank 0 read bank 3 active bank 3 read bank 3 read bank 3 read bank 0 precharge bank 3 precharge bank 0 active bank 0 write bank 3 active bank 3 write bank 3 write bank 3 write bank 0 precharge bank 3 precharge cke ras cs cas we address dqm, dqmu/dqml dq (input) dq (output) bs high-z high-z v ih v ih read cycle ras - cas delay = 3 cas latency = 3 burst length = 4 = v or v ih il write cycle ras - cas delay = 3 cas latency = 3 burst length = 4 = v or v ih il
hm5264165 series, hm5264805 series, hm5264405 series 51 read/single write cycle 0 1 2 3 4 5 6 7 8 9 1011121314151617181920 r:a c:a r:b c:a' r:a c:a c:a a a a a bank 0 active bank 0 read bank 3 active bank 0 write bank 0 precharge bank 3 precharge bank 0 active bank 0 read bank 0 write bank 0 precharge r:b bank 3 active c:a bank 0 read a a+1 a+2 a+3 bank 0 write bank 0 write cke ras cs cas we address dqm, dqmu/dqml dq (input) dq (output) clk bs cke ras cs cas we address dqm, dqmu/dqml bs c:b bc a+1 a+3 a+1 a+2 a+3 c:c v ih v ih read/single write ras - cas delay = 3 cas latency = 3 burst length = 4 = v or v ih il dq (input) dq (output)
hm5264165 series, hm5264805 series, hm5264405 series 52 read/burst write cycle 0 1 2 3 4 5 6 7 8 9 1011121314151617181920 r:a c:a r:b c:a' r:a c:a c:a a a+1 a+2 a+3 a+1 a a+1 a+2 a+3 bank 0 active bank 0 read bank 0 write bank 0 precharge r:b bank 3 active cke ras cs cas we address dqm, dqmu/dqml clk bs cke ras cs cas we address dqm, dqmu/dqml bs a+1 a+2 a+3 a a+3 a bank 0 active bank 0 read bank 3 active clock suspend bank 0 write bank 0 precharge bank 3 precharge v ih read/burst write ras - cas delay = 3 cas latency = 3 burst length = 4 = v or v ih il dq (input) dq (output) dq (input) dq (output)
hm5264165 series, hm5264805 series, hm5264405 series 53 full page read/write cycle high-z r:a c:a r:b r:a c:a r:b high-z bank 0 active bank 0 read bank 3 active burst stop bank 3 precharge bank 0 active bank 0 write bank 3 active burst stop bank 3 precharge cke ras cs cas we address dqm, dqmu/dqml dq (input) dq (output) clk bs cke ras cs cas we address dqm, dqmu/dqml bs v ih v ih a a+1 a+2 a+3 read cycle ras-cas delay = 3 cas latency = 3 burst length = full page = v or v ih il write cycle ras-cas delay = 3 cas latency = 3 burst length = full page = v or v ih il a a+1 a+2 a+3 a+6 a+5 a+4 dq (input) dq (output)
hm5264165 series, hm5264805 series, hm5264405 series 54 auto refresh cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 clk cke cs cas we bs address dqm, dqmu/dqml dq (input) dq (output) high-z rp precharge if needed auto refresh active bank 0 t rc t rc t auto refresh read bank 0 r:a c:a a10=1 ras a a+1 v ih refresh cycle and read cycle ras - cas delay = 2 cas latency = 2 burst length = 4 = v or v ih il self refresh cycle clk cke cs ras cas we bs address dqm, dqmu/dqml dq (input) dq (output) precharge command if needed self refresh entry command auto refresh self refresh exit ignore command or no operation cke low a10=1 rc t rp t self refresh cycle ras - cas delay = 3 cas latency = 3 burst length = 4 = v or v ih il high-z next clock enable rc t next clock enable l srex self refresh entry command
hm5264165 series, hm5264805 series, hm5264405 series 55 clock suspend mode 0123 4 5 6 7 8 9 1011121314151617181920 r:a c:a r:b a a+1 a+2 a+3 b b+1 b+2 r:a c:a r:b c:b a a+1 a+2 b b+1 b+2 b+3 c:b bank0 active active clock suspend start active clock supend end bank0 read bank3 active read suspend start read suspend end bank0 precharge bank3 read earliest bank3 precharge bank0 write bank0 active active clock suspend start active clock suspend end bank3 active write suspend start write suspend end bank3 write bank0 precharge earliest bank3 precharge b+3 cke ras cs cas we address dqm, dqmu/dqml clk bs cke ras cs cas we address dqm, dqmu/dqml bs a+3 high-z high-z t ces t ceh t ces read cycle ras - cas delay = 2 cas latency = 2 burst length = 4 = v or v ih il write cycle ras - cas delay = 2 cas latency = 2 burst length = 4 = v or v ih il dq (output) dq (input) dq (output) dq (input)
hm5264165 series, hm5264805 series, hm5264405 series 56 power down mode clk cke cs ras cas we bs address dqm, dqmu/dqml dq (input) dq (output) precharge command if needed power down entry active bank 0 power down mode exit cke low r: a a10=1 rp t high-z power down cycle ras - cas delay = 3 cas latency = 3 burst length = 4 = v or v ih il initialization sequence 78910 52 53 54 48 49 50 51 auto refresh bank active if needed rc t rc t auto refresh valid 0 123456 clk cke cs ras cas we address dqm, dqmu/dqml dq t valid rsa t rp all banks precharge mode register set v ih v ih 55 high-z code
hm5264165 series, hm5264805 series, hm5264405 series 57 package dimensions hm5264165tt/hm5264805tt/hm5264405tt series (ttp-54d) 0.13 m 0.10 0.80 54 28 127 22.22 22.72 max 1.20 max 10.16 0.13 0.05 11.76 0.20 0 ?5 0.91 max 0.145 0.05 hitachi code jedec eiaj weight (reference value) ttp-54d ? ? 0.53 g 0.28 0.05 0.125 0.04 unit: mm preliminary 0.30 +0.10 ?.05 dimension including the plating thickness base material dimension 0.50 0.10 0.68 0.80
hm5264165 series, hm5264805 series, hm5264405 series 58 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachis or any third partys patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachis sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachis sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 2000 sierra point parkway brisbane, ca 94005-1897 tel: <1> (800) 285-1601 fax: <1> (303) 297-0447 for further information write to:
hm5264165 series, hm5264805 series, hm5264405 series 59 revision record rev. date contents of modification drawn by approved by 0.0 may. 30, 1996 initial issue h. miyashita k. sato 0.1 nov. 29, 1996 correct errors operation of hm5264165/5264805/5264405 series change of description for read/write operation and full-page burst stop dc characteristics (hm5264165) i cc3 max: 7/7/7 ma to 12/12/12 ma i cc4 (cl = 2) max: 100/85/65 ma to 150/130/100 ma i cc4 (cl = 3) max: 150/125/100 ma to 200/180/140 ma i cc4 test conditions: bl = 4 to bl = 8 i cc6 max: 2/2/2 ma to 3/3/3 ma addition of i cc5 test conditions: address = v il or v ih fixed addition of notes 8 and 9 dc characteristics (hm5264805) i cc2 max: 40/35/30 ma to 50/45/35 ma i cc3 max: 7/7/7 ma to 12/12/12 ma i cc3 max: 45/40/35 ma to 55/50/40 ma i cc4 (cl = 2) max: 100/85/65 ma to 150/130/100 ma i cc4 (cl = 3) max: 150/125/100 ma to 200/180/140 ma i cc4 test conditions: bl = 4 to bl = 8 i cc6 max: 2/2/2 ma to 3/3/3 ma addition of i cc5 test conditions: address = v il or v ih fixed addition of notes 8 and 9 dc characteristics (hm5264405) i cc3 max: 7/7/7 ma to 12/12/12 ma i cc4 (cl = 2) max: 100/85/65 ma to 140/120/95 ma i cc4 (cl = 3) max: 150/125/100 ma to 190/170/135 ma i cc4 test conditions: bl = 4 to bl = 8 i cc5 max: 130/110/85 ma to 150/125/100 ma i cc6 max: 2/2/2 ma to 3/3/3 ma addition of i cc5 test conditions: address = v il or v ih fixed addition of notes 8 and 9 ac characteristics t ac (cl = 2) max: 12/15/17 ns 9/13/15 ns a. kumata k. sato 0.2 dec. 17, 1996 correct errors change of description for command truth table change of figures for operation of hm5264165, hm5264805, hm5264405 series change of description for self-refresh recommended dc operating conditions change of notes 2 ac characteristics change of symbol: t rwl to t dpl timing waveforms change of full page read/write cycle a. kumata k. sato
hm5264165 series, hm5264805 series, hm5264405 series 60 rev. date contents of modification drawn by approved by 0.3 aug. 18, 1997 addition of hm5264165/5264805/5264405-8 deletion of hm5264165/5264805/5264405-12/15 change of figures for burst length, burst write and read with auto-precharge absolute maximum ratings v t : C1.0 to +4.6 v to C0.5 to v cc + 0.5 ( 4.6 (max)) v cc : C1.0 to +4.6 v to C0.5 to +4.6 v dc characteristics deletion of i cc2 and i cc3 addition of i cc2p max: 3/3 ma addition of i cc2ps max: 2/2 ma addition of i cc2n max: 20/20 ma addition of i cc2ns max: 9/9 ma addition of i cc3p max: 6/6 ma addition of i cc3ps max: 5/5 ma addition of i cc3n max: 30/30 ma addition of i cc3ns max: 20/20 ma i cc5 (cl = 2) max: 150/125/100 ma to 85/60 ma i cc5 (cl = 3) max: 150/125/100 ma to 140/110 ma i cc6 max: 3/3/3 ma to 2/2 ma dc characteristics (hm5264165) i cc1 (cl = 2) max: 130/105/85 ma to 75/60 ma i cc1 (cl = 3) max: 130/105/85 ma to 95/80 ma i cc4 (cl = 2) max: 150/130/100 ma to 145/120 ma i cc4 (cl = 3) max: 200/180/140 ma to 205/170 ma dc characteristics (hm5264805) i cc1 (cl = 2) max: 130/105/85 ma to 65/50 ma i cc1 (cl = 3) max: 130/105/85 ma to 85/70 ma i cc4 (cl = 2) max: 150/130/100 ma to 95/70 ma i cc4 (cl = 3) max: 200/180/140 ma to 155/120 ma dc characteristics (hm5264405) i cc1 (cl = 2) max: 110/95/75 ma to 60/50 ma i cc1 (cl = 3) max: 110/95/75 ma to 80/70 ma i cc4 (cl = 2) max: 140/120/95 ma to 90/70 ma i cc4 (cl = 3) max: 190/170/135 ma to 145/110 ma change of notes 3 to notes 8 ac characteristics t oh min: 3/3/3 ns to 2.5/2.5 ns t. takemura s. ishikawa
hm5264165 series, hm5264805 series, hm5264405 series 61 rev. date contents of modification drawn by approved by 0.4 nov. 7, 1997 addition of l-version operation of hm5264165, hm5264805, hm5264405 change of figures for write with auto-precharge change of description for read operation and dqm control (hm5264805/hm5264405) recommended dc operating conditions change of notes 2 dc characteristics i cc3p , i cc3n test conditions: deletion of dq = high-z i cc5 max: 135/105 ma to 140/110 ma addition of i cc6 (l-version): tbd/tbd m a change of notes 3 and 4 dc characteristics (hm5264165) i cc1 (cl = 3) max: 90/75 ma to 95/80 ma dc characteristics (hm5264805) i cc1 (cl = 3) max: 80/65 ma to 85/70 ma i cc4 (cl = 2) max: 95/70 ma to 115/90 ma dc characteristics (hm5264405) i cc1 (cl = 3) max: 75/65 ma to 80/70 ma i cc4 (cl = 2) max: 90/70 ma to 105/80 ma ac characteristics t ac (cl = 2) max: 8/9 ns to 8/8 ns relationship between frequency and minimum latency change of notes 2 s. kawano s. ishikawa 0.5 dec. 5, 1997 change of figure for mode register configuration addition of description for a7 dc characteristics i li min: C10 m a to C1 m a i li max: 10 m a to 1 m a i lo min: C10 m a to C1.5 m a i lo max: 10 m a to 1.5 m a addition of notes 5 dc characteristics (hm5264165) i cc1 (cl = 3) max: 95/80 ma to 95/ ma i cc4 (cl = 3) max: 205/170 ma to 205/ ma dc characteristics (hm5264805) i cc1 (cl = 3) max: 85/70 ma to 85/ ma i cc4 (cl = 3) max: 155/120 ma to 155/ ma dc characteristics (hm5264405) i cc1 (cl = 3) max: 80/70 ma to 80/ ma i cc4 (cl = 3) max: 145/110 ma to 145/ ma ac characteristics t ck (cl = 3) min: 8/10 ns to 8/ ns t ac (cl = 3) max: 6/8 ns to 6/ ns relationship between frequency and minimum latency deletion of 100 mhz specifications l hzp , l bsh (cl = 3): 3/3/3/3 to 3/3/ l ep (cl = 3): C2/C2/C2/C2 to C2/C2/ l bsr (cl = 3): 2/2/2/2 to 2/2/ capacitance addition of notes 2 m. sakamoto s. ishikawa
hm5264165 series, hm5264805 series, hm5264405 series 62 rev. date contents of modification drawn by approved by 0.6 jan. 23, 1998 addition of cl = 3 for hm5264165/5264805/5264405-10 change of figure for mode register configuration operation of hm5264165, hm5264805, hm5264405 change of figures for write with auto-precharge change of description for read operation and power-up sequence dc characteristics (hm5264165) i cc1 (cl = 3) max: 95/ ma to 95/80 ma i cc4 (cl = 3) max: 205/ ma to 205/170 ma dc characteristics (hm5264805) i cc1 (cl = 3) max: 85/ ma to 85/70 ma i cc4 (cl = 3) max: 155/ ma to 155/120 ma dc characteristics (hm5264405) i cc1 (cl = 3) max: 80/ ma to 80/70 ma i cc4 (cl = 3) max: 145/ ma to 145/110 ma ac characteristics t ck (cl = 3) min: 8/ ns to 8/10 ns t ac (cl = 3) max: 6/8 ns to 6/8 ns relationship between frequency and minimum latency addition of 100 mhz specifications l hzp , l bsh (cl = 3): 3/3/ to 3/3/3/3 l ep (cl = 3): C2/C2/ to C2/C2/C2/C2 l bsr (cl = 3): 2/2/ to 2/2/2/2 timing waveforms: change of title power up sequence to initialization sequence m. sakamoto y. matsuno 1.0 jul. 1, 1998 change of word: cycle to clock : a12/a13 to bs (in figures and timing) pin function change of description for cke and dqm, dqmu/dqml command truth table change of description for burst stop in full page unification of description for dqm truth table auto precharge: change of figure for burst read command interval change of figures for auto precharge write to read command interval(1) and (2) change of description for read command to precharge command interval: to output all data change of description for self-refresh, power-up sequence and initialization sequence change of figures for power-up sequence recommended dc operating conditions change of title: to dc operating conditions addition of notes 2 and 3 dc characteristics i cc6 (l-version) max: tbd to 400 m a relationship between frequency and minimum latency correct error: l dpl : 2/1/1/1 to 2/1/2/1 change of notes 2 and addition of notes 3 timing waveforms: change of read/burst write cycle

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