View 79RC32438-233BB_2603352.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

november 2002 2975 stender way, santa clara, california 95054 telephone: (800) 345-7015 ? twx: 910-338-2070 ? fax: (408) 330-1748 printed in u.s.a. ?2002 integrated device technology, inc. idt ? interprise ? 79rc32438 integrated communications processor user reference manual
general disclaimer integrated device technology, inc. reserves the right to make changes to its products or specifications at any time, without no tice, in order to improve design or performance and to supply the best possible product. id t does not assume any responsibility for us e of any circuitry described other than t he circuitry embodied in an idt product. the company makes no representations that circuitry described herein is free from pat ent infringement or other rights of third part ies which may result from its use. no license is granted by implication or otherwise under any patent, patent rights or other rights, of integrated device technology, inc. code disclaimer code examples provided by idt are for ill ustrative purposes only and should not be relied upon for developing applications. any use of the code examples below is completely at your own risk. idt makes no representations or warranties of any kind concerning the noninfringement, quality, safety or su itability of the code, either express or implied, including without limi tation any implied warranties of merchantability, fitness for a p articu- lar purpose, or non-infringement. further, idt makes no represen tations or warranties as to the truth, accuracy or completeness of any statements, information or materials concerning code exam ples contained in any idt publication or public disclosure or that is contained on any idt internet site. in no event will idt be liable for any direct, consequential, incidental, indirect, punitive or special damages, however they may arise, and even if idt has been previously advised about the possibility of such damages. th e code examples also may be subject to united stat es export control laws and may be subject to the export or import laws of other coun tries and it is your res ponsibility to comply with any applicable laws or regulations. life support policy integrated device technology's products are not authorized for us e as critical components in life support devices or systems un less a specific written agreement pertaining to such intended use is executed between t he manufacturer and an officer of idt. 1. life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) supp ort or sustain life and whose failure to perform, when properly used in accordance with instru ctions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any components of a life support device or system whose failure to per form can be reasonably expecte d to cause the failure of the life support device or system, or to affect its safety or effectiveness. the idt logo is a registered trademark of integrated device tech nology, inc. idt, interprise, ri scontroller, riscore, rc3041, r c3052, rc3081, rc32134, rc32332, rc32333, rc32334, rc32355, rc32351, rc32438, rc32364, rc36100, rc4700, rc4640, rc64145, rc4650, rc5000, rc64474, rc64475 are trademarks of integrated device techn ology, inc. . powering what's next and enabling a digitally connected world are se rvice marks of integrated device technology, inc. q, qsi, s ynchroswitch and turboclock are regist ered trademarks of quality semiconduc- tor, a wholly-owned subsidiary of integrated device technology, inc.
notes 79rc32438 user reference manual i november 4, 2002 about this manual introduction this user reference manual includes hardware and software information on the rc32438, a high perfor- mance integrated processor that combines a high performance 32-bit cpu core with system logic to provide direct connection to boot memory, main memo ry, i/o, and pci. it also includes on-chip peripherals such as dma channels, reset circuitry, interrupts, ti mers, and uarts. each chapter is designed to cover the following topics: ? high level feature summary of the specific module ? summary of the register set asso ciates with a specific module ? outline of the operation of the module ? detailed register description. finding additional information information not included in this manual such as me chanicals, package pin-outs, and electrical character- istics can be found in the data sheet for this devic e, which is available from the idt website (www.idt.com) as well as through your loca l idt sales representative. content summary chapter 1, ?rc32438 device overview,? provides a complete introd uction to the performance capabil- ities of the rc32438. included in this chapter is a summa ry of features for the device as well as a system block diagram and inter nal register maps. chapter 2, ?mips32 4kc processor core,? provides basic information on the architecture and opera- tion of the 4kc? processor core from mi ps? technologies as it applies to the rc32438. chapter 3, ?clocking and initialization,? discusses the reset initialization sequence required by the rc32438 and provides information on boot vector settings and clock signals. chapter 4, ?system integrity functions,? discusses system integrity f unctions, including the registers that log system activity and that can be used to i ndicate the source of har dware or software errors. chapter 5, ?bus arbitration,? describes the internal arbitrat ion mechanism used among the various on-chip modules. the chapter also describes the bus protocol used by an external bus master to gain ownership of the memory and peripheral bus. chapter 6, ?device controller,? describes the operation of the dev ice controller, including registers and device transactions, which prov ides a glueless interface to srams, roms/proms/eeproms, dual port memories, and other devices. chapter 7, ?double data rate (ddr) controller,? describes the features , functions, and operation of the ddr controller, including a description of the registers. chapter 8, ?interrupt controller,? provides information about the interrupt controller and interrupt source descriptions. chapter 9, ?dma controller,? describes the dma controller, channel s, descriptors, registers, transac- tions, and operations. chapter 10, ?pci bus interface,? describes the features, functi ons, and operations of the pci bus interface on the rc32438. chapter 11, ?ethernet interfaces,? discusses the two ethernet interfaces on the rc32438 which can be used in applications such as soho routers or high speed modems for pcs.
idt about this manual documentation conventions and definitions 79rc32438 user reference manual ii november 4, 2002 notes chapter 12, ?general purpose i/o controller,? describes this controller and how it is configured to operate as a general purpose i/o or as an alternate function. chapter 13, ?uart controller,? provides information about the two separate uarts within the rc32438, including the uart registers. chapter 14, ?counter timers,? describes the three general purpos e 32-bit counter/timers on the rc32438. chapter 15, ?i 2 c bus interface,? describes the standard i 2 c bus interface, supporting both master and slave operations, that is implemented on the rc32438. chapter 16, ?serial peripheral interface,? describes the spi master inte rface which uses three signals to connect to low-cost spi peripherals and memory. chapter 17, ?on-chip memory,? describes the operation and support provided by on-chip memory for memory read and write operations on the rc32438. chapter 18, ?debugging and performance monitoring,? discusses the three different debugging features available on the rc32438: ipbus monitor, event monitor, and debug pins. chapter 19, ?jtag boundary scan,? discusses an enhanced jtag interface for low-cost in-circuit emulation. this discussion includes a system logic tap controller, signal definitions, a test data register, an instruction register, and usage considerations. chapter 20,?ejtag system,? describes the ejtag?s features, it s debug control register, tap regis- ters, ejtag probe, hardware breakpoi nts, and other related topics. documentation conventions and definitions throughout this manual the following conventions and terms are used: ? to avoid confusion when dealing wit h a mixture of ?active-low? and ?active-high? signals, the terms assertion and negation are used. the term assert or assertion is used to indicate that a signal is active or true, independent of whether that level is represented by a high or low voltage. the term negate or negation is used to indicate t hat a signal is inactive or false. ? to define the active polarity of a signal, a suff ix will be used. signals ending with an ?n? should be interpreted as being active, or asserted, when at a logic zero (low) level. all other signals (including clocks, buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level. ? to define buses, the most significant bit (msb) will be on the left and least significant bit (lsb) will be on the right. no leading zeros will be included. ? to represent numerical values, ei ther decimal, binary, or hexadecim al formats will be used. the binary format is as follows: 0b ddd, where ?d? represents either 0 or 1; the hexadecimal format is as follows: 0xdd, where ?d? represents the hexadecimal digit( s); otherwise, it is decimal. ? unless otherwise denoted, a byte will refer to an 8- bit quantity. a halfword will refer to a 16-bit quan- tity. a triple-byte will refer to a 24-bit quantity. a word will refer to a 32-bit quantity, and a double or double word will refer to a 64-bit quantity. ? a bit is set when its value is 0b1. a bit is cleared when its value is 0b0. ? the compressed notation abc[x|y|z]d refers to abcxd, abcyd, and abczd. ? the compressed notation abc[x..y ]d refers to abcxd, abc( x+1)d, abc(x+2)d, ... abcyd. ? in words, bit 31 is always the most significant bit and bit 0 is the least signifi cant bit. in halfwords, bit 15 is always the most significant bit and bit 0 is the least significant bit. in by tes, bit 7 is always the most significant bit and bit 0 is the least significant bit. ? the ordering of bytes within words is referred to as either ?big endian? or ?little endian.? big endian systems label byte zero as the mo st significant (leftmost) byte of a word. little endian systems label byte zero as the least signific ant (rightmost) byte of a word.
idt about this manual signal terminology 79rc32438 user reference manual iii november 4, 2002 notes figure 1 example of byte orde ring for ?big endian? or ?little endian? system definition ? a read-only: register, bit, or field is one which can be read but not modified ? a sticky bit is a bit which, once set by hardware, remains set until a zero is written to it. writing a one to a sticky has no effect on its value. ? a zero field in a register, denoted as ?0? in register figures, must be written with a value of zero and returns a value of zero when read. signal terminology throughout this manual, when describing signal trans itions, the following terminology is used: ? rising edge indicates a low-to-high (0 to 1) transition. ? falling edge indicates a high-to-l ow (1 to 0) transition. these terms are illustrated in figure 2. figure 2 signal transitions revision history november 4, 2002 : initial publication. 0 1 2 3 bit 0 bit 31 address of bytes within words: big endian 3 2 1 0 bit 0 bit 31 address of bytes within words: little endian 1 2 3 4 high-to-low transition low-to-high transition single clock cycle
idt about this manual revision history 79rc32438 user reference manual iv november 4, 2002 notes
notes 79rc32438 user reference manual i november 4, 2002 table of contents about this manual introduction .......................................................................................................................... i content summary ................................................................................................................. i documentation conventions and definitions ........................................................................... ii signal terminology .............................................................................................................. iii revision history .................................................................................................................. iii 1 rc32438 device overview introduction ................................................................................................................... ...............1-1 key features ................................................................................................................... ............1-1 system block diagram ........................................................................................................... .....1-2 additional resources........................................................................................................... ........1-2 feature list summary ........................................................................................................... ......1-2 system identification.......................................................................................................... ..........1-5 logic diagram ? rc32438........................................................................................................ .1-7 pin characteristics............................................................................................................ ...........1-8 pin description................................................................................................................ ........... 1-11 default memory map ............................................................................................................. ....1-20 rc32438 internal register map ................................................................................................1- 21 2 mips32 4kc processor core introduction ................................................................................................................... ...............2-1 functional overview ........................................................................................................... ........2-1 features....................................................................................................................... ................2-1 functional overview ............................................................................................................ ........2-3 blocks......................................................................................................................... ........2-3 pipeline description ........................................................................................................... ..........2-6 instruction cache miss .......................................................................................................2- 8 multiply/divide operations..................................................................................................2-9 mdu pipeline ................................................................................................................... ..2-9 branch delay................................................................................................................... .2-14 data bypassing ................................................................................................................2 -14 interlock handling............................................................................................................. 2-16 slip conditions ................................................................................................................ .2-17 instruction interlocks ........................................................................................................2 -18 instruction hazards ..........................................................................................................2- 19 memory management.............................................................................................................. ..2-20 modes of operation..........................................................................................................2-2 1 translation lookaside buffer............................................................................................2-27 virtual to physical address translation ............................................................................2-31
idt table of contents 79rc32438 user reference manual ii november 4, 2002 notes system control coprocessor ...........................................................................................2-35 exceptions ..................................................................................................................... ............2-35 exception conditions .......................................................................................................2-35 exception priority ............................................................................................................. 2-35 exception vector locations..............................................................................................2-36 general exception processing.........................................................................................2-38 debug exception processing ...........................................................................................2-39 exceptions..................................................................................................................... ...2-39 exception handling and servicing flowcharts .................................................................2-49 cp0 registers.................................................................................................................. ..........2-54 cp0 register summary ...................................................................................................2-54 cp0 registers .................................................................................................................. 2-56 hardware and software initialization .........................................................................................2- 79 hardware initialized processor state ...............................................................................2-79 software initialized processor state ................................................................................2-80 caches......................................................................................................................... ..............2-80 cache protocols...............................................................................................................2 -81 instruction cache .............................................................................................................2 -82 data cache ..................................................................................................................... .2-82 memory coherence issues ..............................................................................................2-83 power management............................................................................................................... ....2-83 register-controlled power management .........................................................................2-83 instruction-controlled power management......................................................................2-83 instruction set................................................................................................................ ............2-84 load and store instructions .............................................................................................2-84 computational instructions...............................................................................................2-85 control instructions ..........................................................................................................2 -86 coprocessor instructions .................................................................................................2-86 enhancements to the mips architecture .........................................................................2-86 processor core instructions .................................................................................................... ..2-87 3 clocking and initialization introduction ................................................................................................................... ...............3-1 block diagram .................................................................................................................. ...........3-1 clocking overview .............................................................................................................. .........3-1 reset register description ..................................................................................................... .....3-3 reset and initialization....................................................................................................... ..........3-3 cold reset ..................................................................................................................... ....3-3 boot configuration vector ..................................................................................................3-4 reset/initialization registers ................................................................................................. ......3-6 boot configuration vector register....................................................................................3-6 warm reset ..................................................................................................................... ..3-6 reset register ................................................................................................................. ..3-8 4 system integrity functions introduction ................................................................................................................... ...............4-1 features....................................................................................................................... ................4-1 functional overview ............................................................................................................ ........4-1
idt table of contents 79rc32438 user reference manual iii november 4, 2002 notes system integrity register description.......................................................................................... 4-1 system integrity registers..................................................................................................... ......4-2 error control and status register ......................................................................................4-2 cpu error address register ..............................................................................................4-4 address space monitor .......................................................................................................... .....4-4 watchdog timer................................................................................................................. ..........4-5 watchdog timer count register ........................................................................................4-6 watchdog timer compare register...................................................................................4-6 watchdog timer control register ......................................................................................4-7 ipbus slave acknowledge errors ................................................................................................4 -7 5 bus arbitration introduction ................................................................................................................... ...............5-1 functional overview ............................................................................................................ ........5-1 ipbus register description..................................................................................................... .....5-2 pmbus arbitration register description ......................................................................................5-2 theory of operation............................................................................................................ .........5-3 example ipbus arbiter configurations...............................................................................5-6 ipbus registers ................................................................................................................ ...........5-9 ipbus arbiter control register ...........................................................................................5-9 ipbus arbiter priority conf iguration register ...................................................................5-10 ipbus arbiter bus master configuration register ............................................................ 5-11 ipbus idle transaction cycl e count register ..................................................................5-12 pmbus arbitration.............................................................................................................. ........5-12 ipbus idle..................................................................................................................... ....5-12 ipbus active................................................................................................................... ..5-12 sneak transactions..........................................................................................................5-1 2 bus parking.................................................................................................................... ..5-13 pmbus registers ................................................................................................................ .......5-13 pmbus arbiter processor pr iority register ......................................................................5-13 pmbus arbiter sneak access control register ...............................................................5-13 memory and peripheral bus arbitration.....................................................................................5-14 6 device controller introduction ................................................................................................................... ...............6-1 features....................................................................................................................... ................6-1 device controller regist er description........................................................................................6 -1 theory of operation............................................................................................................ .........6-2 device control registers ....................................................................................................... ......6-5 device [0..5] base register................................................................................................6-5 device [0..5] mask register ...............................................................................................6-5 device [0..5] control register ............................................................................................6-6 device [0..5] timing control register.................................................................................6-8 memory and peripheral bus transaction timer ..........................................................................6-9 bus transaction timer control and status register ........................................................6-10 bus transaction timer compare register .......................................................................6-10 bus transaction timer address register......................................................................... 6-11
idt table of contents 79rc32438 user reference manual iv november 4, 2002 notes device read transaction........................................................................................................ ... 6-11 burst device read transaction .................................................................................................6 -14 device write transaction....................................................................................................... ....6-15 burst device write transaction ................................................................................................. 6-17 decoupled cpu device transactions........................................................................................6-18 device decoupled access control and status register ..................................................6-19 device decoupled access address register...................................................................6-20 device decoupled access data register.........................................................................6-20 7 ddr controller introduction ................................................................................................................... ...............7-1 features....................................................................................................................... ................7-1 additional resources........................................................................................................... ........7-1 ddr controller register description ...........................................................................................7 -1 theory of operation............................................................................................................ .........7-1 ddr address multiplexing scheme ...................................................................................7-3 ddr command encoding..................................................................................................7-5 ddr registers.................................................................................................................. ...........7-5 ddr control register ........................................................................................................7-5 ddr read data capture register .....................................................................................7-9 ddr address mapping .................................................................................................... 7-11 ddr [0|1] base register ..................................................................................................7-12 ddr [0|1] mask register..................................................................................................7-13 ddr 0 alternate base register .......................................................................................7-13 ddr 0 alternate mask register .......................................................................................7-14 ddr 0 alternate mapping register..................................................................................7-14 ddr data bus multiplexing..............................................................................................7-14 ddr initialization ............................................................................................................. ..........7-16 ddr custom transaction register ..................................................................................7-17 ddr refresh timer .............................................................................................................. .....7-18 refresh timer count register..........................................................................................7-18 refresh timer compare register ....................................................................................7-19 refresh timer control register........................................................................................7-19 ddr read transaction........................................................................................................... ...7-20 ddr write transaction .......................................................................................................... ....7-21 ddr refresh transaction........................................................................................................ ..7-23 ddr custom transaction......................................................................................................... .7-24 example of ddr sdram initialization ......................................................................................7-25 8 interrupt controller introduction ................................................................................................................... ...............8-1 features....................................................................................................................... ................8-1 block diagram .................................................................................................................. ...........8-2 interrupt controller register description .....................................................................................8 -2 interrupt pending [2..6] register ........................................................................................8-3 interrupt test [2..6] register...............................................................................................8- 3 interrupt mask [2..6] register.............................................................................................8-4
idt table of contents 79rc32438 user reference manual v november 4, 2002 notes interrupt status description ................................................................................................... ......8-4 non-maskable interrupts ........................................................................................................ .....8-6 non-maskable interrupt pin status register......................................................................8-7 9 dma controller introduction ................................................................................................................... ...............9-1 features....................................................................................................................... ................9-1 dma registers.................................................................................................................. ...........9-1 data flow within the rc32438 ................................................................................................... .9-3 the ipbus?..................................................................................................................... ..9-3 4kc core as bus master ....................................................................................................9-3 dma controller................................................................................................................. ..9-4 no alignment restrictions..................................................................................................9-4 data flow using the dma controller .................................................................................9-5 memory-to-memory transfer..............................................................................................9-5 dma channels................................................................................................................... ..........9-6 internal dma operation ......................................................................................................... ......9-7 dma descriptor register....................................................................................................9-8 dma registers .................................................................................................................. .9-9 dma stopping conditions ..................................................................................................9-9 dma request event.........................................................................................................9-10 dma descriptor list and chaining ...................................................................................9-10 dma [0..9] control register .............................................................................................9-12 dma [0..9] status register...............................................................................................9-13 dma [0..9] status mask register .....................................................................................9-14 dma [0..9] descriptor pointer register ............................................................................9-15 dma [0..9] next descriptor pointer register....................................................................9-15 external dma operations ........................................................................................................ ..9-16 device control and status field for external dma ..........................................................9-16 device command field for external dma........................................................................9-16 memory to memory dma operations ........................................................................................9-19 examples ....................................................................................................................... ............9-20 10 pci bus interface introduction ................................................................................................................... .............10-1 features....................................................................................................................... ..............10-1 use of decoupled pci transactions..........................................................................................10-2 ipbus access................................................................................................................... ..........10-2 pci register description ....................................................................................................... ....10-3 pci control register ........................................................................................................10- 4 pci status register..........................................................................................................10 -7 pci status mask register ..............................................................................................10-10 reset .......................................................................................................................... .............10-13 disabled mode.................................................................................................................. .......10-14 pci host mode .................................................................................................................. ......10-14 reset and initialization ...................................................................................................10-1 4 bus arbitration................................................................................................................ 10-14
idt table of contents 79rc32438 user reference manual vi november 4, 2002 notes interrupts ..................................................................................................................... ...10-15 pci satellite mode ............................................................................................................. ......10-15 reset and initialization ...................................................................................................10-1 5 bus arbitration................................................................................................................ 10-16 interrupts ..................................................................................................................... ...10-17 pci serial eeprom interface .......................................................................................10-17 pci transactions ............................................................................................................... ......10-17 pci master..................................................................................................................... ..........10-18 i/o read....................................................................................................................... ..10-18 i/o write ...................................................................................................................... ...10-19 memory read.................................................................................................................10- 19 memory write .................................................................................................................10 -19 configuration read ........................................................................................................10-19 configuration write.........................................................................................................10- 20 memory read line.........................................................................................................10-21 error handling ...............................................................................................................1 0-21 pci configuration address register ..............................................................................10-22 pci configuration data register....................................................................................10-23 pci local base address [0|1|2|3] register ....................................................................10-23 pci local base address [0|1|2|3] control......................................................................10-24 pci local base address [0|1 |2|3] mapping register .....................................................10-25 decoupled pci master transactions .......................................................................................10-25 pci decoupled access control register........................................................................10-26 pci decoupled access status register.........................................................................10-26 pci decoupled access status register.........................................................................10-27 pci decoupled access da ta register............................................................................10-29 pci master?pci to memory dma (dma channel 8) .............................................................10-29 memory read.................................................................................................................10- 31 memory read multiple ...................................................................................................10-31 memory read line.........................................................................................................10-31 i/o read....................................................................................................................... ..10-31 error handling ...............................................................................................................1 0-31 pci dma channel 8 configuration register ..................................................................10-31 pci master ? memory to pci dma (dma channel 9) ...........................................................10-32 memory write .................................................................................................................10 -34 memory write and invalidate..........................................................................................10-34 i/o write ...................................................................................................................... ...10-34 error handling ...............................................................................................................1 0-34 pci dma channel 9 configuration register ..................................................................10-35 pci target..................................................................................................................... ...........10-35 i/o read....................................................................................................................... ..10-36 i/o write ...................................................................................................................... ...10-37 memory read.................................................................................................................10- 37 memory write .................................................................................................................10 -37 configuration read ........................................................................................................10-37 configuration write.........................................................................................................10- 37 memory read multiple ...................................................................................................10-37 memory read line.........................................................................................................10-38 memory write and invalidate..........................................................................................10-38 error handling ...............................................................................................................1 0-38
idt table of contents 79rc32438 user reference manual vii november 4, 2002 notes pci target control register ...........................................................................................10-38 transaction ordering ........................................................................................................... ....10-39 pci messaging unit ............................................................................................................. ....10-40 pci inbound message [0|1] register .............................................................................10-41 pci outbound message [0|1] register...........................................................................10-41 pci inbound doorbell register ......................................................................................10-42 pci inbound interrupt cause register ...........................................................................10-42 pci inbound interrupt mask register.............................................................................10-43 pci outbound doorbell register....................................................................................10-44 pci outbound interrupt cause register ........................................................................10-44 pci outbound interrupt mask register ..........................................................................10-45 pci configuration registers .................................................................................................... 10-45 vendor id register.........................................................................................................10-4 7 device id register .........................................................................................................10-4 7 command register ........................................................................................................10-47 status register...............................................................................................................1 0-49 device revision id register...........................................................................................10-51 class code register ......................................................................................................10-51 cache line size register...............................................................................................10-51 master latency register ................................................................................................10-52 header type register ....................................................................................................10-52 bist register.................................................................................................................1 0-53 pci base address [0|1|2 |3] register..............................................................................10-53 subsystem vendor id ....................................................................................................10-54 subsystem id register ..................................................................................................10-54 interrupt line register....................................................................................................10-5 5 interrupt pin register .....................................................................................................10-5 5 minimum grant register ................................................................................................10-55 maximum latency register............................................................................................10-56 target ready time-out register ....................................................................................10-56 retry limit register........................................................................................................10- 57 pci base address [0|1|2 |3] control ...............................................................................10-57 pci base address [0|1|2|3] mapping register...............................................................10-59 pci management register.............................................................................................10-60 11 ethernet interfaces introduction ................................................................................................................... ............. 11-1 features....................................................................................................................... .............. 11-1 block diagram .................................................................................................................. ......... 11-1 functional overview ............................................................................................................ ...... 11-1 input and output fifos ......................................................................................................... .... 11-2 ethernet register description.................................................................................................. .. 11-2 ethernet interface control register.................................................................................. 11-5 ethernet fifo transmit threshold register .................................................................... 11-7 address recognition logic ...................................................................................................... .. 11-7 ethernet address recognition control register............................................................... 11-9 ethernet hash table [0|1] register ................................................................................ 11-11 ethernet station address [0|1|2|3] low register ........................................................... 11-11 ethernet station address [0|1|2|3] high register........................................................... 11-12
idt table of contents 79rc32438 user reference manual viii november 4, 2002 notes dma interface.................................................................................................................. ........ 11-12 ethernet input dma operations ..................................................................................... 11-12 ethernet output dma operations .................................................................................. 11-14 ethernet statistics............................................................................................................ ........ 11-16 ethernet receive byte count register .......................................................................... 11-17 ethernet receive packet count register....................................................................... 11-17 ethernet receive undersized pack et count register.................................................... 11-17 ethernet receive fragment count register .................................................................. 11-18 ethernet transmit byte count register.......................................................................... 11-18 pause control frames ........................................................................................................... 11-19 ethernet generate pause frame register..................................................................... 11-19 ethernet pause frame status register ......................................................................... 11-20 ethernet control frame station address 0 register...................................................... 11-20 ethernet control frame station address 1 register...................................................... 11-21 ethernet control frame station address 2 register...................................................... 11-21 ethernet medium access controller (mac)............................................................................. 11-22 ethernet mac configuration register #1....................................................................... 11-22 ethernet mac configuration register #2....................................................................... 11-23 ethernet back-to-back inter-packet gap register......................................................... 11-27 ethernet non back-to-back inter-packet gap register ................................................. 11-27 ethernet collision window and retry register .............................................................. 11-28 ethernet maximum frame length register ................................................................... 11-29 ethernet mac test register........................................................................................... 11-29 ethernet mii management interface ........................................................................................ 11-30 mii management configuration register........................................................................ 11-30 mii management command register ............................................................................ 11-31 mii management address register................................................................................ 11-32 mii management write data register ............................................................................ 11-32 mii management read data register............................................................................ 11-33 mii management indicators register ............................................................................. 11-33 ethernet clock prescalar ....................................................................................................... .. 11-34 programming example ............................................................................................................ 11-34 12 general purpose i/o controller introduction ................................................................................................................... .............12-1 functional overview ............................................................................................................ ......12-1 theory of operation............................................................................................................ .......12-2 gpio pin configured as input .........................................................................................12-2 gpio pin configured as output ......................................................................................12-3 gpio pin configured as an alternate function ...............................................................12-3 gpio pins as interrupt sources ......................................................................................12-3 gpio pins as non-maskable interrupt sources ..............................................................12-3 general purpose i/o register description ................................................................................12-4 gpio function register ...................................................................................................12-4 gpio configuration register ...........................................................................................12-4 gpio data register .........................................................................................................12-5 gpio interrupt level register..........................................................................................12-5 gpio interrupt status register ........................................................................................12-5
idt table of contents 79rc32438 user reference manual ix november 4, 2002 notes gpio non-maskable interrupt enable register ...............................................................12-6 13 uart controller introduction ................................................................................................................... .............13-1 features....................................................................................................................... ..............13-1 functional overview ............................................................................................................ ......13-1 uart register description...................................................................................................... ..13-2 baud rate selection ............................................................................................................ ......13-3 uart interrupts................................................................................................................ .........13-4 uart channel reset ............................................................................................................. ...13-4 uart registers................................................................................................................. ........13-4 reset register ................................................................................................................. 13-5 receive buffer register ...................................................................................................13-5 transmit holding register................................................................................................13-5 interrupt enable register .................................................................................................13-6 interrupt identification register ........................................................................................13-7 fifo control register ......................................................................................................13-8 line control register .......................................................................................................13- 9 modem control register ................................................................................................13-10 line status register....................................................................................................... 13-1 1 modem status register..................................................................................................13-13 scratch register.............................................................................................................13 -14 divisor latch low register ............................................................................................13-14 divisor latch high register............................................................................................13-15 14 counter/timers functional overview ............................................................................................................ ......14-1 counter/timers register description.........................................................................................14- 1 theory of operation............................................................................................................ .......14-1 counter timer [0|1|2] count register...............................................................................14-2 counter timer [0|1|2] compare register .........................................................................14-2 counter timer [0|1|2] control register.............................................................................14-3 15 i2c bus interface introduction ................................................................................................................... .............15-1 features....................................................................................................................... ..............15-1 block diagram .................................................................................................................. .........15-1 functional overview and theor y of operation ..........................................................................15-1 i2c register description....................................................................................................... .....15-2 i 2 c bus control register..................................................................................................15-2 i2c bus data input register ............................................................................................15-3 i2c bus data output register..........................................................................................15-4 i2c bus clock prescalar........................................................................................................ ....15-4 i2c bus master interface ....................................................................................................... ....15-5 example i2c bus transactions ........................................................................................15-7 i2c bus master comm and register.................................................................................15-9 i2c bus master status register.....................................................................................15-10
idt table of contents 79rc32438 user reference manual x november 4, 2002 notes i2c bus master status mask register ........................................................................... 15-11 i2c bus slave interface ........................................................................................................ ...15-12 example of i2c bus transaction....................................................................................15-12 i2c bus slave status register.......................................................................................15-14 i2c bus slave status mask register .............................................................................15-15 i2c bus slave address register....................................................................................15-17 i2c bus slave acknowledge register............................................................................15-18 programming example ............................................................................................................ 15-18 16 serial peripheral interface functional overview ............................................................................................................ ......16-1 block diagram .................................................................................................................. .........16-1 spi clock prescalar............................................................................................................ .......16-3 clock prescalar register..................................................................................................16-3 spi control register ........................................................................................................16- 4 spi status register..........................................................................................................16 -5 spi data register ............................................................................................................16 -6 spi setup...................................................................................................................... .............16-7 serial bit i/o pins............................................................................................................ ...........16-7 serial i/o function register .............................................................................................16-7 serial i/o configuration register .....................................................................................16-8 serial i/o data register ...................................................................................................16-9 master programming example ................................................................................................16-10 spi initialization............................................................................................................. .16-10 17 on-chip memory introduction ................................................................................................................... .............17-1 theory of operation............................................................................................................ .......17-1 on-chip memory base register .......................................................................................17-1 on-chip memory mask register.......................................................................................17-2 18 debugging and performance monitoring introduction ................................................................................................................... .............18-1 features....................................................................................................................... ..............18-1 debug and performance register description ..........................................................................18-1 ipbus monitor .................................................................................................................. ..........18-2 ipbus monitor registers ........................................................................................................ ....18-3 ipbus monitor trigger configuration register..................................................................18-3 ipbus monitor trigger select register .............................................................................18-6 ipbus monitor manual trigger register ...........................................................................18-8 ipbus monitor trigger condition 0 register.....................................................................18-9 ipbus monitor trigger condition 1 register.....................................................................18-9 ipbus monitor trigger condition 2 register...................................................................18-10 ipbus monitor trigger condition 3 register...................................................................18-10 ipbus monitor filter select register .............................................................................. 18-11 ipbus monitor filter control 0 register..........................................................................18-12 ipbus monitor filter control 1 register..........................................................................18-13 ipbus monitor filter control 2 register..........................................................................18-13
idt table of contents 79rc32438 user reference manual xi november 4, 2002 notes ipbus monitor record control .......................................................................................18-14 ipbus monitor trigger position.......................................................................................18-15 ipbus monitor trigger time............................................................................................18-15 ipbus monitor record formats......................................................................................18-16 event monitor.................................................................................................................. .........18-17 event monitor control register ......................................................................................18-20 event monitor [0..7] count register ...............................................................................18-20 event monitor 0 compare register................................................................................18-21 debug pins ..................................................................................................................... .........18-22 19 jtag boundary scan introduction ................................................................................................................... .............19-1 system logic tap controll er overview.....................................................................................19-2 signal definitions ............................................................................................................. ..........19-2 test data register (dr)........................................................................................................ .....19-3 boundary scan registers ................................................................................................19-3 instruction register (ir)...................................................................................................... .......19-5 extest ......................................................................................................................... ..19-6 sample/preload ........................................................................................................19-7 bypass ......................................................................................................................... ..19-7 clamp.......................................................................................................................... ...19-7 deviceid ....................................................................................................................... .19-7 validate ....................................................................................................................... .19-8 reserved......................................................................................................................1 9-8 unused ......................................................................................................................... .19-8 usage considerations ........................................................................................................... ....19-8 20 ejtag system introduction ................................................................................................................... .............20-1 functional description ......................................................................................................... ......20-1 ejtag components.........................................................................................................20-1 register and memory map overview...............................................................................20-2 ejtag processor core extensions...........................................................................................20-6 overview ....................................................................................................................... ...20-6 debug mode execution....................................................................................................20-6 debug exceptions ..........................................................................................................20-13 debug mode exceptions ................................................................................................20-19 interrupts and nmis........................................................................................................20-2 1 reset and soft reset of processor................................................................................20-22 ejtag instructions.........................................................................................................20-2 3 ejtag coprocessor 0 registers ...................................................................................20-24 debug control register ......................................................................................................... ..20-30 hardware breakpoints ........................................................................................................... ..20-32 instruction breakpoint features .....................................................................................20-32 data breakpoint features ..............................................................................................20-33 overview of instruction and data breakpoint registers.................................................20-33 conditions for matching breakpoints .............................................................................20-35 debug exceptions from breakpoints..............................................................................20-40
idt table of contents 79rc32438 user reference manual xii november 4, 2002 notes breakpoints used as triggerpoints ................................................................................20-42 instruction breakpoint registers ....................................................................................20-43 data breakpoint registers .............................................................................................20-47 recommendations for implementing hardware breakpoints.........................................20-51 breakpoint examples .....................................................................................................20-52 ejtag test access port......................................................................................................... .20-54 tap signals.................................................................................................................... 20-55 tap controller................................................................................................................2 0-56 instruction register and special instructions .................................................................20-58 tap data registers........................................................................................................20-59 examples of use ............................................................................................................20-7 0 on-chip interfaces............................................................................................................. ......20-74 optional jtag_trst_n pin..........................................................................................20-74 input buffers with pull-up/down and ou tput drivers for chip pins................................20-74 connecting multi-core test access port (tap) controllers ...........................................20-75 off-chip and probe interfaces .................................................................................................2 0-75 logical signals ...............................................................................................................2 0-76 ac timing characteristics..............................................................................................20-77 dc electrical charac teristics..........................................................................................20-79 mechanical connector ...................................................................................................20-80 target system pcb design............................................................................................20-81 probe requirements and recommendations ................................................................20-83 appendix a 4kc processor core instructions introduction ................................................................................................................... .............. a-1 understanding the instruction set .............................................................................................. a-1 instruction fields ............................................................................................................. .. a-2 instruction descriptive name and mnemonic.................................................................... a-3 format field ................................................................................................................... ... a-3 purpose field .................................................................................................................. .. a-3 description field .............................................................................................................. .a-3 restrictions field............................................................................................................. .. a-4 operation field................................................................................................................ .. a-4 exceptions field............................................................................................................... .a-5 programming notes and implementation notes fields..................................................... a-5 operation section notation and functions ................................................................................. a-5 instruction execution ordering.......................................................................................... a-5 special symbols in pseudocode notation ........................................................................ a-6 pseudocode functions...................................................................................................... a-7 op and function subfield notation ..................................................................................a-11 cpu opcode map................................................................................................................. .....a-11 instruction set................................................................................................................ ........... a-13 index ............................................................................................................................... ........................i-1
notes 79rc32438 user reference manual xiii november 4, 2002 list of tables table 1.1 pin description....................................................................................................... ......... 1-11 table 1.2 rc32438 default memory map following a cold reset ................................................1-20 table 1.3 internal register map ................................................................................................. ....1-21 table 2.1 4kc core instruction latencies.......................................................................................2 -10 table 2.2 4kc core instruction repeat rates ................................................................................ 2-11 table 2.3 pipeline interlocks................................................................................................... ........2-16 table 2.4 instruction interlocks................................................................................................ .......2-18 table 2.5 instruction hazards................................................................................................... ......2-19 table 2.6 user mode segments .................................................................................................... .2-23 table 2.7 kernel mode segments .................................................................................................. 2-25 table 2.8 physical address and cache a ttributes for dseg, dmseg, and drseg address spaces..............................................................................................................2-2 6 table 2.9 cpu access to dr seg address range............................................................................2-27 table 2.10 cpu access to dm seg address range ..........................................................................2-27 table 2.11 tlb tag entry fields ................................................................................................. .....2-29 table 2.12 tlb data entry fields................................................................................................ .....2-30 table 2.13 tlb instructions..................................................................................................... .........2-35 table 2.14 priority of exceptions ............................................................................................... .......2-36 table 2.15 exception vector base addresses..................................................................................2-37 table 2.16 exception vector offsets ............................................................................................. ...2-37 table 2.17 exception vectors .................................................................................................... .......2-37 table 2.18 debug exception vector addresses ...............................................................................2-39 table 2.19 register states an interrupt exception ...........................................................................2-43 table 2.20 register states on a watch exception ...........................................................................2-44 table 2.21 cp0 register states on an address exception error .....................................................2-44 table 2.22 cp0 register states on a tlb refill exception..............................................................2-45 table 2.23 cp0 register states on a tlb invalid exception ...........................................................2-46 table 2.24 register states on a tlb modified exception ................................................................2-49 table 2.25 cp0 registers........................................................................................................ .........2-55 table 2.26 cp0 register field types ............................................................................................. ..2-56 table 2.27 index register field descriptions ...................................................................................2 -57 table 2.28 random register field descriptions ..............................................................................2-57 table 2.29 entrylo0, entrylo1 regi ster field descriptions .............................................................2-58 table 2.30 cache coherency attributes........................................................................................... 2-58 table 2.31 context register field descriptions ...............................................................................2-5 9 table 2.32 pagemask register field descriptions...........................................................................2-59 table 2.33 values for the mask field of the pagemask register .....................................................2-60 table 2.34 wired register field descriptions ..................................................................................2- 61 table 2.35 badvaddr register field descriptions............................................................................2-61 table 2.36 count register field descriptions ..................................................................................2- 61 table 2.37 entryhi register field descriptions ................................................................................2- 62 table 2.38 compare register field description...............................................................................2-62 table 2.39 status register field description ...................................................................................2 -63 table 2.40 cause register field descriptions .................................................................................2-6 6 table 2.41 cause register excc ode field descriptions..................................................................2-67 table 2.42 epc register field description ......................................................................................2 -68 table 2.43 prid register field descriptions....................................................................................2 -68 table 2.44 config register field descriptions .................................................................................2- 69 table 2.45 cache coherency attributes........................................................................................... 2-70
idt list of tables 79rc32438 user reference manual xiv november 4, 2002 notes table 2.46 config1 register field descriptions ? select 1.............................................................2-70 table 2.47 lladdr register fi eld descriptions ................................................................................2-7 2 table 2.48 watchlo register field descriptions..............................................................................2-72 table 2.49 watchhi register field descriptions ..............................................................................2-73 table 2.50 debug register fi eld descriptions .................................................................................2-7 4 table 2.51 depc register field description....................................................................................2- 76 table 2.52 errctl register field descriptions................................................................................... 2-77 table 2.53 taglo register field descriptions ..................................................................................2- 77 table 2.54 datalo register fi eld descriptions ................................................................................2-7 8 table 2.55 errorepc register field descriptions ............................................................................2-78 table 2.56 desave register field descriptions ...............................................................................2-79 table 2.57 instruction and data cache attributes............................................................................2-81 table 2.58 byte access within a word ............................................................................................ .2-85 table 3.1 processor clock pll multiplier modes .............................................................................3-2 table 3.2 reset register map.................................................................................................... ......3-3 table 3.3 boot configuration encoding........................................................................................... .3-5 table 4.1 system integrity register map......................................................................................... .4-1 table 4.2 address space monitor undec oded address error reporting .........................................4-5 table 4.3 ipbus slave acknowledge error reporting ......................................................................4-8 table 5.1 bus master index...................................................................................................... ........5-1 table 5.2 ipbus arbitration register map ........................................................................................ 5-2 table 5.3 pmbus arbitration register map ......................................................................................5- 2 table 6.1 device controller register map........................................................................................ 6-1 table 6.2 default values for device configuration registers...........................................................6-4 table 7.1 ddr controller register map........................................................................................... 7-1 table 7.2 supported ddr configurations ........................................................................................7- 2 table 7.3 ddr address multiplexing in 32-bit mode ........................................................................7-3 table 7.4 ddr address multiplexing in 16-bit mode ........................................................................7-4 table 7.5 ddr command encoding ................................................................................................7- 5 table 8.1 interrupt controller register map ..................................................................................... 8-2 table 8.2 ipend2 interrupt source description...............................................................................8-4 table 8.3 ipend3 interrupt source description...............................................................................8-5 table 8.4 ipend5 interrupt source description...............................................................................8-5 table 8.5 ipend6 interrupt source description...............................................................................8-6 table 9.1 dma register map ...................................................................................................... .....9-1 table 9.2 dma channels and device selects..................................................................................9-6 table 9.3 external dma operations............................................................................................... 9-17 table 9.4 memory to dma fifo dma operations .........................................................................9-20 table 9.5 dma fifo to memory dma operations .........................................................................9-20 table 10.1 pci bus interface fifo sizes......................................................................................... 10-3 table 10.2 pci register map ..................................................................................................... ......10-3 table 10.3 pci arbitration pin functionality in pc i host mode with internal arbiter enabled........10-15 table 10.4 pci arbitration pin functionality in pci host mode using external arbiter..................10-15 table 10.5 pci arbitration pin functi onality in pci satellite mode ................................................10-16 table 10.6 supported pci transactions.........................................................................................10 -17 table 10.7 pci device fields to idsel mapping...........................................................................10-20 table 10.8 pci to memory dma operations ..................................................................................10-30 table 10.9 memory to pci dma operations ..................................................................................10-33 table 10.10 pci configuration registers ......................................................................................... 10-46 table 11.1 ethernet register map................................................................................................ .... 11-2 table 11.2 ethernet interface input dma operations..................................................................... 11-13 table 11.3 ethernet interface output dma operations.................................................................. 11-14 table 11.4 padding operation.................................................................................................... .... 11-26 table 12.1 general purpose i/o pi n alternate function ..................................................................12-1 table 12.2 possible gpio configurations........................................................................................1 2-3
idt list of tables 79rc32438 user reference manual xv november 4, 2002 notes table 12.3 ethernet register map................................................................................................ ....12-4 table 13.1 uart input/output pins ............................................................................................... ..13-1 table 13.2 uart register map.................................................................................................... ....13-2 table 13.3 divisor values for typical b aud rates and ipbus clock frequencies ...........................13-3 table 15.1 i2c register map..................................................................................................... .......15-2 table 15.2 i2c bus master interface commands.............................................................................15-5 table 15.3 i2c bus data transfer abbreviations .............................................................................15-7 table 16.1 serial i/o pin configuration ......................................................................................... ...16-2 table 16.2 spi register map..................................................................................................... .......16-3 table 18.1 debug and performance register map ..........................................................................18-1 table 18.2 event monitor sources ................................................................................................ .18-17 table 18.3 debug pin operation .................................................................................................. ..18-22 table 19.1 jtag pin descriptions................................................................................................ ....19-2 table 19.2 instructions supported by rc32438?s jtag boundary scan ........................................19-6 table 19.3 system controller device identification register............................................................19-7 table 20.1 overview of coprocesso r 0 registers for ejtag...........................................................20-3 table 20.2 overview of debug control register as memory-mapped register for ejtag .............20-3 table 20.3 overview of instruction ha rdware breakpoint registers ................................................20-4 table 20.4 overview of data hardware breakpoint registers .........................................................20-4 table 20.5 overview of test access port registers.........................................................................20-5 table 20.6 overview of test access port registers.........................................................................20-7 table 20.7 physical address and cache attr ibute for dseg?s dmsg and drseg ................................20-9 table 20.8 access to dmseg address range...................................................................................20-9 table 20.9 access to drseg address range ..................................................................................20-10 table 20.10 sync instruction references.......................................................................................20 -12 table 20.11 ?required? cp0 and dseg hazard spacing ..................................................................20-13 table 20.12 priority of non-debug and debug exceptions..............................................................20-14 table 20.13 debug exception vector location.................................................................................20-1 5 table 20.14 priority of non-debug and debug exceptions..............................................................20-19 table 20.15 coprocessor 0 registers for ejtag.............................................................................20-25 table 20.16 debug register fi eld descriptions ...............................................................................20-2 6 table 20.17 depc register field description..................................................................................20- 30 table 20.18 desave register field description .............................................................................20-30 table 20.19 dcr register field descriptions ..................................................................................20- 31 table 20.20 instruction breakpoint register summary ....................................................................20-34 table 20.21 data breakpoint regi ster description...........................................................................20-34 table 20.22 instruction breakpoint condition parameters ...............................................................20-36 table 20.23 data breakpoint condition parameters ........................................................................20-37 table 20.24 bytelane at unaligned address for 32-bit processors .............................................20-39 table 20.25 behavior on precise excepti ons from data breakpoints ..............................................20-41 table 20.26 behavior on precise excepti ons from data breakpoints ..............................................20-41 table 20.27 rules for update of bs bits on data triggerpoints ......................................................20-43 table 20.28 instruction breakpoint register mapping......................................................................20-43 table 20.29 ibs register field description...................................................................................... 20-44 table 20.30 iban register field description....................................................................................2 0-45 table 20.31 ibmn register field description ...................................................................................20 -45 table 20.32 ibasidn register field description..............................................................................20-4 6 table 20.33 ibcn register field description....................................................................................2 0-46 table 20.34 data breakpoint register mapping...............................................................................20-47 table 20.35 dbs register field description ....................................................................................20 -47 table 20.36 dban register field description ..................................................................................20- 48 table 20.37 dbmn register field description..................................................................................20- 49 table 20.38 dbasidn register field description ............................................................................20-49 table 20.39 dbcn register field description..................................................................................20- 50 table 20.40 dbvn register field description ..................................................................................20- 51
idt list of tables 79rc32438 user reference manual xvi november 4, 2002 notes table 20.41 ejtag tap instruction overview .................................................................................20-58 table 20.42 ejtag tap data registers..........................................................................................20 -59 table 20.43 device id register field description ............................................................................20-6 1 table 20.44 implementation regist er field description ...................................................................20-63 table 20.45 data register field description....................................................................................2 0-64 table 20.46 data register contents for 32-bit processors ..............................................................20-64 table 20.47 address register field description ..............................................................................20-6 5 table 20.48 ejtag control register field description....................................................................20-66 table 20.49 combinations of probtrap and proben........................................................................20-70 table 20.50 bypass register field description................................................................................20- 70 table 20.51 manufid field value example ......................................................................................20- 71 table 20.52 information provided to probe at processor access ....................................................20-72 table 20.53 tap signals overview ................................................................................................ ..20-76 table 20.54 tap signals overview ................................................................................................ ..20-77 table 20.55 tap signals overview ................................................................................................ ..20-77 table 20.56 tap signals timing values........................................................................................... 20-78 table 20.57 system reset signal timing value...............................................................................20-79 table 20.58 voltage sense for i/o signal timing value...................................................................20-79 table 20.59 dc electrical characteristics ....................................................................................... .20-80 table 20.60 ejtag connector pinout.............................................................................................. 20-81 table a.1 symbols used in instruction operation statements ........................................................ a-6 table a.1 accesslength specifications for loads/stores................................................................ a-9 table a.2 encoding of the opcode field ........................................................................................a- 11 table a.3 special opcode encoding of function field...................................................................a-11 table a.4 special2 opcode encoding of function field................................................................ a-12 table a.5 regimm encoding of rt field ......................................................................................... a- 12 table a.6 cop0 encoding of rs field ............................................................................................ a -13 table a.7 cp0 encoding of function field when rs=co ............................................................... a-13 table a.8 instruction set....................................................................................................... ......... a-13
notes 79rc32438 user reference manual iii november 4, 2002 list of figures figure 1.1 rc32438 block diagram ............................................................................................... ..1-2 figure 1.2 system identification register (sysid) ............................................................................1-5 figure 1.3 logic diagram for the rc32438 .......................................................................................1 -7 figure 2.1 rc32438 block diagram ................................................................................................ ..2-3 figure 2.2 address translation during a ca che access in the 4kc core .........................................2-5 figure 2.3 4kc core pipeline stages............................................................................................. ....2-7 figure 2.4 4kc instruction cache miss timing ..................................................................................2- 8 figure 2.5 load/store cache miss timing......................................................................................... 2-9 figure 2.6 mdu pipeline behavior du ring multiply operations .......................................................2-11 figure 2.7 mdu pipeline flow during a 32x16 multiply operation..................................................2-12 figure 2.8 mdu pipeline flow during a 32x32 multiply operation..................................................2-13 figure 2.9 mdu pipeline flow during an 8- bit divide (div) operation ...........................................2-13 figure 2.10 mdu pipeline flow during a 16- bit divide (div) operation ...........................................2-13 figure 2.11 mdu pipeline flow during a 24- bit divide (div) operation ...........................................2-13 figure 2.12 mdu pipeline flow during a 32- bit divide (div) operation ...........................................2-14 figure 2.13 iu pipeline branch delay............................................................................................ ....2-14 figure 2.14 iu pipeline data bypass ............................................................................................. ....2-15 figure 2.15 iu pipeline m to e bypass ........................................................................................... ...2-15 figure 2.16 iu pipeline a to e data bypass ...................................................................................... 2-16 figure 2.17 iu pipeline slip after mfhi ......................................................................................... ....2-16 figure 2.18 instruction cache miss slip ......................................................................................... ...2-18 figure 2.19 address translation during a cache access .................................................................2-21 figure 2.20 4k processor core virtual memory map ........................................................................2-22 figure 2.21 user mode virtual address space..................................................................................2-2 3 figure 2.22 kernel mode virtual address space...............................................................................2-24 figure 2.23 debug mode virtual address space...............................................................................2-26 figure 2.24 jtlb entry (tag and data)........................................................................................... ..2-28 figure 2.25 overview of a virtual-to-ph ysical address translation...................................................2-31 figure 2.26 32-bit virtual address translation.................................................................................. .2-32 figure 2.27 tlb address translation flow in the 4kc processor core.............................................2-34 figure 2.28 register states on a copr ocessor unusable exception.................................................2-47 figure 2.29 general exception handler (hw) ...................................................................................2-5 0 figure 2.30 general exception serv icing guidelines (sw) ...............................................................2-51 figure 2.31 tlb miss exception handler (hw) .................................................................................2-52 figure 2.32 tlb exception servicing guidelines (sw) .....................................................................2-53 figure 2.33 reset, soft reset, and nmi exception handling and servicing guidelines ...................2-54 figure 2.34 wired and random entries in the tlb ...........................................................................2-60 figure 2.35 cache array formats................................................................................................. .....2-81 figure 2.36 instruction set formats............................................................................................. ......2-84 figure 3.1 system block diagram of reset and b oot configuration vector generation ...................3-1 figure 3.2 rc32438 clocking architecture........................................................................................ 3-2 figure 3.3 cold reset ........................................................................................................... .............3-4 figure 3.4 pci reset in host mode ............................................................................................... ....3-4 figure 3.5 boot configuration vector register (bcv) .......................................................................3-6 figure 3.6 externally initiated warm reset ...................................................................................... .3-7 figure 3.7 internally initiated warm reset...................................................................................... ...3-8 figure 3.8 pci reset in satellite mode.......................................................................................... ....3-8 figure 3.9 reset register (reset)............................................................................................... ....3-8 figure 4.1 error control and status register (errcs).....................................................................4-2
idt list of figures 79rc32438 user reference manual iv november 4, 2002 notes figure 4.2 cpu error addre ss register (cea)..................................................................................4-4 figure 4.3 watchdog timer count register (wtcount).................................................................4-6 figure 4.4 watchdog timer compare register (wtcompare) ......................................................4-6 figure 4.5 watchdog timer contro l register (wtc).........................................................................4-7 figure 5.1 illustration of ipbus arbitration algorithm.......................................................................... 5-3 figure 5.2 ipbus arbitration algor ithm flow chart ............................................................................5-5 figure 5.3 ipbus arbiter configuration for strict priority arbitration ..................................................5-6 figure 5.4 example operation of ipbus arbiter with strict priority arbitration...................................5-6 figure 5.5 ipbus arbiter configurati on for fair arbitration ................................................................5-7 figure 5.6 example operation of ipbus ar biter with fair arbitration.................................................5-7 figure 5.7 ipbus arbiter configuration for pr iority arbitration with fairness .....................................5-7 figure 5.8 example operation of ipbus arbiter wi th priority arbitrati on with fairness......................5-8 figure 5.9 ipbus arbiter configurati on for weighted round robin...................................................5-8 figure 5.10 example operation of ipbus ar biter with weighted round robin ...................................5-8 figure 5.11 ipbus arbiter control register (ipac)..............................................................................5 -9 figure 5.12 ipbus arbiter priority configurat ion [0..3] register (ipap[0..3]c) ..................................5-10 figure 5.13 ipbus arbiter bus master [0..16] co nfiguration register (ipabm[0..16]) .......................5-11 figure 5.14 ipbus idle transaction cycl e count register (ipaitcc)...............................................5-12 figure 5.15 pmbus arbiter processor priority register (pmapp).....................................................5-13 figure 5.16 pmbus arbiter sneak access control register (pmasac) ...........................................5-13 figure 5.17 external bus arbitration............................................................................................ ......5-15 figure 5.18 external bus arbitration with rc32438 requesting that ownership be relinquished..............................................................................................................5- 15 figure 6.1 connecting devices to the rc 32438 data bus (right aligned).......................................6-3 figure 6.2 device [0..5] base r egister (dev[0..5]base)..................................................................6-5 figure 6.3 device [0..5] mask r egister (dev[0..5]mask).................................................................6-5 figure 6.4 device [0..5] control register (dev[0..5]c) .....................................................................6-6 figure 6.5 device [0..5] timing contro l register (dev[0..5]tc) .......................................................6-8 figure 6.6 bus timer control and st atus register (btcs) .............................................................6-10 figure 6.7 bus transaction timer com pare register (btcompare) ...........................................6-10 figure 6.8 bus transaction timer a ddress register (btaddr).....................................................6-11 figure 6.9 generic device read transaction..................................................................................6-12 figure 6.10 device read transaction 1 (waitackn configured as wait) .......................................6-13 figure 6.11 device read transaction (waitack n configured as transfer acknowledge) ............6-13 figure 6.12 generic burst devi ce read transaction ........................................................................6-14 figure 6.13 burst device read transaction......................................................................................6 -15 figure 6.14 generic device write transaction 1 ................................................................................6-16 figure 6.15 generic burst device write transaction.........................................................................6-17 figure 6.16 device decoupled access control and status register (devdacs) ............................6-19 figure 6.17 device decoupled access address register (devdaa) ...............................................6-20 figure 6.18 device decoupled access data register (devdad).....................................................6-20 figure 7.1 ddr control register (ddrc) .........................................................................................7 -5 figure 7.2 ddr read data capture edge select configurations ...................................................7-10 figure 7.3 ddr read data captur e register (ddrrdc)...............................................................7-10 figure 7.4 ddr0 alternate address mapping..................................................................................7-12 figure 7.5 ddr [0|1] base regi ster (ddr[0|1]base).....................................................................7-12 figure 7.6 ddr [0|1] mask regi ster (ddr[0|1]mask)....................................................................7-13 figure 7.7 ddr 0 alternate base register (ddr0abase).............................................................7-13 figure 7.8 ddr 0 alternate mask register (ddr0amask)............................................................7-14 figure 7.9 ddr 0 alternate mappi ng register (ddr0amap).........................................................7-14 figure 7.10 ddr data bus multiple xing address range expansion.................................................7-15 figure 7.11 32-bit bank ddr data bus multiplexing .........................................................................7-15 figure 7.12 16-bit bank ddr data bus multiplexing .........................................................................7-16 figure 7.13 ddr custom transacti on register (ddrcust) ...........................................................7-17 figure 7.14 refresh timer count register (rcount) .....................................................................7-18
idt list of figures 79rc32438 user reference manual v november 4, 2002 notes figure 7.15 refresh timer compar e register (rcompare)...........................................................7-19 figure 7.16 refresh timer contro l register (rtc) ...........................................................................7-19 figure 7.17 ddr sdram read transaction with wrong page active in bank (bank page miss) ..........................................................................................................7-20 figure 7.18 ddr sdram write transacti on with wrong page active in bank (bank page miss) ...........................................................................................................7-22 figure 7.19 ddr sdram refresh trans action with active pages ...................................................7-23 figure 7.20 ddr sdram custom transaction.................................................................................7-25 figure 8.1 mapping of interrupts to the cpu cause register ...........................................................8-2 figure 8.2 interrupt pending [2..6] register (ipend[2..6]) ................................................................8-3 figure 8.3 interrupt test [2..6] register (itest[2..6]) .......................................................................8- 3 figure 8.4 interrupt mask [2..6] register (imask[2..6]).....................................................................8-4 figure 8.5 non-maskable interrupt pin status...................................................................................8 -7 figure 9.1 dma block diagram .................................................................................................... .....9-4 figure 9.2 anatomy of dma operations............................................................................................ 9-5 figure 9.3 memory to memory dma transfers..................................................................................9-6 figure 9.4 dma descriptor register.............................................................................................. ....9-8 figure 9.5 dma chaining example................................................................................................. .9-11 figure 9.6 dma [0..9] control register (dma[0..9]c)......................................................................9-12 figure 9.7 dma [0..9] status register (dma[0..9]s) .......................................................................9-13 figure 9.8 dma [0..9] status mask register (dma[0..9]sm)...........................................................9-14 figure 9.9 dma [0..9] descriptor poin ter register (dma [0..9]dptr) .............................................9-15 figure 9.10 dma [0..9] next descriptor po inter register (dma[0..9]ndptr) ..................................9-15 figure 9.11 device control and status val ue for external dma descriptors ....................................9-16 figure 9.12 device command field for external dma descriptors...................................................9-16 figure 9.13 external dma operati on (transfer request mode)........................................................9-17 figure 9.14 external dma operat ion (burst request mode).............................................................9-18 figure 9.15 sampling of dmadonenx during ex ternal peripheral r ead transactions...................9-18 figure 9.16 sampling of dmadonenx during exte rnal peripheral writ e transactions...................9-18 figure 9.17 assertion of dmafinnx during exte rnal peripheral read transactions .......................9-19 figure 9.18 assertion of dmafinnx during exte rnal peripheral writ e transactions .......................9-19 figure 9.19 device command field for memo ry to memory dma descriptors .................................9-19 figure 10.1 pci interface block diagram ......................................................................................... .10-1 figure 10.2 pci control register (pcic)......................................................................................... ..10-4 figure 10.3 pci status register (pcis) .......................................................................................... ..10-7 figure 10.4 pci status mask register (pcism) .............................................................................10-10 figure 10.5 pci configuration addr ess register (pcicfga) .........................................................10-22 figure 10.6 pci configuration data register (pcicfgd)...............................................................10-23 figure 10.7 pci local base address [0|1|2 |3] register (pcilba[0|1|2|3])......................................10-23 figure 10.8 pci local base address [0|1|2 |3] control (pcilba[0|1|2|3]c).....................................10-24 figure 10.9 pci local base address [0|1|2|3] mapping register (pcilba[0|1|2|3]m)....................10-25 figure 10.10 pci decoupled access c ontrol register (pcidac).....................................................10-26 figure 10.11 pci decoupled access st atus register (pcidas).......................................................10-26 figure 10.12 pci decoupled access status mask register (pcidasm)).........................................10-27 figure 10.13 pci decoupled access da ta register (pcidad).........................................................10-29 figure 10.14 device command field for pci to memory dma descriptors ......................................10-30 figure 10.15 device control and status value fo r pci to memory dma descriptors .......................10-30 figure 10.16 pci dma channel 8 configur ation register (pcidma8c)...........................................10-31 figure 10.17 device command field for memo ry to pci dma descriptors ......................................10-33 figure 10.18 device control and status value fo r memory to pci dma descriptors .......................10-33 figure 10.19 pci dma channel 9 configur ation register (pcidma9c)...........................................10-35 figure 10.20 pci target control register (pcitc) ...........................................................................10-38 figure 10.21 pci inbound message [0|1] register (pciim[0|1]) .......................................................10-41 figure 10.22 pci outbound message [0|1] register (pciom[0|1])...................................................10-41 figure 10.23 pci inbound doorbell r egister (pciid)........................................................................10-42
idt list of figures 79rc32438 user reference manual vi november 4, 2002 notes figure 10.24 pci inbound interrupt c ause register (pciiic)............................................................10-42 figure 10.25 pci inbound interrupt ma sk register (pciiim).............................................................10-43 figure 10.26 pci outbound doorbell register (pciod) ...................................................................10-44 figure 10.27 pci outbound interrupt cause register (pcioic).......................................................10-44 figure 10.28 pci outbound interrupt mask register (pcioim) ........................................................10-45 figure 10.29 vendor id register (vendor_id)...............................................................................10-47 figure 10.30 device id register (device_id) .................................................................................10-4 7 figure 10.31 command register (command) ................................................................................10-47 figure 10.32 status register (status)........................................................................................... .10-49 figure 10.33 device revision id register (revision_id)...............................................................10-51 figure 10.34 class code register (class_code) .........................................................................10-51 figure 10.35 class code register (class_code) .........................................................................10-51 figure 10.36 master latency regi ster (master_latency)..........................................................10-52 figure 10.37 header type regist er (header_type).....................................................................10-52 figure 10.38 header type register (bist) .......................................................................................1 0-53 figure 10.39 pci base address [0|1|2|3] register (pba[0|1|2|3]).....................................................10-53 figure 10.40 subsystem vendor id register (svi) ...........................................................................10-54 figure 10.41 subsystem id regi ster (subsystem_id)..................................................................10-54 figure 10.42 interrupt line regist er (interrupt_line) ................................................................10-55 figure 10.43 interrupt pin regist er (interrupt_pin)....................................................................10-55 figure 10.44 minimum grant regi ster (min_gnt) ...........................................................................10-55 figure 10.45 maximum latency register (max_lat) ......................................................................10-56 figure 10.46 target time-out r egister (trdy_timeout) ..............................................................10-56 figure 10.47 retry limit regist er (retry_limit) ...........................................................................10-57 figure 10.48 pci base address [0|1|2|3] control (pba[0|1|2|3]c)....................................................10-57 figure 10.49 pci base address [0|1|2|3] mapping register (pba[0|1|2|3]m)...................................10-59 figure 10.50 pci management register (pmgt)..............................................................................10-60 figure 11.1 ethernet interface with management feature ................................................................11-1 figure 11.2 ethernet interface contro l register (eth[0|1]intfc) ....................................................11-5 figure 11.3 ethernet fifo transmit thres hold register (eth[0 |1]fifott) ....................................11-7 figure 11.4 representation of mac address ....................................................................................11- 7 figure 11.5 ethernet address recognition c ontrol register (eth[0|1]arc)....................................11-9 figure 11.6 ethernet address fi ltering algorithm............................................................................11-1 0 figure 11.7 ethernet hash table [0|1] register (eth[0|1 ]hash[0|1])............................................11-11 figure 11.8 ethernet station address [0|1|2|3] low register (eth[0|1]sal[0|1|2|3]).....................11-11 figure 11.9 ethernet station address [0|1|2|3] high register (eth[0|1]sah[0|1|2|3]) ...................11-12 figure 11.10 device control and status value for ethernet receive descriptors.............................11-13 figure 11.11 device control and status value for ethernet transmit descriptors............................11-15 figure 11.12 ethernet receive byte count (eth[0|1]rbc) ..............................................................11-17 figure 11.13 ethernet receive packet count (eth[0|1]rpc) ..........................................................11-17 figure 11.14 ethernet receive undersized packet count (eth[0|1]rupc).....................................11-17 figure 11.15 ethernet receive fragment count (eth[0|1]rfc) ......................................................11-18 figure 11.16 ethernet transmit byte count (eth[0|1]tbc)..............................................................11-18 figure 11.17 ethernet generate pause fram e register (eth[0|1]gpf) ..........................................11-19 figure 11.18 ethernet pause frame status register (eth[0|1]pfs) ...............................................11-20 figure 11.19 ethernet control frame stati on address 0 (eth[0|1]cfsa0)......................................11-20 figure 11.20 ethernet control frame stati on address 1 (eth[0|1]cfsa1)......................................11-21 figure 11.21 ethernet control frame stati on address 2 (eth[0|1]cfsa2)......................................11-21 figure 11.22 ethernet mac configuration register #1 (eth[0|1]mac1)..........................................11-22 figure 11.23 ethernet mac configuration register #2 (eth[0|1]mac2)..........................................11-23 figure 11.24 ethernet back-to-back inter-pack et gap register (eth[0|1]ipgt) .............................11-27 figure 11.25 ethernet non back-to-back inter-pa cket gap register (eth[0|1]ipgr) .....................11-27 figure 11.26 ethernet collision window and re try register (eth[0|1]clrt)..................................11-28 figure 11.27 ethernet maximum frame lengt h register (eth[0|1]maxf) ......................................11-29 figure 11.28 ethernet mac test regi ster (eth[0|1]mtest) ...........................................................11-29
idt list of figures 79rc32438 user reference manual vii november 4, 2002 notes figure 11.29 mii management configurat ion register (miimcfg)...................................................11-30 figure 11.30 mii management command register (miimcmd) .......................................................11-31 figure 11.31 mii management address register (miimaddr).........................................................11-32 figure 11.32 mii management write da ta register (miimwtd).......................................................11-32 figure 11.33 mii management read data register (miimrdd).......................................................11-33 figure 11.34 mii management indicators register (miimind) ..........................................................11-33 figure 11.35 ethernet management clock pr escalar register (ethmcp) .......................................11-34 figure 12.1 gpio function register (gpiofunc) ...........................................................................12-4 figure 12.2 gpio configuration register (gpiocfg)......................................................................12-4 figure 12.3 gpio data register (gpiod).........................................................................................1 2-5 figure 12.4 gpio interrupt level register (gpioilevel)................................................................12-5 figure 12.5 gpio interrupt status register (gpioistat) ................................................................12-5 figure 12.6 gpio non-maskable interrupt enable register (gpionmien)......................................12-6 figure 13.1 uart [0|1] reset register ........................................................................................... ..13-5 figure 13.2 uart [0|1] receive buffer register (uart[0|1]rb)......................................................13-5 figure 13.3 uart [0|1] transmit holdi ng register (uart[0|1]th) ..................................................13-5 figure 13.4 uart [0|1] interrupt enable register (uart[0|1]ie) .....................................................13-6 figure 13.5 uart [0|1] interrupt identific ation register (uart[0|1]ii)..............................................13-7 figure 13.6 uart [0|1] fifo control register (uart[0|1]fc).........................................................13-8 figure 13.7 uart [0|1] line control register (uart[ 0|1]lc) ..........................................................13-9 figure 13.8 uart[0|1] modem contro l register (uart0mc) ........................................................13-10 figure 13.9 uart [0|1] line status register (uart[0|1]ls) ..........................................................13-11 figure 13.10 uart[0|1] modem status register (uart0ms)..........................................................13-13 figure 13.11 uart [0|1] scratch register (uart[0|1]s)..................................................................13-14 figure 13.12 uart [0|1] divisor latch low register (uart[0|1]dll) .............................................13-14 figure 13.13 uart [0|1] divisor latch high register (uart[0|1]dlh) ............................................13-15 figure 14.1 counter timer [0|1|2] count register (count[0|1|2])...................................................14-2 figure 14.2 counter timer [0|1|2] compar e register (compare[0|1|2]) ........................................14-2 figure 14.3 counter timer [0|1|2] cont rol register (ctc[0|1|2]) ......................................................14-3 figure 15.1 i2c bus interface block diagram....................................................................................1 5-1 figure 15.2 i 2 c bus control register (i2cc).....................................................................................15-2 figure 15.3 i2c bus data input register (i2cdi) ..............................................................................15- 3 figure 15.4 i2c bus data output register (i2cdo)..........................................................................15-4 figure 15.5 i2c bus clock prescala r register (i2ccp) ....................................................................15-4 figure 15.6 using the i2c bus clock (scl) to adapt the operating rate.........................................15-6 figure 15.7 master operation: master tr ansmitter addressing a slave receiver (7-bit address) ................................................................................................................ 15-8 figure 15.8 master operation: master re ceiver addressing a slave transmitter (7-bit address) ................................................................................................................ 15-8 figure 15.9 master operation: master interf ace initiated repeated start condition .........................15-9 figure 15.10 master operation: addressing a 10-bit slave as a slave transmitter ............................15-9 figure 15.11 i2c bus master comm and register (i2cmcmd)...........................................................15-9 figure 15.12 i2c bus master status register (i2cms).....................................................................15-10 figure 15.13 i2c bus master status mask register (i2cmsm) ........................................................15-11 figure 15.14 slave operation: master tr ansmitter addressing a slave receiver (7-bit address) ..............................................................................................................15 -13 figure 15.15 slave operation: master re ceiver addressing a slave transmitter (7-bit address) ..............................................................................................................15 -13 figure 15.16 slave operation: addressing a 10- bit slave as a slave transmitter............................15-14 figure 15.17 i2c bus slave status register (i2css)........................................................................15-14 figure 15.18 i2c bus slave status mask register (i2cssm)...........................................................15-15 figure 15.19 i2c bus slave addre ss register (i2c saddr).............................................................15-17 figure 15.20 i2c bus slave acknowledge register (i2csack) .......................................................15-18 figure 16.1 spi and pci serial eeproms interfacing......................................................................16-1 figure 16.2 spi clock prescala r register (spcp) ............................................................................16-3
idt list of figures 79rc32438 user reference manual viii november 4, 2002 notes figure 16.3 spi control register (spc) .......................................................................................... ..16-4 figure 16.4 serial peripheral interfac e (spi) clock/data timing.......................................................16-5 figure 16.5 spi status register (sps)........................................................................................... ...16-5 figure 16.6 spi data register (spd) ............................................................................................. ...16-6 figure 16.7 serial i/o function register (siofunc)........................................................................16-7 figure 16.8 serial i/o configurati on register (siocfg)...................................................................16-8 figure 16.9 serial i/o data register (siod)..................................................................................... .16-9 figure 17.1 on-chip memory base register (ocmbase) ................................................................17-1 figure 17.2 on-chip memory mask register (ocmmask) ...............................................................17-2 figure 18.1 ipbus monitor on-chip memory usage .........................................................................18-2 figure 18.2 ipbus monitor trigger confi guration register (ipbmtcfg) ..........................................18-3 figure 18.3 ipbus monitor trigger se lect register (ipbmts)...........................................................18-6 figure 18.4 ipbus monitor manual tri gger register (ipbmmt) ........................................................18-8 figure 18.5 ipbus monitor trigger condi tion 0 register (ipbmtc0) ................................................18-9 figure 18.6 ipbus monitor trigger condi tion 1 register (ipbmtc1) ................................................18-9 figure 18.7 ipbus monitor trigger condi tion 2 register (ipbmtc2) ..............................................18-10 figure 18.8 ipbus monitor trigger condi tion 3 register (ipbmtc3) ..............................................18-10 figure 18.9 ipbus monitor filter select register (ipbmfs)............................................................18-11 figure 18.10 ipbus monitor filter control 0 register (ipbmfc0) .....................................................18-12 figure 18.11 ipbus monitor filter control 1 register (ipbmfc1 ......................................................18-13 figure 18.12 ipbus monitor filter control 2 register (ipbmfc2) .....................................................18-13 figure 18.13 ipbus monitor record c ontrol register (ipbmrc) ......................................................18-14 figure 18.14 ipbus monitor trigger po sition register (ipbmtp)......................................................18-15 figure 18.15 ipbus monitor trigger time register (ipbmtt)...........................................................18-15 figure 18.16 ipbus monitor transaction summary record format ..................................................18-16 figure 18.17 ipbus monitor clock cycle record format ..................................................................18-17 figure 18.18 event monitor control register (emc) .........................................................................18-20 figure 18.19 event monitor [0..7] count register (em[0..7]count)................................................18-20 figure 18.20 event monitor 0 compare register (em0compare) .................................................18-21 figure 19.1 dual tap controll er block diagram ...............................................................................19-1 figure 19.2 diagram of the jtag logic ........................................................................................... .19-2 figure 19.3 state diagram of rc32438?s tap controller .................................................................19-3 figure 19.4 diagram of observe-only input cell................................................................................19 -4 figure 19.5 diagram of output cell .............................................................................................. .....19-4 figure 19.6 diagram of output enable cell....................................................................................... 19-5 figure 19.7 diagram of bidirectional cell ...................................................................................... ...19-5 figure 19.8 system controller device id instruction format.............................................................19-8 figure 20.1 simplified ejtag block diagram ...................................................................................20- 2 figure 20.2 virtual address spaces with debug mode segments ....................................................20-8 figure 20.3 debug register format ............................................................................................... .20-26 figure 20.4 depc register forma................................................................................................. .20-29 figure 20.5 desave register format ............................................................................................20 -30 figure 20.6 dcr register format ................................................................................................. ..20-31 figure 20.7 instruction breakpoint overview...................................................................................20 -33 figure 20.8 data breakpoint overview............................................................................................ 20-33 figure 20.9 ibs register format ................................................................................................. ....20-44 figure 20.10 iban register format ............................................................................................... ....20-44 figure 20.11 ibmn register format............................................................................................... ....20-45 figure 20.12 ibasidn register format ............................................................................................ .20-45 figure 20.13 ibcn register format............................................................................................... ....20-46 figure 20.14 dbs register format................................................................................................ ....20-47 figure 20.15 dban register format............................................................................................... ...20-48 figure 20.16 dbmn register format............................................................................................... ..20-49 figure 20.17 dbasidn register format............................................................................................ 20-49 figure 20.18 dbcn register format ............................................................................................... ..20-50
idt list of figures 79rc32438 user reference manual ix november 4, 2002 notes figure 20.19 dbvn register format............................................................................................... ...20-51 figure 20.20 data break on store with value compare....................................................................20-54 figure 20.21 data break on store with value compare....................................................................20-54 figure 20.22 test access port (tap) overview ................................................................................20-5 5 figure 20.23 ejtag tap controller state diagram..........................................................................20-56 figure 20.24 jtag_tdi to jtag_tdo path in shift mode state .....................................................20-57 figure 20.25 jtag_tdi to jtag_tdo path for sele cted data register(s) in shift-dr state .........20-57 figure 20.26 jtag_tdi to jtag_tdo path in shft- dr state and all instruction is selected .......20-59 figure 20.27 jtag_tdi to jtag_tdo path in shift-dr state and fastdata instruction is selected .................................................................................................................... 20-59 figure 20.28 device id register format .......................................................................................... .20-61 figure 20.29 implementation register format ..................................................................................20- 62 figure 20.30 data register format ............................................................................................... ....20-63 figure 20.31 address register format............................................................................................ ..20-65 figure 20.32 ejtag control register format...................................................................................20- 65 figure 20.33 bypass register format ............................................................................................. ..20-70 figure 20.34 tap operation example.............................................................................................. .20-71 figure 20.35 write processor access example.................................................................................20-7 3 figure 20.36 read processor access example ................................................................................20-74 figure 20.37 daisy chaining of multi-co re ejtag tap controllers..................................................20-75 figure 20.38 signal flow between chip, ta rget system pcb, and probe .......................................20-76 figure 20.39 tap signals timing ................................................................................................. .....20-78 figure 20.40 system reset signal timing......................................................................................... 20-79 figure 20.41 voltage sense for i/o signal timing.............................................................................20- 79 figure 20.42 ejtag connector mechanical dimensions..................................................................20-81 figure 20.43 target system elec trical ejtag connection ...............................................................20-82 figure 20.44 target system layout for ejtag connection..............................................................20-83 figure a.1 example of instruction description .................................................................................. a -2 figure a.1 example of instruction fields........................................................................................ ... a-3 figure a.2 example of instruction descriptive and mnemonic name ............................................... a-3 figure a.3 example of instruction format........................................................................................ .a-3 figure a.4 example of instruction purpose....................................................................................... a-3 figure a.5 example of instruction description .................................................................................. a -4 figure a.6 example of instruction restrictions ................................................................................. a -4 figure a.7 sample instruction operation ......................................................................................... .a-5 figure a.8 sample instruction exception ......................................................................................... .a-5 figure a.9 sample instruction programming notes .......................................................................... a-5 figure a.10 unaligned word load using lwl and lwr ................................................................. a-74 figure a.11 bytes loaded by lwl instruction.................................................................................. a-7 5 figure a.12 unaligned word load using lwl and lwr ................................................................. a-78 figure a.13 bytes loaded by lwl instruction.................................................................................. a-7 9
idt list of figures 79rc32438 user reference manual x november 4, 2002 notes
notes 79rc32438 user reference manual 1 - 1 november 4, 2002 chapter 1 rc32438 device overview introduction the objective of this chapter is to provide an overview of the capabi lities of the rc32438 device. in addi- tion, it is a centralized resource for three standard items: ? summary of the address map for all the registers included in this device. the functionality of each register bit is covered in the re levant chapter within this manual. ? default address memory map. ? pin description list, pin types, driv e strengths, and alternate functions. the rc32438 is a general-purpose in tegrated processor that incorporates a high performance cpu core and a number of on-chip peripherals. the integrat ed processor is designed to transfer information from io modules to main memory with minimal cpu inte rvention, using a highly s ophisticated direct memory access (dma) engine. all data transfers through the rc32438 are achieved by writing data from an on-chip io peripheral to main memory and then out to another io module. key features the key features of this part include the following: ? a 32-bit cpu core 100% compatible with the mips32 instruction set architecture (isa). specifi- cally, this core features the 4kc developed by mi ps technologies inc. (www.mips.com). this core issues a single instruction per cycle, includes a five stage pipeline and is optimized for applications that require integer arithmetic. the versi on in the rc32438 includes 16 kb instruction and 16 kb data caches. both caches are 4-way set associ ative and can be locked on a per line basis, which allows the programmer control over this prec ious on-chip memory resource. the core also features a memory management uni t (mmu). the cpu core also incorporates an enhanced joint test access group (ejtag) interface that is used to interface to in-circuit emulator tools, providing access to internal registers and enabling the part to be controlled externally, simplifying the system debug process. the use of this core allows idt' s customers to leverage the broad range of soft- ware and development tools available for the mips architecture, including operating systems, compilers and in-circuit emulators. ? high performance double data rate (ddr) memory controller. this supports both x16 and x32 memory configurations up to 2gb. the module provides all of t he signals required to interface to both memory modules and discrete devices, includi ng two chip selects, differential clocking outputs, and data strobes. ? a dedicated local memory/io controller incl uding a de-multiplexed 16-bit data and 26-bit address bus. this device includes all of the signals require d to interface directly to up to six intel or motorola-style external peripher als. this interface can be conf igured to support both 8-bit and 16- bit peripherals. ? two ethernet channels supporting 10mbps and 100mbps speeds, and providing a standard media independent interface (mii) off-chip, to enable a wide range of external devices to be connected up efficiently. ? a pci interface compatible with version 2.2 of the pci specification. an on-chip arbiter supports up to four external bus masters, supporting both fixed priority and rotati ng priority arbitration schemes. the part can support both satellite and host pci configurations, enabling the rc32438 to act as a slave controller for a pci add-in card appl ication, or as the primar y pci controller in the system. the pci interface can be operated synchronous ly or asynchronously to the other io inter- faces on the rc32438 device ? two standard 16550-compatible serial ports, wi th both channels including hardware flow control signals
idt rc32438 device overview system block diagram 79rc32438 user reference manual 1 - 2 november 4, 2002 notes ? an i2c interface ? a serial peripheral interface (spi) ? 4 kb of on-chip memory (configured as 2kx32 bits) for use as scratch pad memory that can be accessed by the cpu core and other io modules ? three general-purpose 32-bit counter/timers ? an interrupt controller that multiplexes all of the interrupt signals coming from on-chip modules and general purpose io (gpio) pins onto one of five available interrupt sources to the cpu core. system block diagram an internal block diagram is shown in figure 1.1. figure 1.1 rc32438 block diagram additional resources this device provides a performance upgrade fo r existing users of the rc32332, rc32333, and rc32334 (referred to as the rc3233x series) integr ated communications processors. idt has developed an application note that addresses the migration of software from the rc3233x to the rc32438. this docu- ment, a n-368 ?migrating rc32332/rc32334 software to the rc32438 device , can be found on the company?s web site at www.idt.com. feature list summary 32-bit processor ? mips32 architecture ? single-cycle 32x16 multiply accumulate instructions ? 16 kb instruction and data caches ? memory management unit ? 8 -word write buffer that supports byte merging ? power-down modes ejtag mmu d. cache i. cache mips-32 cpu core ice interrupt controller 3 counter timers bus/system dma controller arbiter ddr ddr & device 2 uarts (16550) gpio interface pci master/target memory & peripheral bus ch. 1 ch. 2 serial channels gpio pins pci bus controller controller spi i 2 c spi bus i 2 c bus : : 10/100 2 ethernet interfaces mii mii integrity monitor ipbus tm interface pci arbiter (host mode) controllers pmbus
idt rc32438 device overview feature list summary 79rc32438 user reference manual 1 - 3 november 4, 2002 notes ? debugging through enhanced jtag (ejtag) interface ? version 2.5 compatible ? non-intrusive real-time debugging ? single stepping ? instruction and data breakpoints ddr memory controller ? supports up to 2gb of ddr sdram (using data bus multiplexing and two chip selects) ? 2 chip selects (each chip sele ct supports 4 internal ddr banks) ? supports 16-bit or 32-bit data bus wi dth using 8, 16, or 32-bit devices ? supports 64 mb, 128 mb, 256 mb, 512 mb, and 1gb ddr sdram devices ? data bus multiplexing support allows inte rfacing to standard ddr dimms and sodimms ? automatic refresh generation memory and peripheral device controller ? provides ?glueless? interfac e to standard sram, flash, rom, dual-port memory, and peripheral devices ? demultiplexed address and data buses ? 16-bit data bus ? 26-bit address bus ? 6 chip selects ? supports alternate bus masters ? control for external data bus buffers ? supports 8-bit and 16-bit width devices ? automatic byte gathering and scattering ? flexible protocol c onfiguration parameters ? programmable number of wait states (0 to 63) ? programmable postread/postwrite delay (0 to 31) ? supports external wait state generation ? supports intel and motorola style peripherals ? write protect capability per chip select ? programmable bus transaction timer generat es warm reset when counter expires ? supports up to 64 mb of memory per chip select counter/timers ? three general purpose 32- bit counter timers interrupt controller ? allows status of all interrupt sources to be read ? each interrupt source may be masked ? provides interrupt test capability system integrity functions ? programmable watchdog timer generates nmi when counter expires ? address space monitor reports error in re sponse to accesses to undecoded address regions
idt rc32438 device overview feature list summary 79rc32438 user reference manual 1 - 4 november 4, 2002 notes dma controller ? 10 dma channels ? two channels for pci (pci to memory and memory to pci) ? four ethernet channels ? two for each ethernet interface (transmit/receive) ? two dma channels for memory to memory dma operations ? two dma channel for external dma operations ? provides flexible de scriptor based operation ? supports external per ipheral dma operations ? supports unaligned transfers (i.e., source or destination address may be on any byte boundary) with arbitrary byte length. two ethernet interfaces ? 10 and 100 mb/s iso/iec 8802-3:1996 compliant ? two ieee 802.3u compatible media independent interfac es (mii) with serial management interface ? mii supports ieee 802.3u auto-negotiation speed selection ? supports 64 entry hash table based multicast address filtering ? 512 byte transmit and receive fifos ? supports flow control functions outlined in ieee std. 802.3x-1997 pci interface ? 32-bit pci revision 2.2 compliant ? supports host or satellite operation in both master and target modes ? pci clock ? supports pci clock frequencie s from 16 mhz to 66 mhz ? pci clock may be asynchronous to master clock (clk) ? pci arbiter in host mode ? supports 6 external masters ? fixed priority or round robin arbitration ? i 2 o ?like? pci messaging unit universal asynchronous receiver transmitter (uart) ? compatible with the 16550 and 16450 uarts ? two completely separate serial channels ? modem control functions (cts, rts, dsr, dtr, ri, dcd) ? 16-byte transmit and receive buffers ? programmable baud rate generator derived from the system clock ? fully programmable seri al characteristics: ? 5, 6, 7, or 8 bit characters ? even, odd or no parity bit generation and detection ? 1, 1-1/2 or 2 stop bit generation ? line break generation and detection ? false start bit detection ? internal loopback mode i 2 c-bus ? supports standard 100 kbps mode as well as 400 kbps fast mode ? supports 7-bit and 10-bit addressing
idt rc32438 device overview system identification 79rc32438 user reference manual 1 - 5 november 4, 2002 notes ? supports four modes: ? master transmitter ? master receiver ? slave transmitter ? slave receiver serial peripheral interface (spi) ? supports master mode general purpose i/o controller ? 32 general purpose input/output pins ? each pin may be used as an active high or active low level interrupt or non-maskable interrupt input ? each signal may be used as bit input or output port on-chip memory ? 4 kb of high speed sram organized as 1k x 32 bits ? supports burst and non-burst word, half-wo rd, and byte cpu, pci, and dma accesses on-chip debugging support ? ipbus monitor provides an on-chip ?logi c analyzer? for hardware and software debugging ? eight 24-bit statistics counters ? external debug support pins provide exter nal visibility to internal operation enhanced jtag and ice interface ? compatible with ieee std. 1149.1-1990 system identification in addition to the mips processor revi sion identification (prid) register located in cp0 of the cpu, the rc32438 contains a system identificati on register (sysid). the sysid register, which is always located at address 0x1800_0018, may be used by software to det ermine the vendor, implementation, and revision of an integrated processor. the format for this register is shown in figure 1.2. figure 1.2 system identification register (sysid) rev description: revision. this field contains the revision of the integrated processor. it may be used by software to identify the revision of a particular implementation. initial value: 0x0 read value: revision number write effect: read-only imp description: implementation. this field contains the implementation id of the integrated processor. rc32438 ? 6 sysid 0 31 8 rev 12 vendor 12 imp
idt rc32438 device overview system identification 79rc32438 user reference manual 1 - 6 november 4, 2002 notes initial value: 0x6 read value: implementation write effect: read-only vendor description: vendor. this field contains the vendor of the integrated processor. the currently defined vendor is: 0 integrated device technology initial value: 0x0 read value: vendor write effect: read-only
idt rc32438 device overview logic diagram ? rc32438 79rc32438 user reference manual 1 - 7 november 4, 2002 notes logic diagram ? rc32438 figure 1.3 logic diagram for the rc32438 miscellaneous signals memory and peripheral bus clk coldrstn rstn 4 miimdc miimdio mii0cl mii0crs mii0rxclk mii0rxd[3:0] mii0rxdv mii0rxer mii0txclk mii0txd[3:0] mii0txenp mii0txer mii1cl mii1crs mii1rxclk mii1rxd[3:0] mii1rxdv mii1rxer mii1txclk mii1txd[3:0] mii1txenp mii1txer bdirn bgn boen brn bwen[1:0] csn[5:0] maddr[21:0] mdata[15:0] oen rwn waitackn ddraddr[13:0] ddrba[1:0] ddrcasn ddrcke ddrckn[1:0] ddrckp[1:0] ddrcsn[1:0] ddrdata[31:0] ddrdm[7:0] ddrdqs[3:0] ddrrasn ddrvref ddrwen pciad[31:0] pcicben[3:0] pciclk pcidevseln pciframen pcigntn[3:0] pciirdyn pcilockn pcipar pciperrn pcireqn[3:0] pcirstn pciserrn pcistopn pcitrdyn gpio[31:0] sdo sda scl jtag_tck jtag_tdi jtag_tdo jtag_tms jtag_trst_n inst cpu ipbmtrigout 4 4 4 32 4 4 4 32 4 8 32 2 2 2 2 14 16 22 6 2 ejtag / ice signals debug signals general purpose i/o i 2 c-bus serial i/o pci bus ddr bus ethernet rc32438 vcccore vcci/o vss vccp (pll) vssp (pll) power/ground sdi sck ddroen[3:0] 4 ejtag_tms extclk plltest
idt rc32438 device overview pin characteristics 79rc32438 user reference manual 1 - 8 november 4, 2002 notes pin characteristics function pin name type buffer i/o type internal resistor notes 1 memory and peripheral bus bdirn o lvttl high drive bgn o lvttl low drive boen o lvttl high drive brn i lvttl sti 2 pull-up bwen[1:0] o lvttl high drive csn[5:0] o lvttl high drive maddr[21:0] o lvttl high drive mdata[15:0] i/o lvttl high drive oen o lvttl high drive rwn o lvttl high drive waitackn i lvttl sti pull-up ddr bus ddraddr[13:0] o sstl_2 sstl_2 ddrba[1:0] o sstl_2 sstl_2 ddrcasn o sstl_2 sstl_2 ddrcke o sstl_2 / lvcmos sstl_2 ddrckn[1:0] o sstl_2 sstl_2 ddrckp[1:0] o sstl_2 sstl_2 ddrcsn[1:0] o sstl_2 sstl_2 ddrdata[31:0] i/o sstl_2 sstl_2 ddrdm[7:0] i/o sstl_2 sstl_2 ddrdqs[3:0] i/o sstl_2 sstl_2 ddroen[3:0] o sstl_2 sstl_2 ddrrasn o sstl_2 sstl_2 ddrvref i analog sstl_2 ddrwen o sstl_2 sstl_2 table 1 pin characteristics (part 1 of 4)
idt rc32438 device overview pin characteristics 79rc32438 user reference manual 1 - 9 november 4, 2002 notes pci bus interface pciad[31:0] i/o pci pci pcicben[3:0] i/o pci pci pciclk i pci pci pcidevseln i/o pci pci pull-up on board pciframen i/o pci pci pull-up on board pcigntn[3:0] i/o pci pci pull-up on board pciirdyn i/o pci pci pull-up on board pcilockn i/o pci pci pcipar i/o pci pci pciperrn i/o pci pci pcireqn[3:0] i/o pci pci pull-up on board pcirstn i/o pci pci pull-down on board pciserrn i/o pci open col- lector; pci pull-up on board pcistopn i/o pci pci pull-up on board pcitrdyn i/o pci pci pull-up on board general purpose i/o gpio[23:0] i/o lvttl low drive pull-up gpio[24] i/o pci pull-up on board gpio[25] i/o lvttl pull-up gpio[30:26] 3 i/o pci pull-up on board gpio[31] i/o lvttl low drive pull-up serial interface sck i/o lvttl low drive pull-up pull-up on board sdi i/o lvttl low drive pull-up pull-up on board sdo i/o lvttl low drive pull-up pull-up on board i 2 c bus interface scl i/o lvttl low drive / sti pull-down pull-down on board sda i/o lvttl low drive / sti pull-up pull-up on board function pin name type buffer i/o type internal resistor notes 1 table 1 pin characteristics (part 2 of 4)
idt rc32438 device overview pin characteristics 79rc32438 user reference manual 1 - 10 november 4, 2002 notes ethernet interfaces mii0cl i lvttl sti pull-down mii0crs i lvttl sti pull-down mii0rxclk i lvttl sti pull-up mii0rxd[3:0] i lvttl sti pull-up mii0rxdv i lvttl sti pull-down mii0rxer i lvttl sti pull-down mii0txclk i lvttl sti pull-up mii0txd[3:0] o lvttl low drive mii0txenp o lvttl low drive mii0txer o lvttl low drive mii1cl i lvttl sti pull-down mii1crs i lvttl sti pull-down mii1rxclk i lvttl sti pull-up mii1rxd[3:0] i lvttl sti pull-up mii1rxdv i lvttl sti pull-down mii1rxer i lvttl sti pull-down mii1txclk i lvttl sti pull-up mii1txd[3:0] o lvttl low drive mii1txenp o lvttl low drive mii1txer o lvttl low drive miimdc o lvttl low drive miimdio i/o lvttl low drive pull-up ejtag / ice jtag_trst_n i lvttl sti pull-up jtag_tck i lvttl sti pull-up jtag_tdi i lvttl sti pull-up jtag_tdo o lvttl low drive jtag_tms i lvttl sti pull-up ejtag_tms i lvttl sti pull-up debug cpu o lvttl low drive inst o lvttl low drive ipbmtrigout o lvttl low drive plltest o lvttl low drive function pin name type buffer i/o type internal resistor notes 1 table 1 pin characteristics (part 3 of 4)
idt rc32438 device overview pin description 79rc32438 user reference manual 1 - 11 november 4, 2002 notes pin description the following table lists the function of the pins pr ovided on the rc32438. some of the functions listed may be multiplexed onto the same pin. miscellaneous clk i lvttl sti extclk o lvttl high drive coldrstn i lvttl sti rstn i/o lvttl low drive / sti pull-up pull-up on board 1. external pull-up required in most system applications. some applications may require additional pull-ups not identified in this table. 2. schmidt trigger input (sti) 3. pcimuintn is an alternate function of gpio[30]. when configured as an alternate function, this pin is tri-stated when not as- serted (i.e., it acts as an open collector output). signal type name/description system clk i master clock. this is the master clock input. the processor frequency is a mul- tiple of this clock frequency. this clock is used as the system clock for all mem- ory and peripheral bus operations. extclk o external clock. this clock is used for all memory and peripheral bus opera- tions. coldrstn i cold reset. the assertion of this signal initiates a cold reset. this causes the processor state to be initialized, boot configuration to be loaded, and the internal pll to lock onto the master clock (clk). rstn i/o reset. the assertion of this bidirectional signal initiates a warm reset. this sig- nal is asserted by the rc32438 during a warm reset. memory and peripheral bus bdirn o external buffer direction. memory and peripheral bus external data bus buffer direction control. if the rc32438 memory and peripheral bus is connected to the a side of a transceiver such as an idt74fct245, then this pin may be directly connected to the direction control (e.g., bdir) pin of the transceiver. bgn o bus grant. this signal is asserted by the rc32438 to indicate that the rc32438 has relinquished ownership of the memory and peripheral bus. boen o external buffer enable. this signal provides an output enable control for an external buffer on the memory and peripheral data bus. brn i bus request. this signal is asserted by an external device to request owner- ship of the memory and peripheral bus. bwen[1:0] o byte write enables. these signals are memory and peripheral bus by write enable signals. bwen[0] corresponds to byte lane mdata[7:0] bwen[1] corresponds to byte lane mdata[15:8] table 1.1 pin description (part 1 of 9) function pin name type buffer i/o type internal resistor notes 1 table 1 pin characteristics (part 4 of 4)
idt rc32438 device overview pin description 79rc32438 user reference manual 1 - 12 november 4, 2002 notes csn[5:0] o chip selects. these signals are used to select an external device on the mem- ory and peripheral bus. maddr[21:0] o address bus. 22-bit memory and peripheral bus address bus. maddrp[25:22] are available as gpio alternate functions mdata[15:0] i/o data bus. 16-bit memory and peripheral data bus. during a cold reset, these pins function as inputs that are used to load the boot configuration vector. oen o output enable. this signal is asserted when data should be driven on by an external device on the memory and peripheral bus. rwn o read write. this signal indicates if the transaction on the memory and periph- eral bus is a read transaction or a write transaction. a high level indicates a read from an external device. a low level indicates a write to an external device. waitackn i wait or transfer acknowledge. when configured as wait, this signal is asserted during a memory and peripheral bus transaction to extend the bus cycle. when configured as a transfer acknowledge, this signal is asserted during a transaction to signal the completion of the transaction. ddr bus ddraddr[13:0] o ddr address bus. 13-bit multiplexed ddr bus address bus. this bus is used to transfer the addresses to the ddrs. ddrba[1:0] o ddr bank address. these signals are used to transfer the bank address to the ddrs. ddrcasn o ddr column address strobe. ddr column address strobe which is asserted during ddr transactions. ddrcke o ddr clock enable. ddr clock enable which is asserted during normal ddr operation. this signal is negated during following a cold reset or during a power down operation. ddrckn[1:0] i/o ddr negative ddr clock. these signals are the negative clock of the differen- tial ddr clock pair. two copies of this output are provided to reduce signal load- ing. ddrckp[1:0] i/o ddr positive ddr clock. these signals are the positive clock of the differen- tial ddr clock pair. two copies of this output are provided to reduce signal load- ing. ddrcsn[1:0] o ddr chip selects. these active low signals are used to select ddr device(s) on the ddr bus. ddrdata[31:0] i/o ddr data bus. 32-bit ddr data bus used to transfer data between the rc32438 and the ddr(s). data is transferred on both edges of the clock. ddrdm[7:0] i/o ddr data write enables. byte data write enables are used to enable specific byte lanes during ddr writes. ddrdm[0] corresponds to ddrdata[7:0] ddrdm[1] corresponds to ddrdata[15:8] ddrdm[2] corresponds to ddrdata[23:16] ddrdm[3] corresponds to ddrdata[31:24] ddrdm[4] corresponds to ddrdata[39:32] ddrdm[5] corresponds to ddrdata[47:40] ddrdm[6] corresponds to ddrdata[55:48] ddrdm[7] corresponds to ddrdata[54:56] (refer to the ddr data bus multiplexing section in chapter 7.) signal type name/description table 1.1 pin description (part 2 of 9)
idt rc32438 device overview pin description 79rc32438 user reference manual 1 - 13 november 4, 2002 notes ddrdqs[3:0] i/o ddr data strobes. ddr byte data strobes are used to clock data between ddrs and the rc32438. these strobes ar e inputs during ddr reads and out- puts during ddr writes. ddrdqs[0] corresponds to ddrdata[7:0]. ddrdqs[1] corresponds to ddrdata[15:8]. ddrdqs[2] corresponds to ddrdata[23:16]. ddrdqs[3] corresponds to ddrdata[31:24]. ddroen[3:0] o ddr bus switch output enables. in systems that support data bus multiplex- ing, these pins are used to enable external data bus switches. ddrrasn o ddr row address strobe. ddr row address strobe is asserted during ddr transactions. ddrvref i ddr voltage reference. sstl_2 ddr voltage reference generated by an external source. ddrwen o ddr write enable. ddr write enable which is asserted during ddr write trans- actions. pci bus pciad[31:0] i/o pci multiplexed address/data bus . address is driven by a bus master during initial pciframen assertion. data is then driven by the bus master during writes or by the bus target during reads. pcicben[3:0] i/o pci multiplexed command/byte enable bus . pci command is driven by the bus master during the initial pciframen assertion. byte enables are driven by the bus master during subsequent data phase(s). pciclk i pci clock . clock used for all pci bus transactions. pcidevseln i/o pci device select . this signal is driven by a bus target to indicate that the tar- get has decoded the address as one of its own address spaces. pciframen i/o pci frame . driven by a bus master. assertion indicates the beginning of a bus transaction. negation indicates the last datum. pcigntn[3:0] i/o pci bus grant . in pci host mode with internal arbiter: the assertion of these signals indicates to the agent that the internal rc32438 arbiter has granted the agent access to the pci bus. in pci host mode with external arbiter: pcigntn[0]: asserted by an external arbiter to indicate to the rc32438 that access to the pci bus has been granted. pcigntn[3:1]: unused and driven high. in pci satellite mode: pcigntn[0]: this signal is asserted by an external arbiter to indicate to the rc32438 that access to the pci bus has been granted. pcigntn[1]: this signal takes on the alternate function of pcieecs and is used as a pci serial eepr om chip select. pcigntn[3:2]: unused and driven high. note : when the gpio register is programmed in the alternate function mode for bits gpio [26] and [28], these bits be come pcigntn [4] and [5] respectively. pciirdyn i/o pci initiator ready . driven by the bus master to indicate that the current datum can complete. signal type name/description table 1.1 pin description (part 3 of 9)
idt rc32438 device overview pin description 79rc32438 user reference manual 1 - 14 november 4, 2002 notes pcilockn i/o pci lock . this signal is asserted by an external bus master to indicate that an exclusive operation is occurring. pcipar i/o pci parity . even parity of the pciad[31:0] bus. driven by the bus master during address and write data phases. driven by the bus target during the read data phase. pciperrn i/o pci parity error . this signal is asserted by the receiving bus agent 2 clocks after the data is received if a parity error was detected. pcireqn[3:0] i/o pci bus request. in pci host mode with internal arbiter: these signals are inputs whose assertion indicates to the internal rc32438 arbiter that an agent desires ownership of the pci bus. in pci host mode with external arbiter: pcireqn[0]: asserted by the rc32438 to request ownership of the pci bus. pcireqn[3:1]: unused and driven low. in pci satellite mode: pcireqn[0]: this signal is asserted by the rc32438 to request use of the pci bus. pcireqn[1]: pciidselp and is used as a chip select during configuration read and write transactions. pcireqn[3:2]: unused and driven low. note : when the gpio register is programmed in the alternate function mode for bits gpio [24] and [27], these bits be come pcireqn [4] and [5] respectively. pcirstn i/o pci reset . in host mode this signal is asserted by the rc32438 to generate a pci reset. in satellite mode, assertion of this signal initiates a warm reset. pciserrn i/o pci system error . this signal is driven by an agent to indicate an address par- ity error, data parity error during a special cycle command, or any other system error. requires an external pull-up. pcistopn i/o pci stop . driven by the bus target to terminate the current bus transaction for example to indicate a retry. pcitrdyn i/o pci target ready . driven by the bus target to indicate that the current datum can complete. general purpose input/output gpio[0] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u0sout alternate function: uart channel 0 serial output gpio[1] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u0sinp alternate function: uart channel 0 serial input gpio[2] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u0rin alternate function: uart channel 0 ring indicator signal type name/description table 1.1 pin description (part 4 of 9)
idt rc32438 device overview pin description 79rc32438 user reference manual 1 - 15 november 4, 2002 notes gpio[3] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u0dcdn alternate function: uart channel 0 data carrier detect gpio[4] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u0dtrn alternate function: uart channel 0 data terminal ready gpio[5] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u0dsrn alternate function: uart channel 0 data set ready gpio[6] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u0rtsn alternate function: uart channel 0 request to send gpio[7] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u0ctsn alternate function: uart channel 0 clear to send gpio[8] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u1sout alternate function: uart channel 1 serial output gpio[9] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u1sinp alternate function: uart channel 1 serial input gpio[10] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u1dtrn alternate function: uart channel 1 data terminal ready gpio[11] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u1dsrn alternate function: uart channel 1 data set ready gpio[12] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u1rtsn alternate function: uart channel 1 request to send gpio[13] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u1ctsn alternate function: uart channel 1 clear to send gpio[14] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: dmareqn0 alternate function: external dma channel 0 request signal type name/description table 1.1 pin description (part 5 of 9)
idt rc32438 device overview pin description 79rc32438 user reference manual 1 - 16 november 4, 2002 notes gpio[15] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: dmareqn1 alternate function: external dma channel 1 request gpio[16] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: dmadonen0 alternate function: external dma channel 0 done gpio[17] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: dmadonen1 alternate function: external dma channel 1 done gpio[18] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: dmafinn0 alternate function: external dma channel 0 finished gpio[19] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: dmafinn1 alternate function: external dma channel 1 finished gpio[20] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: maddr[22] alternate function: memory and peripheral bus address gpio[21] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: maddr[23] alternate function: memory and peripheral bus address gpio[22] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: maddr[24] alternate function: memory and peripheral bus address gpio[23] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: maddr[25] alternate function: memory and peripheral bus address gpio[24] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: pcireqn[4] alternate function: pci request 4 gpio[25] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: afspare1 alternate function: reserved gpio[26] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: pcigntn[4] alternate function: pci grant 4 signal type name/description table 1.1 pin description (part 6 of 9)
idt rc32438 device overview pin description 79rc32438 user reference manual 1 - 17 november 4, 2002 notes gpio[27] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: pcireqn[5] alternate function: pci request 5 gpio[28] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: pcigntn[5] alternate function: pci grant 5 gpio[29] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ipbmtriginp alternate function: ipbus monitor trigger input gpio[30] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: pcimuintn alternate function: pci messaging unit interrupt output gpio[31] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. spi interface sck i/o serial clock . this signal is used as the serial clock output in spi mode and in pci satellite mode with suspended cpu execution during pci serial eeprom loading. this pin may be used as a bit input/output port. sdi i/o serial data input . this signal is used to shift in serial data in spi mode and in pci satellite mode with suspended cpu execution during pci serial eeprom loading. this pin may be used as a bit input/output port. sdo i/o serial data output . this signal is used shift out serial data in spi mode and in pci satellite mode with suspended cpu execution during pci serial eeprom loading. this pin may be used as a bit input/output port. i 2 c bus interface scl i/o i 2 c clock. i 2 c-bus clock. sda i/o i 2 c data bus. i 2 c-bus data bus. ethernet interfaces mii0cl i ethernet 0 mii collision detected. this signal is asserted by the ethernet phy when a collision is detected. mii0crs i ethernet 0 mii carrier sense. this signal is asserted by the ethernet phy when either the transmit or receive medium is not idle. mii0rxclk i ethernet 0 mii receive clock. this clock is a continuous clock that provides a timing reference for the reception of data. mii0rxd[3:0] i ethernet 0 mii receive data. this nibble wide data bus contains the data received by the ethernet phy. mii0rxdv i ethernet 0 mii receive data valid. the assertion of this signal indicates that valid receive data is in the mii receive data bus. mii0rxer i ethernet 0 mii receive error. the assertion of this signal indicates that an error was detected somewhere in the ethernet frame currently being sent in the mii receive data bus. signal type name/description table 1.1 pin description (part 7 of 9)
idt rc32438 device overview pin description 79rc32438 user reference manual 1 - 18 november 4, 2002 notes mii0txclk i ethernet 0 mii transmit clock. this clock is a continuous clock that provides a timing reference for the transfer of transmit data. mii0txd[3:0] o ethernet 0 mii transmit data. this nibble wide data bus contains the data to be transmitted. mii0txenp o ethernet 0 mii transmit enable. the assertion of this signal indicates that data is present on the mii for transmission. mii0txer o ethernet 0 mii transmit coding error. when this signal is asserted together with miitxenp, the ethernet phy will transmit symbols which are not valid data or delimiters. mii1cl i ethernet 1 mii collision detected. this signal is asserted by the ethernet phy when a collision is detected. mii1crs i ethernet 1 mii carrier sense. this signal is asserted by the ethernet phy when either the transmit or receive medium is not idle. mii1rxclk i ethernet 1 mii receive clock. this clock is a continuous clock that provides a timing reference for the reception of data. mii1rxd[3:0] i ethernet 1 mii receive data. this nibble wide data bus contains the data received by the ethernet phy. mii1rxdv i ethernet 1 mii receive data valid. the assertion of this signal indicates that valid receive data is in the mii receive data bus. mii1rxer i ethernet 1 mii receive error. the assertion of this signal indicates that an error was detected somewhere in the ethernet frame currently being sent in the mii receive data bus. mii1txclk i ethernet 1 mii transmit clock. this clock is a continuous clock that provides a timing reference for the transfer of transmit data. mii1txd[3:0] o ethernet 1 mii transmit data. this nibble wide data bus contains the data to be transmitted. mii1txenp o ethernet 1 mii transmit enable. the assertion of this signal indicates that data is present on the mii for transmission. mii1txer o ethernet 1 mii transmit coding error. when this signal is asserted together with miitxenp, the ethernet phy will transmit symbols which are not valid data or delimiters. miimdc o mii management data clock. this signal is used as a timing reference for transmission of data on the management interface. miimdio i/o mii management data. this bidirectional signal is used to transfer data between the station management entity and the ethernet phy. ejtag/ice ejtag_tms i ejtag mode . the value on this signal controls test operation of the ejtag controller. jtag_tck i jtag clock . this is an input test clock, used to clock the shifting of data into or out of the boundary scan logic, jtag controller or the ejtag controller. jtag_tck is independent of the system and the processor clock with nominal 50% duty cycle. jtag_tdi i jtag data input . jtag mode: this is the serial data input to where data is shifted into the boundary scan logic, jtag controller, or the ejtag controller. signal type name/description table 1.1 pin description (part 8 of 9)
idt rc32438 device overview pin description 79rc32438 user reference manual 1 - 19 november 4, 2002 notes jtag_tdo o jtag data output . jtag mode: this is the serial data shifted out from the boundary scan logic, jtag controller, or the ejtag controller. when no data is being shifted out, this signal is tri-stated. jtag_tms i jtag mode . the value on this signal controls test operation of the boundary scan logic or jtag controller. jtag_trst_n i jtag reset . this active low signal asynchronously resets the boundary scan logic, jtag tap controller, and the ej tag debug tap controller. an external pull-up on the board is recommended to meet the jtag specification in cases where the tester can access this signal, however, specific systems when run- ning in functional mode ordinarily should either: 1) drive low this signal 2) use an external pull-down on the board 3) clock jtag_tck. debug cpu o cpu transaction. this signal is asserted during all cpu instruction fetches and data transfers to/from the ddr and devices on the memory and peripheral bus. the signal is negated during pci and dma transactions to/from the ddr and devices on the memory and peripheral bus. inst o instruction or data. this signal is driven high during cpu instruction fetches on the memory and peripheral bus memory or ddr bus. ipbmtrigout o ipbus monitor trigger output. this signal is asserted for one master clock (clk) clock cycle when the ipbus monitor triggers. signal type name/description table 1.1 pin description (part 9 of 9)
idt rc32438 device overview default memory map 79rc32438 user reference manual 1 - 20 november 4, 2002 notes default memory map the rc32438 contains 2 initially-enabled physical address regions. they are: b oot device region (i.e., device 0) and an internal register region. associ ated with each memory region (i.e., device, ddr, or on- chip memory) is a base and mask register pair. when a bit in the mask register is set, then the corre- sponding physical address bit generated by the cpu parti cipates in address comparisons for the region. if a bit in the mask register is cleared, then the co rresponding physical address bit does not participate in address comparisons for the region. when the cpu, pci, or dma controller generates a physical address, the address is compared with all non-masked bits in each base register. if all non-masked physical address bits match a base register, then the corresponding addr ess region is selected. if no base register matches or if multiple base registers match, then no regi on is selected and the address space monitor reports an error (see chapter 4, system integrity). the initial default memory map following a cold rese t is shown in table 1.2. software may alter this default configuration by modifyi ng the base and mask registers. ba se and mask registers should not be modified for the region(s) from which the cpu is executing. physical address range size rc32438 memory region reset initialization 0x0000_0000 to 0x17ff_ffff 384 mb unused 0x1800_0000 to 0x181f_ffff 2 mb rc32438 internal registers 0x1820_0000 to 0x1bff_ffff 62 mb unused 0x1c00_0000 to 0x1fff_ffff 64 mb device 0 (csn[0]) dev0base 0x1c00 dev0mask 0xfc00 0x2000_0000 to 0xffff_ffff approx. 3 gb unused table 1.2 rc32438 default memo ry map following a cold reset
idt rc32438 device overview rc32438 internal register map 79rc32438 user reference manual 1 - 21 november 4, 2002 notes rc32438 internal register map the physical address of a rc32438 internal register is equal to the register offset, shown in table 1.3, added to the base value 0x1800_0000. the rc32438 internal register region is not fully decoded. 1 unless otherwise noted, all registers should be accessed as aligned 32-bit quantities. also , all internal registers should be accessed through non-cacheable addresses. 1. addresses for each function may be partitioned into two r egions. region one includes addresses from the start of the function?s address range to one less than the lowest address that modulo 256 is zero and which is greater than or equal to the highest defined register for that function. region two consists of those function addresses not in region one. for the system identification function, region one would consist of 0x00_0000 through 0x00_00ff and region two could consist of 0x00_0100 through 0x00_7fff. reads from a region one reserved address return zero. writes to a region one reserved address are ignored. reads and writes to region two result in an undecoded address error. for more information, see the address space monitor section in chapter 4. function register offset register name register function system identification 0x00_0000 through 0x00_0017 reserved 0x00_0018 sysid system identification 0x00_001c reserved 0x00_0020 through 0x00_7fff reserved reset and initialization 0x00_8000 reset reset 0x00_8004 bcv boot configuration 0x00_8008 1 cea cpu error address note : this register can only be accessed by the cpu. it cannot be accessed by ipbus masters. 0x00_800c through 0x00_ffff reserved device controller 0x01_0 000 dev0base device 0 base 0x01_0004 dev0mask device 0 mask 0x01_0008 dev0c device 0 control 0x01_000c dev0tc device 0 timing control 0x01_0010 dev1base device 1 base 0x01_0014 dev1mask device 1 mask 0x01_0018 dev1c device 1 control 0x01_001c dev1tc device 1 timing control 0x01_0020 dev2base device 2 base 0x01_0024 dev2mask device 20 mask 0x01_0028 dev2c device 2 control 0x01_002c dev2tc device 2 timing control 0x01_0030 dev3base device 3 base 0x01_0034 dev3mask device 3 mask table 1.3 internal register map (part 1 of 12)
idt rc32438 device overview rc32438 internal register map 79rc32438 user reference manual 1 - 22 november 4, 2002 notes 0x01_0038 dev3c device 3 control 0x01_003c dev3tc device 3 timing control device controller (cont.) 0x01_0040 dev4base device 4 base 0x01_0044 dev4mask device 40 mask 0x01_0048 dev4c device 4 control 0x01_004c dev4tc device 4 timing control 0x01_0050 dev5base device 5 base 0x01_0054 dev5mask device 5 mask 0x01_0058 dev5c device 5 control 0x01_005c dev5tc device 5 timing control 0x01_0060 btcs bus timer control and status 0x01_0064 btcompare bus transaction timer compare 0x01_0068 btaddr bus transaction timer address 0x01_006c devdacs device decoupled access control and status 0x01_0070 devdaa device decoupled access address 0x01_0074 devdad device decoupled access data 0x01_0078 through 0x01_7fff reserved ddr controller 0x01_8000 ddr0base ddr 0 base 0x01_8004 ddr0mask ddr 0 mask 0x01_8008 ddr1base ddr 1 base 0x01_800c ddr1mask ddr 1 mask 0x01_8010 ddrc ddr control 0x01_8014 ddr0abase ddr 0 alternate base 0x01_8018 ddr0amask ddr 0 alternate mask 0x01_801c ddr0amap ddr 0 alternate mapping 0x01_8020 ddrcust ddr custom transaction 0x01_8024 through 0x01_bfff reserved pmbus arbiter 0x02_0000 pmapp pmbus arbiter processor priority 0x02_0004 pmasac pmbus arbiter sneak access con- trol 0x02_0008 through 0x02_7fff reserved counter/timers 0x02_8000 count0 counter timer 0 count 0x02_8004 compare0 counter timer 0 compare 0x02_8008 ctc0 counter timer 0 control 0x02_800c count1 counter timer 1 count function register offset register name register function table 1.3 internal register map (part 2 of 12)
idt rc32438 device overview rc32438 internal register map 79rc32438 user reference manual 1 - 23 november 4, 2002 notes 0x02_8010 compare1 counter timer 1 compare 0x02_8014 ctc1 counter timer 1 control 0x02_8018 count2 counter timer 2 count 0x02_801c compare2 counter timer 2 compare 0x02_8020 ctc2 counter timer 2 control 0x02_8024 rcount refresh timer count 0x02_8028 rcompare refresh timer compare 0x02_802c rtc refresh timer control 0x02_8030 thro ugh 0x02_ffff reserved system integrity functions 0x03_0000 through 0x03_002c reserved 0x03_0030 errcs error control and status 0x03_0034 wtcount watchdog timer count 0x03_0038 wtcompare watchdog timer compare 0x03_003c wtc watchdog timer control 0x03_0040 through 0x03_7fff reserved interrupt controller 0x03_8000 ipend2 interrupt pending 2 0x03_8004 itest2 interrupt test 2 0x03_8008 imask2 interrupt mask 2 0x03_800c ipend3 interrupt pending 3 0x03_8010 itest3 interrupt test 3 0x03_8014 imask3 interrupt mask 3 0x03_8018 ipend4 interrupt pending 4 0x03_801c itest4 interrupt test 4 0x03_8020 imask4 interrupt mask 4 0x03_8024 ipend5 interrupt pending 5 0x03_8028 itest5 interrupt test 5 0x03_802c imask5 interrupt mask 5 0x03_8030 ipend6 interrupt pending 6 0x03_8034 itest6 interrupt test 6 0x03_8038 imask6 interrupt mask 6 0x03_803c nmips non-maskable interrupt pin status 0x03_8040 thro ugh 0x03_ffff reserved dma controller 0x04_0000 dma0c dma 0 control 0x04_0004 dma0s dma 0 status 0x04_0008 dma0sm dma 0 status mask function register offset register name register function table 1.3 internal register map (part 3 of 12)
idt rc32438 device overview rc32438 internal register map 79rc32438 user reference manual 1 - 24 november 4, 2002 notes 0x04_000c dma0dptr dma 0 descriptor pointer 0x04_0010 dma0ndptr dma 0 next descriptor pointer 0x04_0014 dma1c dma 1 control dma controller (cont.) 0x04_0018 dma1s dma 1 status 0x04_001c dma1sm dma 1 status mask 0x04_0020 dma1dptr dma 1 descriptor pointer 0x04_0024 dma1ndptr dma 1 next descriptor pointer 0x04_0028 dma2c dma 2 control 0x04_002c dma2s dma 2 status 0x04_0030 dma2sm dma 2 status mask 0x04_0034 dma2dptr dma 2 descriptor pointer 0x04_0038 dma2ndptr dma 2 next descriptor pointer 0x04_003c dma3c dma 3 control 0x04_0040 dma3s dma 3 status 0x04_0044 dma3sm dma 3 status mask 0x04_0048 dma3dptr dma 3 descriptor pointer 0x04_004c dma3ndptr dma 3 next descriptor pointer 0x04_0050 dma4c dma 4 control 0x04_0054 dma4s dma 4 status 0x04_0058 dma4sm dma 4 status mask 0x04_005c dma4dptr dma 4 descriptor pointer 0x04_0060 dma4ndptr dma 4 next descriptor pointer 0x04_0064 dma5c dma 5 control 0x04_0068 dma5s dma 5 status 0x04_006c dma5sm dma 5 status mask 0x04_0070 dma5dptr dma 5 descriptor pointer 0x04_0074 dma5ndptr dma 5 next descriptor pointer 0x04_0078 dma6c dma 6 control 0x04_007c dma6s dma 6 status 0x04_0080 dma6sm dma 6 status mask 0x04_0084 dma6dptr dma 6 descriptor pointer 0x04_0088 dma6ndptr dma 6 next descriptor pointer 0x04_008c dma7c dma 7 control 0x04_0090 dma7s dma 7 status 0x04_0094 dma7sm dma 7 status mask 0x04_0098 dma7dptr dma 7 descriptor pointer function register offset register name register function table 1.3 internal register map (part 4 of 12)
idt rc32438 device overview rc32438 internal register map 79rc32438 user reference manual 1 - 25 november 4, 2002 notes 0x04_009c dma7ndptr dma 7 next descriptor pointer 0x04_00a0 dma8c dma 8 control 0x04_00a4 dma8s dma 8 status dma controller (cont.) 0x04_00a8 dma8sm dma 8 status mask 0x04_00ac dma8dptr dma 8 descriptor pointer 0x04_00b0 dma8ndptr dma 8 next descriptor pointer 0x04_00b4 dma9c dma 9 control 0x04_00b8 dma9s dma 9 status 0x04_00bc dma9sm dma 9 status mask 0x04_00c0 dma9dptr dma 9 descriptor pointer 0x04_00c4 dma9ndptr dma 9 next descriptor pointer 0x04_00c8 dma10c dma 10 control 0x04_00cc dma10s dma 10 status 0x04_00d0 dma10sm dma 10 status mask 0x04_00d4 dma10dptr dma 10 descriptor pointer 0x04_00d8 dma10ndptr dma 10 next descriptor pointer 0x04_00dc dma11c dma 11 control 0x04_00e0 dma11s dma 11 status 0x04_00e4 dma11sm dma 11 status mask 0x04_00e8 dma11dptr dma 11 descriptor pointer 0x04_00ec dma11ndptr dma 11 next descriptor pointer 0x04_00f0 dma12c dma 12 control 0x04_00f4 dma12s dma 12 status 0x04_00f8 dma12sm dma 12 status mask 0x04_00fc dma12dptr dma 12 descriptor pointer 0x04_0100 dma12ndptr dma 12 next descriptor pointer 0x04_0104 through 0x04_3fff reserved ipbus arbiter 0x04_4000 ipap0c ipbus arbiter priority 0 configura- tion 0x04_4004 ipap1c ipbus arbiter priority 1 configura- tion 0x04_4008 ipap2c ipbus arbiter priority 2 configura- tion 0x04_400c ipap3c ipbus arbiter priority 3 configura- tion 0x04_4010 ipabm0c ipbus arbiter bus master 0 config- uration function register offset register name register function table 1.3 internal register map (part 5 of 12)
idt rc32438 device overview rc32438 internal register map 79rc32438 user reference manual 1 - 26 november 4, 2002 notes 0x04_4014 ipabm1c ipbus arbiter bus master 1 config- uration 0x04_4018 ipabm2c ipbus arbiter bus master 2 config- uration ipbus arbiter (cont.) 0x04_401c ipabm3c ipbus arbiter bus master 3 config- uration 0x04_4020 ipabm4c ipbus arbiter bus master 4 config- uration 0x04_4024 ipabm5c ipbus arbiter bus master 5 config- uration 0x04_4028 ipabm6c ipbus arbiter bus master 6 config- uration 0x04_402c ipabm7c ipbus arbiter bus master 7 config- uration 0x04_4030 ipabm8c ipbus arbiter bus master 8 config- uration 0x04_4034 ipabm9c ipbus arbiter bus master 9 config- uration 0x04_4038 through 0x04_4040 reserved 0x04_4044 ipabm13c ipbus arbiter bus master 13 con- figuration 0x04_4048 ipabm14c ipbus arbiter bus master 14 con- figuration 0x04_404c ipabm15c ipbus arbiter bus master 15 con- figuration 0x04_4050 ipabm16c ipbus arbiter bus master 16 con- figuration 0x04_4054 ipac ipbus arbiter control 0x04_4058 ipaitcc ipbus arbiter idle transaction cycle count 0x04_405c through 0x04_7fff reserved gpio controller 0x04_8000 gpiofunc gpio function 0x04_8004 gpiocfg gpio configuration 0x04_8008 gpiod gpio data 0x04_800c gpioilevel gpio interrupt level 0x04_8010 gpioistat gpio interrupt status 0x04_8014 gpionmien gpio nonmaskable interrupt enable 0x04_8018 thro ugh 0x04_ffff reserved function register offset register name register function table 1.3 internal register map (part 6 of 12)
idt rc32438 device overview rc32438 internal register map 79rc32438 user reference manual 1 - 27 november 4, 2002 notes uart 0x05_0000 uart0rb / uart0th / uart0dll uart 0 receive buffer / uart 0 transmit holding / uart 0 divisor latch low 0x05_0004 uart0ie / uart0dlh uart 0 interrupt enable / uart 0 divisor latch high 0x05_0008 uart0ii / uart0fc uart 0 interrupt identification / uart 0 fifo control 0x05_000c uart0lc uart 0 line control 0x05_0010 uart0mc uart 0 modem control 0x05_0014 uart0ls uart 0 line status 0x05_0018 uart0ms uart 0 modem status 0x05_001c uart0s uart 0 scratch 0x05_0020 uart1rb / uart1th / uart1dll uart 1 receive buffer / uart 1 transmit holding / uart 1 divisor latch low 0x05_0024 uart1ie / uart1dlh uart 1 interrupt enable / uart 1 divisor latch high 0x05_0028 uart1ii / uart1fc uart 1 interrupt identification / uart 1 fifo control 0x05_002c uart1lc uart 1 line control 0x05_0030 uart1mc uart 1 modem control 0x05_0034 uart1ls uart 1 line status 0x05_0038 uart1ms uart 1 modem status 0x05_003c uart1s uart 1 scratch 0x05_0040 uart0rr uart 0 reset 0x05_0044 uart1rr uart 1 reset 0x05_0048 through 0x05_7fff reserved ethernet interface 0 0x05_8000 eth0intfc ethernet 0 interface control 0x05_8004 eth0fifott ethernet 0 fifo transmit threshold 0x05_8008 eth0arc ethernet 0 address recognition control 0x05_800c eth0hash0 ethernet 0 hash table 0 0x05_8010 eth0hash1 ethernet 0 hash table 1 0x05_8014 through 0x05_8020 reserved 0x05_8024 eth0pfs ethernet 0 pause frame status management clock 0x05_8028 ethmcp ethernet management clock pre- scalar 0x05_802c through 0x05_80ff reserved 0x05_8100 eth0sal0 ethernet 0 station address 0 low function register offset register name register function table 1.3 internal register map (part 7 of 12)
idt rc32438 device overview rc32438 internal register map 79rc32438 user reference manual 1 - 28 november 4, 2002 notes 0x05_8104 eth0sah0 ethernet 0 station address 0 high 0x05_8108 eth0sal1 ethernet 0 station address 1 low 0x05_810c eth0sah1 ethernet 0 station address 1 high 0x05_8110 eth0sal2 ethernet 0 station address 2 low 0x05_8114 eth0sah2 ethernet 0 station address 2 high 0x05_8118 eth0sal3 ethernet 0 station address 3 low 0x05_811c eth0sah3 ethernet 0 station address 3 high 0x05_8120 eth0rbc ethernet 0 receive byte count 0x05_8124 eth0rpc ethernet 0 receive packet count 0x05_8128 eth0rupc ethernet 0 receive undersized packet count 0x05_812c eth0rfc ethernet 0 receive fragment count 0x05_8130 eth0tbc ethernet 0 transmit byte count 0x05_8134 eth0gpf ethernet 0 generate pause frame 0x05_8138 through 0x05_81ff reserved 0x05_8200 eth0mac1 ethernet 0 mac configuration 1 0x05_8204 eth0mac2 ethernet 0 mac configuration 2 0x05_8208 eth0ipgt ethernet 0 back-to-back inter- packet gap 0x05_820c eth0ipgr ethernet 0 non back-to-back inter- packet gap 0x05_8210 eth0clrt ethernet 0 collision window retry 0x05_8214 eth0maxf ethernet 0 maximum frame length 0x05_8218 reserved 0x05_821c eth0mtest ethernet 0 mac test mii management 0x05_8220 miimcfg mii management configuration mii management 0x05_8224 miimcmd mii management command mii management 0x05_8228 miimaddr mii management address mii management 0x05_822c miimwtd mii management write data mii management 0x05_8230 miimrdd mii management read data mii management 0x05_8234 miimind mii management indicators 0x05_8238 through 0x05_823c reserved 0x05_8240 eth0cfsa0 ethernet 0 control frame station address 0 0x05_8244 eth0cfsa1 ethernet 0 control frame station address 1 0x05_8248 eth0cfsa2 ethernet 0 control frame station address 2 function register offset register name register function table 1.3 internal register map (part 8 of 12)
idt rc32438 device overview rc32438 internal register map 79rc32438 user reference manual 1 - 29 november 4, 2002 notes 0x05_824c through 0x5_ffff reserved ethernet interface 1 0x06_0000 eth1intfc ethernet 1 interface control 0x06_0004 eth1fifott ethernet 1 fifo transmit threshold 0x06_0008 eth1arc ethernet 1 address recognition control 0x06_000c eth1hash0 ethernet 1 hash table 0 0x06_0010 eth1hash1 ethernet 1 hash table 1 0x06_0014 through 0x06_0020 reserved 0x06_0024 eth1pfs ethernet 1 pause frame status 0x06_0028 through 0x06_00ff reserved 0x06_0100 eth1sal0 ethernet 1 station address 0 low 0x06_0104 eth1sah0 ethernet 1 station address 0 high 0x06_0108 eth1sal1 ethernet 1 station address 1 low 0x06_010c eth1sah1 ethernet 1 station address 1 high 0x06_0110 eth1sal2 ethernet 1 station address 2 low 0x06_0114 eth1sah2 ethernet 1 station address 2 high 0x06_0118 eth1sal3 ethernet 1 station address 3 low 0x06_011c eth1sah3 ethernet 1 station address 3 high 0x06_0120 eth1rbc ethernet 1 receive byte count 0x06_0124 eth1rpc ethernet 1 receive packet count 0x06_0128 eth1rupc ethernet 1 receive undersized packet count 0x06_012c eth1rfc ethernet 1 receive fragment count 0x06_0130 eth1tbc ethernet 1 transmit byte count 0x06_0134 eth1gpf ethernet 1 generate pause frame 0x06_0138 through 0x06_01ff reserved 0x06_0200 eth1mac1 ethernet 1 mac configuration 1 0x06_0204 eth1mac2 ethernet 1 mac configuration 2 0x06_0208 eth1ipgt ethernet 1 back-to-back inter- packet gap 0x06_020c eth1ipgr ethernet 1 non back-to-back inter- packet gap 0x06_0210 eth1clrt ethernet 1 collision window retry 0x06_0214 eth1maxf ethernet 1 maximum frame length 0x06_0218 reserved 0x06_021c eth1mtest ethernet 1 mac test 0x06_0220 through 0x06_023c reserved function register offset register name register function table 1.3 internal register map (part 9 of 12)
idt rc32438 device overview rc32438 internal register map 79rc32438 user reference manual 1 - 30 november 4, 2002 notes 0x06_0240 eth1cfsa0 ethernet 1 control frame station address 0 0x06_0244 eth1cfsa1 ethernet 1 control frame station address 1 0x06_0248 eth1cfsa2 ethernet 1 control frame station address 2 0x06_024c through 0x6_ffff reserved i2c bus 0x07_0000 i2cc i 2 c bus control 0x07_0004 i2cdi i 2 c bus data input 0x07_0008 i2cdo i 2 c bus data output 0x07_000c i2ccp i 2 c bus clock prescalar 0x07_0010 i2cmcmd i 2 c bus master command 0x07_0014 i2cms i 2 c bus master status 0x07_0018 i2cmsm i 2 c bus master status mask 0x07_001c i2css i 2 c bus slave status 0x07_0020 i2cssm i 2 c bus slave status mask 0x07_0024 i2csaddr i 2 c bus slave address 0x07_0028 i2csack i 2 c bus slave acknowledge 0x07_002c through 0x7_7fff reserved serial peripheral interface 0x07_8000 spcp spi clock prescalar 0x07_8004 spc spi control 0x07_8008 sps spi status 0x07_800c spd spi data 0x07_8010 siofunc serial i/o function 0x07_8014 siocfg serial i/o configuration 0x07_8018 siod serial i/o data 0x07_801c through 0x7_ffff reserved pci bus interface 0x08_0000 pcic pci control 0x08_0004 pcis pci status 0x08_0008 pcism pci status mask 0x08_000c pcicfga pci configuration address 0x08_0010 pcicfgd pci configuration data 0x08_0014 pcilba0 pci local base address 0 0x08_0018 pcilba0c pci local base address 0 control 0x08_001c pcilba0m pci local base address 0 mapping 0x08_0020 pcilba1 pci local base address 1 function register offset register name register function table 1.3 internal register map (part 10 of 12)
idt rc32438 device overview rc32438 internal register map 79rc32438 user reference manual 1 - 31 november 4, 2002 notes 0x08_0024 pcilba1c pci local base address 1 control pci bus interface (cont.) 0x08_0028 pcilba1m pci local base address 1 mapping 0x08_002c pcilba2 pci local base address 2 0x08_0030 pcilba2c pci local base address 2 control 0x08_0034 pcilba2m pci local base address 2 mapping 0x08_0038 pcilba3 pci local base address 3 0x08_003c pcilba3c pci local base address 3 control 0x08_0040 pcilba3m pci local base address 3 mapping 0x08_0044 pcidac pci decoupled access control 0x08_0048 pcidas pci decoupled access status 0x08_004c pcidasm pci decoupled access status mask 0x08_0050 pcidad pci decoupled access data 0x08_0054 pcidma8c pci dma channel 8 configuration 0x08_0058 pcidma9c pci dma channel 9 configuration 0x08_005c pcitc pci target control 0x08_0060 through 0x8_7fff reserved pci messaging unit 0x08_8000 through 0x8_800c reserved 0x08_8010 pciim0 pci inbound message 0 0x08_8014 pciim1 pci inbound message 1 0x08_8018 pciom0 pci outbound message 0 0x08_801c pciom1 pci outbound message 1 0x08_8020 pciid pci inbound doorbell 0x08_8024 pciiic pci inbound interrupt cause 0x08_8028 pciiim pci inbound interrupt mask 0x08_802c pciod pci outbound doorbell 0x08_8030 pcioic pci outbound interrupt cause 0x08_8034 pcioim pci outbound interrupt mask 0x08_8038 through 0x8_ffff reserved debug and performance monitoring 0x09_0000 ipbmtcfg ipbus monitor trigger configura- tion 0x09_0004 ipbmts ipbus monitor trigger select 0x09_0008 ipbmmt ipbus monitor manual trigger 0x09_000c ipbmtc0 ipbus monitor trigger condition 0 0x09_0010 ipbmtc1 ipbus monitor trigger condition 1 0x09_0014 ipbmtc2 ipbus monitor trigger condition 2 0x09_0018 ipbmtc3 ipbus monitor trigger condition 3 function register offset register name register function table 1.3 internal register map (part 11 of 12)
idt rc32438 device overview rc32438 internal register map 79rc32438 user reference manual 1 - 32 november 4, 2002 notes 0x09_001c ipbmfs ipbus monitor filter select debug and performance monitoring (cont.) 0x09_0020 ipbmfc0 ipbus monitor filter control 0 0x09_0024 ipbmfc1 ipbus monitor filter control 1 0x09_0028 ipbmfc2 ipbus monitor filter control 2 0x09_002c ipbmrc ipbus monitor record control 0x09_0030 ipbmtt ipbus monitor trigger time 0x09_0034 ipbmtp ipbus monitor trigger position 0x09_0038 emc event monitor control 0x09_003c em0compare event monitor 0 compare 0x09_0040 em0count event monitor 0 count 0x09_0044 em1count event monitor 1 count 0x09_0048 em2count event monitor 2 count 0x09_004c em3count event monitor 3 count 0x09_0050 em4count event monitor 4 count 0x09_0054 em5count event monitor 5 count 0x09_0058 em6count event monitor 6 count 0x09_005c em7count event monitor 7 count 0x09_0060 through 0x9_7fff reserved on-chip memory 0x09_8000 oc mbase on-chip memory base 0x09_8004 ocmmask on-chip memory mask 0x09_8008 through 0x9_ffff reserved 1. addresses for each function may be partitio ned into two regions. region one includes a ddresses from the start of the function?s address range to one less than the lowest address that modulo 2 56 is zero and which is greater than or equal to the highest de- fined register for that function. region tw o consists of those function addresses not in region one. for the system identificat ion function, region one would consist of 0x00_0000 through 0x00_00ff and region two could consist of 0x00_0100 through 0x00_7fff. reads from a region one reserved address return zero . writes to a region one rese rved address are ignored. reads and writes to region two result in an undec oded address error. for more information, refer to the address space monitor section in chapter 4. function register offset register name register function table 1.3 internal register map (part 12 of 12)
notes 79rc32438 user reference manual 2 - 1 november 4, 2002 chapter 2 mips32 4kc processor core introduction the mips32? 4kc? processor core from mips ? technologies is a high per formance, low power, 32 bit mips risc core intended for custom system-on-si licon applications. the 4kc processor incorporates aspects of both the mips technologies r3000 ? and r4000 ? processors. this chapter provides basic infor- mation on the architecture and operation of the 4kc pr ocessor core as it applies to the rc32438. additional information about the 4kc core can be obtained by c ontacting mips technologies or visiting their 4kc web page at: http://www.mips.com/products/s2p4.html. functional overview the 4kc core contains a fully-associative tr anslation lookaside buffer (tlb) based mmu (memory management unit) and a pipelined mdu (multiply/divide unit). the instruction and data caches are both 16 kbytes in size and organized as 4-way set associative. on a cache miss, loads are blocked only until the first critical word becomes avail able. the pipeline resumes execution while the remaining words are being written to the cache. both caches are virtually indexed and physically tagged. vi rtual indexing allows the cache to be indexed in the same clock in which the address is generated rather than waiting for the virtual- to-physical address translation in the memory management unit (mmu). the 4kc core executes the mips32 instruction set architecture (isa). the mips32 isa contains all mips ii instructions as well as special multiply-accu mulate, conditional move, prefetch, wait, and zero/one detect instructions. the r4000-style memory management unit of the 4kc core contains a 3-entry instruc- tion tlb (itlb), a 3-entry data tlb (dtlb), and a 16 dual -entry joint tlb (jtlb) with variable page sizes. the 4kc mdu supports a maximum issue rate of on e 32x16 multiply (mul/mult/multu), multiply-add (madd/maddu), or multiply-subtra ct (msub/msubu) operation per cl ock, or one 32x32 mul, madd, or msub every other clock. the basic enhanced jtag (e jtag) features provide cpu run control with stop, single stepping and re-start, and with software breakpoi nts through the sdbbp instruction. in addition, optional instruction and data virtual address hardwar e breakpoints, and optional connection to an external ejtag probe through the test access port (tap) may be included. features ? 32-bit address and data paths ? mips32 compatible instruction set ? all mipsii? instructions ? multiply-add and multiply-subtract instructions (madd, maddu, msub, msubu) ? targeted multiply instruction (mul) ? zero and one detect instructions (clz, clo) ? wait instruction (wait) ? conditional move instructions (movz, movn) ? prefetch instruction (pref)
idt mips32 4kc processor core features 79rc32438 user reference manual 2 - 2 november 4, 2002 notes ? cache sizes ? 16kb instruction and data caches ? 4-way set associative ? loads that miss in the cache are block ed only until critical word is available ? write-through, no write-allocate ? 128 bit (16-byte) cache line size, word sect ored - suitable for standard 32-bit wide single-port sram ? virtually indexed, physically tagged ? cache line locking support ? r4000 style privileged resource architecture ? count/compare registers for real-time timer interrupts ? instruction and data watch regi sters for software breakpoints ? separate interrupt exception vector ? programmable memory management unit ? 16 dual-entry r4000 style jt lb with variable page sizes ? 3-entry instruction tlb ? 3-entry data tlb ? multiply-divide unit ? max issue rate of one 32x16 multiply per clock ? max issue rate of one 32x32 multiply every other clock ? early in divide control. minimum 11, maximum 34 clock latency on divide ? power control ? no minimum frequency ? power-down mode (triggered by wait instruction) ? support for software-controlled clock divider ? ejtag debug support ? cpu control with start, stop, and single stepping ? software breakpoints via the sdbbp instruction ? optional hardware breakpoints on virtual addresses; 4 instruction and 2 data breakpoints, 2 instruction and 1 data breakpoint, or no breakpoints ? test access port (tap) facilitate s high speed download of application code
idt mips32 4kc processor core functional overview 79rc32438 user reference manual 2 - 3 november 4, 2002 notes functional overview figure 2.1 shows a block diagram of the 4kc cpu core. figure 2.1 rc32438 block diagram blocks the following sections describe the vari ous blocks in the 4kc processor core. execution unit the execution unit includes: 32-bit adder used for calculating the data address address unit for calculating the next instruction address logic for branch determination and branch target address calculation load aligner bypass multiplexers used to avoid stalls when ex ecuting instruction str eams where data-producing instructions are followed closel y by consumers of their results zero/one detect unit for implementing the clz and clo instructions alu for performing bitwise logical operations shifter and store aligner the core execution unit implements a load-store ar chitecture with single-cycle arithmetic logic unit (alu) operations (logical, shift, add, subtract) and an autonomous multiply-divide unit. the core contains thirty-two 32-bit general-purpose regi sters used for scalar integer opera tions and address calculation. the register file consists of two re ad ports and one write port and is fully by passed to minimize operation latency in the pipeline. multiply/divide unit (mdu) the multiply/divide unit performs mu ltiply and divide operations. in the 4kc processor, the mdu consists of a 32x16 booth-encoded multiplier, result-accumulation registers (hi and lo), a divide state machine, and all multiplexers and control logic required to perform these functions. this pi pelined mdu supports execu- tion of a 16x16 or 32x16 multiply operation every cl ock cycle; 32x32 multiply operations can be issued every other clock cycle. appropriate interlocks are implemented to stall the issue of back-to-back 32x32 multiply operations. divide operations are implemented wi th a simple 1 bit per clock iterative algorithm and may require up to 35 clock cycles (worst case scenario) to complete. in the early stages of executions, the algorithm detects a sign extension of the dividend and, if its actual size is 24, 16, or 8 bits. based on this system coprocessor cache controller mdu tlb or fm mmu d-cache biu tap ejtag power mgmt i-cache off-chip debug i/f execution core (rf/alu/shift thin i/f on-chip bus(es)
idt mips32 4kc processor core functional overview 79rc32438 user reference manual 2 - 4 november 4, 2002 notes information, the divider will skip 7, 15, or 23 iterations respectively (out of a total of 32 iterations). an attempt to issue a subsequent mdu instruction while a di vide is still in progress ca uses a pipeline stall until the divide operation is completed. an additional multiply instruction, mul, is implement ed. this instruction specifies that the lower 32 bits of the multiply result be placed in the register file in stead of the hi/lo register pai r. by avoiding the explicit move from the lo (mflo) instruction (required w hen using the lo register) and by supporting multiple destination registers, the throughput of mu ltiply-intensive operations is increased. two instructions, multiply-add (madd/maddu) and multiply-subtract (msub/msubu), are used to perform the multiply-add and multiply-subtract operat ions. the madd instruction multiplies two numbers and then adds the product to the current contents of the hi and lo registers. similarly, the msub instruc- tion multiplies two operands and then subtracts the pr oduct from the hi and lo registers. the madd/ maddu and msub/msubu operations are commonly used in digital si gnal processor (dsp) algorithms. system control coprocessor (cp0) in the mips architecture, cp0 is responsible for t he virtual-to-physical address translation, cache proto- cols, the exception control system, the processor? s diagnostics capability, operating mode selection (kernel vs. user mode), and the enabling/disabling of interrupts. configuration information, such as cache size, set associativity, and ejtag debug features, is available by accessing the cp0 registers. additional informa- tion on cp0 registers can be found in the cp0 register s section. additional information on ejtag can be found in chapter 20. memory management unit (mmu) each core contains an mmu that interfaces betw een the execution unit and the cache controller, shown in figure 2.1. although the 4kc core implements a 32-bit architecture, the memory management unit (mmu) is modeled after the mmu found in the 64-bit r 4000 family, as defined by the mips32 architecture. the 4kc core implements an mmu based on a transla tion lookaside buffer (tlb). the tlb actually consists of three translation buffers: a 16 dual-entry fully associative join t tlb (jtlb), a 3-entry fully asso- ciative instruction tlb (itlb), and a 3-entry fully associative data tlb(dtlb). the itlb and dtlb, also referred to as the micro tlbs, are managed by the har dware and are not software visible. the micro tlbs contain subsets of the jtlb. when translating addresses, the corresponding micro tlb (i or d) is accessed first. if there is no matching entry, the jtlb is used to translate the address and refill the micro tlb. if the entry is not found in the jtlb, an exception is tak en. to minimize the micro tlb miss penalty, the jtlb is looked-up in parallel with the dtlb for data references. this results in a 1 cycle stall for a dtlb miss and a 2 cycle stall for an itlb miss. figure 2.2 shows how the itlb, dtlb, and jtlb are used in the 4kc core.
idt mips32 4kc processor core functional overview 79rc32438 user reference manual 2 - 5 november 4, 2002 notes figure 2.2 address translation during a cache access in the 4kc core cache controller the data and instruction cache controllers support 16 kb 4-way set associative caches. there are sepa- rate cache controllers for the i-cache and d-cache. each cache controller contains and manages a one-li ne fill buffer. besides accumulating data to be written to the cache, the fill buffer is accessed in parallel with the cache and data can be bypassed back to the core. bus interface unit (biu) the bus interface unit (biu) controls the external interface signals. it also contains the implementation of a 32-byte collapsing write-buffer. the purpose of this buffer is to hold and combine write transactions before issuing them to the external interface. si nce the data caches for all cores follow a write-through cache policy, the write-buffer significantly reduces t he number of write transactions on the external inter- face, as well as reducing the amount of stalling in t he core due to issuance of multiple writes in a short period of time. the write-buffer is organized as two 16-byte buffers . each buffer contains data from a single 16-byte aligned block of memory. one buffer contains the data currently being transferred on the external interface, while the other buffer contains accumulating data from the core. power management the 4kc processor core offers a number of powe r management features, including low-power design, active power management, and power-down modes of operation. this core is a static design that supports a wait instruction designed to signal the rest of the device that execution and clocking should be halted, thereby reducing system power c onsumption during idle periods. the 4kc core provides tw o mechanisms for system-level, low-power support: register-controlled power management instruction-controlled power management i-cache d-cache comparator comparator instruction hit/miss data hit/miss virtual address virtual address itlb jtlb dtlb instruction address calculator data address calculator entry entry iva
idt mips32 4kc processor core pipeline description 79rc32438 user reference manual 2 - 6 november 4, 2002 notes in register-controlled power management mode, the 4k c core provides three bits in the cp0 status register for software control of the power management function and allows interrupts to be serviced even when the core is in power-down mode. in instructi on-controlled power-down mode, execution of the wait instruction is used to invoke low-power mode. for additional information on power managemen t, refer to the power management section. instruction cache the instruction cache is 16 kbytes in size. the ca che is virtually indexed and physically tagged, allowing the virtual-to-physical address translation to occur in parallel with the cache ac cess rather than having to wait for the physical address translation. the tag holds 22 bits of the physical address, 4 valid bits, a lock bit, and the lrf (least recently filled) replacement bit. all cores support instruction cache locking. cache lo cking allows critical code to be locked into the cache on a per-line basis, enabling the system designer to maximize the efficiency of the system cache. cache locking is always available on all instructi on cache entries. entries can be marked as locked or unlocked (by setting or clearing the lock-bit) on a per-entry basis using the cache instruction. data cache the data cache is 16-kbytes in size. the cache is virtually indexed and physi cally tagged, allowing the virtual-to-physical address translation to occur in parallel with the cache access. the tag holds 22 bits of the physical address, 4 valid bits, a lo ck bit, and the lrf replacement bit. in addition to instruction cache locking, all cores also support a data cache lo cking mechanism identical to the instruction cache, with critical data segment s to be locked into the cache on a per-line basis. the locked contents cannot be selected for replacemen t on a cache miss, but can be updated on a store hit. cache locking is always available on all data ca che entries. entries can be marked as locked or unlocked on a per-entry basis using the cache instruction. the physical data cache memory must be byte-w ritable to support non-word store operations. ejtag controller all cores provide basic ejtag support with debug m ode, run control, single step and software break- point instruction (sdbbp) as part of the core. these features allow for the basic software debug of user and kernel code. optional ejtag features include hardware breakpoints. a 4k core may have four instruction break- points and two data breakpoints, two instruction breakpoints and one data breakpoint, or no breakpoints. the hardware instruction breakpoints can be confi gured to generate a debug exception when an instruction is executed anywhere in the virtual address space. bit mask and addres s space identifier (asid) values may apply in the address compare. these breakpoint s are not limited to code in ram like the software instruction breakpoint (sdbbp). the data breakpoint s can be configured to generate a debug exception on a data transaction. the data transaction may be qualifi ed with both virtual address, data value, size, and load/store transaction type. bit mask and asid values may apply in the address compare, and byte mask may apply in the value compare. an optional test access port (tap) provides fo r the communication from an ejtag probe to the cpu through a dedicated port, may also be applied to the core. this provides t he possibility for debugging without debug code in the application and for dow nload of application code to the system. for additional information on the ejtag contro ller, refer to chapter 20, ejtag system. pipeline description the mips32 4kc processor core implements a 5-st age pipeline similar to the original r3000 pipeline. the five stages are: instruction (i stage) execution (e stage)
idt mips32 4kc processor core pipeline description 79rc32438 user reference manual 2 - 7 november 4, 2002 notes memory (m stage) align/accumulate (a stage) writeback (w stage) this pipeline allows the processor to achieve high frequency while minimizing device complexity, reducing both cost and power consumption. the 4kc co re implements a ?bypass? mechanism that allows the result of an operation to be sent directly to the in struction that needs it without having to write the result to the register and then read it back. figure 2.3 shows the operations performed in each pipeline stage of the 4kc processor. figure 2.3 4kc core pipeline stages during the instruction fetch stage: an instruction is fetched from the instruction cache the itlb performs a virtual- to-physical address translation. during the execution stage: operands are fetched from the register file operands from m and a stage are bypassed to this stage the arithmetic logic unit (alu) begins the arithmet ic or logical operation fo r register-to-register instructions the alu calculates the data virtual address for load and store instructions the alu determines whether the br anch condition is true and calculat es the virtual branch target address for branch instructions instruction logic selects an instruction address all multiply and divide operations begin in this stage. during the memory fetch stage: the arithmetic or logic alu operation completes the data cache fetch and the data virtual-to-phy sical address translation are performed for load and store instructions data tlb and data cache lookup are perfo rmed and a hit/miss determination is made a 16x16 or 32x16 mul operation completes in the ar ray and stalls for one clock in the m stage to complete the carry-propagate-add in the m stage a 32x32 mul operation stalls for two clocks in the m stage to complete second cycle of the array and the carry-propagate-add in the m stage a 16x16 or 32x16 mult/madd/msub operation completes in the array a 32x32 mult/madd/msub operation stalls for one clock in the mmdu stage of the mdu pipeline to complete second cycle in the array i a->e bypass m->e bypass a->e bypass e m a w i-cache i-tlb regrd i dec d-ac i-ac1 i-ac2 alu op d-cache d-tlb align mul regw regw regw regw regw mult, macc 16x16, 32x16 cpa cpa mult, macc 32x32 sign adjust divide iu-pipeline mdu-pipeline i-ac2 d-ac align mul i-tlb i dec alu op d-cache d-tlb divide mult, macc sign adjust i-cache regrd i-ac1 regw cpa : i$ tag and data read : i-tlb look-up : instruction decode : register file read : instruction address calc stage 1 and 2 : arithmetic logic and shift operations : data address calculation : d$ tag and data read : d-tlb look-up : load data aligner : register file write or hi/lo write : the mul instr. uses mdu-pipeline write reg file : carry propagate adder : multiply and multiply accumulate instructions : divide instructions : last stage of divide is a sign adjustment : one or more stall cycles.
idt mips32 4kc processor core pipeline description 79rc32438 user reference manual 2 - 8 november 4, 2002 notes a divide operation stalls for a maximum of 32 clocks in the mmdu st age of the mdu pipeline. during the align/accumulate stage: a separate aligner aligns l oaded data with its word boundary a mul operation makes the result available for wr iteback. the actual register writeback is per- formed in the w stage a mult/madd/msub operation performs the carr y-propagate-add. this includes the accumulate step for the madd/msub operations. the actual re gister writeback to hi and lo is performed in the w stage. a divide operation perform the final sign-adjust. the actual register writeback to hi and lo is per- formed in the w stage. during the writeback stage: for register-to-register or load instructions, the resu lt is written back to the register file during the w stage. instruction cache miss when the instruction cache is indexed, the instruct ion address is translated to determine if the required instruction resides in the cache. an instruction cache miss occurs when the requested instruction address does not reside in the instruction cache. when a cache miss is detected in the i stage, the core transitions to the e stage. the pipeline stalls in the e stage unt il the miss is resolved. the bus interface unit must select the address from multiple sources. if the addre ss bus is busy, the request will remain in this arbitra- tion stage (b-asel in figure 2.4) until the bus is avai lable. the core drives the selected address onto the bus. the number of clocks required to access the bus is determined by the access time of the array that contains the data. the number of cloc ks required to return the data once the bus is accessed is also deter- mined by the access time of the array. once the data is returned to the core, the critical word is written to the instruct ion register for immediate use. the bypass mechanism allows the core to us e the data once it becomes available, as opposed to having the entire cache line written to the instru ction cache, then reading out the required word. figure 2.4 shows a timing diagram of an instruction cache miss for the 4kc core. figure 2.4 4kc instruction cache miss timing when the data cache is indexed, the data address is translated to determine if the required data resides in the cache. a data cache miss occurs when t he requested data address does not reside in the data cache. when a data cache miss is detected in the m stage (d -tlb), the core transitions to the a stage. the pipeline stalls in the a stage until the miss is reso lved (requested data is returned). the bus interface unit arbitrates between multiple requests and selects the correct address to be driven onto the bus (b-asel in figure 2.5). the core drives the selected address ont o the bus. the number of clocks required to access the bus is determined by the access time of the array containing the data. the number of clocks required to return the data once the bus is accessed is also determined by the access time of the array. e e ee i i dec i-cache i-tlb i-tlb b-asel bus* ic-bypass regrd alu op i-a2 i-a1 * contains all of the cycles that address and data are utilizing the bus.
idt mips32 4kc processor core pipeline description 79rc32438 user reference manual 2 - 9 november 4, 2002 notes once the data is returned to the core, the critical word of data passes through the aligner before being forwarded to the execution unit and register file. the bypass mechanism allows the core to use the data once it becomes available, as opposed to having the entire cache line written to the data cache, then reading out the required word. figure 2.5 shows a timing diagram of a data cache miss for the 4kc core. figure 2.5 load/store cache miss timing multiply/divide operations the 4kc core implements the standard mips ii? multip ly and divide instructions. in addition, several new instructions have been added that enhance the core?s performance. the targeted multiply instruction, mul, specifies t hat multiply results are placed in the general purpose register file instead of the hi/lo r egister pair. by avoidi ng the explicit mflo instruction, required when using the lo register, and by supporting multiple desti nation registers, the throughput of multiply-intensive operations is increased. four instructions ? multiply-add (madd), multip ly-add-unsigned (maddu), mu ltiply-subtract (msub), and multiply-subtract-unsigned (msu bu) ? are used to perform the multiply-accumulate and multiply- subtract operations. the madd/maddu instructi on multiplies two numbers and then adds the product to the current contents of the hi and lo registers. simila rly, the msub/msubu instruction multiplies two oper- ands and then subtracts the product from the hi and lo registers. the ma dd/maddu and msub/msubu operations are commonly used in dsp algorithms. all multiply operations (except the mul instruction) wr ite to the hi/lo register pair. all integer operations write to the general purpose registers (gpr). becaus e mdu operations write to different registers than integer operations, integer instructions that foll ow mdu operations can exec ute before the mdu operation has finished. the mflo and mfhi instructions are used to move data from the hi/lo register pair to the gpr file. if a mflo or mfhi instruction is issued befor e the mdu operation finishes, the instruction will stall to wait for the data. mdu pipeline the 4kc processor core contains an autonomous multip ly/divide unit (mdu) with a separate pipeline for multiply and divide operations. this pipeline operates in parallel with the integer unit (iu) pipeline and does not stall when the iu pipeline stalls. this allows long-running mdu operations, su ch as a divide, to be partially masked by system stalls and/or other integer unit instructions. the mdu consists of a 32x16 booth encoded multiplier, result/accumulation registers (hi and lo), a divide state machine, and all necessary multiplexers and control logic. the fi rst number shown (?32? of 32x16) represents the rs operand. the second number (?16? of 32x16) represents the rt operand. the core only checks the latter (rt) operand value to determi ne how many times the operation must pass through the multiplier. the 16x16 and 32x16 operations pass thr ough the multiplier once. a 32x32 operation passes through the multiplier twice. d-tlb d-cache alu1 b-asel regr bus* regw align dc bypass * contains all of the time that address and data are utilizing the bus. w a a a a m e
idt mips32 4kc processor core pipeline description 79rc32438 user reference manual 2 - 10 november 4, 2002 notes the mdu supports execution of a 16x16 or 32x16 mu ltiply operation every clock cycle; 32x32 multiply operations can be issued every other clock cycle. appropriate interlocks are implemented to stall the issue of back-to-back 32x32 multiply operations. multiply o perand size is automatically determined by logic built into the mdu. divide operati ons are implemented with a simple 1 bit per clock iterative algorithm with an early in detection of sign extensio n on the dividend (rs). any attempt to issue a subsequent mdu instruction while a divide is still active causes an iu pi peline stall until the divide operation is completed. table 2.1 lists the latencies (number of cycles until a result is available) for multiply and divide instruc- tions. the latencies are listed in terms of pipeline clo cks. in this table ?latency? refers to the number of cycles necessary for the first instruction to pr oduce the result needed by the second instruction. in table 2.1, a latency of one means that the first and second instruction can be issued back to back in the code without the mdu causing any stalls in the iu pipeline. a latency of two means that if the instruc- tions are issued back to back, the iu pipeline will be stalled for one cy cle. an mul operation is special because it needs to stall the iu pipeline in order to ma intain its register file write slot. consequently, the mul 16x16 or 32x16 operation will always force a one cycle stall of the iu pipeline, and the mul 32x32 will force a two cycle stall. if the integer instruction immediately following the mul operation uses its (mul operation) result, an additional st all is forced on the iu pipeline. operand size of 1st instruction 1 1. for multiply operations, this is the rt operand. for divide operations, this is the rs operand. instruction sequence latency clocks 1st instruction 2nd instruction 16 bit mult/multu, madd/ maddu, or msub/ msubu madd/maddu, msub/ msubu, or mfhi/mflo 1 32 bit mult/multu, madd/ maddu, or msub/ msubu madd/maddu, msub/ msubu, or mfhi/mflo 2 16 bit mul integer operation 2 2. integer operation refers to any integer instruction t hat uses the result of a previous mdu operation. 2 3 3. this does not include the 1 or 2 iu pipeline stalls (16 bit or 32 bit) that mul operat ion causes regardless of the following instruction. these stalls do not add to the latency of 2. 32 bit mul integer operation 2 2 3 8 bit divu mfhi/mflo 9 16 bit divu mfhi/mflo 17 24 bit divu mfhi/mflo 25 32 bit divu mfhi/mflo 33 8 bit div mfhi/mflo 10 4 4. if both operands are positive, the sign adjust stage is bypassed. latency is then the same as for divu. 16 bit div mfhi/mflo 18 4 24 bit div mfhi/mflo 26 4 32 bit div mfhi/mflo 34 4 any mfhi/mflo integer operation 2 2 any mthi/mtlo madd/maddu or msub/msubu 1 table 2.1 4kc core instruction latencies
idt mips32 4kc processor core pipeline description 79rc32438 user reference manual 2 - 11 november 4, 2002 notes table 2.2 lists the repeat rates (peak issue rate of cycles until the operation c an be reissued) for multiply accumulate/subtract instructions. the repeat rates are lis ted in terms of pipeline clocks. in this table ?repeat rate? refers to the case where the first mdu inst ruction is back to back with the second instruction. the 32x16 multiply operation requires one clock of each pipeline stage to complete. the 32x32 requires two clocks in the mmdu pipe-stage. the mdu pipeline is shown as the shaded areas of figure 2.6 and always starts a computation in the final phase of the e stage. as shown in figure 2.6, the mmdu pipe-stage of the mdu pipeline occurs in parallel with the m stage of the iu pipeline, the amdu stage occurs in parallel with the a stage, and the wmdu stage occurs in parallel with the w stage. however, in case the instruction in the mdu pipeline needs multiple passes through t he same mdu stage, this parallel behavior will be skewed by one or more clocks. this is not a problem because results in the mdu pipeline are written to hi and lo registers, while the integer pipeline results are written to the register file. figure 2.6 shows the pipeline flow for the following sequence: 32x16 multiply (mult1) add 32x32 multiply (mult2) sub figure 2.6 mdu pipeline behavior during multiply operations operand size of 1st instruction instruction sequence repeat rate 1st instruction 2nd instruction 16 bit mult/multu, madd/maddu, msub/msubu madd/maddu, msub/msubu 1 32 bit mult/multu, madd/maddu, msub/msubu madd/maddu, msub/ msubu 2 table 2.2 4kc core instruction repeat rates i e a w m cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 mult 1 add mult 2 i e a mdu w mdu m mdu i e a mdu w mdu m mdu m mdu sub i e a w m
idt mips32 4kc processor core pipeline description 79rc32438 user reference manual 2 - 12 november 4, 2002 notes the following is a cycle-by- cycle analysis of figure 2.6. 1. the first 32x16 multiply operat ion (mult1) enters the i stage and is fetched from the instruction cache. 2. an add operation enters the i stage. the mult1 operation enters the e stage. the integer and mdu pipelines share the i and e pipeline stages. at the end of the e stage in cycle 2, the multiply opera- tion (mult1) is passed to the mdu pipeline. 3. in cycle 3 a 32x32 multiply operation (mult2) ent ers the i stage and is fetched from the instruction cache. since the add operation has not yet reached the m stage by cycle 3, there is no activity in the m stage of the integer pipeline at this time. 4. in cycle 4 the sub instruction enters i stage. the second multiply operation (mult2) enters the e stage. and the add operation enters m stage of the in teger pipe. since the mult1 multiply is a 32x16 operation, only one clock is requi red for the mmdu stage, hence the mult1 operation passes to the amdu stage of the mdu pipeline. 5. in cycle 5 the sub instruction enters e stage. the mult2 multiply enters the mmdu stage. the add operation enters the a stage of the integer pipe line. the mult1 operation completes and is written back in to the hi/lo register pair in the wmdu stage. 6. since a 32x32 multiply requires two passes th rough the multiplier, with each pass requiring one clock, the 32x32 mult2 remains in the mmdu stage in cycle 6. the sub instruction enters m stage in the integer pipeline. the add operation completes and is written to the register file in the w stage of the integer pipeline. 7. the mult2 multiply operation progresses to t he amdu stage, and the sub instruction progress to a stage. 8. the mult2 operation completes and is written to the hi/lo registers pair the wmdu stage, while the sub instruction write to the register file in w stage. 32x16 multiply the 32x16 multiply operation begins in the last phase of the e stage, which is shared between the integer and mdu pipelines. in the latter phase of the e stage, the rs and rt operands arrive and the booth recoding function occurs at this time. the multiply calculation requires one clock and occurs in the mmdu stage. in the amdu stage, the carry-propagate-add func tion occurs and the operation is completed. the result is written back to the hi/lo regist er pair in the first half of the wmdu stage. figure 2.7 shows a diagram of a 32x16 multiply operation. figure 2.7 mdu pipeline flow during a 32x16 multiply operation 32x32 multiply the 32x32 multiply operation begins in the last phase of the e stage, which is shared between the integer and mdu pipelines. in the latter phase or th e e stage, the rs and rt operands arrive and the booth recoding function occurs at this time. the multiply calculation requires two cloc ks and occurs in the mmdu stage. in the amdu stage, the carry-propagate-add (cpa ) function occurs and the operation is completed. the result is written back to the hi/lo regist er pair in the first half of the wmdu stage. figure 2.8 shows a diagram of a 32x32 multiply operation. booth array cpa e m mdu a mdu reg wr w mdu clock 1 2 3 4
idt mips32 4kc processor core pipeline description 79rc32438 user reference manual 2 - 13 november 4, 2002 notes figure 2.8 mdu pipeline flow during a 32x32 multiply operation divide operations divide operations are implemented using a simple non- restoring division algorithm . this algorithm works only for positive operands, thus the first cycle of the mmdu stage is used to negate the rs operand (rs adjust) if needed. note that this cycle is executed even if the adjustment is not necessary. at maximum, the next 32 clocks (3-34) execute an iterative add/subtra ct function. in cycle 3, an early in detection is performed in parallel with the add/subtract. the adj usted rs operand is detected to be zero extended on the upper most 8, 16, or 24 bits. if this is the case the fo llowing 7, 15, or 23 cycles of the add/subtract iterations are skipped. the remainder adjust (rem adjust) cycle is required if the remainder was negative. note that this cycle is taken even if the remainder was positive. a sign adjust is performed on the quotient and/or remainder if necessary. note that the sign adjust cycle is skipped if both operands are positive. in this case the rem adjust is moved to the amdu stage. figures 2.9 through 2.12 show the latency for 8, 16, 24, and 32-bit divide operations, respectively. the repeat rate is either 11, 19, 27, or 35 cycles (one less if the sign adjust stage is skipped) since a second divide can be in the rs adjust stage when the first divide is in the reg wr stage. figure 2.9 mdu pipeline flow during an 8-bit divide (div) operation figure 2.10 mdu pipeline flow during a 16-bit divide (div) operation figure 2.11 mdu pipeline flow during a 24-bit divide (div) operation booth array e m mdu m mdu a mdu reg wr w mdu cpa array booth clock 1 2 3 4 5 rs adjust e stage m mdu stage m mdu stage m mdu stage a mdu stage rem adjust add/subtract clock 1 2 4-10 11 12 w mdu stage 13 reg wr sign adjust m mdu stage add/subtract 3 early in rs adjust e stage m mdu stage m mdu stage m mdu stage a mdu stage rem adjust add/subtract clock 1 2 4-18 19 20 w mdu stage 21 reg wr sign adjust m mdu stage add/subtract 3 early in rs adjust e stage m mdu stage m mdu stage m mdu stage a mdu stage rem adjust add/subtract clock 1 2 4-26 27 28 w mdu stage 29 reg wr sign adjust m mdu stage add/subtract 3 early in
idt mips32 4kc processor core pipeline description 79rc32438 user reference manual 2 - 14 november 4, 2002 notes figure 2.12 mdu pipeline flow during a 32-bit divide (div) operation branch delay the pipeline has a branch delay of one cycle. the one- cycle branch delay is a result of the branch deci- sion logic operating during the e pipeline stage. this al lows the branch target address calculated in the previous stage to be used for the instruction access in the following e stage. the branch delay slot means that no bubbles are injected into the pipeline on br anch instructions. the address calculation and branch condition check are both performed in the e stage. the ta rget pc is used for the next instruction in the i stage (2nd instruction after the branch). the pipeline begins the fetch of eit her the branch path or the fall-thr ough path in the cycle following the delay slot. after the branch decision is made, the proc essor continues with the fetch of either the branch path (for a taken branch) or the fa ll-through path (for the non-taken branch). the branch delay means that the instruction immedi ately following a branch is always executed, regard- less of the branch direction. if no useful instructi on can be placed after the branch, then the compiler or assembler must insert a nop instruction in the delay slot. figure 2.13 illustrates the branch delay. figure 2.13 iu pipeline branch delay data bypassing most mips32 instructions use one or two register va lues as source operands for the execution. these operands are fetched from the register file in the first part of e stage. the alu straddles the e to m boundary, and can present the result early in m stage. howe ver, the result is not written in the register file until w stage. this leaves following instructions unabl e to use the result for 3 cycles. to overcome this problem, data bypassing is used. between the register file and the alu, a data bypa ss multiplexer is placed on both operands (see figure 2.14). this enables the 4k core to forward data from pr eceding instructions which have the target register of the first instruction as one of the source operands. an m to e bypass and an a to e bypass feed the bypass multiplexers. a w to e bypass is not needed, as the regi ster file is capable of making an internal bypass of rd write data directly to the rs and rt read ports. rs adjust e stage m mdu stage m mdu stage m mdu stage a mdu stage rem adjust add/subtract clock 1 2 4-34 35 36 w mdu stage 37 reg wr sign adjust m mdu stage add/subtract 3 early in one cycle jump target instruction delay slot instruction one clock branch delay one cycle one cycle one cycle one cycle one cycle iema w iema w iema jump or branch
idt mips32 4kc processor core pipeline description 79rc32438 user reference manual 2 - 15 november 4, 2002 notes figure 2.14 iu pipeline data bypass figure 2.15 shows the data bypass for an add1 instruction followed by a sub2 and another add3 instruction. the sub2 instruction uses the output from the add1 instruction as one of the operands, and thus the m to e bypass is used. the following add3 uses the result from both the first add1 instruction and the sub2 instruction. since the add1 data is now in a stage, the a to e bypass is used, and the m to e bypass is used to bypass the sub2 data to the add2 instruction. figure 2.15 iu pipeline m to e bypass load delay load delay means that data fetched by a load instruction is not available in the integer pipeline until after the load aligner is in a stage. all in structions need the source operands av ailable in e stage. an instruction immediately following a load instruction will, if it has the same source register as the target of the load, cause an instruction interlock pipeline slip in e stage (see the instruction interlocks section). if the second instruction after the load (not the first instruction), us es the data from the load, the a to e bypass exists to provide for stall free operation (refer to figure 2.14). an instruction flow of this is shown in figure 2.16. bypass multiplexers e stage m stage a stage w stage i stage load data, hi/lo data or cp0 data a to e bypass m to e bypass instruction alu m stage alu e stage reg file rs addr rt addr rs read rt read rd write one cycle one cycle one cycle one cycle one cycle one cycle r3=r2+r1 ema w iema w iema add 1 r4=r3-r7 sub 2 r5=r3+r4 add 3 i a to e bypass m to e bypass m to e bypass
idt mips32 4kc processor core pipeline description 79rc32438 user reference manual 2 - 16 november 4, 2002 notes figure 2.16 iu pipeline a to e data bypass move from hi/lo and cp0 delay as indicated in figure 2.14, not on ly load data but also data from a mo ve from the hi or lo register instruction (mfhi/mflo) or a move from cp0 (mfc0) can enter the iu-p ipeline in a stage. that is, data is not available in the integer pipeline until early in t he a stage. the a to e bypass is available for this data. but as for loads, the instruction immediately following one of these instructions can not use this data right away. if it does, it will cause an instruction interlock slip in e stage (refer to the instruction interlocks section). an interlock slip after an mfhi is illustrated in figure 2.17. figure 2.17 iu pipeline slip after mfhi interlock handling smooth pipeline flow is interrupted when cache misses occur or when data dependencies are detected. interruptions handled using hardware, such as cache mi sses, are referred to as interlocks. at each cycle, interlock conditions are checked for all active instructions. table 2.3 lists the types of pipeline interlocks for the 4kc processor core. interlock type source slip stage itlb miss instruction tlb i stage icache miss instruction cache e stage instructions producer-consumer hazards e/m stage hardware dependencies (mdu/tlb) e stage dtlb miss data tlb m stage table 2.3 pipeline interlocks (part 1 of 2) one cycle one cycle one cycle one cycle one cycle one cycle iema w iema w iema load instruction consumer of load data instruction data bypass from a to e one clock load delay one cycle one cycle one cycle one cycle one cycle one cycle one cycle iema w ema w slip i mfhi (to r3) add (r4=r3+r5) data bypass from a to e
idt mips32 4kc processor core pipeline description 79rc32438 user reference manual 2 - 17 november 4, 2002 notes in general, mips processors support two types of hardware interlocks: stalls, which are resolved by halting the pipeline slips, which allow one part of the pipeline to adv ance while another part of the pipeline is held static. the 4kc processor core handles all interlocks as slips. slip conditions on every clock, internal logic determines whether each pipe stage is allowed to advance. these slip conditions propagate backwards down the pipe. for exam ple, if the m stage does not advance, neither will the e or i stages. slipped instructions are retried on s ubsequent cycles until they issue. the back end of the pipeline advances normally during slips in an attempt to resolve the conflict. nops are inserted into the bubble in the pipeline. figure 2.18 shows a diagram of a two-cycle slip. in the first clock cycle, the pipeline is full and the cache miss is detected. instruction i0 is in the a stage, instruction i1 is in the m stage, instruction i2 is in the e stage, and instruction i3 is in the i stage. the cache mi ss occurs in clock 2 when the i4 instruction fetch is attempted. i4 advances to the e-stage and waits for the instruction to be fetched from main memory. in this example it takes two clocks (3 and 4) to fetch the i4 instruction from memory. once the cache miss is resolved in clock 4 and the instruction is bypassed to the cache, the pipeline is restarted, causing the i4 instruction to finally execute it?s e-stage operations. data cache miss load that misses in data cache w stage multi-cycle cache op sync store when write through buffer full ejtag breakpoint on store va match needing data value comparison store hitting in fill buffer interlock type source slip stage table 2.3 pipeline interlocks (part 2 of 2)
idt mips32 4kc processor core pipeline description 79rc32438 user reference manual 2 - 18 november 4, 2002 notes figure 2.18 instruction cache miss slip instruction interlocks most instructions can be issued at a rate of one per clock cycle. in some cases, in order to ensure a sequential programming model, the issue of an instruction is delayed to ensure that the results of a prior instruction will be available. table 2.4 details the instruction interact ions that delay the issuance of an instruction into the processor pipeline. 1st instruction 2nd instruction issue delay (in clock cycles) slip stage lb/lbu/lh/lhu/ll/lw/lwl/lwr consumer of load data 1 e stage mfc0 consumer of destination register 1e stage mult/madd/ msub 16x32b mflo/mfhi 0 m stage 32x32b 1 m stage mul 16x32b consumer of target data 2 e stage 32x32b 3 e stage mul 16x32b non-consumer of target data 1e stage 32x32b 2 e stage mfhi and mflo consumer of target data 1 e stage mult/madd/ msub 16x32b mult/mul/madd/ msub/mthi/mtlo/div 0e stage 32x32b 1 e stage div mult/mul/madd/ msub/mthi/mtlo/ mfhi/mflo/div until div com- pletes e stage table 2.4 instruction interlocks (part 1 of 2) 1 cache miss detected 1 2 0 0 e m i 1 i 2 i 3 a i 0 i 3 i 0 i 1 i 2 i 4 i 4 i 2 i 3 i 4 i 5 i 5 i 3 i 4 i 5 3 execute e-stage stage i 4 0 i 5 i 6 3 clock 123 4 56 2 critical word received
idt mips32 4kc processor core pipeline description 79rc32438 user reference manual 2 - 19 november 4, 2002 notes instruction hazards in general, the core ensures that instructions ar e executed following a fully sequential program model. each instruction in the program sees the results of t he previous instruction. there are some exceptions to this model. these exceptions are refe rred to as instruction hazards. table 2.5 shows the instruction hazards that exist in the core. the first and second instruction fields indi- cate the combination of instructions that do not ensure a sequential programming model. the spacing field indicates the number of unrelated instructions (suc h as nops or ssnops) that should be placed between the first and second instructions of t he hazard in order to ensure that the effects of the first instruction are seen by the second instruction. entries in the table t hat are listed as 0 are traditional mips hazards which are not hazards on the 4kc core. (mt compare to ti mer interrupt cleared is system dependent since timer interrupt is an output of the core that can be returned to the core on one of the si_int pins. this number is the minimum time due its passage through the core?s i/o registers. typical implementations will not add any latency to this). mfc0 consumer of target data 1 e stage tlbwr/tlbwi load/store/pref/ cache/cop0 op 2e stage tlbr 1 e stage 1st instruction 2nd instruction spacing (instructions) watch register write instruction fetch matching watch register 2 load/store reference matching watch register 0 tlbwi/tlbwr instruction fetch affected by new page mapping 3 load/store affected by new page mapping 0 tlbp/tlbr 0 tlbr move from coprocessor zero register 0 move to entryhi tlbwr/tlbwi/tlbp 1 move to entrylow0 or entrylo1 tlbwr/tlbwi 0 move to entryhi load/store affected by new asid 1 move to entryhi instruction fetch affected by new asid 3 tlbp move from coprocessor zero register 0 move to index register tlbr/tlbwi 1 table 2.5 instruction hazards (part 1 of 2) 1st instruction 2nd instruction issue delay (in clock cycles) slip stage table 2.4 instruction interlocks (part 2 of 2)
idt mips32 4kc processor core memory management 79rc32438 user reference manual 2 - 20 november 4, 2002 notes memory management the mmu in a 4kc processor core will translate any virtual address to a physical address before a request is sent to the cache controllers for tag co mparison or to the bus interface unit for an external memory reference. this translation is a very useful feature for operating systems when trying to manage physical memory to accommodate multiple tasks acti ve in the same memory, possibly on the same virtual address but of course in different locations in physical memory. other features handled by the mmu are protection of memory areas and defining the cache protocol. in the 4kc processor core, the mmu is tlb based. the tlb consists of three address translation buffers: a 16 dual-entry fully associative joint tlb (j tlb), a 3-entry instructi on micro tlb (itlb), and a 3- entry data micro tlb (dtlb). when an address is transla ted, the appropriate micro tlb (itlb or dtlb) is accessed first. if the translation is not found in the micro tlb, the jtlb is accessed. if there is a miss in the jtlb, an exception is taken. figure 2.19 shows how the memory management unit inte racts with cache accesses in the 4kc core. change to cu bits in status register coprocessor instruction 1 move to epc, errorpc, or depc eret 1 move to status register eret 0 set of ip in cause register interrupted instruction 3 any other move to coprocessor 0 registers instruction affected by change 2 cache instruction operating on i$ instruction fetch seeing new cache state 3 ll move from lladdr 1 move to compare instruction not seeing timer interrupt 4 1 1. this is the minimum value. actual va lue is system-dependent since it is a function of the sequential logic between the si-timerint output and the external logic which fe eds si-timerint back into one of the si_int inputs. 1st instruction 2nd instruction spacing (instructions) table 2.5 instruction hazards (part 2 of 2)
idt mips32 4kc processor core memory management 79rc32438 user reference manual 2 - 21 november 4, 2002 notes figure 2.19 address translation during a cache access modes of operation the 4kc processor core supports three modes of operation: user mode kernel mode debug mode user mode is most often used for application progr ams. kernel mode is typically used for handling exceptions and privileged operating system f unctions, including cp0 management and i/o device accesses. debug mode is used for software debugging and most likely occurs within a software develop- ment tool. the address translation performed by t he mmu depends on the mode in which the processor is operating. virtual memory segments the virtual memory segments are different depending on the mode of operation. figure 2.20 shows the segmentation for the 4 gbyte (232 bytes) virtual memo ry space addressed by a 32-bit virtual address, for the three modes of operation. the core enters kernel mode both at reset and when an exception is recognized. while in kernel mode, software has access to the entire address space, as we ll as all cp0 registers. user mode accesses are limited to a subset of the virtual address space (0x0000_0000 to 0x7fff_ffff) and can be inhibited from accessing cp0 functions. in user mode, virtual addresses 0x8000_0000 to 0xffff_ffff are invalid and cause an exception if accessed. debug mode is entered on a debug exception. whil e in debug mode, the debug software has access to the same address space and cp0 registers as for ke rnel mode. in addition, while in debug mode the core has access to the debug segment dseg. this area over lays part of the kernel segment kseg3. dseg access in debug mode can be turned on or off, allowing full access to the entire kseg3 in debug mode, if so desired. instruction virtual address (iva) data virtual address (dva) jtlb itlb instruction cache ram dtlb data cache ram iva entry entry data physical address (dpa) instruction physical address (ipa) tag (ipa) tag (dpa) comparator comparator data hit/miss instruction hit/ miss
idt mips32 4kc processor core memory management 79rc32438 user reference manual 2 - 22 november 4, 2002 notes figure 2.20 4k processor core virtual memory map each of the segments shown in figure 2.20 is either mapped or unmapped. t he following two subsec- tions, unmapped segments and mapped segments, explain t he distinction. following this, the user mode, kernel mode, and debug mode sections specify which segments are actually mapped and unmapped. unmapped segments an unmapped segment in the 4kc core does not use t he tlb to translate from virtual to physical address. especially after reset, it is important to have unmapped memory segments because the tlb is not yet programmed to perform the translation. unmapped segments have a fixed simple translation from virtual to physical address. except for kseg0, unmapped segments are always uncached. the cacheability of kseg0 is set in the k0 field of the cp0 register config (see the config r egister (cp0 register 16, select 0) section later in this chapter. mapped segments a mapped segment in the 4kc core does use the tlb. the translation of mapped segments is handled on a per-page basis. included in this translation is information defining whether the page is cacheable or not, and the protection attributes that apply to the page. useg kuseg kuseg kseg0 kseg1 kseg2 kseg3 kseg2 kseg1 kseg0 kseg3 kseg3 dseg user mode kernel mode debug mode virtual address 0x7fff_ffff 0x8000_0000 0x9fff_ffff 0xbfff_ffff 0xdfff_ffff 0xf1ff_ffff 0xf3ff_ffff 0xffff_ffff 0xa000_0000 0xc000_0000 0xe000_0000 0xf200_0000 0xf400_0000 0x0000_0000
idt mips32 4kc processor core memory management 79rc32438 user reference manual 2 - 23 november 4, 2002 notes user mode in user mode, a single 2 gbyte (231 bytes) unifo rm virtual address space called the user segment (useg) is available. figure 2.21 shows the location of user mode virtual address space. figure 2.21 user mode virtual address space the user segment starts at address 0x0000_0000 and ends at address 0x7fff_ffff. accesses to all other addresses cause an address error exception. the processor operates in user mode when the status register contains the following bit values: um = 1 exl = 0 erl = 0 in addition to the above values, the dm bit in the d ebug register must be 0. tabl e 2.6 lists the character- istics of the useg user mode segments. all valid user mode virtual addresses have their most-significant bit cleared to 0, indicating that user mode can only access the lower half of the virtual memo ry map. any attempt to reference an address with the most-significant bit set while in us er mode causes an address error exception. the system maps all references to useg through t he tlb. the virtual address is extended with the contents of the 8-bit asid field to form a unique virtual address before tr anslation. bit settings within the tlb entry for the page determine the cacheability of a reference. kernel mode the processor operates in kernel mode when the dm bit in the debug regi ster is 0 and the status register contains one or more of the following values: um = 0 erl = 1 exl = 1 address bit value status register segment name address range segment size bit value exl erl um 32-bit a(31)=0 0 0 1 useg 0x0000_0000 0x7fff_ffff 2 gbyte 2 31 bytes) table 2.6 user mode segments 0x0000_0000 0x8000_0000 0x7fff_ffff 0xffff_ffff 32 bit address error 2gb mapped useg
idt mips32 4kc processor core memory management 79rc32438 user reference manual 2 - 24 november 4, 2002 notes when a non-debug exception is detected, exl or erl will be set and the processor will enter kernel mode. at the end of the exception handler routine, an exception return (eret) instruction is generally executed. the eret instruction jumps to the except ion pc, clears erl, and clears exl if erl=0. this may return the processor to user mode. kernel mode virtual address space is divided into regions differentiat ed by the high-order bits of the virtual address, as shown in figure 2.22. also, tabl e 2.7 lists the characteristics of the kernel mode segments. figure 2.22 kernel mode virtual address space kernel virtual address space unmapped, 512mb kuseg kseg0 kseg1 kseg2 kseg3 mapped, 2048mb kernel virtual address space unmapped, uncached, 512mb kernel virtual address space mapped, 512mb kernel virtual address space mapped, 512mb 0x0000_0000 0x8000_0000 0xa000_0000 0xc000_0000 0xe000_0000 0x7fff_ffff 0x9fff_ffff 0xbfff_ffff 0xdfff_ffff 0xffff_ffff
idt mips32 4kc processor core memory management 79rc32438 user reference manual 2 - 25 november 4, 2002 notes kernel mode, user space (kuseg) in kernel mode, when the most-significant bit of the virtual address (a31) is cleared, the 32-bit kuseg virtual address space is selected and covers the full 231 bytes (2 gbyte) of the current user address space mapped to addresses 0x0000_0000 - 0x7fff_ffff. the vi rtual address is extended with the contents of the 8-bit asid field to form a unique virtual address. when erl = 1 in the status register, the user address region becom es a 231-byte unmapped and uncached address space. while in this setting, the kus eg virtual address maps directly to the same physical address, and does not include the asid field. kernel mode, kernel space 0 (kseg0) in kernel mode, when the most-significant three bits of the virtual address are 1002, 32-bit kseg0 virtual address space is selected; it is the 229-byte (512- mbyte) kernel virtual space located at addresses 0x8000_0000 - 0x9fff_ffff. references to ks eg0 are unmapped; the physical address selected is defined by subtracting 0x8000_0000 from the virtual addre ss. the k0 field of the config register controls cacheability. kernel mode, kernel space 1 (kseg1) in kernel mode, when the most-significant three bi ts of the 32-bit virtual address are 1012, 32-bit kseg1 virtual address space is selected. kseg1 is the 229-by te (512-mbyte) kernel virtual space located at addresses 0xa000_0000 - 0xbfff_ffff. references to kseg1 are unmapped; the physical address selected is defined by subtracting 0xa000_0000 from the virtual address. caches are disabled for accesses to these addresses, and physical memory (or memory-m apped i/o device registers) are accessed directly. kernel mode, kernel space 2 (kseg2) in kernel mode, when um = 0, erl = 1, or exl = 1 in the status register, and dm = 0 in the debug register, and the most-significant three bits of the 32-bit virtual address are 1102, 32-bit kseg2 virtual address space is selected. this 229-byte (512-mbyte) kernel virtual space is mapped through the tlb in the 4kc processor core. kernel mode, kernel space 3 (kseg3) in kernel mode, when the most-signi ficant three bits of the 32-bit virtual address are 1112, the kseg3 virtual address space is selected. this 229-byte ( 512-mbyte) kernel virtual space is mapped through the tlb in the 4kc processor core. address bit values status register is one of these values segment name address range segment size um exl erl a(31)=0 (um = 0 or exl = 1 or erl = 1) and dm = 0 kuseg 0x0000_0000 0x7fff_ffff 2 gbytes (2 31 bytes) a(31:29)=100 2 kseg0 0x8000_0000 0x9fff_ffff 512 mbytes (2 29 bytes) a(31:29)=101 2 kseg1 0xa000_0000 0xbfff_ffff 512 mbytes (2 29 bytes) a(31:29)=110 2 kseg2 0xc000_0000 0xdfff_ffff 512 mbytes (2 29 bytes) a(31:29)=111 2 kseg3 0xe000_0000 0xffff_ffff 512 mbytes (2 29 bytes) table 2.7 kernel mode segments
idt mips32 4kc processor core memory management 79rc32438 user reference manual 2 - 26 november 4, 2002 notes debug mode debug mode address space is identical to ker nel mode address space with respect to mapped and unmapped areas, except for kseg3. in kseg3, a debug se gment dseg co-exists in the virtual address range 0xff20_0000 to 0xff3f_ffff. the layout is shown in figure 2.23. figure 2.23 debug mode virtual address space the dseg is sub-divided into the dmseg segment at 0xff20_0000 to 0xff2f_ffff which is used when the probe services the memory segment, and the dr seg segment at 0xff30_0000 to 0xff3f_ffff which is used when memory mapped debug registers are acce ssed. the subdivision and attributes for the segments are shown in table 2.8. accesses to memory that would normally cause an exc eption if tried from ker nel mode cause the core to re-enter debug mode via a debug mode exception. this in cludes accesses usually causing a tlb exception (4kc core only), with the result that such ac cesses are not handled by the usual memory management routines. the unmapped kseg0 and kseg1 segments from kernel mode address space are available from debug mode, which allows the debug handler to be executed from uncached and unmapped memory. conditions and behavior for access to drseg and ejtag registers the behavior of cpu access to the drseg addre ss range at 0xff30_0000 to 0xff3f_ffff is deter- mined as shown in table 2.9. segment name sub-segment name virtual address generates physical address cache attribute dseg dmseg 0xff20_0000 through 0xff2f_ffff mseg maps to addresses 0x0_0000 - 0xf_ffff in ejtag probe mem- ory space. uncached drseg 0xff30_0000 through 0xff3f_ffff drseg maps to the breakpoint registers 0x0_0000 - 0xf_ffff table 2.8 physical address and cache attribut es for dseg, dmseg, and drseg address spaces 0x0000_0000 0xff20_0000 0xff40_0000 0xffff_ffff dseg kseg1 kseg0 unmapped mapped if mapped in kernel mode
idt mips32 4kc processor core memory management 79rc32438 user reference manual 2 - 27 november 4, 2002 notes debug software is expected to read the debug control register (dcr) to deter mine which other memory mapped registers exist in drseg. t he value returned in response to a read of any unimplemented memory mapped register is unpredictable, and writes are ignored to any unimple mented register in the drseg. the allowed access size is limited for the drseg. only word size transactions are al lowed. operation of the processor is undefined for other transaction sizes. conditions and behavior for access to dmseg, ejtag memory the behavior of cpu access to the dmseg addre ss range at 0xff20_0000 to 0xff2f_ffff is deter- mined by table 2.10. the case with access to the dmseg when the proben bit in the dcr register is 0 is not expected to happen. debug software is expected to check the state of the proben bit in dcr register before attempting to reference dmseg. if such a reference does happen, t he reference hangs until it is satisfied by the probe. the probe can not assume that there will never be a reference to dmseg if the proben bit in the dcr register is 0 because there is an inherent race between the debug software sampling the proben bit as 1 and the probe clearing it to 0. translation lookaside buffer the following subsections discuss the tlb memo ry management scheme used in the 4kc processor core. the tlb consists of one joint and two micro address translation buffers: 16 dual-entry fully associative joint tlb (jtlb) 3-entry fully associative instruction micro tlb (itlb) 3-entry fully associative data micro tlb (dtlb). transaction lsnm bit in debug register access load / store 1 kernel mode address space (kseg3) fetch don?t care drseg, see comments below load / store 0 table 2.9 cpu access to drseg address range transaction proben bit in dcr register lsnm bit in debug register access load / store don?t care 1 kernel mode address space (kseg3) fetch 1 don?t care dmseg load / store 1 0 fetch 0 don?t care see comments below load / store 0 0 table 2.10 cpu access to dmseg address range
idt mips32 4kc processor core memory management 79rc32438 user reference manual 2 - 28 november 4, 2002 notes joint tlb the 4kc core implements a 16 dual-entry, fully associat ive joint tlb that maps 32 virtual pages to their corresponding physical addresses. the jtlb is organized as 16 pairs of even and odd entries containing pages that range in size from 4-kbytes to 16-mb ytes into the 4-gbyte physical address space. the purpose of the tlb is to translate virtual addr esses and their corresponding address space identifier (asid) into a physical memory address. the translati on is performed by comparing the upper bits of the virtual address (along with t he asid bits) against each of the entries in the tag portion of the jtlb structure. because this structure is used to translate both instru ction and data virtual addresses, it is referred to as a ?joint? tlb. the jtlb is organized in page pairs to minimize its overall size. each virtual tag entry corresponds to two physical data entries, an even page entry and an odd page entry. the highest order virtual address bit not participating in the tag comparison is used to det ermine which of the two data entries is used. since page size can vary on a page-pair basis, the determinati on of which address bits participate in the compar- ison and which bit is used to make the even-odd det ermination must be determi ned dynamically during the tlb lookup. figure 2.24 show the contents of one of the 16 dual-entries in the jtlb. figure 2.24 jtlb entry (tag and data) pagemask[24:13] d0 g asid[7:0] pfn0[31:12] c0[2:0] d1 pfn1[31:12] c1[2:0] vpn2[31:13] v0 v1 g tag entry data entries 19 1 8 20 3 1 1
idt mips32 4kc processor core memory management 79rc32438 user reference manual 2 - 29 november 4, 2002 notes table 2.11 and table 2.12 explain each of the fields in a jtlb entry. field name description pagemask[24:13] page mask value. the page mask defines the page size by masking the appropriate vpn2 bits from being involved in a comparison. it is also used to determine which address bit is used to make the even-odd page (pfn0-pfn1) determination. see the table below. the pagemask column above show all the legal values for pagemask. because each pair of bits can only have the same value, the physical entry in the jtlb will only save a compressed version of the pagemask using only 6 bits. however, this is transparent to software, which will always work with a 12 bit field. vpn2[31:13] virtual page number divided by 2. this field contains the upper bits of the virtual page number. because it represents a pair of tlb pages, it is divided by 2. bits 31:25 are always included in the tlb lookup comparison. bits 24:13 are included depending on the page size, defined by pagemask. g global bit. when set, indicates that this entry is global to all processes and/or threads and thus disables inclusion of the asid in the comparison. asid[7:0] address space identifier. identifies which process or thread this tlb entry is associ- ated with. table 2.11 tlb tag entry fields pagemask[11:0] page size even/odd bank select bit 0000_0000_0000 4kb vaddr[12] 0000_0000_0011 16kb vaddr[14] 0000_0000_1111 64kb vaddr[16] 0000_0011_1111 256kb vaddr[18] 0000_1111_1111 1mb vaddr[20] 0011_1111_1111 4mb vaddr[22] 1111_1111_1111 16mb vaddr[24]
idt mips32 4kc processor core memory management 79rc32438 user reference manual 2 - 30 november 4, 2002 notes in order to fill an entry in the jtlb, software ex ecutes a tlbwi or tlbwr instruction (see the tlb instructions section). prior to invoking one of thes e instructions, several cp0 registers must be updated with the information to be written to a tlb entry: pagemask is set in the cp0 pagemask register vpn2 and asid are set in the cp0 entryhi register pfn0, c0, d0, v0 and g bit are set in the cp0 entrylo0 register pfn1, c1, d1, v1 and g bit are set in the cp0 entrylo1 register. note that the global bit ?g? is part of both entrylo0 and entrylo1. the resulting ?g? bit in the jtlb entry is the logical and between the two fields in entry lo0 and entrylo1. for additional information, refer to section ?cp0 registers? on page 2-56. the address space identifier (asid) helps to reduce the frequency of tlb flushing on a context switch. the existence of the asid allows multiple processe s to exist in both the tlb and instruction caches. the asid value is stored in the entryhi register and is compared to the asid value of each entry. instruction tlb the itlb is a small 3-entry, fully associative tlb dedi cated to performing translations for the instruction stream. the itlb only maps 4-kbyte pages/sub-pages. the itlb is managed by hardware and is transparent to software. if a fetch address cannot be trans- lated by the itlb, the jtlb is accessed to attempt to translate it in the followi ng clock cycle. if successful, the translation information is copied into the itlb . the itlb is then re-accessed and the address will be successfully translated. this results in an itlb miss penalty of at least 2 cycles (if the jtlb is busy with other operations, it may take additional cycles). field name description pfn0[31:12], pfn1[31:12] physical frame number. defines the upper bits of the physical address. for page sizes larger than 4 kbytes, only a subset of these bits is actually used. c0[2:0], c1[2:0] cacheability. contains an encoded value of the cacheability attributes and determines whether the page should be placed in the cache or not. the field is encoded as fol- lows: d0, d1 ?dirty? or write-enable bit. indicates that the page has been written, and/or is writable. if this bit is set, stores to the page are permitted. if the bit is cleared, stores to the page cause a tlb modified exception. v0, v1 valid bit. indicates that the tlb entry and, thus, the virtual page mapping are valid. if this bit is set, accesses to the page are permitted. if the bit is cleared, accesses to the page cause a tlb invalid exception. table 2.12 tlb data entry fields c[2:0] coherency attribute 000 cacheable, noncoherent, writ e-through, no write allocated 001 cacheable, noncoherent, writ e-through, no write allocated 010 uncached 011 cacheable, noncoherent, writ e-through, no write allocated 100 cacheable, noncoherent, writ e-through, no write allocated 101 cacheable, noncoherent, writ e-through, no write allocated 110 cacheable, noncoherent, writ e-through, no write allocated 111 cacheable, noncoherent, writ e-through, no write allocated
idt mips32 4kc processor core memory management 79rc32438 user reference manual 2 - 31 november 4, 2002 notes data tlb the dtlb is a small 3-entry, fully associative tl b which provides a faster translation for load/store addresses than is possible with the jtlb . the dtlb only maps 4-kbyte pages/sub-pages. like the itlb, the dtlb is managed by hardware and is transparent to software. unlike the itlb, when translating load/store addresses, the jtlb is accessed in parallel with the dtlb. if there is a dtlb miss and a jtlb hit, the dtlb can be reloaded that cycle. the dtlb is then re-accessed and the translation will be successful. this parallel access reduc es the dtlb miss penalty to 1 cycle. virtual to physical address translation converting a virtual address to a physical address begins by comparing the virtual address from the processor with the virtual addresses in the tlb. there is a match when the virtual page number (vpn) of the address is the same as the vpn field of the entry, and either: the global (g) bit of both the even and odd pages of the tlb entry are set, or the asid field of the virtual address is t he same as the asid field of the tlb entry. this match is referred to as a tlb hit. if there is no match, a tlb miss exception is taken by the processor and software is allowed to refill the tl b from a page table of virtual/physical addresses in memory. figure 2.25 shows the logical translati on of a virtual address into a physi cal address. in this figure, the virtual address is extended with an 8-bit address-space identifier (asi d), which reduces the frequency of tlb flushing during a context switch . this 8-bit asid contains the number assigned to that process and is stored in the cp0 entryhi register. figure 2.25 overview of a virtua l-to-physical address translation if there is a virtual address match in the tlb, the physical frame number (pfn) is output from the tlb and concatenated with the offset, to form the physica l address. the offset represents an address within the page frame space. as shown in figure 2.25, the offset does not pass through the tlb. 1.virtual address (va) represented by the virtual page number (vpn) is compared with tag in tlb. 2. if there is a match, the page frame number (pfn0 or pfn1) representing the upper bits of the physical address (pa) is output from the tlb. 3. the offset, which does not pass through the tlb, is then concatenated with the pfn. offset vpn gasid virtual address tlb entry offset pfn tlb g asid vpn2 c0 d0 v0 pfn0 pfn1 c1 d1 v1 physical address
idt mips32 4kc processor core memory management 79rc32438 user reference manual 2 - 32 november 4, 2002 notes figure 2.26 shows a flow diagram of the 4kc core address translation process. the top portion of the figure shows a virtual address for a 4-kbyte page size. t he width of the offset is defined by the page size. the remaining 20 bits of the address represent the virtual page number (vpn), that index the 1m-entry page table. the bottom portion of figure 2.26 shows the virtual address for a 16-mbyte page size. the remaining 8 bits of the address represent the vpn , that index the 256-entry page table. figure 2.26 32-bit virtual address translation hits, misses, and multiple matches each jtlb entry contains a tag and two data fields . if a match is found, the upper bits of the virtual address are replaced with the page frame number (pfn) stored in the corresponding entry in the data array of the jtlb. the granularity of jtlb mappings is defined in terms of tlb pages. the 4kc core jtlb supports pages of different sizes ranging from 4 kb to 16 mb in power s of 4. if a match is found, but the entry is invalid (i.e., the v bit in the data fi eld is 0), a tlb invalid exception is taken. if no match occurs (tlb miss), an exception is taken and software refills the tlb from the page table resident in memory. figure 2.27 show the translation and exception flow of the tlb. software can write over a selected tlb entry or use a hardware mechanism to write into a random entry. the random register selects which tlb entry to use on a tlbwr. this register decrements almost every cycle, wrapping to the maximum once it?s value is equal to the wired register. thus, tlb entries below the wired value cannot be replaced by a tlbwr allowing important mappings to be preserved. in order to reduce the possibility for a livelock situation, the random register in cludes a 10b lfsr that introduces a pseudo-random perturbation into the decrementing. the 4kc core implements a tlb write-compare mechanism to ensure that multiple tlb matches do not occur. on the tlb write operation, the vpn2 field to be written is compared with all other entries in the tlb. if a match occurs, the 4kc core takes a machine-check exc eption, sets the ts bit in the cp0 status register, and aborts the write operation. for additional informati on on exceptions, see the exceptions section later in this chapter. there is a hidden bit in each tlb entry that is cleared on a coldreset. this bit is set once the tlb entry is written and is included in the match det ection. therefore, uninitialized tlb entries will not cause a tlb shutdown. 11 virtual address with 1m (2 20 ) 4-kbyte pages virtual address with 256 (2 8 )16-mbyte pages 8 bits = 256 pages 20 bits = 1m pages virtual-to-physical bit 31 of the virtual address selects user and kernel address spaces. offset passed unchanged to physical memory. virtual-to-physical translation in tlb offset passed unchanged to physical memory. 32-bit physical address asid vpn offset pfn0/1 offset tlb tlb asid vpn offset 0 23 31 32 24 39 31 32 39 0 12 0 31 88 24 820 12
idt mips32 4kc processor core memory management 79rc32438 user reference manual 2 - 33 november 4, 2002 notes note: this hidden initialization bit leaves the entire jtlb invalid after a coldreset, eliminating the need to flush the tlb. but, to be compatible with other mips processors, it is recommended that software initialize all tlb entries with uniq ue tag values and v bits cleared before the first access to a mapped location. page sizes and replacement algorithm to assist in controlling both the amount of mapped space and the replacement c haracteristics of various memory regions, the 4kc core provides two mechani sms. first, the page size can be configured, on a per entry basis, to map page sizes ranging from 4 kbyte to 16 mbyte (in multiples of 4). the cp0 pagemask register is loaded with the desired page size, which is then entered into the tlb when a new entry is written. thus, operating systems can provide special-purpose maps. for example, a typical frame buffer can be memory mapped with only one tlb entry. the second mechanism controls t he replacement algorithm when a tl b miss occurs. to select a tlb entry to be written with a new mapping, the 4kc core provides a random replac ement algorithm. however, the processor also provides a mechanism whereby a programmable number of mappings can be locked into the tlb via the cp0 wired register, thus avoi ding random replacement. for additional information, see the wired register (cp0 register 6, se lect 0) section later in this chapter.
idt mips32 4kc processor core memory management 79rc32438 user reference manual 2 - 34 november 4, 2002 notes figure 2.27 tlb address translation flow in the 4kc processor core tlb instructions table 2.13 lists the 4kc core?s tlb-related instructio ns. for additional information on these instructions, see appendix a, 4kc processor core instructions. for valid address space, see the section describing modes of operation in this chapter. virtual address (input) vpn and asid user mode? no yes no yes no yes no no no no no no no yes yes yes yes yes yes yes exception global valid dirty noncacheable physical address (output) user address? address error unmapped address kseg0/kseg1 address vpn match? g = 1? c=010 or asid match? v = 1? d = 1? write? tlb modified tlb invalid tlb refill access cache access main
idt mips32 4kc processor core exceptions 79rc32438 user reference manual 2 - 35 november 4, 2002 notes system control coprocessor the system control coprocessor (c p0) is implemented as an integral part of the 4kc processor core and supports memory management, address translati on, exception handling, and other privileged opera- tions. certain cp0 registers are used to support me mory management. for additional information on the cp0 register set, see the cp0 regist ers section later in this chapter. exceptions the 4kc processor core receives exceptions from a number of sources, including translation lookaside buffer (tlb) misses, arithmetic overflows, i/o in terrupts, and system calls. when the cpu detects one of these exceptions, the normal sequence of instruct ion execution is suspended and the processor enters kernel mode. in kernel mode, the core disables interrupts and fo rces execution of a softw are exception processor (called a handler) located at a fixed address. the handler saves the context of the processor, including the contents of the program counter, the current operati ng mode, and the status of the interrupts (enabled or disabled). this context is saved so it c an be restored when the exception has been serviced. when an exception occurs, the core loads the excepti on program counter (epc) register with a location where execution can restart after t he exception has been serviced. the re start location in the epc register is the address of the instruction that caused the exception or, if the instruction was executing in a branch delay slot, the address of the branch instruction im mediately preceding the delay slot. to distinguish between the two, software must read the bd bit in the cp0 cause register. exception conditions when an exception condition occurs, the relevant instru ction and all those that follow it in the pipeline are cancelled. accordingly, any stall conditions and any later exception conditions that may have refer- enced this instruction are inhibited; there is no benef it in servicing stalls for a cancelled instruction. when an exception condition is detected on an instructi on fetch, the core aborts that instruction and all instructions that follow. when this instruction reaches the w stage, the exception flag causes it to write various cp0 registers with the exception state, c hange the current program counter (pc) to the appropriate exception vector address, and clear the e xception bits of earlier pipeline stages. this implementation allows all preceding instructi ons to complete execution and prevents all subse- quent instructions from completing. thus, the val ue in the epc (errorepc for errors or depc for debug exceptions) is sufficient to restart execution. it also ensures that exceptions are taken in the order of execu- tion; an instruction taking an exception may itself be killed by an instruction further down the pipeline that takes an exception in a later cycle. exception priority table 2.14 lists all possibl e exceptions and the relative priority of each, highest to lowest. several of these exceptions can happen simultaneously. if that happens, the exception with the highest priority is the one taken. op code description of instructions tlbp translation lookaside buffer probe tlbr translation lookaside buffer read tlbwi translation lookaside buffer write index tlbwr translation lookaside buffer write random table 2.13 tlb instructions
idt mips32 4kc processor core exceptions 79rc32438 user reference manual 2 - 36 november 4, 2002 notes exception vector locations the reset, soft reset, and nmi exceptions are always vectored to location 0xbfc0_0000. debug exceptions are vectored to location 0xbfc0_0480 or to location 0xff20_0200 if the probtrap bit is 0 or 1, respectively, in the ejtag control register (ecr). addr esses for all other exceptions are a combination of a vector offset and a base address. table 2.15 gives the base address as a func tion of the exception and exception condition reset assertion of si_coldreset signal. soft reset assertion of si_reset signal. dss ejtag debug single step. dint ejtag debug interrupt. caused by the asse rtion of the external ej_dint input, or by setting the ejtagbrk bit in the ecr register. nmi asserting edge of si_nmi signal. machine check tlb write that conflicts with an existing entry. interrupt assertion of unmasked hw or sw interrupt signal. deferred watch deferred watch (unmasked by k|dm->!(k|dm) transition). dib ejtag debug hardware instruction break matched. watch a reference to an address in one of the watch registers (fetch). adel fetch address alignment error. user mode fetch reference to kernel address. tlbl fetch tlb miss. fetch tlb hit to page with v=0. ibe instruction fetch bus error. dbp ejtag breakpoint (execution of sdbbp instruction). sys execution of syscall instruction. bp execution of break instruction. cpu execution of a coprocessor instruction for a coprocessor that is not enabled. ri execution of a reserved instruction. ov execution of an arithmetic instruction that overflowed. tr execution of a trap (when trap condition is true). ddbl / ddbs ejtag data addre ss break (address only) or ejtag data value break on store (address and value). watch a reference to an address in one of the watch registers (data). adel load address alignment error. user mode load reference to kernel address. ades store address alignment error. user mode store to kernel address. tlbl load tlb miss. load tlb hit to page with v=0. tlbs store tlb miss. store tlb hit to page with v=0. table 2.14 priority of exceptions
idt mips32 4kc processor core exceptions 79rc32438 user reference manual 2 - 37 november 4, 2002 notes whether the bev bit is set in the status register. t able 2.16 gives the offsets from the base address as a function of the exception. table 2.17 combines these tw o tables into one that contains all possible vector addresses as a function of the state t hat can affect the vector selection. exception status bev 01 reset, soft reset, nmi 0xbfc0_0000 debug (with probtrap = 0 in the ecr ) 0xbfc0_0480 debug (with probtrap = 1 in the ecr ) 0xff20_0200 (in dmseg handled by probe, and not system memory) other 0x8000_0000 0xbfc0_0200 table 2.15 exception vector base addresses exception vector offset tlb refill, exl = 0 (4kc core) 0x000 reset, soft reset, nmi 0x000 (uses reset base address) general exception 0x180 interrupt, cause iv = 1 0x200 table 2.16 exception vector offsets exception bev exl iv ejtag probtrap vector reset, soft reset, nmi x x x x 0xbfc0_0000 debug x x x 0 0xbfc0_0480 debug x x x 1 0xff20_0200 (in dmseg) tlb refill 0 0 x x 0x8000_0000 tlb refill 0 1 x x 0x8000_0180 tlb refill 1 0 x x 0xbfc0_0200 tlb refill 1 1 x x 0xbfc0_0380 interrupt 0 0 0 x 0x8000_0180 interrupt 0 0 1 x 0x8000_0200 interrupt 1 0 0 x 0xbfc0_0380 interrupt 1 0 1 x 0xbfc0_0400 all others 0 x x x 0x8000_0180 all others 1 x x x 0xbfc0_0380 table 2.17 exception vectors
idt mips32 4kc processor core exceptions 79rc32438 user reference manual 2 - 38 november 4, 2002 notes general exception processing with the exception of reset, soft reset, nmi, and debug exceptions, which have their own special processing as described bel ow, exceptions have the same basic processing flow: 1. if the exl bit in the status register is cleared, the epc register is loaded with the pc at which execu- tion will be restarted and the bd bit is set appropriate ly in the cause register. if the instruction is not in the delay slot of a branch, the bd bit in c ause will be cleared and the value loaded into the epc register is the current pc. if the instruction is in t he delay slot of a branch, the bd bit in cause is set and epc is loaded with pc-4. if the exl bit in the status register is set, the epc register is not loaded and the bd bit is not changed in the cause register. 2. the ce and exccode fields of the cause regist ers are loaded with the values appropriate to the exception. the ce field is loaded, but not defi ned, for any exception type other than a coprocessor unusable exception. 3. the exl bit is set in the status register. 4. the processor is started at the exception vector. the value loaded into epc represents the restart address for the exception and need not be modified by exception handler software in the normal case. software need not look at the bd bit in the cause register unless is wishes to identify the address of the instruction that actually caused the exception. note that individual exception types may load additional information into other registers. this is noted in the description of each exception type below. operation: if status exl = 0 then if instructioninbranchdelayslot then epc << pc - 4 causebd << 1 else epc << pc causebd << 0 endif if exceptiontype = tlbrefill then vectoroffset << 0x000 elseif (exceptiontype = interrupt) and (causeiv = 1) then vectoroffset << 0x200 else vectoroffset << 0x180 endif else vectoroffset << 0x180 endif causece << faultingcoprocessornumber causeexccode << exceptiontype statusexl << 1 if statusbev = 1 then pc << 0xbfc0_0200 + vectoroffset else pc << 0x8000_0000 + vectoroffset endif
idt mips32 4kc processor core exceptions 79rc32438 user reference manual 2 - 39 november 4, 2002 notes debug exception processing all debug exceptions have the same basic processing flow: 1. the depc register is loaded with the program counter (pc) value at which execution will be restarted and the dbd bit is set appropriately in the debug register. the value loaded into the depc register is the current pc if the instruction is not in the delay slot of a branch, or the pc-4 of the branch if the instruction is in the delay slot of a branch. 2. the dss, dbp, ddbl, ddbs, dib and dint bits (d * bits at [5:0]) in the debug register are updated appropriately depending on the debug exception type. 3. halt and doze bits in the debug register are updated appropriately. 4. dm bit in the debug register is set to 1. 5. the processor is started at the debug exception vector. the value loaded into depc represents the re start address for the debug exception and need not be modified by the debug exception handler software in the usual case. debug software need not look at the dbd bit in the debug register unless it wishes to ident ify the address of the instruction that actually caused the debug exception. a unique debug exception is indicated through the dss, dbp, ddbl, ddbs, dib and dint bits (d* bits at [5:0]) in the debug register. no other cp0 registers or fiel ds are changed due to the debug exception, thus no additional state is saved. operation: if instructioninbranchdelayslot then depc << pc-4 debugdbd << 1 else depc << pc debugdbd << 0 endif debugd* bits at at [5:0] <- debugexceptiontype debughalt << haltstatusatdebugexception debugdoze << dozestatusatdebugexception debugdm << 1 if ejtagcontrolregisterprobtrap = 1 then pc << 0xff20_0200 else pc << 0xbfc0_0480 endif the same debug exception vector location is used for all debug exceptions. the location is determined by the probtrap bit in the ejtag control register (ecr), as shown in table 2.18. exceptions the following subsections describe each of the exc eptions listed in the same sequence as shown in table 2.14. probtrap bit in ecr register debug exception vector address 0 0xbfc0_0480 1 0xff20_0200 in dmseg table 2.18 debug exception vector addresses
idt mips32 4kc processor core exceptions 79rc32438 user reference manual 2 - 40 november 4, 2002 notes reset exception a reset exception occurs when the si_coldreset signal is asserted to the processor. this exception is not maskable. when a reset exception occurs, the proc essor performs a full reset initialization, including aborting state machines, establishing cr itical state, and generally placing the processor in a state in which it can execute instructions from uncached, unmapped address space. on a reset exception, the state of the processor in not defined, with the following exceptions: the random register is initialized to t he number of tlb entries - 1 (4kc core. the wired register is initialized to zero (4kc core) the config register is initialized with its boot state the rp, bev, ts, sr, nmi, and erl fields of the stat us register are initialized to a specified state the i, r, and w fields of the watchlo register are initialized to 0 the errorepc register is loaded with pc-4 if the st ate of the processor indicates that it was execut- ing an instruction in the delay slot of a branch. otherwise, the errorepc r egister is loaded with pc. note that this value may or may not be predictable. pc is loaded with 0xbfc0_0000. cause register exccode value: none additional state saved: none entry vector used: reset (0xbfc0_0000) operation: random << tlbentries - 1 wired << 0 config << configurationstate statusrp << 0 statusbev << 1 statusts << 0 statussr << 0 statusnmi << 0 statuserl << 1 watchloi << 0 watchlor << 0 watchlow << 0 if instructioninbranchdelayslot then errorepc << pc - 4 else errorepc << pc endif pc << 0xbfc0_0000 soft reset exception a soft reset exception occurs when the si_reset signal is asserted to the processor. this exception is not maskable. when a soft reset exception occurs, the pr ocessor performs a subset of the full reset initial- ization. although a soft reset exception does not unnecessa rily change the state of the processor, it may be forced to do so in order to place the processor in a st ate in which it can execute instructions from uncached, unmapped address space. since bus, cache, or other op erations may be interrupted, portions of the cache, memory, or other processor state may be inconsistent. in addition to any hardware initialization required, the following state is established on a soft reset exception: the bev, ts, sr, nmi, and erl fields of the status register are initialized to a specified state.
idt mips32 4kc processor core exceptions 79rc32438 user reference manual 2 - 41 november 4, 2002 notes the errorepc register is loaded with pc-4 if the st ate of the processor indicates that it was execut- ing an instruction in the delay slot of a branch. otherwise, the errorepc r egister is loaded with pc. note that this value may or may not be predictable. pc is loaded with 0xbfc0_0000. cause register exccode value: none additional state saved: none entry vector used: reset (0xbfc0_0000) operation: statusbev << 1 statusts << 0 statussr << 1 statusnmi << 0 statuserl << 1 if instructioninbranchdelayslot then errorepc << pc - 4 else errorepc << pc endif pc << 0xbfc0_0000 debug single step exception a debug single step exception occurs after the cp u has executed one/two instructions in non-debug mode, when returning to non-debug mode after debug mode. one instruction is allowed to execute when returning to a non jump/branch instruction, otherwise two instructions are allowed to execute since the jump/branch and the instruction in the delay slot are executed as one step. debug single step exceptions are enabled by the sst bit in the debug register, and are always disabled for the first one/two instructions after a deret. the depc register points to the instruction on wh ich the debug single step exception occurred, which is also the next instruction to single step or execute when returning from debug mode. so the depc will not point to the instruction which has just been single stepped, but rather the following instruction. the dbd bit in the debug register is never set for a debug single step exception, since the jump/branch and the instruc- tion in the delay slot is executed in one step. exceptions occurring on the inst ruction(s) executed with debug si ngle step exception enabled are taken even though debug single step was enabled. for a normal exception (other than reset), a debug single step exception is then taken on the first instruction in the normal exception handler. debug exceptions are unaf- fected by single step mode, e.g. returning to a sdbbp instruction with debug single step exceptions enabled causes a debug software breakpoi nt exception, and the depc will point to the sdbbp instruction. however, returning to an instruction (not jump/br anch) just before the sdbbp instruction, causes a debug single step exception with the depc pointing to the sdbbp instruction. to ensure proper functionality of single step, the debug single step exception has priority over all other exceptions, except reset and soft reset. debug register debug status bit set dss additional state saved none entry vector used
idt mips32 4kc processor core exceptions 79rc32438 user reference manual 2 - 42 november 4, 2002 notes debug exception vector debug interrupt exception a debug interrupt exception is either caused by the ejtagbrk bit in the ejtag control register (controlled through the tap), or caused by the debug interrupt request signal to the cpu. the debug interrupt exception is an asynchronous debug exception which is taken as soon as possible, but with no specific relation to the executed instructions . the depc register is set to the instruction where execution should continue after t he debug handler is through. the dbd bit is set based on whether the interrupted instruction was executing in the delay slot of a branch. debug register debug status bit set dint additional state saved none entry vector used debug exception vector non-maskable interrupt (nmi) exception a non-maskable interrupt exception occurs when t he si_nmi signal is asserted to the processor. si_nmi is an edge sensitive signal - onl y one nmi exception will be taken eac h time it is asserted. an nmi exception occurs only at instruction boundaries, so it does not cause any reset or other hardware initializa- tion. the state of the cache, memory, and other proc essor states are consistent and all registers are preserved, with the following exceptions: the bev, ts, sr, nmi, and erl fields of the status register are initialized to a specified state. the errorepc register is loaded with pc-4 if the st ate of the processor indicates that it was execut- ing an instruction in the delay slot of a branch. otherwise, the errorepc register is loaded with pc. pc is loaded with 0xbfc0_0000. cause register exccode value: none additional state saved: none entry vector used: reset (0xbfc0_0000) operation: statusbev << 1 statusts << 0 statussr << 0 statusnmi << 1 statuserl << 1 if instructioninbranchdelayslot then errorepc << pc - 4 else errorepc << pc endif pc << 0xbfc0_0000 machine check exception a machine check exception occurs when the processor detects an inter nal inconsistency. the following condition causes a machine check exception:
idt mips32 4kc processor core exceptions 79rc32438 user reference manual 2 - 43 november 4, 2002 notes the detection of multiple matching entries in t he tlb in a tlb-based mmu. the core detects this condition on a tlb write and prevents the write from being completed. the ts bit in the status reg- ister is set to indicate this condi tion. this bit is only a status flag and does not affect the operation of the device. software clears this bit at the appropriate time. this c ondition is resolved by flushing the conflicting tlb entries. the tlb write can then be completed. cause register exccode value: mcheck additional state saved: none entry vector used: general exception vector (offset 0x180) interrupt exception the interrupt exception occurs when one or more of the eight interrupt requests is enabled by the status register and the interrupt input is asse rted. the delay from assertion of an unmasked interrupt to fetch of the first instructions at the exception vector is a mi nimum of 5 clock cycles. more may be needed if a committed instruction has to complete before the exception can be taken. a sync instruction which has already started flushing the cache and write buffers must wait until this is completed before the interrupt exception can be taken. register exccode value: int additional state saved: entry vector used: general exception vector (offset 0x180) if the iv bit in the cause register is 0; interrupt vector (offset 0x200) if the iv bit in the cause register is 1. debug instruction break exception a debug instruction break exception occurs when an instruction hardware breakpoint matches an executed instruction. the depc register and dbd bit in the debug register indicates the instruction that caused the instruction hardware breakpoint to match. th is exception can only occur if instruction hardware breakpoints are implemented. debug register debug status bit set: dib additional state saved: none entry vector used: debug exception vector register state value cause ip indicates the interrupts that are pending. table 2.19 register states an interrupt exception
idt mips32 4kc processor core exceptions 79rc32438 user reference manual 2 - 44 november 4, 2002 notes watch exception ? instruction fetch or data access the watch facility provides a software debugging v ehicle by initiating a watch exception when an instruction or data reference matches the address info rmation stored in the watchhi and watchlo registers. a watch exception is taken immediately if the exl and er l bits of the status register are both zero and the dm bit of the debug is also zero. if any of those bits is a one at the time that a watch exception would normally be taken, the wp bit in the cause register is set, and the exception is deferred until both all three bits are zero. software may use the wp bit in the c ause register to determine if the epc register points at the instruction that caused the watch exception, or if the exception actually o ccurred while in kernel mode. the watch exception can occur on either an instruct ion fetch or a data access. watch exceptions that occur on an instruction fetch have a higher priority than watch exceptions that occur on a data access. register exccode value: watch additional state saved: entry vector used: general exception vector (offset 0x180) address error exception ? instruction fetch/data access an address error exception occurs on an instruction or data access when an attempt is made to execute one of the following: fetch an instruction, load a word, or store a word that is not aligned on a word boundary load or store a halfword that is not aligned on a halfword boundary reference the kernel addres s space from user mode. note that in the case of an instruction fetch t hat is not aligned on a word boundary, pc is updated before the condition is detected. therefore, both epc and b advaddr point to the unaligned instruction address. in the case of a data access the exception is taken if either an unaligned address or an address that was inac- cessible in the current processor mode was referenced by a load or store instruction. cause register exccode value: adel: reference was a load or an instruction fetch ades: reference was a store additional state saved: register state value cause wp indicates that the watch exception was deferred until after status exl , status erl , and debug dm were zero. this bit directly causes a watch exception, so software must clear this bit as part of the exception handler to prevent a watch exception loop at the end of the current handler execution. table 2.20 register states on a watch exception register state value badvaddr failing address context vpn2 unpredictable table 2.21 cp0 register states on an a ddress exception error (part 1 of 2)
idt mips32 4kc processor core exceptions 79rc32438 user reference manual 2 - 45 november 4, 2002 notes entry vector used: general exception vector (offset 0x180) tlb refill exception ? instruction fetch or data access during an instruction fetch or data access, a tlb re fill exception occurs when no tlb entry in a tlb- based mmu matches a reference to a mapped address sp ace and the exl bit is 0 in the status register. note that this is distinct from the case in which an ent ry matches but has the valid bit off. in that case, a tlb invalid exception occurs. cause register exccode value: tlbl: reference was a load or an instruction fetch tlbs: reference was a store additional state saved: entry vector used: tlb refill vector (offset 0x000) if statusexl = 0 at the time of exception; general exception vector (offset 0x180) if statusexl = 1 at the time of exception. tlb invalid exception ? instruction fetch or data access (4kc core) during an instruction fetch or data access, a tlb inva lid exception occurs in one of the following cases: no tlb entry in a tlb-based mmu matches a re ference to a mapped address space; and the exl bit is 1 in the status register a tlb entry in a tlb-based mmu matches a reference to a mapped address space, but the matched entry has the valid bit off the virtual address is greater than or equal to the bounds address in a fm-based mmu. cause register exccode value: tlbl: reference was a load or an instruction fetch tlbs: reference was a store additional state saved: entryhi vpn2 unpredictable entrylo0 unpredictable entrylo1 unpredictable register state value badvaddr failing address context the badvpn2 fields contains va 31:13 of the failing address. entryhi the vpn2 field contains va 31:13 of the failing address; the asid field contains the asid of the reference that missed. entrylo0 unpredictable entrylo1 unpredictable table 2.22 cp0 register states on a tlb refill exception register state value table 2.21 cp0 register states on an a ddress exception error (part 2 of 2)
idt mips32 4kc processor core exceptions 79rc32438 user reference manual 2 - 46 november 4, 2002 notes entry vector used: general exception vector (offset 0x180) bus error exception ? instruction fetch or data access a bus error exception occurs when an instruction or data access makes a bus request (due to a cache miss or an uncacheable reference) and that request termi nates in an error. the bus error exception can occur on either an instruction fetch or a data access. bu s error exceptions that occur on an instruction fetch have a higher priority than bus error ex ceptions that occur on a data access. bus errors taken on the requested (critical) word of an instruction fetch or data load are precise. other bus errors, such as stores or non-critical words of a burst read, can be imprecise. these errors are taken when the eb_rberr or eb_wberr signals are asserted and may occur on an instruction that was not the source of the offending bus cycle. cause register exccode value: ibe:error on an instruction reference dbe:error on a data reference additional state saved: none entry vector used: general exception vector (offset 0x180) debug software breakpoint exception a debug software breakpoint exception occurs when an sdbbp instruction is executed. the depc register and dbd bit in the debug r egister will indicate the sdbbp in struction that caused the debug excep- tion. debug register debug status bit set: dbp additional state saved: none entry vector used: debug exception vector execution exception ? system call the system call exception is one of the six executi on exceptions. all of thes e exceptions have the same priority. a system call exception occu rs when a syscall instruction is executed. register state value badvaddr failing address context the badvpn2 field contains va 31:13 of the failing address. entryhi the vpn2 field contains va 31:13 of the failing address; the asid field contains the asid of the reference that missed. entrylo0 unpredictable entrylo1 unpredictable table 2.23 cp0 register states on a tlb invalid exception
idt mips32 4kc processor core exceptions 79rc32438 user reference manual 2 - 47 november 4, 2002 notes cause register exccode value: sys additional state saved: none entry vector used: general exception vector (offset 0x180) execution exception ? breakpoint the breakpoint exception is one of the six execution exceptions. all of these exceptions have the same priority. a breakpoint exception occurs when a break instruction is executed. cause register exccode value: bp additional state saved: none entry vector used: general exception vector (offset 0x180) execution exception ? reserved instruction the reserved instruction exception is one of the six execution exceptions. all of these exceptions have the same priority. a reserved instruction exception occurs when a reserved or undefined major opcode or function field is executed. cause register exccode value: ri additional state saved: none entry vector used: general exception vector (offset 0x180) execution exception ? coprocessor unusable the coprocessor unusable exception is one of the si x execution exceptions. all of these exceptions have the same priority. a coprocessor unusable exce ption occurs when an attempt is made to execute a coprocessor instruction for one of the following: a corresponding coprocessor unit that has not been marked usable by setting its cu bit in the sta- tus register cp0 instructions, when the unit has not been marked usable, and the processor is executing in user mode. cause register exccode value: cpu additional state saved: register state value cause ce unit number of the coprocessor being referenced figure 2.28 register states on a coprocessor unusable exception
idt mips32 4kc processor core exceptions 79rc32438 user reference manual 2 - 48 november 4, 2002 notes entry vector used: general exception vector (offset 0x180) execution exception ? integer overflow the integer overflow exception is one of the six exec ution exceptions. all of these exceptions have the same priority. an integer overflow exception occurs when selected integer instructions result in a 2?s complement overflow. cause register exccode value: ov additional state saved: none entry vector used: general exception vector (offset 0x180) execution exception ? trap the trap exception is one of the six execution excepti ons. all of these exceptions have the same priority. a trap exception occurs when a trap instruction results in a true value. cause register exccode value: tr additional state saved: none entry vector used: general exception vector (offset 0x180) debug data break exception a debug data break exception occurs when a data hardwa re breakpoint matches the load/store transac- tion of an executed load/store instruction. the depc r egister and dbd bit in the d ebug register will indicate the load/store instruction that caused the data hardware breakpoint to match. the load/store instruction that caused the debug exception has not completed e.g. not updated the register file, and the instruction can be re-executed after returning from the debug handler. debug register debug status bit set: ddbl for a load instruction or ddbs for a store instruction additional state saved: none entry vector used: debug exception vector tlb modified exception ? data access during a data access, a tlb modified exception occu rs on a store reference to a mapped address if the following condition is true: the matching tlb entry in a tlb-bas ed mmu is valid, but not dirty. cause register exccode value: mod additional state saved:
idt mips32 4kc processor core exceptions 79rc32438 user reference manual 2 - 49 november 4, 2002 notes entry vector used: general exception vector (offset 0x180) exception handling and servicing flowcharts the remainder of this chapter cont ains flowcharts for the following exceptions and guidelines for their handlers: general exceptions and their exception handler tlb miss exceptions and their exception handler (4kc core) reset, soft reset and nmi exceptions, and a guideline to their handler debug exceptions. generally speaking, the exceptions are handled by hardware (hw); the exceptions are then serviced by software (sw). note that unexpected debug excepti ons to the debug exception vector at 0xbfc0_0200 may be viewed as a reserved instruction since uncont rolled execution of a sdbbp instruction caused the exception. the deret instruction must be used at return from the debug exception handler, in order to leave debug mode and return to non-debug mode. the deret instruction returns to the address in the depc register. register state value badvaddr failing address context the badvpn2 field contains va 31:13 of the failing address. entryhi the vpn2 field contains va 31:13 of the failing address; the asid field contains the asid of the reference that missed. entrylo0 unpredictable entrylo1 unpredictable table 2.24 register states on a tlb modified exception
idt mips32 4kc processor core exceptions 79rc32438 user reference manual 2 - 50 november 4, 2002 notes figure 2.29 general exception handler (hw) to general exception servicing guidelines =1 (bootstrap) =0 (normal) status.bev comments pc << 0x8000_0000 + 180 (unmapped, cached) pc << 0xbfc0_0200 + 180 (unmapped, uncached) exl << 1 epc << (pc - 4) epc << pc instr. in br.dly. slot? =0 processor forced to kernel mode & interrupt disabled =0 =1 check if exception within another exception exl entryhi and context are set only for tlb invalid, modified, & refill exceptions. badva is set only for tlb invalid, modified, and refill exceptions. note: not set on bus errors. entryhi << vpn2, asid context << vpn2 set cause exccode,ce badva << va exceptions other than reset, soft rese t, nmi, or first-level tlb miss. note: interrupts can be masked by ie or ims, and watch is masked if exl = 1.
idt mips32 4kc processor core exceptions 79rc32438 user reference manual 2 - 51 november 4, 2002 notes figure 2.30 general exception servicing guidelines (sw) eret mtc0 - epc,status exl = 1 service code * eret is not allowed in the branch delay slot of another jump instruction * processor does not execute the instruction which is in the eret?s branch delay slot * pc << epc ; exl << 0 * llbit << 0 check cause value & jump to appropriate service code * after exl=0, all exceptions allowed. (except interrupt if masked by ie) (optional - only to enable interrupts while keeping kernel mode) mtc0 - set status bits: um << 0, exl << 0, ie << 1 mfc0 - context, epc, status, cause * unmapped vector so tlbmod, tlbinv, or tlb refill exceptions not possible * exl=1 so watch, interrupt exceptions disabled * os/system to avoid all other exceptions * only reset, soft reset, nmi exceptions possible comments
idt mips32 4kc processor core exceptions 79rc32438 user reference manual 2 - 52 november 4, 2002 notes figure 2.31 tlb mi ss exception handler (hw) to tlb exception se rvicing guidelines vec. off. = 0x180 epc << (pc - 4) cause.bd << 1 epc << pc cause.bd << 0 vec. off. = 0x000 exl << 1 points to general exception processor forced to kernel mode & interrupt disabled = 0 = 1 (bootstrap) = 0 (normal) pc << 0x8000_0000 + vec.off.(unmapped. cached) pc << 0xbfc0_0200 + vec.off.(unmapped. uncached) status.bev check if exception within another exception = 1 = 1 = 0 exl exl entryhi << vpn2, asid context << vpn2 set cause exccode,ce badva << va instr. in br.dly. slot? no yes
idt mips32 4kc processor core exceptions 79rc32438 user reference manual 2 - 53 november 4, 2002 notes figure 2.32 tlb excepti on servicing guidelines (sw) comments eret service code mfc0 - context * unmapped vector so tlbmod, tlbinv, or tlb refill exceptions not possible * exl=1 so watch, interrupt exceptions disabled * os/system to avoid all other exceptions * only reset, soft reset, nmi exceptions possible * load the mapping of the virtual address in context reg. move it to entrylo and write into the tlb * there could be a tlb miss again during the mapping of the data or instruction address. the processor will jump to the general exception vector since the exl is 1. (option to complete the first level refill in the general exception handler or eret to the original instruction and take the exception again) * eret is not allowed in the branch delay slot of another jump instruction * processor does not execute the instruction which is in the eret?s branch delay slot * pc << epc ; exl << 0 * llbit << 0
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 54 november 4, 2002 notes figure 2.33 reset, soft reset, and nmi exception handling and servicing guidelines cp0 registers the system control coprocessor (cp0) provides t he register interface to the mips32 4kc processor core and supports memory management, address trans lation, exception handling, and other privileged operations. each cp0 register has a unique number that identifies it; this number is referred to as the register number. for instance, the pagemask register is register number 5. for more information on the ejtag registers, refer to chapter 20, ejtag system. after updating a cp0 register, there is a hazard peri od of zero or more instructions from the update instruction (mtc0) and until the effect of the update has taken place in the core. cp0 register summary table 5-1 lists the cp0 regi sters in numerical order. status: bev << 1 ts << 0 sr << 1/0 nmi << 0/1 (optional) reset service code soft reset service code nmi service code eret =0 =1 =0 =1 status .sr status.nmi pc << 0xbfc0_0000 errorepc << pc random << tlbentries - 1 wired << 0 config << reset state status : rp << 0 bev << 1 ts << 0 sr << 0 nmi << 0 erl << 1 watchlo : reset exception soft reset or nmi exception reset, soft reset & nmi exception handling (hw) reset, soft reset & nmi servicing guidelines (sw)
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 55 november 4, 2002 notes register number register name function 0 index 1 1. registers used in memory management. index into the tlb array 1 random 1 randomly generated index into the tlb array 2 entrylo0 1 low-order portion of the tlb entry for even-num- bered virtual pages 3 entrylo1 1 low-order portion of the tlb entry for odd-num- bered virtual pages 4 context 2 2. registers used in exception processing. pointer to page table entry in memory 5 pagemask 1 controls the variable page sizes in tlb entries 6wired 1 controls the number of fixed (?wired?) tlb entries 7 reserved reserved 8badvaddr 2 reports the address for the most recent address- related exception 9 count 2 processor cycle count 10 entryhi 1 high-order portion of the tlb entry. 11 compare 2 timer interrupt control 12 status 2 processor status and control 13 cause 2 cause of last exception 14 epc 2 program counter at last exception 15 prid processor identification and revision 16 config/config1 configuration register 17 lladdr load linked address 18 watchlo 2 watchpoint address (low order) 19 watchhi 2 watchpoint address (high order) and mask 20 - 22 reserved reserved 23 debug 3 3. registers used in debug. debug control and exception status 24 depc 3 program counter at last debug exception 25 reserved reserved 26 errctl controls access to data and spram arrays for cache instruction 27 reserved reserved 28 taglo/datalo low-order portion of cache tag interface 29 reserved reserved 30 errorepc 2 program counter at last error 31 desave 3 debug handler scratchpad register table 2.25 cp0 registers
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 56 november 4, 2002 notes cp0 registers the cp0 registers provide the interface between the isa and the architecture. each register is discussed below, with the registers presented in numerical order, first by register number, then by select field number. for each register de scribed below, field descriptions incl ude the read/write properties of the field and the reset state of the field. table 2.26 summarizes the read/write properties of the field. index register (cp0 register 0, select 0) the index register is a 32-bit read/ write register that contains t he index used to access the tlb for tlbp, tlbr, and tlbwi instructions. the width of t he index field is implementation-dependent as a func- tion of the number of tlb entries that are impl emented. the minimum val ue for tlb-based mmus is ceiling(log2(tlbentries)). the operati on of the processor is undefined if a value greater than or equal to the number of tlb entries is written to the index register. this register is only valid with the tlb. iindex register format read/write notation hardware interpretation software interpretation r/w a field in which all bits are readable and writable by software and, potentially, by hard- ware. hardware updates of this field are visible by software read. software updates of this field are visible by hardware read. if the reset state of this field is ?undefined,? either software or hardware must initialize the value before the first read will return a predictable value. this should not be con- fused with the formal definition of undefined behavior. r a field that is either static or is updated only by hardware. if the reset state of this field is either ?0? or ?preset?, hardware initializes this field to zero or to the appropriate state, respectively, on powerup. if the reset state of this field is ?unde- fined?, hardware updates this field only under those conditions specified in the description of the field. a field to which the value written by soft- ware is ignored by hardware. software may write any value to this field without affecting hardware behavior. software reads of this field return the last value updated by hardware. if the reset state of this field is ?unde- fined,? software reads of this field result in an unpredictable va lue except after a hardware update done under the condi- tions specified in the description of the field. 0 a field that hardware does not update, and for which hardware can assume a zero value. a field to which the value written by soft- ware must be zero. software writes of non-zero values to this field may result in undefined behavior of the hardware. software reads of this field return zero as long as all previous software writes are zero. if the reset state of this field is ?unde- fined,? software must write this field with zero before it is guaranteed to read as zero. table 2.26 cp0 register field types 31 30 43 0 p 0 index
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 57 november 4, 2002 notes random register (cp0 register 1, select 0) the random register is a read-onl y register whose value is used to index the tlb during a tlbwr instruction. the width of the random field is calcul ated in the same manner as that described for the index register above. the value of the register varies between an upper and lower bound as follow: a lower bound is set by the number of tlb entries reserved for exclusive use by the operating sys- tem (the contents of the wired register). the entry indexed by the wired register is the first entry available to be written by a tlb write random operation. an upper bound is set by the total number of tlb entries minus 1. the random register is decremented by one almost every clock wrapping after the value in the wired register is reached. to enhance the level of random ness and reduce the possibility of a live lock condition, an lfsr register is used that prevents the decrement pseudo-randomly. the processor initializes the random register to the upper bound on a reset exception and when the wired register is written. this register is only valid with the tlb. random register format entrylo0, entrylo1 (cp0 registers 2 and 3, select 0) the pair of entrylo registers act as the inte rface between the tlb and the tlbr, tlbwi, and tlbwr instructions. for a tlb-based mmu, entrylo0 holds the entries for even pages and entrylo1 holds the entries for odd pages. the contents of the entrylo0 and entrylo1 registers are undefined after an address error, tlb invalid, tlb modified, or tlb refill ex ceptions. these registers ar e only valid with the tlb. fields description read/ write reset state name bit(s) p 31 probe failure. set to 1 when the previous tlbprobe (tlbp) instruction failed to find a match in the tlb. r undefined 0 30:4 must be written as zero; returns zero on read. 0 0 index 3:0 index to the tlb entry affected by the tlbread and tlbwrite instructions. r/w undefined table 2.27 index register field descriptions 31 43 0 0 random fields description read/ write reset state name bit(s) 0 31:4 must be written as zero; returns zero on read. 0 0 random 3:0 tlb random index r tlb entries - 1 table 2.28 random regi ster field descriptions
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 58 november 4, 2002 notes entrylo0, entrylo1 register format table 2.30 lists the encoding of the c field of the en trylo0 and entrylo1 registers and the k0 field of the config register. 31 30 29 26 25 6 5 3 2 1 0 r0 pfn cdvg fields description read/ write reset state name bit(s) r 31:30 reserved. should be ignored on writes; returns zero on read. r0 0 29:26 these 4 bits are normally part of the pfn. however, since the core supports only 32-bits of physical address, the pfn is only 20-bits wide. therefore, bits 29:26 of this register must be written with zeros. r/w 0 pfn 25:6 page frame number. corresponds to bits 31:12 of the physical address. r/w undefined c 5:3 coherency attribute of the page. see table 2.30. r/w undefined d 2 ?dirty? or write-enable bit, indicating that the page has been written, and/or is writable. if this bit is a one, stores to the page are permitted. if this bit is a zero, stores to the page cause a tlb modified exception. r/w undefined v 1 valid bit, indicating that the tlb entry, and thus the virtual page mapping are valid. if this bit is a one, accesses to the page are permitted. if this bit is a zero, accesses to the page cause a tlb invalid exception. r/w undefined g 0 global bit. on a tlb write, the logical and of the g bits in both the entrylo0 and entrylo1 registers become the g bit in the tlb entry. if the tlb entry g bit is a one, asid comparisons are ignored during tlb matches. on a read from a tlb entry, the g bits of both entrylo0 and entrylo1 reflect the state of the tlb g bit. r/w undefined table 2.29 entrylo0, entrylo1 register field descriptions c(5:3) value cache coherency attributes 0, 1, 3 1 , 4, 5, 6 1. these two values are required by the mips32 architecture . no other values are used. for example, values 0, 1, 4, 5 and 6 are not used and are mapped to 3. the value 7 is not used and is mapped to 2. note that these values do have meaning in other mips technologies proc essor implementations. refer to the mips32 specifica- tion for more information. cacheable, noncoherent, write through, no write allocate 2 1 , 7 uncached table 2.30 cache coherency attributes
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 59 november 4, 2002 notes context register (cp0 register 4, select 0) the context register is a read/write register contai ning a pointer to an entry in the page table entry (pte) array. this array is an operating system data structure that stores virtual-to-physi cal translations. during a tlb miss, the operating system loads the tlb with the missing translation from t he pte array. the context register duplicates some of the info rmation provided in the badvaddr r egister but is organized in such a way that the operating system can directly refer ence an 8-byte page table entry (pte) in memory. a tlb exception (tlb refill, tlb invalid, or tlb m odified) causes bits va31: 13 of the virtual address to be written into the badvpn2 field of the context r egister. the ptebase field is written and used by the operating system. refer to table 2.31. the badvpn2 fi eld of the context register is not defined after an address error exception. this regi ster is only valid with the tlb. context register format pagemask register (cp0 register 5, select 0) the pagemask register is a read/wr ite register used for reading from and writing to the tlb. it holds a comparison mask that sets the variable page size for each tlb entry, as shown in table 2.33. behavior is undefined if a value other than those listed is us ed. this register is only valid with the tlb. pagemask register format 31 23 22 4 3 0 ptebase badvpn2 0 fields description read/ write reset state name bit(s) ptebase 31:23 this field is for use by the operating system and is normally written with a value that allows the operat- ing system to use the context register as a pointer into the current pte array in memory. r/w undefined badvpn2 22:4 this field is written by hardware on a tlb miss for the 4kc core. it contains bits va 31:13 of the virtual address that missed. r undefined 0 3:0 must be written as zero; returns zero on read. 0 0 table 2.31 context register field descriptions 31 25 24 13 12 0 0mask 0 fields description read/ write reset state name bit(s) mask 24:13 the mask field is a bit mask in which a ?1? indicates that the corresponding bit of the virtual address should not participate in the tlb match. r/w undefined 0 31:25 and 12:0 must be written as zero; returns zero on read. 0 0 table 2.32 pagemask register field descriptions
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 60 november 4, 2002 notes wired register (cp0 register 6, select 0) the wired register is a read/wr ite register that specifies the boundary between the wired and random entries in the tlb as shown in figure 2.34. the width of the wired field is calculated in the same manner as that described for the index register above. wired ent ries are fixed, non-replac eable entries that are not overwritten by a tlbwr instruction. wired entries c an be overwritten by a tlbwi instruction. the wired register is set to zero by a reset exception. writing the wired register causes t he random register to reset to its upper bound. the operation of the processor is undefined if a value greater than or equal to the number of tlb entries is written to the wired r egister. this register is only valid with a tlb. figure 2.34 wired and random entries in the tlb wired register format page size bit 24 23 22 21 20 19 18 17 16 15 14 13 4 kbytes 000000000000 16 kbytes 000000000011 64 kbytes 000000001111 256 kbytes 000000111111 1 mbyte 000011111111 4 mbyte 001111111111 16 mbyte 111111111111 table 2.33 values for the mask field of the pagemask register 31 43 0 0wired entry 0 entry 10 entry n-1 10 wired register wired random
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 61 november 4, 2002 notes badvaddr register (cp0 register 8, select 0) the badvaddr register is a read-onl y register that captures the most recent virtual address that caused one of the following exceptions: address error (adel or ades) tlb refill tlb invalid tlb modified the badvaddr register does not capture address inform ation for cache or bus errors, since neither is an addressing error. badvaddr register format count register (cp0 register 9, select 0) the count register acts as a time r, incrementing at a constant rate, whether or not an instruction is executed, retired, or any forward progress is m ade through the pipeline. the counter increments every other clock. the count register can be written for f unctional or diagnostic purposes , including at reset or to synchronize processors. whether the count register continues incrementing while the processor is in debug mode is determined by the countdm bit in the debug register. refer to section ?debug register (cp0 register 23)? on page 2-73. count register format fields description read/ write reset state name bit(s) 0 31:4 must be written as zero; returns zero on read. 0 0 wired 3:0 tlb wired boundary. r/w 0 table 2.34 wired register field descriptions 31 0 badvaddr fields description read/ write reset state name bit(s) badvaddr 31:0 bad virtual address r undefined table 2.35 badvaddr re gister field descriptions 31 0 count fields description read/ write reset state name bit(s) count 31:0 interval counter. r/w undefined table 2.36 count register field descriptions
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 62 november 4, 2002 notes entryhi register (cp0 register 10, select 0) the entryhi register contains the virtual address match information used for tlb read, write, and access operations. a tlb exception (tlb refill, tlb invalid, or tlb modified) causes bits va31:13 of the virtual address to be written into the vpn2 field of the entryh i register. the asid field is written by software with the current address space identifier value and is us ed during the tlb comparison process to determine tlb match. the vpn2 field of the entryhi register is not defined after an address error exception. this register is only valid with the tlb. entryhi register format compare register (cp0 register 11, select 0) the compare register acts in conjunction with the c ount register to implement a timer and timer inter- rupt function. the timer interrupt is an output of the cores. the compare register maintains a stable value and does not change on its own. when the value of th e count register equals the value of the compare register, the si_timerint pin is asserted. this pin wil l remain asserted until the compare register is written. the si_timerint pin can be fed back into the core on one of the interrupt pins to generate an interrupt. traditionally, this has been done by multiplexing it with har dware interrupt 5 to set interrupt bit ip(7) in the cause register. for diagnostic purposes, the compare register is a read/write register. in normal use, however, the compare register is write- only. writing a value to the compare regi ster, as a side effect, clears the timer interrupt. compare register format 31 13 12 8 7 0 vpn2 0 asid fields description read/ write reset state name bit(s) vpn2 31:13 va 31:13 of the virtual address (virtual page number / 2). this field is written by hardware on a tlb excep- tion or on a tlb read, and is written by software before a tlb write. r/w undefined 0 12:8 must be written as zero; returns zero on read. 0 0 asid 7:0 address space identifier. this field is written by hard- ware on a tlb read and by software to establish the current asid value for tlb write and against which tlb references match each entry?s tlb asid field. r/w undefined table 2.37 entryhi register field descriptions 31 0 compare fields description read/ write reset state name bit(s) compare 31:0 interval count compare value r/w undefined table 2.38 compare register field description
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 63 november 4, 2002 notes status register (cp0 register 12, select 0) the status register (sr) is a r ead/write register that contains the operating mode, interrupt enabling, and the diagnostic states of the proces sor. fields of this register combine to create operating modes for the processor, as follows: interrupt enable: interrupts are enabled when all of the following conditions are true: ie = 1 exl = 0 erl = 0 dm = 0 if these conditions are met, the settings of the im and ie bits enable the interrupt. operating modes: if the dm bit in the debug register is 1, the processor is in debug mode. otherwise the processor is in either kernel or us er mode. the following cpu status regi ster bit settings determine user or kernel mode. user mode: um = 1, exl = 0, and erl = 0 kernel mode: um = 0, or exl = 1, or erl = 1 coprocessor accessibility: the status register cu bi ts control coprocessor a ccessibility. if any copro- cessor is unusable, an instruction that accesses it generates an exception. coprocessor 0 is always enabled in kernel mode, regardless of the setting of the cu0 bit. status register format 31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 8 7 5 4 3 2 1 0 cu3-cu0 rp r re 0 be v ts sr n mi 00 im7-im0 r u m rer l ex l ie fields description read/ write reset state name bit(s) cu3-cu0 31:28 controls access to coprocessors 3, 2, 1, and 0, respectively: 0: access not allowed 1: access allowed coprocessor 0 is always usable when the processor is running in kernel mode, independent of the state of the cu0 bit. the core does not support coprocessors 1-3, but cu3:1 can still be set. however, processor behavior is unpredictable if a coprocessor instruction to copro- cessors 1-3 is attempted with the corresponding cu3:1 bit set. r/w undefined rp 27 enables reduced power mode. the state of the rp bit is available on the bus interface as the si_rp sig- nal. r/w 0 for cold reset only. r 26 this bit must be ignored on writes and read as zero. r 0 table 2.39 status register field description (part 1 of 3)
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 64 november 4, 2002 notes re 25 used to enable reverse-endian memory references while the processor is running in user mode: 0: user mode uses configured endianness 1: user mode uses reversed endianness kernel or debug mode references are not affected by the state of this bit. r/w undefined 0 24:23 this bit must be written as zero; returns zero on read. r 0 bev 22 controls the location of exception vectors: 0: normal 1: bootstrap r/w 1 ts 21 tlb shutdown. this bit is set if a tlbwi or tlbwr instruction is issued that would cause a tlb shut- down condition if allowed to complete. software can only write a 0 to this bit to clear it and cannot force a 0-1 transition. r/w 0 sr 20 indicates that the entry through the reset exception vector was due to a soft reset: 0: not soft reset (nmi or hard reset) 1: soft reset software can only write a 0 to this bit to clear it and cannot force a 0-1 transition. r/w 1 for soft reset; 0 otherwise nmi 19 indicates that the entry through the reset exception vector was due to an nmi. 0: not nmi (soft or hard reset) 1: nmi software can only write a 0 to this bit to clear it and cannot force a 0-1 transition. r/w 1 for nmi; 0 other- wise 0 18 must be written as zero; returns zero on read. r 0 r 17:16 reserved. must be ignored on write and read as zero. r0 im[7:0] 15:8 interrupt mask: controls the enabling of each of the external, internal, and software interrupts. an inter- rupt is taken if interrupts are enabled and the corre- sponding bits are set in both the interrupt mask field of the status register and the interrupt pending field of the cause register and the ie bit is set in the sta- tus register. 0: interrupt request disabled 1: interrupt request enabled r/w undefined r 7:5 reserved. must be ignored on write and read as zero. r0 um 4 indicates that the processor is operating in user mode: 0: processor is operating in kernel mode 1: processor is operating in user mode note that the processor can also be in kernel mode if exr or erl are set. this condition does not affect the state of the um bit. r/w undefined fields description read/ write reset state name bit(s) table 2.39 status register field description (part 2 of 3)
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 65 november 4, 2002 notes cause register (cp0 register 13, select 0) the cause register primarily descri bes the cause of the most recent exception. in addition, fields also control software interrupt requests and the vector thr ough which interrupts are dispatched. with the excep- tion of the ip[1:0], iv, and wp fields, all fields in the cause register are read-only. cause register format r 3 reserved. must be ignored on write and read as zero. r0 erl 2 error level. set by the processor when a reset, soft reset, or nmi exception is taken. 0: normal level 1: error level when erl is set: the processor is running in kernel mode. interrupts are disabled. the eret instruction uses the return address held in errorepc instead of epc. kuseg is treated as an unmapped and uncached region. this allows main memory to be accessed in the presence of cache errors. behavior is unde- fined if erl is set while executing code in useg/ kuseg. r/w 1 exl 1 exception level. set by the processor when any exception other than a reset, soft reset, or nmi exception is taken. 0: normal level 1: exception level when exl is set: the processor is running in kernel mode. interrupts are disabled. in the 4kc core, tlb refill exceptions use the general exception vector instead of the tlb refill vector. epc is not updated if another exception is taken. r/w undefined ie 0 interrupt enable. acts as the master enable for soft- ware and hardware interrupts: 0: disables interrupts 1: enables interrupts r/w undefined 31 30 29 28 27 24 23 22 21 16 15 10 9 8 7 6 2 1 0 bd 0 ce 0 iv wp 0 ip[7:2] ip[1:0] 0 exc code 0 fields description read/ write reset state name bit(s) table 2.39 status register field description (part 3 of 3)
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 66 november 4, 2002 notes fields description read/ write reset state name bit(s) bd 31 indicates whether the last exception taken occurred in a branch delay slot: 0: not in delay slot 1: in delay slot note that the bd bit is not updated on a new excep- tion if the exl bit is set. r undefined ce 29:28 coprocessor unit number referenced when a copro- cessor unusable exception is taken. this field is loaded by hardware on every exception but is unpre- dictable for all exceptions except for coprocessor unusable. r undefined iv 23 indicates whether an interrupt exception uses the general exception vector or a special interrupt vector: 0: use the general exception vector (0x180) 1: use the special interrupt vector (0x200) r/w undefined wp 22 indicates that a watch exception was deferred because status exl or status erl were a one at the time the watch exception was detected. this bit both indicates that the watch exception was deferred and causes the exception to be initiated once status exl and status erl are both zero. as such, software must clear this bit as part of the watch exception handler to prevent a watch exception loop. software can only write a 0 to this bit to clear it and cannot force a 0-1 transition. r/w undefined ip[7:2] 15:10 indicates an external interrupt is pending: 15: hardware interrupt 5 or timer interrupt 14: hardware interrupt 4 13: hardware interrupt 3 12: hardware interrupt 2 11: hardware interrupt 1 10: hardware interrupt 0 r undefined ip[1:0] 9:8 controls the request for software interrupts: 9: request software interrupt 1 8: request software interrupt 0 r/w undefined exc code 6:2 exception code ? see table 2.41. r undefined 0 30, 27:24, 21:16, 7, 1:0 must be written as zero; returns zero on read. r 0 table 2.40 cause register field descriptions
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 67 november 4, 2002 notes exception program counter (cp0 register 14, select 0) the exception program counter (epc ) is a read/write register that contains the address at which processing resumes after an exception has been serviced. all bits of the epc register are significant and must be writable. for synchronous (precise) exceptions, t he epc contains one of the following: the virtual address of the instruction that was the direct cause of the exception the virtual address of the immedi ately preceding branch or jump in struction, when the exception causing instruction is in a branch delay slot and t he branch delay bit in the cause register is set. on new exceptions, the processor does not write to the epc register when the exl bit in the status register is set. however, the register c an still be written via the mtc0 instruction. epc register format exception code value mnemonic description 0 int interrupt 1 mod tlb modification exception 2 tlbl tlb exception (load or instruction fetch) 3 tlbs tlb exception (store) 4 adel address error exception (load or instruction fetch) 5 ades address error exception (store) 6 ibe bus error exception (instruction fetch) 7 dbe bus error exception (data reference: load or store) 8 sys syscall exception 9 bp breakpoint exception 10 ri reserved instruction exception 11 cpu coprocessor unusable exception 12 ov integer overflow exception 13 tr trap exception 14-22 ? reserved 23 watch reference to watchhi/watchlo address 24 mcheck machine check 25-31 ? reserved table 2.41 cause register exccode field descriptions 31 0 epc
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 68 november 4, 2002 notes processor identification (cp0 register 15, select 0) the processor identification (prid) register is a 32-bit r ead-only register that c ontains information iden- tifying the manufacturer, manufacture r options, processor identification, and revision level of the processor. prid register format config register (cp0 register 16, select 0) the config register specifies variou s configuration and capabilities informat ion. most of the fields in the config register are initialized by hardware during the reset exception process, or are constant. one field, k0, must be initialized by software in the reset exception handler. register format ? select 0 fields description read/ write reset state name bit(s) epc 31:0 exception program counter r/w undefined table 2.42 epc register field description 31 24 23 16 15 8 7 0 r company id processor id revision fields description read/ write reset state name bit(s) r 31:24 reserved. must be ignored on write and read as zero. r0 company id 23:16 identifies the company that designed or manufac- tured the processor. in all three cores this field con- tains a value of 1 to indicate mips technologies, inc. r1 processor id 15:8 identifies the type of processor. this field allows soft- ware to distinguish between the various types of mips technologies processors. this field contains a value of 0x80 for the 4kc processor. r0x80 revision 7:0 specifies the revision number of the processor. this field allows software to distinguish between one revi- sion and another of the same processor type. cur- rent values are: 0x1: 1.1-2.2 0x2: 2.3-2.4 0x3: 2.5-2.6 0x4: 3.0 0x5: 3.1 0x6: 3.2 0x7: 3.3 0x8: 3.4 0x9: 3.5 rpreset table 2.43 prid register field descriptions 31 30 28 27 25 24 21 20 19 18 17 16 15 14 13 12 10 9 7 6 3 2 0 m k23 ku r mdu r mm bm be at ar mt 0 k0
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 69 november 4, 2002 notes fields description read/ write reset state name bit(s) m 31 this bit is hardwired to ?1? to indicate the presence of the config1 register. r1 k23 30:28 this field is reserved (must be written as 0; returns 0 on read). fm: r/w tlb: 0 fm: 010 tlb: 000 ku 27:25 this field is reserved (must be written as 0; returns 0 on read). fm: r/w tlb: 0 fm: 010 tlb: 000 0 24:21 must be written as 0. returns 0 on read. 0 0 mdu 20 this bit indicates the mdu type. 0 = fast multiplier array 1 = reserved rpreset 0 19 must be written as 0. returns 0 on read. 0 0 mm 18:17 this field contains the merge mode for the 32-byte collapsing write buffer: 00 = no merging 01 = sysad valid merging 10 = full merging 11 = reserved r externally set bm 16 burst order. 0: sequential 1: subblock r externally set be 15 indicates the endian mode in which the processor is running: 0: little endian 1: big endian r externally set at 14:13 architecture type implemented by the processor. this field is always 00 to indicate mips32. r00 ar 12:10 architecture revision level. this field is always 000 to indicate revision 1. 0: revision 1 1-7: reserved r000 mt 9:7 mmu type: 1: standard tlb all other values: reserved rpreset 0 6:3 must be written as zero; returns zero on read. 0 0 k0 2:0 kseg0 coherency algorithm. refer to table 2.45 for the field encoding. r/w 010 table 2.44 config register field descriptions
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 70 november 4, 2002 notes config1 register (cp0 register 16, select 1) the config1 register is an adjunct to the config register and enc odes additional capabilities information. all fields in the config1 register are read-only. the instruction and data cache configuration parameters include encodings for the number of sets per way, the line size, and the associativity. the total cache size for a cache is therefore: associativity * line size * sets per way if the line size is zero, there is no cache implemented. config1 register format ? select 1 c(2:0) value cache coherency attribute 0, 1, 3 1 , 4, 5, 6 1. these two values are required by the mips32 arch itecture. no other values are used. for ex- ample, values 0, 1, 4, 5 and 6 are not used and are mapped to 3. the value 7 is not used and is mapped to 2. note that these values do have m eaning in other mips technologies processor im- plementations. refer to the mips32 specification for more information. cacheable, noncoherent, write-through, no write allocate 2 1 , 7 uncached table 2.45 cache coherency attributes 3130 2524 2221 1918 1615 1312 109 7654 3 210 0 mmu size is il ia ds dl da 0 pc wr ca ep fp fields description read/ write reset state name bit(s) 0 31 this bit is reserved to and must be read or written as zero. r0 mmu size 30:25 this field contains the number of entries in the tlb minus one. the field is read as 15 decimal. rpreset is 24:22 this field contains the number of instruction cache sets per way. three options are available. all others values are reserved: 0x0: 64 0x1: 128 0x2: 256 0x3 - 0x7: reserved rpreset il 21:19 this field contains the instruction cache line size. if an instruction cache is present, it must contain a fixed line size of 16 bytes. 0x0: no icache present 0x3: 16 bytes 0x1, 0x2, 0x4 - 0x7: reserved rpreset ia 18:16 this field contains the level of instruction cache asso- ciativity. 0x0: direct mapped 0x1: 2-way 0x2: 3-way 0x3: 4-way 0x4 - 0x7: reserved rpreset table 2.46 config1 register field descriptions ? select 1 (part 1 of 2)
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 71 november 4, 2002 notes load linked address (cp0 register 17, select 0) the lladdr register contains the physical address r ead by the most recent load linked (ll) instruction. this register is for diagnostic purposes only, and serves no function during normal operation. lladdr register format ds 15:13 this field contains the number of data cache sets per way: 0x0: 64 0x1: 128 0x2: 256 0x3 - 0x7: reserved rpreset dl 12:10 this field contains the data cache line size. if a data cache is present, it must contain a line size of 16 bytes. 0x0: no dcache present 0x3: 16 bytes 0x1, 0x2, 0x4 - 0x7: reserved rpreset da 9:7 this field contains the type of set associativity for the data cache: 0x0: direct mapped 0x1: 2-way 0x2: 3-way 0x3: 4-way 0x4 - 0x7: reserved rpreset 0 6:5 must be written as zero; returns zero on read. 0 0 pc 4 performance counter registers implemented. always a 0 since the cores do not implement any. r0 wr 3 watch registers implemented. this bit always reads as 1 since the cores each contain one pair of watch registers. r1 ca 2 code compression (mips16?) implemented. this bit always reads as 0 because mips16 is not sup- ported. r0 ep 1 ejtag present: this bit is always set to indicate that the core implements ejtag. r1 fp 0 fpu implemented. this bit is always zero since the core does not contain a floating-point unit. r0 31 28 27 0 0 paddr[31:4] fields description read/ write reset state name bit(s) table 2.46 config1 register field descriptions ? select 1 (part 2 of 2)
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 72 november 4, 2002 notes watchlo register (cp0 register 18) the watchlo and watchhi registers together provide the interface to a watchpoint debug facility that initiates a watch exception if an instruction or data a ccess matches the address specified in the registers. as such, they duplicate some functions of the ej tag debug solution. watch exceptions are taken only if the exl and erl bits are zero in the status register. if either bit is a one, the wp bit is set in the cause register, and the watch exception is deferred until both the exl and erl bits are zero. the watchlo register specifies the base virtual address and the type of reference (instruction fetch, load, store) to match. watchlo register format watchhi register (cp0 register 19) the watchlo and watchhi registers together provide the interface to a watchpoint debug facility that initiates a watch exception if an instruction or data a ccess matches the address specified in the registers. as such, they duplicate some functions of the ej tag debug solution. watch exceptions are taken only if the exl and erl bits are zero in the status register. if either bit is a one, the wp bit is set in the cause register, and the watch exception is deferred until both the exl and erl bits are zero. the watchhi register contains info rmation that qualifies the virtual address specified in the watchlo register: an asid, a global (g) bit, and an optional address mask. if the g bi t is 1, any virtual address refer- ence that matches the specified address will cause a wa tch exception. if the g bit is a 0, only those virtual fields description read/ write reset state name bit(s) 0 31:28 must be written as zero; returns zero on read. 0 0 paddr[31:4] 27:0 this field encodes the physical address read by the most recent load linked instruction. r undefined table 2.47 lladdr register field descriptions 31 3210 vaddr i r w fields description read/ write reset state name bit(s) vaddr 31:3 this field specifies the virtual address to match. note that this is a doubleword address, since bits [2:0] are used to control the type of match. r/w undefined i 2 if this bit is set, watch exceptions are enabled for instruction fetches that match the address. r/w 0 for cold reset only. r 1 if this bit is set, watch exceptions are enabled for loads that match the address. r/w 0 for cold reset only. w 0 if this bit is set, watch exceptions are enabled for stores that match the address. r/w 0 for cold reset only. table 2.48 watchlo register field descriptions
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 73 november 4, 2002 notes address references for which the asid value in the watc hhi register matches the asid value in the entryhi register cause a watch exception. the optional mask field provides address masking to qualify the address specified in watchlo. watchhi register format debug register (cp0 register 23) the debug register is used to control the debug ex ception and provide information about the cause of the debug exception and when re-entering at the debug exception vector due to a normal exception in debug mode. the read-only informati on bits are updated every time the debug exception is taken or when a normal exception is taken when already in debug mode. only the dm bit and the ejtagver field are vali d when read from non-debug mode; the value of all other bits and fields is unpredictable. operation of t he processor is undefined if the debug register is written from non-debug mode. some of the bits and fields are only updated on debug exceptions and/or exceptions in debug mode, as shown below: ? dss, dbp, ddbl, ddbs, dib, dint are updat ed on both debug exceptions and on exceptions in debug modes ? dexccode is updated on exceptions in debug mode, and is undefined after a debug exception ? halt and doze are updated on a debug exception, and is undefined after an exception in debug mode ? dbd is updated on both debug and on exceptions in debug modes. all bits and fields are undefined w hen read from normal mode, except those explicitly described to be defined, such as ejtagver and dm. debug register format 31 30 29 24 23 16 15 12 11 3 2 0 0 g 0 asid 0 mask 0 fields description read/ write reset state name bit(s) 0 31 must be written as zero; returns zero on read. 0 0 g 30 if this bit is one, any address that matches that spec- ified in the watchlo register causes a watch excep- tion. if this bit is zero, the asid field of the watchhi register must match the asid field of the entryhi reg- ister to cause a watch exception. r/w undefined 0 29:24 must be written as zero; returns zero on read. 0 0 asid 23:16 asid value which is required to match that in the entryhi register if the g bit is zero in the watchhi register. r/w undefined table 2.49 watchhi register field descriptions 31 30 29 28 27 26 25 24 23 22 21 20 19 18 dbd dm r lsnm doze halt countdm ibusep r dbusep iexi r 17 15 14 10 9 8 7 6 5 4 3 2 1 0 ver dexccode r sst r dint dib ddbs ddbl dbp dss
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 74 november 4, 2002 notes fields description read/ write reset state name bit(s) dbd 31 indicates whether the last debug exception or excep- tion in debug mode, occurred in a branch delay slot: 0: not in delay slot 1: in delay slot r undefined dm 30 indicates that the processor is operating in debug mode: 0: processor is operating in non-debug mode 1: processor is operating in debug mode r0 r 29 reserved. must be written as zero; returns zero on read. r0 lsnm 28 controls access of load/store between dseg and main memory: 0: load/stores in dseg address range goes to dseg. 1: load/stores in dseg address range goes to main memory. r/w 0 doze 27 indicates that the processor was in any kind of low power mode when a debug exception occurred: 0: processor not in low power mode when debug exception occurred 1: processor in low power mode when debug excep- tion occurred r undefined halt 26 indicates that the internal system bus clock was stopped when the debug exception occurred: 0: internal system bus clock stopped 1: internal system bus clock running r undefined countdm 25 indicates the count register behavior in debug mode. encoding of the bit is: 0: count register stopped in debug mode 1: count register increments in debug mode r/w 1 ibusep 24 instruction fetch bus error exception pending. set when an instruction fetch bus error event occurs or if a 1 is written to the bit by software. cleared when a bus error exception on instruction fetch is taken by the processor, and by reset. if ibusep is set when iexi is cleared, a bus error exception on instruction fetch is taken by the processor, and ibusep is cleared. r/w1 0 r 23:22 reserved. must be written as zero; returns zero on read. r0 dbusep 21 data access bus error exception pending. covers imprecise bus errors on data access, similar to behavior of ibusep for imprecise bus errors on an instruction fetch. r/w1 0 table 2.50 debug register field descriptions (part 1 of 2)
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 75 november 4, 2002 notes iexi 20 imprecise error exception inhibit controls exceptions taken due to imprecise error indications. set when the processor takes a debug exception or exception in debug mode. cleared by execution of the deret instruction. otherwise modifiable by debug mode software. when iexi is set then the imprecise error exceptions from bus error on instruction fetch or data access, cache error or machine check are inhibited and deferred until the bit is cleared. r/w 0 r 19:18 reserved. must be written as zero; returns zero on read. r0 ver 17:15 ejtag version r 1 dexccode 14:10 indicates the cause of the latest exception in debug mode. the field is encoded as the exccode field in the cause register for those normal exceptions that may occur in debug mode. value is undefined after a debug exception. r undefined r 9 reserved. must be written as zero; returns zero on read. r0 sst 8 controls if debug single step exception is enabled: 0: no debug single step exception enabled 1: debug single step exception enabled r/w 0 r 7:6 reserved. must be written as zero; returns zero on read. r0 dint 5 indicates that a debug interrupt exception occurred. cleared on exception in debug mode. 0: no debug interrupt exception 1: debug interrupt exception r/w undefined dib 4 indicates that a debug instruction break exception occurred. cleared on exception in debug mode. 0: no debug instruction exception 1: debug instruction exception r undefined ddbs 3 indicates that a debug data break exception occurred on a store. cleared on exception in debug mode. 0: no debug data exception on a store 1: debug instruction exception on a store r undefined ddbl 2 indicates that a debug data break exception occurred on a load. cleared on exception in debug mode. 0: no debug data exception on a load 1: debug instruction exception on a load r undefined dbp 1 indicates that a debug software breakpoint exception occurred. cleared on exception in debug mode. 0: no debug software breakpoint exception 1: debug software breakpoint exception r undefined dss 0 indicates that a debug single step exception occurred. cleared on exception in debug mode. 0: no debug single step exception 1: debug single step exception r undefined fields description read/ write reset state name bit(s) table 2.50 debug register field descriptions (part 2 of 2)
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 76 november 4, 2002 notes debug exception program counter register (cp0 register 24) the debug exception program counter (depc) register is a read/wri te register that contains the address at which processing resumes after a debug exception or debug mode exception has been serviced. for synchronous (precise) debug and debug m ode exceptions, the depc contains either: ? the virtual address of the instruction that was the direct cause of the debug exception, or ? the virtual address of the immediately preceding branch or jump instruction, when the debug exception causing instruction is in a branch delay slot, and the debug branch delay (bdb) bit in the debug register is set. for asynchronous debug exceptions (debug interrupt), the depc contains the virtual address of the instruction where execution should resume after the debug handler code is executed. depc register format errctl register (cp0 register 26, select 0) note: this register was added to version 3.5 of t he core. it is reserved in earlier versions. the errctl register provides a mechanism for enabling software testing of the way-select and data ram arrays for both the icache and dcache. the way-select ion ram test mode is enabled by setting the wst bit. it modifies the functionality of the cache index load tag and index store tag operations so that they modify the way-selection ram and leav e the tag rams untouched. when this bit is set, the lower 6 bits of the pa field in the taglo register are used as the source and destination for index load tag and index store tag cache operations. the wst bit also enables the data ram test mode. when this bit is set, the index store data cache instruction is enabled. this cache operation writes the contents of the datalo register to the word in the data array that is indicated by the index and byte address. the spr bit enables cache accesses to the opt ional scratchpad rams. when this bit is set, index load tag, index store tag, and index store data cach e instructions will send reads or writes to the scratchpad ram port. the effects of these operati ons are dependent on the particular scratchpad imple- mentation. errctl register format 31 0 depc fields description read/ write reset state name bit(s) depc 31:0 the depc register is updated with the virtual address of the instruction that caused the debug exception. if the instruction is in the branch delay slot, the virtual address of the immediately preceding branch or jump instruction is placed in this register. execution of the deret instruction causes a jump to the address in the depc. r/w undefined table 2.51 depc register field description 31 30 29 28 27 0 r wst spr r
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 77 november 4, 2002 notes taglo register (cp0 register 28, select 0) the taglo register acts as the in terface to the cache tag array. the index store tag and index load tag operations of the cache instruction use the taglo regist er as the source of tag information, respectively. taglo register format fields description read/ write reset state name bit(s) wst 29 indicates whether the tag array or the way-select array should be read/written on index load/store tag cache instructions. also enables the index store data cache instruc- tion which writes the contents of datalo to the data array. r/w 0 spr 28 forces indexed cache instructions to operate on the scratchpad ram instead of the cache r/w 0 r31:30, 27:0 must be written as zero; returns zero on reads. 0 0 table 2.52 errctl register field descriptions 31 1098765432 1 0 pa r valid r l lrf r fields description read/ write reset state name bit(s) pa 31:10 this field contains the physical address of the cache line being stored. r/w undefined r 9:8 must be written as zero; returns zero on read. 0 0 valid 7:4 this field indicates whether the corresponding word in the cache line is valid in the cache. r/w undefined r 3 must be written as zero; returns zero on read. 0 0 l 2 specifies the lock bit for the cache tag. when this bit is set, the corresponding cache line should not be replaced by the cache replacement algorithm. r/w undefined lrf 1 lrf. one bit of the lrf bits for the set this cache line is a part of. this bit is inverted every time a new cache line is filled in the cache entry. r/w undefined r 0 must be written as zero; returns zero on read. 0 0 table 2.53 taglo regist er field descriptions
idt mips32 4kc processor core cp0 registers 79rc32438 user reference manual 2 - 78 november 4, 2002 notes datalo register (cp0 register 28, select 1) the datalo register acts as the interface to the cache data array. the index load tag operation of the cache instruction reads the corres ponding data values into the datalo r egister. this register was made writeable on revision 3.5 and the index store data operation of the cache instruction was added. this operation will write the cache data arra y with the value of this register. datalo register format errorepc (cp0 register 30, select 0) the errorepc register is a read-write register, similar to the epc register, except that errorepc is used on error exceptions. all bits of the errorepc register are significant and must be writable. it is also used to store the program counter on reset, soft reset, and non-maskable interrupt (nmi) exceptions. the errorepc register contains the virtual address at which instru ction processing can resume after servicing an error. this address can be: ? the virtual address of the instruction that caused the exception ? the virtual address of the immediately preceding branch or jump instruction when the error causing instruction is in a branch delay slot. unlike the epc register, there is no corresponding branch delay slot indication for the errorepc register. errorepc register format desave register (cp0 register 31) the debug exception save (desave) register is a read/ write register that func tions as a simple memory location. this register is used by the debug exception handler to save one of the gprs that is then used to save the rest of the context to a pre-determined memo ry area (such as in the ejtag probe). this register allows the safe debugging of exception handlers and ot her types of code where the existence of a valid stack for context saving cannot be assumed. desave register format 31 0 data fields description read/ write reset state name bit(s) data 31:0 low-order data read from the cache data array. r/w undefined table 2.54 datalo register field descriptions 31 0 errorepc fields description read/ write reset state name bit(s) errorepc 31:0 error exception program counter r/w undefined table 2.55 errorepc register field descriptions 31 0 desave
idt mips32 4kc processor core hardware and software initialization 79rc32438 user reference manual 2 - 79 november 4, 2002 notes hardware and software initialization the 4kc processor core is not fully initialized by re set. only a minimal subset of the processor state is cleared. this is enough to bring the core up whil e running in unmapped and uncached code space. all other processor states can then be initialized by software. si _coldreset is asserted after power-up to bring the device into a known state. soft reset can be forced by asserting the si_reset pin. this can be used when the device is already up and running and does not need as much initialization. hardware initialized processor state coprocessor zero state much of the hardware initialization occurs in coprocessor zero. ? random - set to maximum value on reset ? wired - set to 0 on reset ? status bev - set to 1 on reset/softreset ? status ts - cleared to 0 on reset/softreset ? status sr - cleared to 0 on reset, set to 1 on softreset ? status nmi - cleared to 0 on reset/softreset ? status erl - set to 1 on reset/softreset ? status rp - cleared to 0 on reset ? watchlo i,r,w - cleared to 0 on reset ? config fields related to static inputs - set to input value by reset ? config k0 - set to 010 (uncached) on reset ? debugdm - cleared to 0 on reset/softreset ( unless ejtagboot option is used to boot into debugmode (see the ejtag debug support section for more information) ? debug lsnm - cleared to 0 on reset/softreset ? debug ibusep - cleared to 0 on reset/softreset ? debug dbusep - cleared to 0 on reset/softreset ? debug iexi - cleared to 0 on reset/softreset ? debug sst - cleared to 0 on reset/softreset. tlb initialization each tlb entry has a ?hidden? state bit which is set by reset/softreset and is cleared when the tlb entry is written. this bit disables matches and pr events ?tlb shutdown? condi tions from being generated by the power-up values in the tlb array (when two or more tlb entries match on a single address). this bit is not visible to software. bus state machines all pending bus transactions are aborted and the state machines in the bus interface unit are reset when a reset or softreset exception is taken. static configuration inputs all static configuration inputs (defining the bus mode and cache size for example) should only be changed during reset. fields description read/ write reset state name bit(s) desave 31:0 debug exception sa ve contents. r/w undefined table 2.56 desave register field descriptions
idt mips32 4kc processor core caches 79rc32438 user reference manual 2 - 80 november 4, 2002 notes fetch address upon reset/softreset, unless the ejtagboot option is used, the fetch is directed to va 0xbfc00000 (pa 0x1fc00000). this address is in kseg1, which is unmapped and uncached, so that the tlb and caches do not require hardware unitization. software initialized processor state software is required to initialize the following parts of the device. register file the register file powers up in an unknown state with the exception of r0 which is always 0. initializing the rest of the register file is not required for proper operation. good code will generally not read a register before writing to it, but the boot code can initialize the register file for added safety. tlb because of the hidden bit indicating initialization, t he 4kc processor core does not require tlb initializa- tion upon coldreset. this is an implementati on-specific feature of the 4kc core. note: when initializing the tlb, care must be taken to avoid creating a ?tlb shutdown? condition where two tlb entries could match on a single address. unique virtual addresses should be written to each tlb entry to avoid this. caches the cache tag and data arrays power up to an unknown state and are not affected by reset. every tag in the cache arrays should be initialized to an invalid st ate using the cache instruction (typically the index invalidate function). this can be a long process, especia lly since the instruction cache initialization needs to be run in an uncached address region. coprocessor zero state miscellaneous cop0 states need to be initialized pr ior to leaving the boot code. there are various exceptions that are blocked by er l=1 or exl=1 and that are not clear ed by reset. these can be cleared to avoid taking spurious excepti ons when leaving the boot code. cause: wp (watch pending), sw0/1 (s oftware interrupts) should be cleared. config: k0 should be set to the desired cache coherency algorithm (cca) prior to accessing kseg0. count: should be set to a known value if timer interrupts are used. compare: should be set to a known value if time r interrupts are used. the write to compare will also clear any pending timer interrupts (thus, co unt should be set before compare to avoid any unexpected interrupts). status: desired state of the device should be set. other cop0 state: other registers should be writt en before they are read. some registers are not explicitly writable, and are only upd ated as a by-product of instruction execution or a taken excep- tion. uninitialized bits should be mask ed off after reading these registers. caches the 4kc processor core supports separate instructi on and data caches which may be flexibly configured at build time for various sizes, organizations, and se t-associativities. the use of separate caches allows instruction and data references to proceed simultaneous ly. both caches are virt ually indexed and physically tagged, allowing cache access to occur in parallel wit h virtual-to-physical address translation. the instruc- tion and data caches are independently configured. each cache is accessed in a single processor cycle.
idt mips32 4kc processor core caches 79rc32438 user reference manual 2 - 81 november 4, 2002 notes cache refills are performed using a 4-word fill buffe r, which holds data returned from memory during a 4- beat burst transaction. the critical miss word is always returned first. the caches ar e blocking until the crit- ical word is returned, but the pipeline may proceed while the other 3 beats of the burst are still active on the bus. table 2.57 lists the instruction and data cache attributes for the rc32438. software can identify the instruction or data cache configuration by reading t he appropriate bits of the config1 register (see section confi g1 register (cp0 register 16, sele ct 1) earlier in this chapter. cache protocols cache organization the instruction and data caches each consist of tw o arrays: a tag array and a data array. the caches are virtually indexed, since a virtual address is used to select the appropriate line within both the tag and data arrays. the caches are physically tagged, as t he tag array contains a physical, not virtual, address. the tag and data arrays hold ?n? ways of informat ion per line, corresponding to the n-way set associa- tivity of the cache, where ?n? c an be between 1 and 4 for a cache. figure 2.35 shows the format of each line of the tag and data arrays for each way. a tag entry consists of the upper 22 bi ts of the physical address (bits [31:10]), 4 valid bits (one for each data word in the line), a lock bit and a lrf bit. a data entry contains the four 32-bit words in the line, for a total of 16 bytes. not every word need be present in the data array, hence the per-word validity information stored with the t ag. a word is the minimum valid quanta, so it is not possible to hold a partially valid subword. once a valid word is resident in the cache, then a byte, halfword, or tri-byte stores can up date a portion of the word. figure 2.35 cache array formats parameter instruction data size 16 kbytes 16 kbytes number of cache sets 256 256 lines per set (associativity) 4 way set associative 4 way set associative line size 16 bytes 16 bytes read unit 32-bits 32-bits write policy n/a write-through without write-allocate miss restart after transfer of miss word miss word cache locking per line per line table 2.57 instruction and data cache attributes tag: data: word3 word2 word1 word0 pa valid l lrf 32 32 32 32 22 4 1 1
idt mips32 4kc processor core caches 79rc32438 user reference manual 2 - 82 november 4, 2002 notes cacheability attributes the 4kc processor core supports t he following cacheability attributes: ? uncached: addresses in a memory area indica ted as uncached are not read from the cache. stores to such addresses are written directly to main memory, without changing cache contents. ? write-through: loads and instruction fetches first search the cache, reading main memory only if the desired data does not reside in the cache. on data store operations, the cache is first searched to see if the target address is cache resident. if it is resident, the cache contents are updated, and main memory is also written. if the cache lookup misses on a store, only main memory is written. hence, the allocation policy on a ca che miss is read-allocate only. some segments of memory employ a fixed cachi ng policy; for example t he kseg1 is always uncache- able. other segments of memory allow the caching pol icy to be selected by software. generally, the cache policy for these programmable regions is defined by a cacheability attribut e field associated with that region of memory. for additional information, see the memory management section earlier in this chapter. replacement policy the replacement policy refers to how a way is c hosen to hold an incoming cache line on a miss which will result in a cache fill, when a cache is at least two-way set associative. in a direct mapped cache (one- way set associative), the replacement policy is irrelevant since there is only one way avail able. the replace- ment policy is least recently fill ed (lrf), first considering invalid wa ys and excluding any locked ways. on a cache miss, the valid, lock and lrf bits for each tag entry of the selected line may be used to determine the way which will be chosen. the number of tag entries which are looked at depends on the set associativity of the cache. first the valid bits are inspected. if an invalid way is av ailable, as determined by all 4 of the valid bits in a tag being zero, then that way will be selected. if more than one invalid way is available, then the first one found starting from way0 will be selected. if all ways are valid, then any locked ways will be e xcluded from consideration for replacement. if all ways are locked, then no replacement can occur to that line. for the unlocked ways, the lrf bits from each tag are used to identify the way which has been filled l east recently, and that way is selected for replace- ment. when the new tag is written during the line fill, it s lrf bit is modified to indicate that way is no longer the least recently filled. instruction cache the instruction cache is a memory block of 16 kb ytes. the virtually indexed, physically tagged cache allows the virtual-to-physical address translation to oc cur in parallel with the cache access rather than having to wait for the physical address translation. the 4kc core supports instruction cache-locking. cac he locking allows critical code or data segments to be locked into the cache on a ?per-line? basis, enabli ng the system programmer to maximize the efficiency of the system cache. the cache locking function is always enabled on all instruction cache entries. entries can then be marked as locked or unlocked on a per entry basis using the cache instruction. data cache the data cache is a memory block of 16 kbytes. the virtually indexed, physically tagged cache allows the virtual-to-physical address translation to occur in parallel with the cache ac cess rather than having to wait for the physical address translation. the core also supports a data cache locking mechanism identical to the instruction cache. critical data segments to be locked into the cache on a ?per-li ne? basis. the locked contents can be updated on a store hit, but cannot be selected fo r replacement on a miss. the cache locking function is always enabled on all data cache entries. entries can then be marked as locked or unlocked on a per entry basis using the cache instruction.
idt mips32 4kc processor core power management 79rc32438 user reference manual 2 - 83 november 4, 2002 notes memory coherence issues a cache presents coherency issues within the memo ry hierarchy which must be considered in the system design. since a cache holds a copy of memory data, it is possible for another memory master to modify a memory location, thus making other copies of t hat location stale if those copies are still in use. a detailed discussion of memory coherence is beyond t he scope of this document, but following are a few related comments. the 4kc processor core contains no direct hardwar e support for managing coheren cy with respect to its caches, so it must be handled via system design or softw are. the 4kc caches are write-through, so all data writes will eventually be sent to memory. due to writ e buffers, however, there could be a delay in how long it takes for the write to memory to actually occu r. if another memory master updates cacheable memory which could also be in the 4kc caches, then those locations may need to be flushed from the cache. the only way to accomplish this invalidati on is by use of the cache instruction. the sync instruction may also be useful to software enforcing memory coherence, as it flushes the 4kc processor core?s write buffers. power management register-controlled power management the rp bit in the cp0 status register a standard so ftware mechanism for placing the system into a low power state. the state of the rp bit is available externally via the si_rp signal. three additional pins, si_exl, si_erl, and ej_debugm support the power m anagement function by allowing the user to change the power state if an exception or error occurs while t he core is in a low power state. setting the rp bit of the cp0 status register causes the core to asse rt the si_rp signal. the external agent can then decide whether to reduce the clock frequency and pl ace the core into power down mode. if an interrupt is taken while the device is in pow er down mode, that interrupt may need to be serviced depending on the needs of the application. the interrupt causes an exception which in turn causes the exl bit to be set. the setting of the exl bit causes the asse rtion of the si_exl signal on the external bus, indi- cating to the external agent that an interrupt has occu rred. at this time the external agent can choose to either speed up the clocks and service the interrupt or let it be serviced at the lower clock speed. the setting of the erl bit causes the assertion of the si_erl signal on the exter nal bus, indicating to the external agent that an error has occurred. at this ti me the external agent can choose to either speed up the clocks and service the error or let it be serviced at the lower clock speed. similarly, the ej_debugm signal indicates that t he processor is in debug mode. debug mode is entered when the processor takes a debug exception. if fast hand ling of this is desired, the external agent can speed up the clocks. the core provides 4 power down signals t hat are part of the system interface: ? the si_rp signal represents the state of the rp bit (27) in the cp0 status register. ? the si_exl signal represents the state of the exl bit (1) in the cp0 status register. ? the si_erl signal represents the state of t he erl bit (2) in the cp0 status register. ? the ej_debugm signal indicates that the processor has entered debug mode. three of the pins change state as the corresponding bits in the cp0 status regi ster are set or cleared. the fourth pin indicates that the processor is in debug mode. instruction-controlled power management the second mechanism for invoking power down mode is through execution of the wait instruction. if the bus is idle at the time the wait instruction reac hes the m stage of the pipeline, the internal clocks are suspended and the pipeline is frozen. however, the inter nal timer and some of the input pins (si_int[5:0], si_nmi, si_reset, si_coldreset, and ej _dint) continue to run. if the bus is not idle at the time the wait instruction reaches the m stage, the pipeline stalls until the bus becomes idle, at which time the clocks are stopped. once the cpu is in instruction controll ed power management mode, any enabled interrupt, nmi,
idt mips32 4kc processor core instruction set 79rc32438 user reference manual 2 - 84 november 4, 2002 notes debug interrupt, or reset condition causes the cpu to exit this mode and resume normal operation. while the part is in this low-power mode, the si_sleep signal is asserted to indicate to external agents what the state of the chip is. instruction set the 4kc core processor has 3 instruction set form ats ? immediate, jump, and register ? as shown in figure 2.36. each cpu instruction consists of a single 32-bit word, aligned on a word boundary. figure 2.36 instruction set formats load and store instructions load and store are immediate (i-type) instructions that move data between memory and the general registers. the only addressi ng mode that load and store instructions directly support is base register plus 16-bit signed immediate offset. scheduling a load delay slot a load instruction that does not allow its result to be used by the instruction immediately following is called a delayed load instruction. the instruction slot immediately following this delayed load instruction is referred to as the load delay slot. the instruction immediately following a load instruction can use the contents of the loaded register. however, in such case s, hardware interlocks in sert additional real cycles. although not required, the scheduling of load del ay slots can be desirable for performance. defining access types access type indicates the size of a core data item to be loaded or stored, set by the load or store instruc- tion opcode. regardless of access type or byte or dering (endianness), the address given specifies the low- order byte in the addressed field. fo r a big-endian configuration, the low- order byte is the most-significant byte; for a little-endian configuration, the low- order byte is the l east-significant byte. op 6-bit operation code rs 5-bit source register specifier rt 5-bit target (source/destinati on) register or branch condition immediate 16-bit immediate value, branc h displacement or address displacement target 26-bit jump target address rd 5-bit destination register specifier sa 5-bit shift amount funct 6-bit function field i-type (immediate) r-type (register) j-type (jump) immediate 0 15 rt 16 20 op 26 31 rs 21 25 target 0 15 op 26 31 rt 16 20 op 26 31 rs 21 25 sa 6 10 rd 11 15 funct 0 5 target 0 25 op 31
idt mips32 4kc processor core instruction set 79rc32438 user reference manual 2 - 85 november 4, 2002 notes the access type and the three low-order bits of the address define the bytes accessed within the addressed word as shown in table 2.58. only the co mbinations shown in tabl e 2.58 are permissible; other combinations cause addr ess error exceptions. computational instructions computational instructions can be ei ther in register (r-type) forma t, in which both operands are regis- ters, or in immediate (i-type) format, in which one operand is a 16-bit immediate. computational instructions perform the following operations on register values: arithmetic logical shift multiply divide these operations fit in the following four categories of computational instructions: ? alu immediate instructions ? three-operand register-type instructions ? shift instructions ? multiply and divide instructions cycle timing for multiply and divide instructions any multiply instruction in the integer pipeline is transferred to the multiplier as remaining instructions continue through the pipeline; the product of the multiply instruction is saved in the hi and lo registers. if the multiply instruction is followed by an mfhi or mf lo before the product is available, the pipeline inter- locks until this product does become available. fo r more information on instruction latency and repeat rates, see the pipeline description section earlier in this chapter. access type low order address bits bytes accessed big endian 31...........0 little endian 31...........0 2 1 0 byte byte word 00001233210 triple byte 000012 210 001 123321 half word 00001 10 010 2332 byte 0000 0 001 1 1 010 2 2 011 33 table 2.58 byte access within a word
idt mips32 4kc processor core instruction set 79rc32438 user reference manual 2 - 86 november 4, 2002 notes jump and branch instructions jump and branch instructions change the control fl ow of a program. all jump and branch instructions occur with a delay of one instruction: that is, the instru ction immediately following the jump or branch (this is known as the instruction in the delay slot) always ex ecutes while the target instruction is being fetched from storage. overview of jump instructions subroutine calls in high-level languag es are usually implemented with jump or jump and link instruc- tions, both of which are j-type instructions. in j-type format, the 26-bit target address shifts left 2 bits and combines with the high-order 4 bits of the current program counter to form an absolute address. returns, dispatches, and large cross-page jumps are usually implemented with the ju mp register or jump and link register instructions. both are r-ty pe instructions that take the 32-bit byte address contained in one of the general purpose registers. for more information about jump instructions, see the instruction set section earlier in this chapter. overview of branch instructions all branch instruction target addresses are comput ed by adding the address of the instruction in the delay slot to the 16-bit offset (shifted left 2 bits and sign-extended to 32 bits). all branches occur with a delay of one instruction. if a conditional branch likely is not taken, the instruction in the delay slot is nullified. branches, jumps, eret, and deret instructions should not be placed in the delay slot of a branch or jump. control instructions control instructions allow the software to initiate traps; they are always r-type. coprocessor instructions cp0 instructions perform operations on the system control coproces sor registers to manipulate the memory management and exception handling facilities of t he processor. for a listing of cp0 instructions, refer to appendix a, 4kc processor co re instructions, in this manual. enhancements to the mips architecture the core execution unit implements the mips32 archit ecture, which includes the following instructions: ? clo ? count leading ones ? clz ? count leading zeros ? madd ? multiply and add word ? maddu ? multiply and add unsigned word ? msub ? multiply and subtract word ? msubu ? multiply and subtract unsigned word ? mul ? multiply word to register ? ssnop ? superscalar inhibit nop. clo - count leading ones the clo instruction counts the number of leading ones in a word. the 32-bit word in the gpr rs is scanned from most-significant to le ast-significant bit. t he number of leading ones is counted and the result is written to the gpr rd. if all 32 bits are set in the gpr rs, the result written to the gpr rd is 32. clz - count leading zeros the clz instruction counts the number of leading zeros in a word. the 32-bit word in the gpr rs is scanned from most-significant to l east-significant bit. the number of leading zeros is counted and the result is written to the gpr rd. if all 32 bits are cleared in the gpr rs, the result written to the gpr rd is 32.
idt mips32 4kc processor core processor core instructions 79rc32438 user reference manual 2 - 87 november 4, 2002 notes madd - multiply and add word the madd instruction multiplies two words and adds t he result to the hi/lo register pair. the 32-bit word value in the gpr rs is multiplied by the 32-bi t value in the gpr rt, treating both operands as signed values, to produce a 64-bit result. the product is added to the 64-bit concatenated values in the hi and lo register pair. the resulting value is then written back to the hi and lo registers. no arithmetic exception occurs under any circumstances. maddu - multiply and add unsigned word the maddu instruction multiplies two unsigned word s and adds the result to the hi/lo register pair. the 32-bit word value in the gpr rs is multiplied by the 32-bit value in the gpr rt, treating both operands as unsigned values, to produce a 64-bit result. the product is added to the 64-bit concatenated values in the hi and lo register pair. the resulting value is t hen written back to the hi and lo registers. no arithmetic exception occurs under any conditions. msub - multiply and subtract word the msub instruction multiplies two words and subtract s the result from the h i/lo register pair. the 32- bit word value in the gpr rs is multiplied by the 32 -bit value in the gpr rt, treating both operands as signed values, to produce a 64-bit result. the product is subtracted from the 64-bit concatenated values in the hi and lo register pair. the resulting value is then wr itten back to the hi and lo registers. no arithmetic exception occurs under any circumstances. msubu - multiply and subtract unsigned word the msubu instruction multiplies two unsigned words and subtracts the result from the hi/lo register pair. the 32-bit word value in the gpr rs is multipli ed by the 32-bit value in the gpr rt, treating both oper- ands as unsigned values, to produce a 64-bit result. t he product is subtracted from the 64-bit concatenated values in the hi and lo register pair. the resulting va lue is then written back to the hi and lo registers. no arithmetic exception occurs under any circumstances. mul - multiply word the mul instruction multiplies two words and writes t he result to a gpr. the 32-bit word value in the gpr rs is multiplied by the 32-bit value in the gp r rt, treating both operands as signed values, to produce a 64-bit result. the least-significant 32 bits of the product are written to the gpr rd. the contents of the hi and lo register pair are not defined after the operati on. no arithmetic exception occurs under any circum- stances. ssnop- superscalar inhibit nop the 4kc processor core treats this instruction as a regular nop. processor core instructions the 4kc processor core instructions are discussed in appendix a of this user manual.
idt mips32 4kc processor core processor core instructions 79rc32438 user reference manual 2 - 88 november 4, 2002 notes
notes 79rc32438 user reference manual 3 - 1 november 4, 2002 chapter 3 clocking and initialization introduction this chapter discusses the reset initialization sequence that is required by the rc32438 device and includes information on the boot vector settings. these se ttings are used to configure the processor for the remainder of the power-up sequence. this chapter also provides a description of the clock signals that are used on the rc32438. block diagram figure 3.1 illustrates how the boot configuration vector and reset signals may be generated in a system. figure 3.1 system block diagram of reset and boot configurati on vector generation clocking overview the rc32438 is designed to simplify the external clocking requirements for an embedded system. the device requires one input clock and from this generates the processor clock (pclk) from which the cpu pipeline operates, the clock for the ddr memory sub system and the clock for the local address/data bus. if the pci interface is desired to be operated synchronous ly to the other rc32438 interfaces, the pci clock can be tied externally to the cl ock for the local address/data bus. internally, the device supports a range of clock mult ipliers and divisors to allow system designers to select a combination that best meets their needs. additionally, this device has been designed to operate from a relatively low external clock frequency without compromising the cpu or memory performance. for example, the use of a 33mhz clock can suppor t a 266mhz cpu pipeline frequency and standard ddr 266 memories. in this case, the local memory bus can be operated at either 66mhz or 33mhz, enabling the pci interface to be operated from the same clock signal if synchronous operation is desired. the use of low external clock frequencies simplifies board design and r educes noise emissions. refer to table 3.1 for more information on the clock ratios that are supported. high speed device or memory fct245 boen oe dir bdirn mdata[31:0] low speed device or memory fct245 oe ... ... vcc coldrstn reset generator rstn external device external device external device rc32438 (boot vector)
idt clocking and initialization clocking overview 79rc32438 user reference manual 3 - 2 november 4, 2002 notes a pll multiplies the master clock input and generat es an internal cpu pipeline clock (pclk) and an ipbus clock (iclk). the cpu pipeline clock (pclk) is divided by two to form the ipbus clock (iclk). all of the logic that interfaces to the ipbus use this clo ck. in addition, the ipbus clock is used to generate the clock signals for the external ddr memory subsystem. the ipbus clock is further divided by the value selected in the external clock divider field in the boot configuration vector to generate an external clock output on the extclk pin. the external clock output (extclk) is used by the memory and peripheral bus. the relationship between clk, pclk, iclk, and the extclk pin are shown in figure 3.2. figure 3.2 rc32438 clocking architecture the cpu pipeline clock is equal to the master cloc k input multiplied by the value selected by the cpu pipeline clock multiplier field in the boot configurat ion vector during a cold reset. table 3.1 shows the supported cpu pipeline clock multiplier field modes. care must be exercised to ensure that the master clock input frequency falls within the range supported by a selected mode. for example, when multiply by 3 is selected, the master clock input frequency must be between 66.6 mhz and 88.6 mhz. cpu pipeline clock multiplier clk pclk min 1 1. frequency in mhz. max 1 min 1 max 1 pll bypass ---- multiply by 3 66.6 88.6 200 266 multiply by 4 50 66.6 200 266 multiply by 6 33.3 44.3 200 266 multiply by 8 25 33.25 200 266 table 3.1 processor clock pll multiplier modes pll divider divider pclk iclk cpu most on-chip logic cpu pipeline clock multiplier (bypass, 3, 4, 6, 8) external clock divider (1, 2, 4) constant 2 rc32438 clk extclk clock for ddr memory
idt clocking and initializatio n reset register description 79rc32438 user reference manual 3 - 3 november 4, 2002 notes reset register description reset and initialization the rc32438 may be reset with either a warm reset or a cold reset. cold reset a cold reset is initiated through the assertion of t he cold reset (coldrstn) pin. the coldrstn pin is typically asserted by an external voltage monitor or re set switch at power-up. a cold reset causes the rc32438 to initialize its internal state, assert the rese t (rstn) bidirectional pin, assert the boen pin, and assert the bdirn pin. no state information of any kind is preserved. figure 3.3 shows a cold reset. using the boot configuration vector the internal phase lock loop locks onto the master clock input (clk) and generates the cpu pipeline clock (pclk) and the ipbus clock (iclk). when the coldrstn signal is negated, the boot configuration vector is obtained fr om the bottom 16-bits of the data bus (mdata[15:0] clocked in on the previous rising edge of clk). 1 once the processor clock stabilizes, the rstn pin is tri-stated. the rc32438 then waits an additional 4096 master clock cycles to allow the rstn pin to be pulled up by an external resistor, then samples the state of the rstn pin and the pcirstn pin if the pci interface is selected to operate in satellite mode by the boot configuration vector. if rstn is negated and if the pci interface is selected to operate in satellite mode the de-glitched pcirstn signal is also negated, then the cpu begins execution by taking a mips soft reset exception. if rstn is still asserted, the rc32438 waits an additional 4096 master clock cycles and repeats the above process. if the pci interface is selected to operate in satellite mode and the de- glitched pcirstn signal is asserted, then the rc32438 rema ins in a reset state until it is negated (or until coldrstn or rstn is asserted at which po int a cold or warm reset process begins). before the boot configuration vector has been read duri ng a cold reset, the external clock (extclk) pin output is held low. within 16 clk clock cycles of reading the boot configuration vector, the rc32438 will begin generating extclk. extclk is guaranteed to be glitch free and maintain a 60/40 duty cycle. register offset 1 1. the address of the register is equal to the regi ster offset added to the base value of 0x1800_0000. register name register function size 0x00_8000 reset reset 32-bit 0x00_8004 bvc boot configuration vector 32-bit 0x00_8008 cea 2 2. note that the cea register is discussed in chapter 4, system integrity functions. cpu error address 32-bit 0x00_800c through 0x00_ffff reserved table 3.2 reset register map 1. the cpu pipeline clock multiplier field (i.e., mdata[3:0]) should be driven to a valid value as soon as possible after power stabilizes. this field is use by the pll before coldrstn is negated. all other fields of the boot configuration vector are sampled only when coldrstn is negated.
idt clocking and initialization reset and initialization 79rc32438 user reference manual 3 - 4 november 4, 2002 notes figure 3.3 cold reset figure 3.4 pci reset in host mode boot configuration vector the boot configuration vector is read by the rc32438 during a cold reset. the vector defines essential rc32438 parameters that are required once the cold reset completes. the encoding of boot configuration ve ctor is described in table 3.3, and the vector input is illustrated in figure 3.5. the value of the boot configuration vect or read in by the rc32438 during a cold reset may be determined by reading the boot conf iguration vector (bcv) register. boot vect clk coldrstn rstn mdata[15:0] bdirn boen >= 4096 clk clock cycles 1 2 3 4 5 6 ffff_ffff 1. coldrstn asserted by external logic. the rc32438 asserts rstn, asserts boen low, drives bdirn low, di sables extclk, and tri- states the data bus and all output pins in response. 2. external logic begins driving valid boot configuration vector on the data bus, and the rc32438 starts sampling it. 3. external logic negates coldrstn and tri-st ates the boot configuration vector on mdata[15:0]. the b oot configuration vector mu st not be tri-stated before coldrstn is negated. the rc 32438 stops sampling the boot configuration vector. 4. the rc32438 starts driving the data bus, mdata[15:0], negates boen, drives bd irn high, and starts driving extclk. 5. rstn negated by the rc32438. 6. cpu begins executing by taking mips reset exception, and the rc32438 starts sampling rstn as a warm reset input. <= 16 clk clock cycles >= 4096 clk clock cycles extclk pci interface enabled cold reset warm reset coldrstn pcirstn (output) rstn note: during and after cold reset, pcirstn is tri-stat ed and requires a pull-down to reach a low state. after the pci interface is enabled in host mode, pc irstn will be driven high and low depending on the (tri-state) reset state of the 79rc32438.
idt clocking and initialization reset and initialization 79rc32438 user reference manual 3 - 5 november 4, 2002 notes signal name/description mdata[3:0] cpu pipeline clock multiplier . this field specifies the value by which the pll multi- plies the master clock input (clk) to obtain the processor clock frequency (pclk). see table 3.1 for master clock input frequency constraints. 0x0 - pll bypass 0x1 - multiply by 3 0x2 - multiply by 4 0x3 - multiply by 6 0x4 - multiply by 8 0x5 to 0xf - reserved mdata[5:4] external clock divider . this field specifies the value by which the ipbus clock (iclk) is divided in order to generate the external clock output on the extclk pin. 0x0 - divide by 1 0x1 - divide by 2 0x2 - divide by 4 0x3 - reserved mdata[6] endian. this bit specifies the endianness. 0x0 - little endian 0x1 - big endian mdata[7] boot device width . this field specifies the width of the boot device (i.e., device 0). 0x0 - 8-bit boot device width 0x1 - 16-bit boot device width mdata[8] fast reset . when this bit is set, rstn is driven for 64 clock cycles. this mode is used only during testing. clear this bit for normal operation. 0x0 - normal reset: rstn driven for minimum of 4096 clock cycles 0x1 - fast reset mdata[11:9] pci mode . this bit controls the operating mode of the pci bus interface. the initial value of the en bit in the pcic register is determined by the pci mode. 0x0 - disabled (en initial value is zero) 0x1 - pci satellite mode with pci target not ready (en initial value is one) 0x2 - pci satellite mode with suspended cpu execution (en initial value is one) 0x3 - pci host mode with external arbiter (en initial value is zero) 0x4 - pci host mode with internal arbiter using fixed priority arbitration algorithm (en initial value is zero) 0x5 - pci host mode with internal arbiter using round robin arbitration algorithm (en initial value is zero) 0x6 - reserved 0x7 - reserved mdata[12] disable watchdog timer . when this bit is set, the watchdog timer is disabled follow- ing a cold reset. 0x0 - watchdog timer enabled 0x1 - watchdog timer disabled mdata[13] pll test mode . when this bit is set the plltest pin output driver is enabled. this mode is used only for factory testing of the pll. when this bit is cleared, the plltest pin is tri-stated. mdata[15:14] reserved . these pins must be driven low during boot configuration. table 3.3 boot configuration encoding
idt clocking and initializatio n reset/initialization registers 79rc32438 user reference manual 3 - 6 november 4, 2002 notes reset/initialization registers boot configuration vector register figure 3.5 boot configurat ion vector register (bcv) warm reset a warm reset may be initiated by one of seven conditions: ? assertion of the reset pin (rstn) by an external agent ? a cpu write of 0x8000_0001 to the reset (reset) register ? an ipbus transaction timer time-out ? a watchdog timer time-out with the wre bit set in the errcs register ? a cpu or pci master write setting the warm reset (wr) bit in the pci management (pcimgt) register in pci configuration space ? assertion of the pci reset signal (pcirstn) when operating in pci satellite mode ? generation of a processor reset by ejtag debug softw are by setting of the prrst bit in the ejtag control register (i.e., assertion of the ej_prrst output signal by the cpu core). when one of these conditions occurs, the rc32438 as serts the rstn pin for a minimum of 4096 clk clock cycles. the rc32438 then tri-states rstn and waits an additional 4096 clk clock cycles and exam- ines the state of the rstn pin and the pcirstn pin if the pci interface is selected to operate in satellite mode by the boot configuration vector. if rstn is negat ed and if the pci interface is selected to operate in satellite mode, the de-glitched pcir stn signal is also negated, and the cpu begins execution by taking a mips soft reset exception. 1 if rstn is still asserted, the warm reset procedure above is repeated. if the pci interface is selected to operate in satellite mode and the de-glitched pcirstn signal is asserted, then the rc32438 remains in a warm reset until it is negated (or until rstn is asserted again at which point the warm reset process repeats). the delay between tri-stating the rs tn pin and then sampling whether it is asserted allows the signal to be pulled up with a resistor. during a warm reset, al l memory and peripheral bus transactions are inhibited. the ddr controller continues operat ion across warm resets and may gen erate a refresh transaction during a warm reset. a warm reset causes the following: ? all blocks within the rc32438 are reset with t he exception of the cpu, cpu biu and ipbus moni- tor ? the cpu to take a mips soft reset exception bcv description: boot configuration vector. this field contains the boot configuration vector read in by the rc32438 during a cold reset. see table 3.3 for a description of the encoding of this vector. initial value: boot configuration vector read value: boot configuration vector write effect: read-only 1. the assertion of csn[0] will occur no sooner than 16 clock cycles after the rc32438 samples rstn negated. bcv 0 31 16 0 16 bcv
idt clocking and initializatio n reset/initialization registers 79rc32438 user reference manual 3 - 7 november 4, 2002 notes ? all registers are reset to their in itial value, except the following: ?btcompare 1 , btaddr, and btcs registers ? pcic register is not modified with the exception of the tnr bit which is cleared ? to bit in the wtc regi ster is not modified ? en bit in the wtc register if the warm re set was not caused by the expiration of the watchdog timer ? wto bit in the errcs register is not modified ? wr bit in the pcis register is not modified ? registers in pci configurat ion space are not modified ? ddr controller registers are not modified ? ipbus monitor registers are not modified ? event monitor regist ers are not modified ? contents of on-chip memory is not modified. 1. note that all pci registers are reset to their initial value if the warm reset was the result of an assertion of the pci reset signal when operating in pci satellite mode. 2. also note that the external clock, extcl k, is always driven during any warm reset. an externally initiated warm reset caused by asserti on of rstn by an external agent is shown in figure 3.6, while an internally initiated warm reset, for example, caused by a write of 0x8000_0001 to the reset register is shown in figure 3.7. figure 3.6 externally initiated warm reset 1. if the warm reset is the result of a bus transaction time-ou t, the btcompare field is initialized to 0xffff. 1. warm reset condition caused by assertion of rstn by an external agent. 2. rc32438 tri-states the data bus, mdat a[15:0], negates all memory control signals, and itself asserts rstn. 3. rc32438 negates rstn after 4096 master clock (clk) cycles. 4. external agent negates rstn. 5. rc32438 samples rstn negated 4096 master clock (clk) cycles af ter step 3 and starts drivin g the data bus, mdata[15:0]. 6. cpu begins executing by taking a mips soft reset exception. the assertion of csn[0] will occur no sooner than 16 clock cycles after the rc32438 samples rstn negated (i.e., step 5). active deasserted active clk coldrstn rstn mdata[15:0] mem control signals ffff_ffff 1 2 4 5 6 3 4096 clock cycles 4096 clock cycles
idt clocking and initializatio n reset/initialization registers 79rc32438 user reference manual 3 - 8 november 4, 2002 notes figure 3.7 internally initiated warm reset figure 3.8 pci reset in satellite mode reset register figure 3.9 reset register (reset) r description: reset. a write of the value 0x8000_0001 to this register causes the rc32438 to generate a warm reset. a write of any other value has no effect. initial value: undefined read value: undefined write effect: write value of 0x8000_0001 generates a warm reset 1. warm reset condition caused by a cpu write of 0x8000_0001 to t he reset register. the rc32438 tri- states the data bus, mdata[1 5:0], negates all memory control signals, and asserts rstn. 2. rc32438 negates rstn after 4096 master clock (clk) cycles. 3. rc32438 samples rstn negated after waiting 4096 or 64 master cl ock (clk) clock cycles depending on the boot configuration mod e and starts driving the data bus, mdata[15:0]. 4. cpu begins executing by taking a mips soft reset exception. the assertion of csn[0] will occur no sooner than 16 clock cycles after the rc32438 samples rstn negated (i.e., step 5). active deasserted active clk coldrstn rstn mdata[15:0] mem control signals 1 3 4 2 ffff_ffff warm reset clk pcirstn (input) rstn mdata[15:0] pci bus signals reset 0 31 32 r
idt clocking and initializatio n reset/initialization registers 79rc32438 user reference manual 3 - 9 november 4, 2002 notes
idt clocking and initializatio n reset/initialization registers 79rc32438 user reference manual 3 - 10 november 4, 2002 notes
notes 79rc32438 user reference manual 4 - 1 november 4, 2002 chapter 4 system integrity functions introduction this chapter describes the system integrity f unctions on the rc32438. the system integrity module includes several registers that log system activity. these registers can be used to indicate the source of hardware or software errors. features ? programmable bus transacti on timer generates warm reset when counter expires ? address space monitor ? programmable watchdog timer generat es nmi when counter expires functional overview the rc32438 supports three functions to monitor acti vity within the system and report potential hard- ware or software error conditions. the first function is the bus transaction timer. the bus transaction timer times memory and peripheral bus transactions, generating a warm reset if a transact ion does not complete within a specified number of clock cycles. the bus transaction ti mer is part of the device controller. for more information on the bus transaction timer, see the memo ry and peripheral bus transaction timer section in chapter 6. a second function is the address space monitor. the address space monitor generates an error in response to bus transactions with invalid rc32438 lo cal address space addresses. this applies to transac- tions generated by the cpu as well as the pci and dma controllers. a third function is the watchdog timer. the watchdog ti mer is a general purpose timer that, if not periodi- cally reset by software, generates a nonmaskable interr upt (nmi) exception to the cpu or a warm reset. the watchdog timer is independent from the three general purpose timers described in chapter 14, counter timers. system integrity functions are c ontrolled, and their status is reported in the error control and status (errcs) register. the bus transaction timer, the address space monitor, and the watchdog are all enabled following a cold reset. the bus timer and watchdog timer can be individually disabled by software. the address of an undecoded cpu read/write operation or ipbus slave acknowledge error is recorded in the cpu error address (cea) regist er. this register is only accessible by the cpu since it is located in the cpu biu. system integrity re gister description register offset 1 register name register function size 0x03_0000 through 0x03_002c reserved 0x03_0030 errcs error control and status 32-bit 0x03_0034 wtcount watchdog timer count 32-bit table 4.1 system integrity register map (part 1 of 2)
idt system integrity functions system integrity registers 79rc32438 user reference manual 4 - 2 november 4, 2002 notes system integrity registers error control and status register figure 4.1 error control and status register (errcs) 0x03_0038 wtcompare watchdog timer compare 32-bit 0x03_003c wtc watchdog timer control 32-bit 0x03_0040 through 0x03_7fff reserved 1. the address of the register is equal to the regi ster offset added to the base value of 0x1800_0000. wto description: watchdog timer time out. when the watchdog timer times-out and either the wne or wre bit in this register is set, this bit is set. initial value: 0x0 read value: status ( this field is not modified due to a warm reset ) write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) wne description: watchdog timer nmi enable. when this bit is cleared, the watchdog timer is masked from gener- ating an nmi. when the watchdog timer expires, and this bit is set, and the wre bit is cleared, an nmi is generated. 0 watchdog timer nmi masked 1 watchdog timer nmi enabled (unmasked) initial value: 0x1 read value: previous value written write effect: modify value ucw description: undecoded cpu write. this bit is set when the cpu writes to an undecoded address space. this bit is presented to the interrupt handler as the undecoded cpu write interrupt source. initial value: 0x0 read value: status write effect: sticky bit. the interrupt service routine must clear this bit. ucr description: undecoded cpu read. this bit is set when the cpu reads from an undecoded address space. this bit is presented to the interrupt handler as the undecoded cpu read interrupt source. register offset 1 register name register function size table 4.1 system integrity register map (part 2 of 2) errcs 0 31 22 0 1 wto 1 wne 1 ucw 1 ucr 1 upw 1 upr 1 udw 1 udr 1 sae 1 wre
idt system integrity functions system integrity registers 79rc32438 user reference manual 4 - 3 november 4, 2002 notes initial value: 0x0 read value: status write effect: sticky bit. the interrupt service routine must clear this bit. upw description: undecoded pci write. this bit is set when the pci interface writes to an undecoded address space. this bit is presented to the interrupt handler as the undecoded pci write interrupt source. initial value: 0x0 read value: status write effect: sticky bit. the interrupt service routine must clear this bit. upr description: undecoded pci read. this bit is set when the pci interface reads from an undecoded address space. this bit is presented to the interrupt handler as the undecoded pci read interrupt source. initial value: 0x0 read value: status write effect: sticky bit. the interrupt service routine must clear this bit. udw description: undecoded dma write. this bit is set when the dma writes to an undecoded address space. this bit is presented to the interrupt handler as the undecoded dma write interrupt source. initial value: 0x0 read value: status write effect: sticky bit. the interrupt service routine must clear this bit. udr description: undecoded dma read. this bit is set when the dma interface reads from an undecoded address space. this bit is presented to the interrupt handler as the undecoded dma read interrupt source. initial value: 0x0 read value: status write effect: sticky bit. the interrupt service routine must clear this bit. sae description: ipbus slave acknowledge error. this bit is set when an ipbus slave signals a slave acknowledge error. initial value: 0x0 read value: status write effect: sticky bit. the interrupt service routine must clear this bit.
idt system integrity functions address space monitor 79rc32438 user reference manual 4 - 4 november 4, 2002 notes cpu error address register figure 4.2 cpu error address register (cea) note: the register address for cea can be found in chapter 3, table 3.2. address space monitor the address space monitor observe s physical addresses in transacti ons generated by the cpu, pci, and dma controller and generates an error if the addr ess does not decode to a valid region within the rc32438 memory map or if an address maps to two r egions due to mis-configuration of a region?s base and mask registers. table 4.2 summarizes the methods used to report an undecoded address or redundant mapping errors to the cpu, pci, and dma controlle r. the address space monitor is always enabled. if an undecoded address error is detected during a singl e byte, half-word, or word dma transfer, then the ca field in the dma descriptor is incremented by one byte, half-word, or word respectively and the count field is decremented accordingly. if an undecoded address error is detected in a burst dma transfer, then the count and ca fields in the dma descriptor are unmodified. wre description: watchdog timer warm reset enable. when this bit is set and the watchdog timer times-out, a warm reset is generated. when this bit is cleared, a warm reset is never generated due to a watch- dog timer time-out. 0 - no warm reset on watchdog timer time-out 1 - generate warm reset on watchdog timer time-out initial value: 0x0 read value: previous value written write effect: modify value addr description: address. this field contains the physical address of the first cpu transaction which resulted in an undecoded address error or slave acknowledge error. this register is only updated when an undecoded address error or slave acknowledge error occurs if the addr field is all ones (i.e., 0xffff_ffff). initial value: 0xffff_ffff read value: physical address of the last cpu transaction that resulted in undecoded address error or previ- ous value written. write effect: modify value cea 0 31 32 addr
idt system integrity functions watchdog timer 79rc32438 user reference manual 4 - 5 november 4, 2002 notes watchdog timer when the watchdog timer nmi enable (wne) bit is se t in the errcs register, the watchdog timer will generate an nmi when it times out. in addition, t he watchdog timer may be configured to generate a warm reset when it times out by setting the watchdog timer wa rm reset enable (wre) bit in the errcs register. if both the wne and wre bits are cleared, the watchdog timer operates as a general purpose counter timer. the watchdog timer is enabled by setting the enable (e n) bit in the watchdog timer control (wtc) register. when this occurs, the watchdog timer begins incrementing its current watchdog timer count value with each ipbus clock (iclk) cycle. the cpu may determine the current watchdog timer count value by reading the watchdog timer count regi ster (wtcount). writing to this register modifies the watchdog timer count value. for normal operation, this regist er should be initialized to zero prior to enabling the watchdog timer. following a cold reset, the watc hdog timer is normally enabled. the watchdog timer may be disabled by setting the disable watchdog time r bit in the boot configuration vector. when the watchdog timer count value matches the value in the watchdog timer compare register (wtcompare), the timer expires 1 . when this occurs, the time out (wto) bit in the watchdog timer control register (wtc) is set. in addition, if either the watchdog timer warm reset enable (wre) bit or watchdog timer nmi enable (wne) bit is set in the error control and status register (errcs), the watchdog timer time-out (wto) bit is set in the errcs register. bus master bus master operation undecoded address error reporting mechanism cpu cpu read operation cpu bus error exception and undecoded cpu read (ucr) bit set in the errcs register. the cpu error addr ess (cea) register contains the address of the undecoded read. cpu write operation cpu core interrupt from ucw bit (undecoded cpu write (ucw) bit is set in the errcs register. the cpu error address (cea) register con- tains the address of the undecoded write. pci pci read operation pci transaction terminated with target abort and undecoded pci read (upr) bit set in errcs register. for additional information, refer to chapter 10, section ?error handling? on page 10-38. pci write operation pci transaction terminated with target abort and undecoded pci write (upw) bit set in errcs register. if the pci transaction resulted in a posted write, then a pci system error is signalled on the pci bus by asserting the serrn signal of the sen bit is set in the pci command register. for additional information, refer to chapter 10, section ?error handling? on page 10-38. dma dma descriptor read error (e) bit set in corresponding dma status (dmaxs) register and undecoded dma read (udr) bit set in errcs register. dma descriptor write error (e) bit in set in corresponding dma status (dmaxs) register and undecoded dma write (udw) bit set in errcs register. dma data read the terminated (t) bit is set in the descriptor in which the error was detected. the undecoded dma read (udr) bit is set in errcs regis- ter. dma data write the terminated (t) bit is set in the descriptor in which the error was detected. the undecoded dma write (udw) bit is set in the errcs reg- ister. table 4.2 address space monitor undecoded address error reporting 1. the counter timer expires at the point when the value in the wtcount register first equals the value in the wtcompare register (i.e., the rising edge of the mast er clock, that is, clk (wtcount == wtcompare)).
idt system integrity functions watchdog timer 79rc32438 user reference manual 4 - 6 november 4, 2002 notes if the watchdog timer is enabled to generate an nmi inte rrupt (i.e., the wne bit is set) and the timer expires, the watchdog timer time-out (wto) bit in the er rcs register is set, the en bit in the wtc register is cleared, and an nmi is generated. note: until the wto bit is cleared by softwar e, another watchdog nmi interrupt cannot be generated. if the watchdog timer is configured to generate a warm reset (i.e., the wre bit is set) and the timer expires, the to bit in the wtc regi ster and the wto bit in the errcs register are set, the en bit in the wtc register is cleared, and a warm reset is genera ted. the to and wto bits are not modified due to a warm reset. setting both the wne and wre bits results in a wa rm reset, causing all watchdog timer registers and fields (except the to and wto bits) to take on their in itial value. if neither the wne bit nor the wre bit is set, the watchdog timer behaves simply as a timer. when it expires, it resets its count value to zero and begins incrementing at the master clock frequency. the to bit is presented as an interrupt source to the interrupt handler. watchdog timer count register figure 4.3 watchdog timer count register (wtcount) watchdog timer compare register figure 4.4 watchdog timer compare register (wtcompare) count description: watchdog timer count. this field contains the current watchdog timer count value. initial value: 0x0000_0000 (this register is not reset after a warm reset) read value: current watchdog timer count write effect: set watchdog timer count compare description: compare value. this field contains the maximum watchdog timer count value. when the value in the wtcount register equals this value, the watchdog timer expires. initial value: 0xffff_ffff read value: previous value written write effect: modify value wtcount 0 31 32 count wtcompare 0 31 32 compare
idt system integrity functions ipbus slave acknowledge errors 79rc32438 user reference manual 4 - 7 november 4, 2002 notes watchdog timer control register figure 4.5 watchdog timer control register (wtc) ipbus slave acknowledge errors the ipbus provides a general mechani sm for slaves to report errors to ipbus masters during a read or write transaction. each ipbus slave that may gener ate an ipbus slave acknowledge error has two sticky bits that serve as interrupt source s. one bit is set on the occurrence of a slave acknowledge error during a read transaction while the other is set on the occurren ce of a slave acknowledge error during a write trans- action. the only ipbus slave in the rc32438 device that generat es slave acknowledge errors is the pci inter- face. see chapter 10, pci bus interface, for conditions that result in a pci slave acknowledge error. table 4.3 summarizes the methods used to report ipbus slave acknowledge errors. the dma controller does not stop a burst transfe r when a slave acknowledge error is detected. it completes the burst transfer and, as a result, the ca fi eld in the descriptor in which the error is detected is set to the last address of the burst transfer. the co unt is updated accordingly. a slave acknowledge error during a memory to peripheral dma results in undefi ned data being written to t he peripheral (in order to complete the dma burst transfer). a slave acknowledge error during a peripheral to memory dma results in data read from the peripheral being discarded (i n order to complete the dma burst transfer). en description: enable. when this bit is set, the watchdog timer is enabled. clearing this bit disables the watch- dog timer. neither enabling nor disabling the timer affects the watchdog timer count value. the en bit is automatically cleared when the watchdog timer expires and the wne bit in the errcs register is set. the state of the en bit is preserved across warm resets not caused by the expiration of the watchdog timer. initial value: see boot configuration vector (i.e., disable watchdog timer bit) read value: previous value written write effect: modify value to description: time out. this bit is set to a one to indicate that the watchdog timer has expired. once this bit is set, it will remain set until a zero is written into this field. initial value: 0x0 read value: status (this field is not modified when a warm reset occurs) write effect: sticky bit wtc 0 31 30 0to en 11
idt system integrity functions ipbus slave acknowledge errors 79rc32438 user reference manual 4 - 8 november 4, 2002 notes . bus master bus master operation ipbus slave acknowledge error reporting mechanism cpu cpu read operation a cpu bus error exception is generated and the slave acknowledge error (sae) bit is set in the errc s register. the cp u error address (cea) register contains the address of the transaction which resulted in an ipbus slave acknowledge error. a sticky bit is set in the ipbus slave that generated the error. the sticky bit may be selected as an interrupt source. for additional information, see chapter 10, section ?error han- dling? on page 10-21. cpu write operation a slave acknowledge error is not generated by the pci interface when a cpu generated pci master write transaction experiences a fatal error. for additional information, see chapter 10, section ?error handling? on page 10-21. pci pci read operation since the only interface that supports slave acknowledge errors in the rc32438 is the pci interface, this condition never occurs. pci write operation since the only interface that supports slave acknowledge errors in the rc32438 is the pci interface, this condition never occurs. dma dma descriptor read this condition never occurs in the rc32438. dma descriptor write this condition never occurs in the rc32438. dma data read this condition never occurs in the rc32438. dma data write this condition never occurs in the rc32438. table 4.3 ipbus slave acknowledge error reporting
notes 79rc32438 user reference manual 5 - 1 november 4, 2002 chapter 5 bus arbitration introduction this chapter describes the internal bus arbitrat ion mechanism used among t he various on-chip modules and explains the bus protocol used by an external bus master to gain ownership of the memory and periph- eral bus. functional overview the rc32438 has two internal buses, the ipbus and pmbus. it also has one external bus, the memory and peripheral bus. a bus master may have ownership of one or more buses at any given time, but no two masters can own the same bus at the same time. ther e are 16 potential ipbus masters. they consist of the 10 dma channels, an external bus mast er (on the memory and peripheral bus), the pci target interface, and the cpu when it is reading or writing devices on the ipbus. each potential ipbus master is assigned a bus ma ster index (see table 5.1). there are seventeen indices. the pci target interface is allocated two indi ces. one for the first tar get read or write transfer and one for subsequent target read transfers. this allows the initial data transfer of a target read or write trans- action to be given a higher priori ty than subsequent reads and writes. index bus master 0 external dma channel 0 1 external dma channel 1 2 ethernet channel 0 receive 3 ethernet channel 0 transmit 4 ethernet channel 1 receive 5 ethernet channel 1 transmit 6 memory to memory (memory to holding fifo) 7 memory to memory (holding fifo to memory) 8 pci (pci to memory) 9 pci (memory to pci) 10 reserved 11 reserved 12 reserved 13 external memory and peripheral bus master 14 pci target 15 pci target - read and write start 16 cpu (cpu accesses to ipbus) table 5.1 bus master index
idt bus arbitration ipbus register description 79rc32438 user reference manual 5 - 2 november 4, 2002 notes ipbus register description pmbus arbitration register description register offset 1 1. the address of the register is equal to the regi ster offset added to the base value of 0x1800_0000. register name register function size 0x04_4000 ipap0c ipbus arbiter priority 0 configuration 32-bit 0x04_4004 ipap1c ipbus arbiter priority 1 configuration 32-bit 0x04_4008 ipap2c ipbus arbiter priority 2 configuration 32-bit 0x04_400c ipap3c ipbus arbiter priority 3 configuration 32-bit 0x04_4010 ipabm0c ipbus arbiter bus master 0 configuration 32-bit 0x04_4014 ipabm1c ipbus arbiter bus master 1 configuration 32-bit 0x04_4018 ipabm2c ipbus arbiter bus master 2 configuration 32-bit 0x04_401c ipabm3c ipbus arbiter bus master 3 configuration 32-bit 0x04_4020 ipabm4c ipbus arbiter bus master 4 configuration 32-bit 0x04_4024 ipabm5c ipbus arbiter bus master 5 configuration 32-bit 0x04_4028 ipabm6c ipbus arbiter bus master 6 configuration 32-bit 0x04_402c ipabm7c ipbus arbiter bus master 7 configuration 32-bit 0x04_4030 ipabm8c ipbus arbiter bus master 8 configuration 32-bit 0x04_4034 ipabm9c ipbus arbiter bus master 9 configuration 32-bit 0x04_4038 through 0x04_4040 reserved 0x04_4044 ipabm13c ipbus arbiter bus master 13 configuration 32-bit 0x04_4048 ipabm14c ipbus arbiter bus master 14 configuration 32-bit 0x04_404c ipabm15c ipbus arbiter bus master 15 configuration 32-bit 0x04_4050 ipabm16c ipbus arbiter bus master 16 configuration 32-bit 0x04_4054 ipac ipbus arbiter control 32-bit 0x04_4058 ipaitcc ipbus arbiter idle transaction cycle count 32-bit 0x04_405c through 0x04_7fff reserved table 5.2 ipbus arbitration register map register offset 1 1. the address of the register is equal to the regi ster offset added to the base value of 0x1800_0000. register name register function size 0x02_0000 pmapp pmbus arbiter processor priority 32-bit 0x02_0004 pmasac pmbus arbiter sneak access control 32-bit 0x02_0008 through 0x02_7fff reserved table 5.3 pmbus arbitration register map
idt bus arbitration theory of operation 79rc32438 user reference manual 5 - 3 november 4, 2002 notes theory of operation the ipbus has four priorities. zero is the lowest and three is the highest. each ipbus priority has an associated ipbus arbite r priority configuration (ipapxc) register. the ipapxc register contains a prio rity transaction count (ptc) and cu rrent priority transaction count (cptc) field. each bus master index has a co rresponding ipbus arbiter bus master configuration (ipabmxc) register. the cmtc fiel d in ipabmxc indicates the current transaction count for the corre- sponding bus master, while mtc indi cates the transaction count. the msk field in ipabmxc allows bus ownership requests to be masked from the corres ponding bus master index. cpu bus ownership requests cannot be masked. the p field in ipabmxc contai ns the ipbus priority for the bus master. the arbiter should be initialized in the following manner. first, the mtc field of all bus masters should be configured. next, the ptc field of all priorities s hould be configured. since the arbiter only looks at the cptc and cmtc fields, the configuration will take af fect in the next epoch (i.e., when cptc reaches zero). the configuration of the arbiter may be modified when the system is running. the ipbus arbiter implements an enhanced weighted round robin arbitration scheme that supports priorities and full resource utilization. figure 5.1 shows a graphical view of the bus arbitration algorithm. in this example, bus masters with indices 4, 8, and 11 are assigned a priority of three (the highest). bu s masters with indices 3 and 15 are assigned a priority of two. bus masters with indices 1, 5, and 14 are assigned a priority of one. finally, bus masters with indices 2, 9, 13, and 16 are assigned a prio rity of zero (the lowest). arbitration requests from the other bus masters are masked. figure 5.1 illustration of ipbus arbitration algorithm the circumference of the circles represent the num ber of ipbus transactions required before the arbitra- tion epoch for that priority restarts. when an arbitrati on epoch restarts, the cmtc field of all bus masters with that priority is set to the corresponding mtc, and the cptc field of the priority is set to the ptc field. the algorithm looks at the highest priority. if there is a bus master requesting service whose cmtc is non-zero, then the bus is granted to that master. if multiple masters exist, then the bus is granted to the master that currently owns the bus. if none of the ma sters currently own the bus, then the bus is granted to the master with the lowest index. the cmtc for t he bus master that was granted the bus and the cptc of all priorities higher than or equal to the master priority are decrement ed. if no such bus master was granted the bus, then the algorithm repeats for the next highest priority. because priority is given to the master which curr ently has the bus, the arbiter will tend to cause trans- actions to the same bus master to be clustered. this feature is desired to allow ipbus transaction merging. if the cmtc field for a bus master reaches zero, t hen the bus master is not granted ownership until the cptc of the corresponding priority reaches zero and the arbitration epoch for the priority restarts. thus, the mtc field of a bus master can be viewed as limiting the percentage of bus bandwidth allocated to the bus master. the mtc fields of all bus masters with a giv en priority are normally less than or equal to the ptc field of the priority. if the sum is less than the ptc fiel d, then the remaining transfers for the priority are allo- cated to lower priorities. m 11 m 8 m 4 m 15 m 3 m 1 m 14 m 5 m 13 m 2 m 9 m 16 priority 3 priority 1 priority 2 priority 0
idt bus arbitration theory of operation 79rc32438 user reference manual 5 - 4 november 4, 2002 notes the minimum percentage of bus bandwidth available for a given priority can be calculated as follows for the above example: where mtci is the mtc for the bus master with index i and ptcj is the ptc for priority j. as an example, the percentage of bus bandwidth avai lable to bus masters 3 and 4 may be calculated as follows: it should be apparent that these equations approximat e bus bandwidth since the ipbus arbiter deals with transactions and not clock cycles. despite this fa ct, the ipbus arbiter provides a mechanism to bound service delays and provide a guaranteed level of service. when the cmtc field of all bus masters requesting serv ice is zero, then instead of allowing the ipbus to go idle, the bus is granted in a fair manner to one of the bus master(s) with the highest priority. ipbus supports transaction merging. this allows burst transfers to the double data rate (ddr) controller that are longer than a maximal length dma bur st (16 words). it also allows the system to limit queueing delays and hence minimize the size of buffers. the ddr controller can supply data at twice the data rate required by the ipbus. the ipbus arbiter passes hints to the ddr controll er when ipbus transaction merging ma y take place. the ddr controller uses this information to speculatively prefetch dat a potentially required for t he next dma transaction. when the disable prefetching (dp) bit is set in the ipbus arbiter control (ipac) register, ddr prefetching hints are disabled (i.e., the ddr controller wi ll never speculatively prefetch data). figure 5.2 depicts a flow chart of the ipbus arbitration algorithm. bw available to priority 3 100% = bw available to priority 2 1 mtc 8 mtc 4 mtc 11 ++ ptc 3 ------------------------------------------------------------------- ? ?? ?? x 100% = bw available to priority 1 1 mtc 8 mtc 4 mtc 11 ++ ptc 3 ------------------------------------------------------------------- ? ?? ?? x 1 mtc 3 mtc 15 + ptc 2 ------------------------------------------- ? ?? ?? x 100% = bw available to priority 0 1 mtc 8 mtc 4 mtc 11 ++ ptc 3 ------------------------------------------------------------------- ? ?? ?? x 1 mtc 3 mtc 15 + p tc2 ------------------------------------------- ? ?? ?? x 1 mtc 1 mtc 5 mtc 14 ++ ptc 3 ------------------------------------------------------------------- ? ?? ?? x100% = bw available to bus master 4 mtc 4 ptc 3 ---------------- x 100% = bw available to bus master 3 mtc 3 ptc 2 ---------------- x 1 mtc 8 mtc 4 mtc 11 ++ ptc 3 ------------------------------------------------------------------- ? ?? ?? x 100% =
idt bus arbitration theory of operation 79rc32438 user reference manual 5 - 5 november 4, 2002 notes figure 5.2 ipbus arbitration algorithm flow chart *the fairness bit is used internally by the arbiter and is not visible to software any bus master requesting ownership of the bus with a non-zero cmtc? any bus master requesting ownership of the bus with a zero cmtc? ? grant ownership to the master with highest priority that is requesting the bus. if multiple bus masters share the highest priority, then choose one in a fair manner as follows: a select the bus master with the lowest index that has highest priority, is re questing ownership of the bus, and does not have its fairness bit set.* b if all of these bus masters have their fairness bit set, then clear the fairne ss bit of all bus masters with highest priority and go back to step a. ? set the fairness bit of the bus master that is granted ownership of the bus. ? decrement the cptc of all priorities. ? decrement the cptc of all priorities. looping done? start is cptc for priority p equal to zero? loop through all priorities p = 0 through 3 ? set the cptc for priority p equal to its corresponding ptc. ? for all bus masters with priority p, set their cmtc equal to the corresponding mtc. ? if the mf bit in the correspondi ng ipapxc regist er is cleared, then for all bus masters with priority p, clear the bus master?s fairness bit.* yes no yes no yes yes no no has the bus been idle for 16 clock cycles? yes no ? grant ownership to the bus master with highest priority that is requesting the bus and has a non -zero cmtc. if multiple masters share these characterist ics, then grant the bus to the master that currently owns the bus. if none of the masters with these characteristics currently own the bus, then grant the bus to the master with the lowest index. ? decrement the cmtc of the bus master that was granted the bus. ? decrement the cptc of all priori ties higher than or equal to the priority of the master that was granted the bus.
idt bus arbitration theory of operation 79rc32438 user reference manual 5 - 6 november 4, 2002 notes example ipbus arbiter configurations to illustrate the operation of the ipbus arbiter, this section examines several ipbus arbiter configura- tions. for simplicity, only three prio rities and four bus masters are cons idered. the examples can be easily extended to all priorities and bus masters. strict priority arbitration figure 5.3 shows an ipbus arbiter configuration that im plements strict priority. in this example, masters with priority three are given preference over masters wi th lower priorities. priori ty two is given preference over priority one. since the ptc and mtc values for priority three are one, a new arbitration epoch begins each time the bus is granted to a priority three master. figure 5.4 illustrates the operation of the ipbus arbite r with the configuration in figure 5.3. each rect- angle represents one transaction or 64 clock cycles. t he value in a rectangle shows the current value of cptc or cmtc. the bottom row shows the current bus master. a rectangle is shaded if the corresponding bus master is requesting ownership of the bus. figure 5.3 ipbus arbiter configuration for strict priority arbitration figure 5.4 example operation of ipbus arbiter with strict priority arbitration fair arbitration figure 5.5 shows an ipbus arbiter configuration that impl ements fair arbitration. in this configuration the mf bit in the ipap3c register must be set. this maintains fairness across arbitration epochs. 1 since all masters have the same priority and a zero mtc, access to the bus is granted in a fair manner using the fair- ness bit method described in figure 5.2. priority 3 ptc 3 =1 mtc 1 =1 mtc 2 =1 priority 2 ptc 2 =1 mtc 3 =1 priority 1 ptc 1 =1 mtc 4 =1 1. if the mf bit were not set, then the fairness bit would be cleared each clock cycle since ptc is equal to one. this would result in the bus being granted unfairly to the bus master with the lowest index. cmtc 1 =1 cmtc 2 =1 cmtc 3 =1 cmtc 4 =1 cptc 1 =1 cptc 2 =1 cptc 3 =1 bus ownership idle 1 1 1 1 1 1 1 master 1 1 1 1 1 1 1 1 master 2 1 1 1 1 1 1 1 master 3 1 1 1 1 1 1 1 master 1 1 1 1 1 1 1 1 master 4 1 1 1 1 1 1 1 idle 1 1 1 1 1 1 1 master 1 1 1 1 1 1 1 1 master 2 1 1 1 1 1 1 1 master 1 1 1 1 1 1 1 1 master 2 1 1 1 1 1 1 1 master 2 1 1 1 1 1 1 1 mf=0
idt bus arbitration theory of operation 79rc32438 user reference manual 5 - 7 november 4, 2002 notes figure 5.5 ipbus arbiter conf iguration for fair arbitration figure 5.6 example operation of ip bus arbiter with fair arbitration priority arbitration with fairness a difficulty with strict prio rity arbitration, presented above, is that it can lead to starvation within a priority. for the example in figure 5.4, it is possible for master two to starve since it has a higher index than master one. if master one continuously requests the bus, master two will starve. priority arbitration with fairness within a priority eliminates this st arvation. as in the fair arbitrati on example, the mf bit in the ipap3c register must be set. this maintain s fairness across arbitration epochs. figure 5.7 shows an ipbus arbiter configuration that im plements priority arbitrat ion with fairness. owner- ship is granted to the bus master with the highest prio rity level which is requesting the bus. if multiple bus masters are requesting ownership and share the same pr iority level, then ownership is granted in a fair manner within the priority level. figure 5.7 ipbus arbiter configuration for priority arbitration with fairness priority 3 ptc 3 =1 mtc 1 =0 mtc 2 =0 mtc 3 =0 mtc 4 =0 priority 2 ptc 2 =0 priority 1 ptc 1 =0 priority 3 ptc 3 =0 mtc 1 =0 mtc 2 =0 priority 2 ptc 2 =0 mtc 3 =0 priority 1 ptc 1 =0 mtc 4 =0 cmtc 1 =0 cmtc 2 =0 cmtc 3 =0 cmtc 4 =0 cptc 1 =0 cptc 2 =0 cptc 3 =1 bus ownership idle 1 0 0 0 0 0 0 master 1 1 0 0 0 0 0 0 master 2 1 0 0 0 0 0 0 master 3 1 0 0 0 0 0 0 master 4 1 0 0 0 0 0 0 master 1 1 0 0 0 0 0 0 idle 1 0 0 0 0 0 0 master 2 1 0 0 0 0 0 0 master 1 1 0 0 0 0 0 0 master 2 1 0 0 0 0 0 0 master 1 1 0 0 0 0 0 0 master 2 1 0 0 0 0 0 0 mf=1
idt bus arbitration theory of operation 79rc32438 user reference manual 5 - 8 november 4, 2002 notes figure 5.8 example operation of ipbus arbite r with priority arbitration with fairness weighted round robin figure 5.9 shows an ipbus arbiter configuration that implements we ighted round robin. master one is allocated 33.3% of the transaction, master two is allocated 4.8%, master three is allocated 14.3%, and master four is allocated 47.6%. figure 5.9 ipbus arbiter configur ation for weighted round robin figure 5.10 example operation of ipbu s arbiter with weighted round robin priority 3 ptc 3 =21 mtc 1 =7 mtc 2 =1 mtc 3 =3 mtc 4 =10 priority 2 ptc 2 =0 priority 1 ptc 1 =0 cmtc 1 =0 cmtc 2 =0 cmtc 3 =0 cmtc 4 =0 cptc 1 =0 cptc 2 =0 cptc 3 =0 bus ownership idle 0 0 0 0 0 0 0 master 1 0 0 0 0 0 0 0 master 2 0 0 0 0 0 0 0 master 3 0 0 0 0 0 0 0 master 1 0 0 0 0 0 0 0 master 4 0 0 0 0 0 0 0 idle 0 0 0 0 0 0 0 master 2 0 0 0 0 0 0 0 master 1 0 0 0 0 0 0 0 master 2 0 0 0 0 0 0 0 master 1 0 0 0 0 0 0 0 master 2 0 0 0 0 0 0 0 mf=1 cmtc 1 =7 cmtc 2 =1 cmtc 3 =3 cmtc 4 =10 cptc 1 =21 cptc 2 =0 cptc 3 =0 bus ownership idle 0 0 21 10 3 1 7 master 1 0 0 20 10 3 1 6 master 2 0 0 19 10 3 0 6 master 3 0 0 18 10 2 0 6 master 1 0 0 17 10 2 0 5 idle 0 0 16 10 2 0 5 master 1 0 0 15 10 2 0 4 master 1 0 0 14 10 2 0 3 master 1 0 0 13 10 2 0 2 master 1 0 0 12 10 2 0 1 master 1 0 0 11 10 2 0 0 master 2 0 0 10 10 1 0 0 mf=0
idt bus arbitration ipbus registers 79rc32438 user reference manual 5 - 9 november 4, 2002 notes ipbus registers ipbus arbiter control register figure 5.11 ipbus arbiter control register (ipac) dp description: disable prefetching . when this bit is set, the ipbus arbiter disables prefetching hints passed to the ddr controller (i.e., the ddr controller will never speculatively prefetch data). initial value: 0x0 read value: previous value written write effect: modify value eep description: enable eager prefetching . when this bit is set, the ipbus arbiter enables ddr controller eager prefetching. initial value: 0x0 read value: previous value written write effect: modify value dwm description: disable write transaction merging . when this bit is set, write transaction merging is disabled for all ipbus masters. initial value: 0x0 read value: previous value written write effect: modify value drm description: disable read transaction merging . when this bit is set, read transaction merging is disabled for all ipbus masters. initial value: 0x0 read value: previous value written write effect: modify value msk description: mask bus ownership requests . when this bit is set, all bus ownership requests are masked except those from the cpu. initial value: 0x0 ipac 0 31 28 0 1 dp 1 eep 1 dwm 1 drm 1 msk
idt bus arbitration ipbus registers 79rc32438 user reference manual 5 - 10 november 4, 2002 notes ipbus arbiter priority configuration register figure 5.12 ipbus arbiter priority conf iguration [0..3] register (ipap[0..3]c) read value: previous value written write effect: modify value ptc description: priority transaction count . this field contains the transaction count for the corresponding arbi- tration priority. initial value: 0x1 read value: previous value written write effect: modify value mf description: maintain fairness . when this bit is set, the fairness bit mentioned in figure 5.2 is not cleared when the cptc for a priority reaches zero. this allows fairness to be maintained across arbitra- tion epochs. the mf bit must be set when fair arbitration or priority arbitration with fairness algorithms are desired. initial value: 0x1 read value: previous value written write effect: modify value cptc description: current priority transaction count . this field contains the current arbitration transaction count for the corresponding arbitration priority. this field is provided for status only and cannot be mod- ified by the cpu. initial value: 0x1 read value: status write effect: read-only ipap[0..3]c 0 31 14 ptc 1 0 2 0 1 mf 14 cptc
idt bus arbitration ipbus registers 79rc32438 user reference manual 5 - 11 november 4, 2002 notes ipbus arbiter bus master configuration register figure 5.13 ipbus arbiter bus master [0..1 6] configuration register (ipabm[0..16]) note: registers 10 through 12 are reserved. only use registers 0 through 9 and 13 through 16. mtc description: master transaction count . this field contains the transaction count for the corresponding bus master. initial value: 0x0 read value: previous value written write effect: modify value p description: priority . this field contains the arbitration priority for the corresponding bus master. initial value: 0x0 read value: previous value written write effect: modify value msk description: mask bus ownership requests . when this bit is set, bus ownership requests from the corre- sponding bus master are masked. cpu bus ownership requests can never be masked. initial value: 0x0 read value: previous value written write effect: modify value (read only for index 16, the cpu) cmtc description: current master transaction count . this field contains the current arbitration transaction count for the corresponding bus master. this field is provided for status only and cannot be modified by the cpu. initial value: 0x0 read value: status write effect: read-only ipabm[0..16]c 0 31 12 cmtc 4 0 12 mtc 2 p msk 1 0 1
idt bus arbitration pmbus arbitration 79rc32438 user reference manual 5 - 12 november 4, 2002 notes ipbus idle transaction cycle count register figure 5.14 ipbus idle transacti on cycle count register (ipaitcc) pmbus arbitration since the pmbus and ddr controller operate at twice the ipbus clock rate, they have twice the avail- able bandwidth. the goal of pmbus arbi tration is to utilize this spare bus bandwidth for cpu transactions to ddr without adversely affecting ipbus performance. since there are buffers associated with the ipbus master bus bridge that links the ipbus to the pmbus, it is possible for the ipbus to be active while the pmbus is idle. ipbus idle if the pmbus and ipbus are idle, then the cpu is grant ed access to memory without delay (i.e., nothing to arbitrate). ipbus active if the ipbus is active and the cpu has hi gher priority than the current or pending 1 ipbus transaction, then the cpu is granted ownership of the pmbus and the ipbus transaction is delayed. if the ipbus is active and the cpu priority is equal to that of the current or pending ipbus transaction, then access to the pmbus is granted in a fair manner (i.e., access alternates between an ipbus transaction and the cpu). sneak transactions (see next section) have no effect on fa ir access (i.e., they are ignored by the arbiter). if the ipbus is active and the cpu priority is less than that of the current or pending ipbus transaction, then access to the pmbus is granted to the ipbus transaction and the cpu is delayed. sneak transactions due to buffering between the ipbus and pmbus, it is possible for the pmbus to be idle while a transac- tion is in progress on the ipbus. s neak transactions allow the cpu to ut ilize otherwise idle pmbus cycles to perform accesses to ddr. sneak tr ansactions are never allowed to devices on the memory and peripheral bus since sneak transactions may delay the completion of an ipbus transaction. control is provided to allow sneak transactions to be disabled. the pmbus arbiter sneak access control (pmasac) register has a sneak transaction enable bit associated with each of the four ipbus priorities. the ipbus sneak priority is equal to the highest va lue of any current or pendi ng ipbus transaction. for a sneak transaction to take place, the sneak transact ion enable bit associated with the ipbus sneak priority must be set in the pmasac register. sneak transacti ons do not count toward fair access to the pmbus. itcc description: idle transaction cycle count . this field contains the number of clock cycles the ipbus must be idle before it is viewed as an idle transaction. see figure 5.2. initial value: 0x10 read value: previous value written write effect: modify value 1. when an ipbus master requests the ipbus, a transaction is considered to be pending since eventually the ipbus will be granted to the master. ipaitcc 0 31 23 0 9 itcc
idt bus arbitration pmbus registers 79rc32438 user reference manual 5 - 13 november 4, 2002 notes bus parking when the pmbus is idle, it is normally parked on the cpu in order to minimize cpu memory access latency. when the park on ipbus (poi) bit is set in the pmbus arbiter sneak access control (pmasac) register, then the pmbus is parked on the ipbus when it is idle. this minimizes ipbus master memory access latency rather than cpu latency. pmbus registers pmbus arbiter processor priority register figure 5.15 pmbus arbiter process or priority register (pmapp) pmbus arbiter sneak access control register figure 5.16 pmbus arbiter sneak access control register (pmasac) p description: processor priority . this two bit field contains the cpu priority used for pmbus arbitration. unlike the priority in the ipabm16c register whic h is used for cpu access es to the ipbus, this priority is used for access to ddr or devices on the memory and peripheral bus. initial value: 0x0 read value: previous value written write effect: modify value p0 description: priority 0 sneak transaction enable . when this bit is set, the cpu may be granted access to the pmbus during otherwise idle cycles while a priority 0 master is granted ownership of the ipbus or ownership is pending to a priority 0 master. initial value: 0x0 read value: previous value written write effect: modify value p1 description: priority 1 sneak access enable . when this bit is set, the cpu may be granted access to the pmbus during otherwise idle cycles while a priority 1 master is granted ownership of the ipbus or ownership is pending to a priority 1 master. initial value: 0x0 pmapp 0 31 2 p 30 0 pmasac 0 31 1 p1 27 0 1 p2 1 p3 1 p0 1 poi
idt bus arbitration memory and peripheral bus arbitration 79rc32438 user reference manual 5 - 14 november 4, 2002 notes memory and peripheral bus arbitration the rc32438 allows external bus masters on the me mory and peripheral bus. an external bus master asserts the bus request (brn) input to the rc32438 to request ownership of the memory and peripheral bus. 1 the rc32438 responds to the assertion of brn by relinquishing ownership of the memory and peripheral bus by asserting bus grant (bgn) and simultaneously tri-stating 2 the following signals: maddr[25:0], mdata[15:0], bwen[1:0], oen, rwn, csn[5:0], boen, bdirn. read value: previous value written write effect: modify value p2 description: priority 2 sneak transaction enable . when this bit is set, the cpu may be granted access to the pmbus during otherwise idle cycles while a priority 2 master is granted ownership of the ipbus or ownership is pending to a priority 2 master. initial value: 0x0 read value: previous value written write effect: modify value p3 description: priority 3 sneak transaction enable . when this bit is set, the cpu may be granted access to the pmbus during otherwise idle cycles while a priority 3 master is granted ownership of the ipbus or ownership is pending to a priority 3 master. initial value: 0x0 read value: previous value written write effect: modify value poi description: park on ipbus . when the pmbus is idle, it is normally parked on the cpu. when the pmbus is idle and this bit is set, the pmbus is parked on the ipbus. initial value: 0x0 read value: previous value written write effect: modify value 1. once an external bus master has requested the bus by asserting brn, it must keep brn asserted until it is granted the bus (i.e., it observes bgn asserted). 2. csn[5:0] and boen shall have been in their negated state for at least one extclk clock cycle before being tri- stated. this is true when both the rc32438 or the external bus master relinquish ownership.
idt bus arbitration memory and peripheral bus arbitration 79rc32438 user reference manual 5 - 15 november 4, 2002 notes when the external bus master observes bgn assert ed, it owns the memory and peripheral bus and may drive the above signals. the external bus master mainta ins brn asserted during the entire time it owns the memory and peripheral bus. it reli nquishes ownership by negating brn 1 and tri-stating the above memory and peripheral bus signals. the rc 32438 acknowledges that external ow nership of the bus has been relin- quished by negating bgn 2 , and it begins driving the memory and per ipheral bus signals. this process is illustrated in figure 5.17. the rc32438 may request that an external bus master relinquish ownership of the memory and periph- eral bus early, for example due to a higher priority internal pending transaction, by negating bgn while brn is asserted. when the external bus master observes this, it relinquishes ownership by negating brn and tri- stating the memory and peripheral bus signals. the rc32438 regains ownership and may drive the memory and peripheral bus signals when it observes brn negated. this process is illustrated in figure 7.17. since brn is an asynchronous input to the rc32438, which is double sampled, it must be negated for at least three extclk cloc k cycles before being asserted. when the rc32438 owns the memory and peripheral bus and there are no device controller transac- tions in progress, the rc32438 may drive or tri-state the data bus (mdata[15:0]). figure 5.17 external bus arbitration figure 5.18 external bus arbitration with rc 32438 requesting that ownership be relinquished 1. once an external bus master has relinquished ownership of the bus by negating brn, it should not assert brn until the rc32438 acknowledges the negation of brn by negating bgn. 2. it is guaranteed that the rc32438 will assert bgn for no less than three extclk clock cycles. extclk brn bgn ownership 1 4 5 2 3 rc32438 owns bus rc32438 owns bus external bus master owns bus 1. external bus master requests ownership of memory and peripheral bus by asserting brn. 2. the rc32438 tri-states memory and peripheral bus signals and assert s bgn to indicate that it has relinquished ownership of th e bus. 3. when the external bus master observes bgn assert ed, it drives memory and peripheral bus signals. 4. external bus master relinquishes ownership of memory and peripheral bus by negating brn. 5. the rc32438 acknowledges ownership and begins driving memory and peripheral bus signals. extclk brn bgn ownership 1 5 6 2 3 rc32438 owns bus rc32438 owns bus external bus master owns bus 4 1. external bus master requests ownership of memory and peripheral bus by asserting brn. 2. the rc32438 tri-states memory and peripheral bus signals and assert s bgn to indicate that it has relinquished ownership of th e bus. 3. when the external bus master observes bgn asse rted, it drives memory and peripheral bus signals. 4. the rc32438 requests that the external bus master relinquish ownership of the memory and peripheral bus by negating bgn 5. the external bus master relinqui shes ownership of the memory and peripheral bus by negating brn. 6. the rc32438 observes that ownership of the bus has b een relinquished and begins driving memory and peripheral bus signals.
idt bus arbitration memory and peripheral bus arbitration 79rc32438 user reference manual 5 - 16 november 4, 2002 notes
notes 79rc32438 user reference manual 6 - 1 november 4, 2002 chapter 6 device controller introduction the device controller on the rc32438 device provides a glueless inte rface to: srams, roms/proms/ eeproms, dual port memories, and many peripheral devices. the device c ontroller generates all of the signals required to support both intel and motorola st yle peripherals and can directly control up to six devices. additional devices may be supported th rough external decoding of the address bus. features ? provides ?glueless? interface to standard sram , flash, rom, dual-por t memory, and peripheral devices ? demultiplexed address and data buses ? 16-bit data bus ? 26-bit address bus ? 6 chip selects ? supports alternate bus masters ? control for external data bus buffers ? supports 8-bit and 16-bit width devices ? automatic byte gathering and scattering ? flexible protocol configuration parameters ? programmable number of wait states (0 to 63) ? programmable postread/postwrite delay (0 to 31) ? supports external wait state generation ? supports intel and motorola style peripherals ? write protect capability per chip select ? programmable bus transacti on timer generates warm reset when counter expires ? supports up to 64 mb of memory per chip select ? provides clocking for external dev ices on the memory and peripheral bus device controller register description register offset 1 register name register function size 0x01_0000 dev0base device 0 base 32-bit 0x01_0004 dev0mask device 0 mask 32-bit 0x01_0008 dev0c device 0 control 32-bit 0x01_000c dev0tc device 0 timing control 32-bit 0x01_0010 dev1base device 1 base 32-bit 0x01_0014 dev1mask device 1 mask 32-bit 0x01_0018 dev1c device 1 control 32-bit 0x01_001c dev1tc device 1 timing control 32-bit 0x01_0020 dev2base device 2 base 32-bit table 6.1 device controller register map
idt device controller theory of operation 79rc32438 user reference manual 6 - 2 november 4, 2002 notes theory of operation the following memory and peripher al bus signals are managed by the device controller during device transactions: ? maddr[25:0] (address bus, maddr[21:0] directly available as i/o pins, maddr[25:22] are gpio alternate functions) ? mdata[15:0] (data bus) ? oen (output enable, may be used as intel style read signal) ? bwen[1:0] (byte write enables, may be used as intel style write signals) ? rwn (motorola style read/write signal) ? csn[5:0] (chip selects) ? waitackn (configurable as intel style wait signal or motorola style transfer acknowledge signal) ? boen (external data bus buffer output enable) ? bdirn (external data bus buffer direction). all memory and peripheral bus trans actions are synchronous to the ma ster clock (extclk). therefore, all of the timing parameters in the device control (devxc) and device timing c ontrol (devxtc) registers are in terms of master clock (extclk) clock cycles. 0x01_0024 dev2mask device 2 mask 32-bit 0x01_0028 dev2c device 2 control 32-bit 0x01_002c dev2tc device 2 timing control 32-bit 0x01_0030 dev3base device 3 base 32-bit 0x01_0034 dev3mask device 3 mask 32-bit 0x01_0038 dev3c device 3 control 32-bit 0x01_003c dev3tc device 3 timing control 32-bit 0x01_0040 dev4base device 4 base 32-bit 0x01_0044 dev4mask device 4 mask 32-bit 0x01_0048 dev4c device 4 control 32-bit 0x01_004c dev4tc device 4 timing control 32-bit 0x01_0050 dev5base device 5 base 32-bit 0x01_0054 dev5mask device 5 mask 32-bit 0x01_0058 dev5c device 5 control 32-bit 0x01_005c dev5tc device 5 timing control 32-bit 0x01_0060 btcs bus timer control and status 32-bit 0x01_0064 btcompare bus transaction timer compare 32-bit 0x01_0068 btaddr bus transaction timer address 32-bit 0x01_006c devdacs device decoupled access control and status 32-bit 0x01_0070 devdaa device decoupled access address 32-bit 0x01_0074 devdad device decoupled access data 32-bit 0x01_0078 through 0x01_7fff reserved 1. the address of the register is equal to the regi ster offset added to the base value of 0x1800_0000. register offset 1 register name register function size table 6.1 device controller register map
idt device controller theory of operation 79rc32438 user reference manual 6 - 3 november 4, 2002 notes the endianess of the rc32438 is selected during boot configuration. regardless of the selected endi- aness, devices are connected to the rc32438 data bus in a right aligned manner, as shown in figure 6.1. 8-bit device data is read and written on mdata[7: 0] and 16-bit device data is read and written on mdata[15:0]. figure 6.1 connecting devices to the rc32438 data bus (right aligned) the width of a device, 8-bits or 16- bits, is configured in the device si ze (ds) field of the device [0..5] control register (dev[0..5]c). the rc32438 perform s byte gathering during read transactions and byte scattering during write transactions, allowing word and half-word read and write operations to any size device. the rc32438?s address bus is always driven with a byte address. 8-bit devices use maddr[25:0], and 16-bit devices use maddr[25:1]. during write trans actions to 16-bit, the byte write enable (bwen[1:0]) signals are used to select byte lanes to be written. the rc32438 supports four transacti on types: a device read transaction, a burst device read transac- tion, a device write transaction, and a burst devic e write transaction. trans action parameters for each device are programmed in the corresponding device [0 ..5] control register (dev[0..5]c) and device [0..5] timing control (dev[0..5]tc) register. in particular, the wait/ack mode (wam) bit in the devxc register controls whether the waitackn si gnal operates as an intel style wait signal or as a motorola style acknowledge signal. although waitackn is classified as an asynchronous input, to support systems that use master clock to generate it, asynchronous input setup and hold times are provided. if the setup and hold times are met for the assertion of waitackn, then the rc32438 is guaran teed to recognize it on a specific rising edge of the clock. by configuring the programmable parameters in the devxc and devxtc registers, intel and motorola style bus transactions may be generated. burst read transactions to devices which do not support burst reads may be disabled by clearing the burst read enable (bre) bit in the corresponding devxc register. burst write transactions to devices which do not suppor t burst writes may be disabled by clearing the burst write enable (bwe) bit in the corresponding devxc regi ster. all writes to a device may be disabled by setting the write protect (wp) bit in the corresponding devxc register. address decoding for each device chip select is c ontrolled by the device [0..5] base (dev[0..5]base) and device [0..5] mask (dev[0..5]mask) registers. the device mask regist er is used to select which bits are used for address decoding. when a bit in this regi ster is a one, the corres ponding address bit is active in address comparisons. if a bit in this register is a zero, then the correspondi ng address bit does not partic- ipate in address comparisons. all of the active addre ss bits not masked by the device mask register are compared to the value in the device base register. if they all match, then the corresponding device chip select is asserted. the device controller provides t he control signals necessary to c ontrol external buffers, such as 74fct245s, on the data bus (mdata[15:0]). the buffe r output enable (boen) pin is the enable for such buffers, while the external buffer direction (bdirn) pin controls the direction. during device transactions, the bdirn output is always in the opposite state of the rwn pin. the boen output is asserted during device transactions if the buffer enable (b e) bit is set in the devxc register. bit 0 0 1 bit 15 16-bit device bit 0 0 bit 7 8-bit device big endian bit 0 1 0 bit 15 16-bit device bit 0 0 bit 7 8-bit device little endian
idt device controller theory of operation 79rc32438 user reference manual 6 - 4 november 4, 2002 notes device zero is the boot device and contains the boot exception vector. since read operations to this device must take place before software can initiali ze the system, the dev0c and dev0tc registers must have default values that allow the boot device to be read following a cold reset. init ial values for the devxc and devxtc registers for all devic es are summarized in table 6.2. these values may be modified during system initialization. the rc32438 only reads data from a memory and peripher al bus device that is actually requested by the cpu or external dma. for these transactions , the rc32438 never ?reads pas t? the ending address of a transaction. for example, if the cpu reads a byte from a memory and peripheral bus address, only that byte is actually read from memory. note: this is not true for pci masters and gener al dma operations; data may be read past the ending address of a transaction. table 6.2 shows the default values fo r the device configuration registers. register field initial value description/comment devxc ds boot configuration device size . boot configuration vector (refer to the boot configuration vector section in chapter 3). be 0x1 buffer enable. initial value places the boot device on buffered data bus. wp 0x1 write protect. initial value disables writes to the boot device. bre 0x0 burst read enable. burst reads are disabled from the boot device. bwe 0x0 burst write enable. burst writes are disabled to the boot device. rws 0x3f read wait states. initially configured for maximum number of wait states. wws 0x3f write wait states. initially configured for maximum number of wait states. wam 0x0 wait/ack mode. initially configured for wait mode. csd 0xf chip select delay. initially configured for maximum delay. oed 0xf output enable delay. initially configured for maximum delay. bwd 0xf byte write enable delay. initially configured for maximum delay. devxtc prd 0xf postread delay. initially configured for maximum delay. pwd 0xf postwrite delay. initially configured for maximum delay. wdh 0x7 write data hold. initially configured for maximum delay. csh 0x3 chip select hold. initially configured for maximum delay. table 6.2 default values for device configuration registers
idt device controller device control registers 79rc32438 user reference manual 6 - 5 november 4, 2002 notes device control registers device [0..5] base register figure 6.2 device [0..5] base register (dev[0..5]base) device [0..5] mask register figure 6.3 device [0..5] mask register (dev[0..5]mask) baseaddr description: base address. this field specifies the upper 16-bits of the device space base address. initial value: 0x0 (device 0 has an initial value of 0x1c00) read value: previous value written write effect: modify value mask description: address mask. this field determines which bits of the upper 16-bits of the address participate in address comparisons. when a bit is set in this field, then the corresponding address bit partici- pates in address comparisons. when a bit is cleared in this field, then the corresponding address bit is masked and does not participate in address comparisons. when the mask field is zero, the device is di sabled and does not appear in the memory map. initial value: 0x0 (device 0 has an initial value of 0xfc00) read value: previous value written write effect: modify value dev[0..5]base 0 31 16 16 baseaddr 0 dev[0..5]mask 0 31 16 16 mask 0
idt device controller device control registers 79rc32438 user reference manual 6 - 6 november 4, 2002 notes device [0..5] control register figure 6.4 device [0..5] control register (dev[0..5]c) ds description: device size. this field specifies the data path width of the device. 0 8-bit device 1 16-bit device 2 reserved 3 reserved initial value: boot configuration parameter (refer to the boot configuration vector section in chapter 3). read value: previous value written write effect: modify value be description: buffer enable. when this bit is set, accesses to the device cause the boen signal to be asserted during device transactions. initial value: 0x1 read value: previous value written write effect: modify value wp description: write protect. when this bit is set, writes to the device are disabled. 0 writes to the device are enabled 1 writes to the device are disabled initial value: 0x1 read value: previous value written write effect: modify value csd description: chip select delay. this field contains the delay in clock cycles by which the assertion of chip select (csnx) is delayed from the start of a transaction. programming this value to be greater than or equal to rws or wws causes csnx not be asserted in the transaction. initial value: 0xf read value: previous value written write effect: modify value dev[0..5]c 16 31 rws 6 0 15 2 ds 1 be 4 csd 1 wp 1 bre 1 bwe 1 wam wws 6 4 oed 4 bwd 1 0
idt device controller device control registers 79rc32438 user reference manual 6 - 7 november 4, 2002 notes oed description: output enable delay. this field contains the delay in clock cycles by which the assertion of out- put enable (oen) is delayed from the start of a read transaction. programming this value to be greater than or equal to rws causes oen not be asserted in the transaction. initial value: 0xf read value: previous value written write effect: modify value bwd description: byte write enable delay. this field contains the delay in clock cycles by which the assertion of the byte write enable signals (bwen[1:0]) are delaye d from the start of a write transaction. pro- gramming this value to be greater than or equal to wws causes bwen[1:0] not be asserted in the transaction. initial value: 0xf read value: previous value written write effect: modify value rws description: read wait states. this field specifies the number of wait states during device read transactions. a value of zero in this field is treated as an rws value of one. initial value: 0x3f read value: previous value written write effect: modify value wws description: write wait states. this field specifies the number of wait states during device write transac- tions. a value of zero in this field is treated as a wws value of one. the wws field must be initialized to a value greater than one if the device is configured to sup- port burst device write transactions and waitackn is configured as a wait input which may be asserted during the transaction. initial value: 0x3f read value: previous value written write effect: modify value bre description: burst read enable. when this bit is set, the device controller performs burst device read trans- actions whenever possible. when this bit is cleared, burst device read transactions are never generated to the device. initial value: 0x0 read value: previous value written write effect: modify value
idt device controller device control registers 79rc32438 user reference manual 6 - 8 november 4, 2002 notes device [0..5] timing control register figure 6.5 device [0..5] timing control register (dev[0..5]tc) bwe description: burst write enable. when this bit is set, the device controller performs burst device write trans- actions whenever possible. when this bit is cleared, burst device write transactions are never generated to the device. initial value: 0x0 read value: previous value written write effect: modify value wam description: wait/ack mode. this bit controls the operation of the waitackn signal. when this bit is a one, the waitackn signal operates as a motorola style active low transfer acknowledge signal. when this bit is a zero, the waitackn signal operates as an intel style active low wait signal. initial value: 0x0 read value: previous value written write effect: modify value prd description: postread delay. this field contains the delay, in clock cycles, from when the rc32438 clocks in data from the data bus during a device read transaction until the start of a new transaction. pro- gramming this value to zero results in a postread delay of one clock cycle. if prd or pwd is equal or less than csh, chip select may remain asserted between transactions to the same device (i.e., back-to-back transactions). initial value: 0xf read value: previous value written write effect: modify value pwd description: postwrite delay. this field contains the delay, in clock cycles, from when the rc32438 negates the byte write enable signals during a device write transaction until the start of a new transaction. programming this value to zero results in a postread delay of one clock cycle. if prd or pwd is equal or less than csh, chip select may remain asserted between transactions to the same device (i.e., back-to-back transactions). if pwd is equal or less than wdh and bwd is zero, the byte write enable signals may remain asserted between write transactions to the same device (i.e., back-to-back write transactions). initial value: 0xf read value: previous value written write effect: modify value dev[0..5]tc 0 31 19 0 4 prd 4 pwd 3 wdh 2 csh
idt device controller memory and peripheral bus transaction timer 79rc32438 user reference manual 6 - 9 november 4, 2002 notes memory and peripheral bus transaction timer when enabled, the memory and peripheral bus transac tion timer times all the memory and peripheral bus transactions. the memory and per ipheral bus transaction timer is enabled by setting the bus transac- tion timer enable (bte) bit in the btcs register. at the start of each memory and peripheral bus transaction in which the bus transaction timer is enabled, an internal 16-bit counter is initialized to zero. the counter increments with each passing external clock (extclk) clock cycle until t he bus transaction completes. if the c ounter value ever exceeds the value in the compare (compare) field in the bus timer compare (btcompare) register, then a bus transac- tion timer time-out occurs. when the bus transaction timer times- out, the following actions occur: ? the bus transaction timer time out (bto) bit in the btcs register is set ? the address of the transaction which caused the time out is recorded in the bus transaction timer address (btaddr) register ? the type of bus transaction (i.e., read or write) is recorded in the tr ansaction type (tt) field of the btcs register ? a warm reset is generated ? compare field is initialized to 0xff ff and the bus transac tion timer is enabled. only devices on the memory and peripheral bus with an intel style wait signal or motorola style transfer acknowledge signal can cause the bus transaction timer to time out. wdh description: write data hold. this field contains the delay, in clock cycles, from when the rc32438 negates the byte write enable signals during a device write transaction until the buffer output enable (boen) is negated and the data bus (mdata[15:0]) is tri-stated. buffer output enable is negated and the data bus is tri-stated when pwd expires regardless of the value of this field. initial value: 0x7 read value: previous value written write effect: modify value csh description: chip select hold. this field contains the delay, in clock cycles, from when the rc32438 negates the byte write enable signals during a device write transaction or when output enable is negated during a device read transaction until the chip select signal is negated. chip select is negated when prd/pwd expires regardless of the value of this field. initial value: 0x3 read value: previous value written write effect: modify value
idt device controller memory and peripheral bus transaction timer 79rc32438 user reference manual 6 - 10 november 4, 2002 notes bus transaction timer control and status register figure 6.6 bus timer control and status register (btcs) bus transaction timer compare register figure 6.7 bus transaction timer compare register (btcompare) tt description: transaction type. this bit records the transaction type (read or write) of the first transaction in which the bus transaction timer timed-out. 0 write transaction 1 read transaction initial value: undefined (this field is not modified due to a warm reset) read value: current value write effect: modify value bto description: bus transaction timer time-out. when the bus transaction timer times-out, this bit is set. initial value: 0x0 read value: status (this field is not modified due to a warm reset) write effect: sticky bit 1 1. a sticky bit is set by the hardware and can only be cleared by the cpu. bte description: bus transaction timer enable. when this bit is set, the bus transaction timer is enabled. when the bus transaction timer is enabled all memory and peripheral bus transactions are timed. initial value: 0x1 (this field is not modified due to a warm reset) read value: previous value written write effect: modify value btcs 0 31 29 0 1 tt 1 bto 1 bte btcompare 0 31 16 16 0compare
idt device controller device read transaction 79rc32438 user reference manual 6 - 11 november 4, 2002 notes bus transaction timer address register figure 6.8 bus transaction time r address register (btaddr) device read transaction this section describes the device read transaction. the transaction in volves five programmable timing parameters: ? chip select delay ( csd ). csd may be programmed to be any value between 0 and 15 clock cycles. ? output enable delay ( oed ). oed may be programmed to be any value between 0 and 15 clock cycles. ? read wait states ( rws ). rws may be programmed to be any value between 1 and 63 clock cycles. ? postread delay ( prd ). prd may be programmed to be any value between 0 and 15 clock cycles. ? chip select hold delay ( csh ). csh may be programmed to be any value between 0 and 3 clock cycles. compare description: bus transaction timer compare value. this field contains the maximum bus transaction timer count value in the external clock (extclk) clock cycles. if a bus transaction exceeds this num- ber of clock cycles then the bus transaction timer times-out. initial value: 0xffff read value: previous value written write effect: modify value addr description: address. this field contains the physical address of the transaction in which the bus transaction timer time out occurred. initial value: undefined (this field is not modified due to a warm reset) read value: current value write effect: read-only btaddr 0 31 32 addr
idt device controller device read transaction 79rc32438 user reference manual 6 - 12 november 4, 2002 notes figure 6.9 generic device read transaction 1 the device read transaction, with wait ackn configured as a wait inpu t, consists of the following steps. 1. the rc32438 drives the address bus (maddr[25: 0]), drives rwn high and bdirn low, and asserts boen 2 on the rising edge of extclk. this indicates the start of a transaction. 2. csd clock cycles after step one, the rc32438 asserts the appropriate chip select (csnx). 3. oed clock cycles after step one, the rc32438 asserts output enable (oen). 4. if waitackn is not asserted during the transaction, then rws clock cycles after step one the rc32438 clocks in the data from the data bus (mdata[15:0]), negates oen and boen. if waitackn is asserted during the transaction, then the rws field is ignored from that point on. the rc32438 clocks in the data on the data bus (mdata[15:0]), negates oen and boen one clock cycle after it samples waitackn negated. 5. csh clock cycles after step four, the rc32438 negates chip select. 6. prd clock cycles after step four, the rc 32438 may modify the address on the address bus (maddr[25:0]) and may begin a new transaction (the postread delay provides time for slow devices to get off the bus before issuing another transaction). figure 6.10 illustrates the effect of asserting the wait ackn signal when it is conf igured as a wait signal. in this transaction, even though rws + prd was programed for eight clock cycles the transaction completes in seven clock cycles. this is because waitackn was asserted during the third clock cycle in the transaction and was negated during the fourth clo ck cycle. this caused the rc32438 to clock in the data on the fifth clock cycle and terminate the transaction early. the trans action could have been extended beyond eight clock cycles by holding wait ackn asserted for several clock cycles. 1. the programmable parameters shown in this figure ar e for illustrative purposes only and may be varied. 2. boen is only asserted if the buffer enable (be) bit is set in the device control register (devxc). extclk maddr[25:0] rwn csnx bwen[1:0] oen mdata[15:0] transaction csd oed rws prd csh address valid data valid transaction boen waitackn
idt device controller device read transaction 79rc32438 user reference manual 6 - 13 november 4, 2002 notes when configured as a wait signal, waitackn must be asserted at least two clock cycles prior to the end of rws. waitackn assertions after th is point are ignored. thus, to use waitackn in this mode rws must have a value greater than or equal to three. figure 6.10 device read transaction 1 (waitackn configured as wait) the waitackn signal may be configured as an intel st yle wait signal or as a motorola style transfer acknowledge signal. up to this point, this section has only considered waitackn configured as a wait signal. when waitackn is configured as transfe r acknowledge, then the read wait states ( rws ) value is ignored and the assertion of waitackn signals the completion of the transaction. figure 6.11 device read transaction 1 (waitackn configured as transfer acknowledge) the device read transaction, with waitackn confi gured as a transfer acknowledge input, consists of the following steps. 1. the rc32438 drives the address bus (maddr[25: 0]), drives rwn high and bdirn low, and asserts boen 2 on the rising edge of extclk. this indicates the start of a transaction. 2. csd clock cycles after step one, the rc32438 asserts the appropriate chip select (csnx). 3. oed clock cycles after step one, the rc32438 asserts output enable (oen). 4. the external device asserts waitackn once it has driven valid data onto the data bus and is ready for the transaction to complete. 1. the programmable parameters shown in this figure ar e for illustrative purposes only and may be varied. 2. boen is only asserted if the buffer enable (be) bit is set in the device control register (devxc). extclk maddr[25:0] rwn csnx bwen[1:0] oen mdata[15:0] transaction csd oed rws csh address valid data valid transaction prd boen waitackn extclk maddr[25:0] rwn csnx bwen[1:0] oen mdata[15:0] transaction csd oed prd csh address valid data valid transaction boen waitackn
idt device controller burst device read transaction 79rc32438 user reference manual 6 - 14 november 4, 2002 notes 5. one clock cycle after the rc32438 samples waitac kn asserted, it clocks in the data on the data bus (mdata[15:0]), and negates oen and boen. 6. csh clock cycles after step five, the rc32438 negates csnx. 7. when the external device observes that csnx is negated, it tri-states the data bus and negates waitackn. 8. prd clock cycles after step five, the rc 32438 may modify the address on the address bus (maddr[25:0]) and may begin a new transaction (the postread delay provides time for slow devices to get off the bus before issuing another transaction). burst device read transaction the burst device read transaction is enabled by setting the burst read enable bit (bre) in the device control register. when this bit is set, consecutive r ead transactions to the same device, such as during cache refills and dma operations, may be performed in a back-to-back manner as shown in figure 6.12. burst device read transactions do not support wait ackn configured as a tr ansfer acknowledge input. regardless of the state of wam in the devxc regist er, wait mode is selected. when configured as a wait signal, waitackn must be asserted at least two cloc k cycles prior to the end of rws. waitackn asser- tions after this point are ignored. thus, to use wa itackn in this mode rws must have a value greater than or equal to three. during burst device read transactions the csnx, oen, and boen signals remain asserted between read operations. the postread delay is inserted only after the last read operation in the transaction. all programmable parameters are exactly the same as in a device r ead transaction descri bed in ?device read transaction? on page 6-11. a burst dev ice read transaction may consist of two or more read operations. the rc32438 provides no indication as to the number of read operations in the transaction. figure 6.12 generic burst device read transaction 1 the burst device read transaction co nsists of the following steps. 1. the rc32438 drives the address bus (maddr[25: 0]), drives rwn high and bdirn low, and asserts boen 2 on the rising edge of extclk. this indicates the start of a transaction. 2. csd clock cycles after step one, the rc32438 asserts the appropriate chip select (csnx). 3. oed clock cycles after step one, the rc32438 asserts output enable (oen). 4. if waitackn is not asserted during the transac tion, then rws clock cycles after step one the rc32438 clocks in the data from the data bus (mdata[15:0]) and modifies the address on the address bus (maddr[25:0]). if waitackn is asserted during the transaction, t hen the rws field is ignored from that point until 1. the programmable parameters shown in this figure ar e for illustrative purposes only and may be varied. 2. boen is only asserted if the buffer enable (be) bit is set in the device control register (devxc). extclk maddr[25:0] rwn csnx bwen[1:0] oen mdata[15:0] transaction csd rws prd csh address valid data 1 transaction oed rws data 2 rws data 3 rws data 4 address valid address valid address valid boen waitackn
idt device controller device write transaction 79rc32438 user reference manual 6 - 15 november 4, 2002 notes waitackn is negated. the rc32438 clocks in the data on the data bus (mdata[15:0]) and modi- fies the address on the address bus (maddr[25:0]) in the clock cycle after it samples waitackn negated. 5. after rws clock cycles, if waitackn is not asserted during the transaction, the rc32438 clocks in the data from the data bus (mdata[15:0]) and if this is not the last read oper ation in the transaction, it modifies the address on t he address bus (maddr[25:0]). if waitackn is asserted during any point during t he read operation, the rws field is ignored from that point until waitackn is negated. if this is no t the last read operation in the transaction, then in the clock cycle after the rc32438 samples waitac kn negated it clocks in the data on the data bus (mdata[15:0]) and modifies the addres s on the address bus (maddr[25:0]). 6. if there are more read operations in the bur st device read transaction, go to step five. 7. csh clock cycles after step five , the rc32438 negates chip select. 8. prd clock cycles after step five, the rc 32438 may modify the address on the address bus (maddr[25:0]) and may begin a new transaction (the postread delay provides time for slow devices to get off the bus before issuing another transaction). figure 6.13 illustrates the effect of asserting the wa itackn signal when it is c onfigured as a wait signal in a burst device read transaction. the transaction in this example had rws programmed as three clock cycles and consists of two read oper ations. the first read operation comp leted in three clock cycles, as programmed. the assertion of waitackn during t he second read operations extends the operations to four clock cycles. figure 6.13 burst device read transaction 1 device write transaction this section describes the device write transaction. the transaction involves six programmable timing parameters: ? chip select delay ( csd ). csd may be programmed to be any value between 0 and 15 clock cycles. ? byte write enable delay ( bwd ). bwd may be programmed to be any value between 0 and 15 clock cycles. ? write wait states ( wws ). wws may be programmed to be any value between 1 and 63 clock cycles. ? postwrite delay ( pwd ). pwd may be programmed to be any value between 0 and 15 clock cycles. ? chip select hold delay ( csh ). csh may be programmed to be any value between 0 and 3 clock cycles. ? write data hold delay ( wdh ). wdh may be programmed to be any value between 0 and 7 clock cycles. 1. the programmable parameters shown in this figure ar e for illustrative purposes only and may be varied. extclk maddr[25:0] rwn csnx bwen[1:0] oen mdata[15:0] boen transaction csd prd csh address valid transaction oed data 1 data 2 address valid waitackn rws
idt device controller device write transaction 79rc32438 user reference manual 6 - 16 november 4, 2002 notes figure 6.14 generic device write transaction 1 the device write transaction, with wa itackn configured as a wait inpu t, consists of the following steps. 1. the rc32438 drives the address bus (maddr[25: 0]), drives rwn low and bdirn high, asserts boen 1 , and drives the data to be written on the data bus (mdata[15:0]) on the rising edge of extclk. this indicates the start of a transaction. 2. csd clock cycles after step one, the rc32438 asserts the appropriate chip select (csnx). 3. bwd clock cycles after step one, the rc32438 asserts the appropriate byte write enables (bwen[1:0]). 4. if waitackn is not asserted during the trans action, the wws clock cycles after step one the rc32438 negates all byte write enables (bwen[1:0]). if waitackn is asserted during the transaction, t he wws field is ignored from that point on. the rc32438 negates all byte write enables in the cl ock cycle after it samples waitackn negated. 5. csh clock cycles after step four, the rc32438 negates chip select. 6. wdh clock cycles after step four, the rc32438 negates boen and tri-states the data bus (mdata[15:0]). 7. pwd clock cycles after step four, the rc 32438 may modify the address on the address bus (maddr[25:0]) and may begin a new transaction. when configured as a wait signal, waitackn must be asserted at least two clock cycles prior to the end of wws. waitackn assertions after this point are ignored. thus, to use waitackn in this mode, wws must have a value greater than or equal to three. the device write transaction, with waitackn c onfigured as a transfer acknowledge input, consists of the following steps. 1. the rc32438 drives the address bus (maddr[25: 0]), drives rwn low and bdirn high, asserts boen 1 , and drives the data to be written on the data bus (mdata[15:0]) on the rising edge of extclk. this indicates the start of a transaction. 2. csd clock cycles after step one, the rc32438 asserts the appropriate chip select (csnx). 3. bwd clock cycles after step one, the rc32438 asserts the appropriate byte write enables (bwen[1:0]). 4. the external device asserts waitackn once it has captured the data on the data bus and is ready for the transaction to complete. 5. csh clock cycles after the rc32438 samples wa itackn asserted, the rc32438 negates csnx. 6. when the external device observes that csnx is negated, it negates waitackn. 7. wdh clock cycles after the rc32438 samples waitackn asserted, the rc32438 negates boen. 8. pwd clock cycles after the rc32438 samples waitac kn asserted, it tri-states the data bus (mdata[15:0]), may modify the address on t he address bus (maddr[25:0]), and may begin a new transaction. 1. boen is only asserted if the buffer enable (be) bit is set in the device control register (devxc). extclk maddr[25:0] rwn csnx bwen[1:0] oen mdata[15:0] transaction csd wws pwd csh address valid transaction data valid wdh bwd boen waitackn
idt device controller burst device write transaction 79rc32438 user reference manual 6 - 17 november 4, 2002 notes burst device write transaction the burst device write transaction is enabled by setting the burst writ e enable bit (bwe) in the device control register. when this bit is set, consecutive wr ite transactions to the same device, such as occur during dma operations, may be performed in a back-to- back manner. burst device write transactions do not support waitackn configured as a transfer acknow ledge input. when configured as a wait signal, wait- ackn must be asserted at least tw o clock cycles prior to the end of wws. waitackn assertions after this point are ignored. thus, to use waitackn in this mode, wws must have a value greater than or equal to three. during burst device write transactions csnx, appropriate bwen[1:0], and boen signals remain asserted between write operations. the postwrite delay is inserted only afte r the last write operation in the transaction. all programmable paramet ers are exactly the same as in a device write transaction described in section ?device write transaction? on page 6-15. a burst device write transacti on may consist of two or more write operations. the rc32438 prov ides no indication as to the num ber of write operations in the transaction. figure 6.15 generic burst device write transaction 1 the burst device write transaction consists of the following steps. 1. the rc32438 drives the address bus (maddr[25: 0]), drives rwn low and bdirn high, asserts boen 2 , and drives the data to be written on the data bus (mdata[15:0]) on the rising edge of extclk. this indicates the start of a transaction. 2. csd clock cycles after step one, the rc32438 asserts the appropriate chip select (csnx). 3. bwd clock cycles after step one, the rc 32438 asserts the appropriate byte write enables (bwen[1:0]). 4. if waitackn is not asserted during the trans action, the wws clock cycles after step one the rc32438 drives the next data to be written on the data bus (mdata[15:0]) and modifies the address on the address bus (maddr[25:0]). if waitackn is asserted during the transaction, the wws field is ignored from that point until wait- ackn is negated. the rc32438 drives the next data to be written on the data bus (mdata[15:0]) and modifies the address on the address bus (maddr [25:0]) in the clock cycle after it samples waitackn negated. 5. after wws clock cycles, if waitackn is not asserted during the transaction, the rc32438 clocks in the data from the data bus (mdata[15:0]) and, if this is not the last write operation in the trans- action, modifies the address on the address bus (maddr[25:0]). if waitackn is asserted during any point during the read operation, the wws field is ignored from 1. the programmable parameters shown in this figure ar e for illustrative purposes only and may be varied. 2. boen is only asserted if the buffer enable (be) bit is set in the device control register (devxc). extclk maddr[25:0] rwn csnx bwen[1:0] oen mdata[15:0] boen transaction csd wws pwd csh address valid data 1 transaction bwd wws wws wws address valid address valid address valid data 2 data 3 data 4 wdh waitackn
idt device controller decoupled cpu device transactions 79rc32438 user reference manual 6 - 18 november 4, 2002 notes that point until waitackn is negated. in the clock cycle after the rc32438 samples waitackn negated, if this is not the last write operation in the transaction, it drives the next data to be written on the data bus (mdata[15:0]) and modifies the address on the address bus (maddr[25:0]). 6. if there are more writes operations in the burst device write transaction, go to step five. 7. csh clock cycles after step five , the rc32438 negates chip select. 8. wdh clock cycles after step fi ve, the rc32438 negates boen. 9. pwd clock cycles after step five, the rc32438 tri- states the data bus (mdata[15:0]), may modify the address on the address bus (maddr[25: 0]), and may begin a new transaction. decoupled cpu devi ce transactions cpu accesses to a device on the memory and peripheral bus may take a significantly longer time to complete than normal pmbus transactions. one reason for this is the fact that the memory and peripheral bus can run at one eighth the frequency of the pmbus. other reasons are wait states, post read delays, and post write delays. locking up the pmbus may have adverse affects on the real-time performance of the system. for example, it may lead to ethernet fifo overflows and underflows. since the pmbus does not support split transactions there is no way to avoid this issue wi th traditional cpu read and write operations. to avoid locking up the pmbus, the device controller suppor ts decoupled cpu accesses. decoupled cpu accesses allow cpu device read and write operations to comple te without locking up the pmbus. the cpu encodes the type of operation (read or write) in the op field and the size of the operation (byte, halfword, triple-byte, word) in the size field. all multi-byte decoupled read and write operations must be contained in a single word (e.g., it is invalid to initiate a decoupled read from a byte address of 0x3 or a word read from a non-word aligned address). initiating a multi-byte decoupled read or write oper ation that crosses a word boundary results in undefined data and the error (err) bit being set in the devdacs register. to initiate a read operation, the cpu writes a lo cal address that maps to a device to the devdaa register. the cpu write completes on the pmbus without del ay. a read of the size specified in the size field is then performed from the device address written. w hen the read completes, the data read from the device updates the data field of the devdad register and the f bit is set. to initiate a write operation, the cpu writes the data to be written to the data field of the devdad register and then writes the address to be written to the devdaa register. both writes complete without delay. a write of the size specified in the size fi eld is then performed to the device using data from the devdad register. when the write completes, the f bit is set. the f bit is presented to the interrupt handler as an interrupt source. if an error occurs during the device operation or if the address written to the devdaa register does not map to a device on the memory and peripheral bus, then the error (err) bit is set in the devdacs register when the f bit is set. note: it is recommended that direct cpu device ac cesses be used only to execute code from device space and that cpu device accesses to slow external devices use decoupled cpu device transactions.
idt device controller decoupled cpu device transactions 79rc32438 user reference manual 6 - 19 november 4, 2002 notes device decoupled access control and status register figure 6.16 device dec oupled access control and status register (devdacs) op description: operation. this field encodes the decoupled access operation. 0 - write 1 - read size description: size. this field encodes the size of the decoupled access operation. 0 - byte 1 - halfword 2 - triple byte 3 - word initial value: 0x0 read value: previous value written write effect: modify value err description: error. this bit is set if an error occurred while executing a decoupled access operation. the err bit is set under the following conditions: - decoupled access to an address that does not map to a device - multi-byte decoupled access that crosses a word boundary - memory and peripheral bus transaction time-out during a decoupled access initial value: 0x0 read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) f description: finished . this bit is set when a decoupled access operation completes. initial value: 0x0 read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) b description: busy . this bit is set when a decoupled access operation is in progress. initial value: 0x0 read value: status write effect: read-only devdacs 0 31 0 26 op 1 err 1 f 1 size 2 b 1
idt device controller decoupled cpu device transactions 79rc32438 user reference manual 6 - 20 november 4, 2002 notes device decoupled access address register figure 6.17 device decoupled a ccess address register (devdaa) device decoupled access data register figure 6.18 device decoupled access data register (devdad) addr description: address field. writing to this register initiates a decoupled access operation to the address writ- ten to this field. the type of operation is defined by the op field in the devdacs register. initial value: 0x0 read value: 0x0 write effect: initiate a decoupled access operation. data description: data field. this register contains the return value of the previous decoupled access operation or the value to be written to the device. data quantities in this field are always right aligned. there- fore, word operations use all four byte lanes. triple-byte operations always use the right three bytes leaving data[31:24] undefined. word operations always use the right two bytes leaving data[31:16] undefined. finally, byte operations always use the right most byte leaving data[31:8] undefined. initial value: 0x0 read value: return value of previous decoupled access operation (value read from device for read opera- tions, or value written to device for write operations) write effect: modify value devdaa 0 31 addr 32 devdad 0 31 data 32
notes 79rc32438 user reference manual 7 - 1 november 4, 2002 chapter 7 ddr controller introduction this chapter describes the features, functions, and oper ations of the double data rate (ddr) controller. a complete description of the ddr registers is also included. features ? supports up to 2gb of ddr sdram (using data bus multiplexing and two chip selects) ? 2 chip selects (each chip select supports 4 internal ddr banks) ? supports 16-bit or 32-bit data bus widt h using 8, 16, or 32-bit devices ? supports 64 mb, 128 mb, 256 mb, 512 mb, and 1gb ddr sdram devices ? data bus multiplexing support allows in terfacing to standard ddr dimms and sodimms ? automatic refresh generation ? provides clock signals required for c ontrol of external memory devices additional resources idt has developed an application note that focu ses on designing an interface between the rc32438 and ddr memory and provides some lay out considerations. this document ? a n-371, interfacing the rc32438 with ddr sdram memory ? can be found on the company?s web site at www.idt.com. ddr controller regi ster description theory of operation the ddr controller provides a glueless interface to industry standard double data rate (ddr) synchronous dynamic random access memories (sdr ams). the ddr controller may be configured to support a 32-bit or 16-bit data path. when a 16-bit data path is selected, the ddr controller performs byte register offset 1 1. the address of the register is equal to the r egister offset added to the base value of 0x1800_0000. register name register function size 0x01_8000 ddr0base ddr 0 base 32-bit 0x01_8004 ddr0mask ddr 0 mask 32-bit 0x01_8008 ddr1base ddr 1 base 32-bit 0x01_800c ddr1mask ddr 1 mask 32-bit 0x01_8010 ddrc ddr control 32-bit 0x01_8014 ddr0abase ddr 0 alternate base 32-bit 0x01_8018 ddr0amask ddr 0 alternate mask 32-bit 0x01_801c ddr0amap ddr 0 alternate mapping 32-bit 0x01_8020 ddrcust ddr custom transaction 32-bit 0x01_8024 through 0x01_ffff reserved table 7.1 ddr controller register map
idt ddr controller theory of operation 79rc32438 user reference manual 7 - 2 november 4, 2002 notes gathering and scattering. the ddr c ontroller provides two chip selects (ddrcsn[1:0]) with each chip select supporting four internal ddr banks. the ddr c onfiguration for both chip selects must be the same. the supported ddr organizations are shown in table 7.2. the rc32438 has a dedicated ddr bus that is managed by the ddr controller. the ddr bus consist of the following pins: ddrckp[1:0] and ddrckn[1:0] (two se ts of differential clock outputs) ddrcke (ddr clock enable) ddrcsn[1:0] (ddr chip selects) ddrrasn (ddr row address strobe) ddrcasn (ddr colu mn address strobe) ddrwen (ddr write enable) ddrdm[7:0] (ddr byte write mask) ddrba[1:0] (ddr bank address) ddraddr[13:0] (multiplexed ddr address bus)] ddrdata[31:0] (ddr data bus) ddrdqs[3:0] (ddr byte data strobes) ddroen[3:0] (bus switch enables us ed when data bus multiplexing is enabled) ddrvref (sstl_2 ddr voltage referenc e generated by an external source) ddr size and type ddr organization total memory per chip select in 16-bit mode 1 1. four times the memory is available with data bus multiplexing. total memory per chip select in 32-bit mode 2 2. twice the memory is available with data bus multiplexing. 64mb components 2m x 8 x 4 banks 16mb 32mb 1m x 16 x 4 banks 8mb 16mb 512k x 32 x 4 banks not applicable 8mb 128mb components 4m x 8 x 4 banks 32mb 64mb 2m x 16 x 4 banks 16mb 32mb 1m x 32 x 4 banks not applicable 16mb 256mb components 8m x 8 x 4 banks 64mb 128mb 4m x 16 x 4 banks 32mb 64mb 2m x 32 x 4 banks not applicable 32mb 512mb components 16m x 8 x 4 banks 128mb 256mb 8m x 16 x 4 banks 64mb 128mb 4m x 32 x 4 banks not applicable 64mb 1024mb components 32m x 8 x 4 banks 256mb 512mb 16m x 16 x 4 banks 128mb 256mb 8m x 32 x 4 banks not applicable 128mb table 7.2 supported ddr configurations
idt ddr controller theory of operation 79rc32438 user reference manual 7 - 3 november 4, 2002 notes two sets of differential ddr cl ocks (ddrckp[1:0] and ddrckn[1:0]) are provided to ease loading constraints and board design. both clocks have the sa me frequency, which is equal to the ipbus clock (iclk), and phase relationship. all dd r transactions are synchronous to these clocks. thus, all of the timing parameters in the ddr c ontrol (ddrc) register are in terms of ddr clock cycles. the ddr controller contains a single control register (ddrc) since ddrs connected to both chip selects must share a common confi guration. the ddr controller suppor ts only sequential burst lengths of two. this burst length refers to the burst length va lue programmed in the ddr? s mode register. by pipe- lining addresses issued to the ddr, the rc32438 can support burst read and write transactions of any length. the data bus width (dbw) field in this regi ster selects the width of the ddr controller data bus (either 16-bits or 32-bits). during ddr transactions, the address bus is multiple xed as shown in table 7.3 for 32-bit data width mode and in table 7.4 for 16-bit data width mode. the exact address multiplexing is dependent on the ddr device type selected in the device type (dtype) fiel d of the ddrc register. selecting a dtype results in the same multiplexing as that for 64mb devices organized as 2m x 8 x 4 banks. address and bank select signals connect directly to the corr esponding ddr pins in both 16-bit and 32-bit data path modes (i.e., no address shifting is required fo r x16 and x32 ddr organizations). each chip select supports four page comparators. although each page comparator is 14 bits in size, not all bits are used in all ddr configurations. when t he cpu performs a read or write operation to ddr space, the page comparator associated with the selected ddr bank is checked. if the bank was left active and the value in the comparator matches the ddr row address, then the access can be made without first closing the currently active page and opening a different page. ot herwise, if the active page in the comparator does not match the ddr row address, then the active page mu st first be closed (i.e., precharged) and the correct page opened (i.e., made active) before the access may be performed. finally, if no page is active in the bank, the required page must first be opened (i.e., m ade active) before the access may be performed. the ddr controller normally operates with a ddr data strobe per byte lane (i.e., ddrdqs[1:0] in 16-bit data bus width mode and ddrdqs[3:0] in 32-bit data bus width mode). some ddr devices have a single data byte strobe for all byte lanes (e.g., x32 ddr devices in a tqfp package). when the single data strobe (sds) bit is set in the ddrc regist er, ddrdqs[0] is used for all byte lanes. ddr address multiplexing scheme ddr organization cycle ddr bank ddr address 10131211109876543210 64mb 2mx8x4 banks (9-bit page) row a24 a23 x 1 x a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 column a24 a23 x x x ap 2 x a10 a9 a8 a7 a6 a5 a4 a3 a2 64mb 1mx16x4 banks (8-bit page) row a23 a22 x x a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 column a23a22x x x ap x x a9a8a7a6a5a4a3a2 64mb 512kx32x4banks (8-bit page) row a22 a21 x x x a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 column a22a21x x x x x apa9a8a7a6a5a4a3a2 128mb 4mx8x4 banks (10-bit page) row a25 a24 x x a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 column a25 a24 x x x ap a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 128mb 2mx16x4 banks (9-bit page) row a24 a23 x x a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 column a24 a23 x x x ap x a10 a9 a8 a7 a6 a5 a4 a3 a2 128mb 1mx32x4 banks (8-bit page) row a23 a22 x x a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 column a23a22x x x x x apa9a8a7a6a5a4a3a2 table 7.3 ddr address multiplexing in 32-bit mode (part 1 of 2)
idt ddr controller theory of operation 79rc32438 user reference manual 7 - 4 november 4, 2002 notes 256mb 8mx8x4 banks (10-bit page) row a26 a25 x a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 column a26 a25 x x x ap a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 256mb 4mx16x4 banks (9-bit page) row a25 a24 x a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 column a25 a24 x x x ap x a10 a9 a8 a7 a6 a5 a4 a3 a2 256mb 2mx32x4 banks (8-bit page) row a24 a23 x a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 column a24a23x x x x x apa9a8a7a6a5a4a3a2 512mb 16mx8x4 banks (11-bit page) row a27 a26 x a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 column a27 a26 x x a12 ap a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 512mb 8mx16x4 banks (10-bit page) row a26 a25 x a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 column a26 a25 x x x ap a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 512mb 4mx32x4 banks (9-bit page) row a25 a24 x a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 column a25 a24 x x x x a10 ap a9 a8 a7 a6 a5 a4 a3 a2 1024mb 32mx8x4 banks (11-bit page) row a28 a27 a26 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 column a28 a27 x x a12 ap a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 1024mb16mx16x4 banks (10-bit page) row a27 a26 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 column a27 a26 x x x ap a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 1024mb 8mx32x4 banks (9-bit page) row a26 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 column a26 a25 x x x x a10 ap a9 a8 a7 a6 a5 a4 a3 a2 1. don?t care. 2. auto precharge. ddr organization cycle ddr bank ddr address 10131211109876543210 64mb 2mx8x4 banks (9-bit page) row a23 a22 x 1 x a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 column a23 a22 x x x ap 2 x a9a8a7a6a5a4a3a2a1 64mb 1mx16x4 banks (8-bit page) row a22 a21 x x a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 column a22a21x x x ap x x a8a7a6a5a4a3a2a1 128mb 4mx8x4 banks (10-bit page) row a24 a23 x x a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 column a24 a23 x x x ap a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 128mb 2mx16x4 banks (9-bit page) row a23 a22 x x a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 column a23 a22 x x x ap x a9 a8 a7 a6 a5 a4 a3 a2 a1 256mb 8mx8x4 banks (10-bit page) row a25 a24 x a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 column a25 a24 x x x ap a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 256mb 4mx16x4 banks (9-bit page) row a24 a23 x a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 column a24 a23 x x x ap x a9 a8 a7 a6 a5 a4 a3 a2 a1 table 7.4 ddr address multiplexing in 16-bit mode (part 1 of 2) ddr organization cycle ddr bank ddr address 10131211109876543210 table 7.3 ddr address multiplexing in 32-bit mode (part 2 of 2)
idt ddr controller ddr registers 79rc32438 user reference manual 7 - 5 november 4, 2002 notes ddr command encoding ddr registers ddr control register figure 7.1 ddr control register (ddrc) 512mb 16mx8x4 banks (11-bit page) row a26 a25 x a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 column a26 a25 x x a11 ap a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 512mb 8mx16x4 banks (10-bit page) row a25 a24 x a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 column a25 a24 x x x ap a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 1024mb 32mx8x4 banks (11-bit page) row a27 a26 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 column a27 a26 x x a11 ap a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 1024mb 16mx16x4 banks (10-bit page) row a26 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 column a26 a25 x x x ap a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 1. don?t care. 2. auto precharge. command description ddrrasn ddrcasn ddrwen nop no operation h h h active select active bank and row l h h read select bank and column, perform read hlh write select bank and column, perform write hll auto-refresh enter aut o-refresh mode l l h precharge deactivate row in bank or banks l h l table 7.5 ddr command encoding ddr organization cycle ddr bank ddr address 10131211109876543210 table 7.4 ddr address multiplexing in 16-bit mode (part 2 of 2) ddrc 16 31 re 1 cl 2 rcd 2 ap 1 rp 2 rfc 4 0 15 0 5 dtype dbw 1 2 atp 2 wr 3 ata sds 1 dbm 1 5
idt ddr controller ddr registers 79rc32438 user reference manual 7 - 6 november 4, 2002 notes ata description: active to active/auto refresh. this field specifies the minimum number of ddr clock cycles between an active and a subsequent active or auto refresh command. 0 5 clock cycles 1 6 clock cycles 2 7 clock cycles 3 8 clock cycles 4 9 clock cycles 5 10 clock cycles 6 11 clock cycles 7 12 clock cycles initial value: 0x3 (this field is not modified due to a warm reset) read value: previous value written write effect: modify value dbw description: data bus width. this field specifies the width of the ddr control data bus. 0 16-bit data bus width 1 32-bit data bus width initial value: 0x0 (this field is not modified due to a warm reset) read value: previous value written write effect: modify value wr description: write recovery. this field specifies the minimum number of ddr clock cycles from the comple- tion of a write operation to a precharge command. 0 3 clock cycles 1 4 clock cycles 2 5 clock cycles 3 6 clock cycles initial value: 0x3 (this field is not modified due to a warm reset) read value: previous value written write effect: modify value
idt ddr controller ddr registers 79rc32438 user reference manual 7 - 7 november 4, 2002 notes dtype description: ddr device type . this field selects the ddr device type. 0 64mb, 512k x 32 x 4 1 64mb, 1m x 16 x 4 2 64mb, 2m x 8 x 4 3 reserved 4 128mb, 1m x 32 x 4 5 128mb, 2m x 16 x 4 6 128mb, 4m x 8 x 4 7 reserved 8 256mb, 2m x 32 x 4 9 256mb, 4m x 16 x 4 10 256mb, 8m x 8 x 4 11 reserved 12 reserved 13 512mb, 4m x 32 x 4 14 512mb, 8m x 16 x 4 15 512mb, 16m x 8 x 4 16 reserved 17 1gb, 8m x 32 x 4 18 1gb, 16m x 16 x 4 19 1gb, 32m x 8 x 4 20 reserved . . . 31 reserved initial value: 0x1 (this field is not modified due to a warm reset) read value: previous value written write effect: modify value rfc description: refresh clock cycles. this field specifies the auto refresh command period in ddr clock cycles. permissible values are zero through 15. a value of zero has the same effect as program- ming this field to one. initial value: 0xf (this field is not modified due to a warm reset) read value: previous value written write effect: modify value rp description: precharge delay. this field specifies the number of ddr clock cycles between a precharge command and a subsequent row access. 0 1 clock cycle 1 2 clock cycles 2 3 clock cycles 3 4 clock cycles initial value: 0x3 (this field is not modified due to a warm reset) read value: previous value written write effect: modify value
idt ddr controller ddr registers 79rc32438 user reference manual 7 - 8 november 4, 2002 notes ap description: auto precharge enable. this field controls the value driven on auto precharge (shown as ?ap? in tables 7.3 and 7.4) bit during ddr transactions. if auto precharge is enabled, the row being accessed is precharged at the completion of a read or write transaction. 0 auto precharge disabled (ap=0). 1 auto precharge enabled (ap=1). initial value: 0x1 (this field is not modified due to a warm reset) read value: previous value written write effect: modify value rcd description: active to read or write delay. this field specifies the minimum number of ddr clock cycles between the issuing of a ddr active command and a read or write command. 0 1 clock cycle 1 2 clock cycles 2 3 clock cycles 3 4 clock cycles initial value: 0x2 (this field is not modified due to a warm reset) read value: previous value written write effect: modify value cl description: cas latency. this field contains the cas latency value in ddr clock cycles. 0 2 clock cycles 1 2.5 clock cycles 2 3 clock cycles 3 4 clock cycles initial value: 0x2 (this field is not modified due to a warm reset) read value: previous value written write effect: modify value dbm description: data bus multiplexing. when this bit is set, data bus multiplexing is enabled. for more informa- tion, refer to the ddr data bus multiplexing section in this chapter. initial value: 0x0 (this field is not modified due to a warm reset) read value: previous value written write effect: modify value sds description: single data strobe. the ddr controller normally operates with a ddr data strobe per byte lane (i.e., ddrdqs[1:0] in 16-bit data bus width mode and ddrdqs[3:0] in 32-bit data bus width mode). some ddr devices have a single data byte strobe for all byte lanes. when this bit is set, ddrdqs[0] is used for all byte lanes. initial value: 0x0 (this field is not modified due to a warm reset) read value: previous value written write effect: modify value
idt ddr controller ddr registers 79rc32438 user reference manual 7 - 9 november 4, 2002 notes ddr read data capture register figure 7.2 shows the pclk 1 edges which can be configured fo r ddr read data capture. the edges shown correspond to the pclk edges which will capture the first data word of the read transaction (i.e., ddrdata[31:0] = d0). subsequent data words are captured with subsequent pclk positive edges. note that the capturing edges are relative to the cas lat ency (cl) programmed in t he ddrc register. figure 7.2 shows the capturing edges when cl = 2. as a rule, the first capture edge (ces=0) is always the positive pclk edge corresponding to cl + 1/2 ddrckp edges fr om the time the first read command is issued (ddrcmd = read). 2 atp description: active to precharge. this field specifies the minimum number of ddr clock cycles from an active command to read or write command with auto precharge (this field corresponds to the t ras (min) ddr timing parameter). 0 5 clock cycles 1 6 clock cycles 2 7 clock cycles 3 8 clock cycles initial value: 0x3 (this field is not modified due to a warm reset) read value: previous value written write effect: modify value re description: refresh enable. when this bit is set and the ddr refresh timer expires, a ddr refresh transac- tion is queued. when this bit is cleared, a ddr refresh transaction is never generated regardless of the state of the refresh timer. initial value: 0x1 (this field is not modified due to a warm reset) read value: previous value written write value: modify value 1. pclk is the internal clock used by the ddr controller. 2. ddrcmd represents the co ncatenation of ddrrasn , ddrcasn, and ddrwen.
idt ddr controller ddr registers 79rc32438 user reference manual 7 - 10 november 4, 2002 notes figure 7.2 ddr read data capture edge select configurations the selection of which pclk edge is used to c apture data depends on the read data access loop delay (i.e., ddrckpx -> ddrdata) of a system. this select ion has to take into account the pclk->ddrckp delay, as well as ddrckp and ddrdata board dela ys. for systems with a short read data access loop delay, ces may be configured to 0 or 1. for syst ems with a long read data access loop delay, ces may be configured to 2 or 3. the user must do a care ful analysis of the board delays when programming ces. when the ace bit is set (recommended), the ddr co ntroller automatically determines which pclk edge should be used to capture the read data (i.e., the ces field is ignored). in this mode the user must only ensure that the read data access l oop delay does not exceed one ddrckp cycles. figure 7.3 ddr read data capture register (ddrrdc) ces description: capture edge select. this bit controls the pclk edge used to capture data during a ddr read transaction when the auto capture enable (ace) bit is cleared. 0 - capture data on early positive edge of pclk that corresponds to the negative edge of ddrckp[1:0] 1 - capture data on early positive edge of pclk that corresponds to the positive edge of ddrckp[1:0] 2 - capture data on late positive edge of pclk that corresponds to the negative edge of ddrckp[1:0] 3 - capture data on late positive edge of pclk that corresponds to the positive edge of ddrckp[1:0] col a0 nop rd nop nop nop nop nop nop nop bnkx d0 d1 pclk (internal) ddrckpx ddrcknx ddrcsnx ddraddr[13:0] ddrcmd ddrcke ddrba[1:0] ddrdm[7:0] ddroen[3:0] ddrdqsx ddrdata[y:0] 0 1 2 3 capture edge select (ces) cl 0 31 ddrrdc 29 2 0ces 1 ace
idt ddr controller ddr registers 79rc32438 user reference manual 7 - 11 november 4, 2002 notes ddr address mapping the ddr banks can be located anywhere in the rc 32438?s local address space. the address of the ddr banks corresponding to each ddr chip select can be allocated independently. address decoding for each ddr chip select is controlled by the ddr base (ddr[1|0]base) and ddr mask (ddr[1|0]mask) regist ers. the ddr mask register is used to select which bits are used for address decoding. when a bit in this register is a one, the corresponding address bit is ac tive in address compari- sons. if a bit in this register is a zero, then t he corresponding address bit does not participate in address comparisons. the base address register specifies the base physical addres s for each ddr chip select. all of the active address bits not masked by the ddr mask register are compared to the value in the ddr base register. if they all match, then the co rresponding ddr chip select is asserted. to facilitate pci booting from a ddr-only memo ry system, an alternate address mapping range is supported for ddr chip select zero (see figure 7.4) . the alternate address range is configured using the ddr alternate base (ddr0abase) and ddr alternate ma sk (ddr0amask) register s. the ddr alternate mapping (ddr0amap) register spec ifies the value of ddr address bits that are mapped by the ddr mask register. this allows the ddr address to be offset from the rc32438?s local address. the normal and alternate base and mask registers for ddr chip select zero allow two rc32438 local address ranges to be mapped to the same ddr chip select. care should be exercised when using this feature to ensure data cache coherence. initial value: 0x0 (this field is not modified due to a warm reset) read value: previous value written write value: modify value ace description: auto capture enable. when this bit is set the ddr controller automatically determines the pclk edge used to capture data during a ddr read transaction. initial value: 0x1 (this field is not modified due to a warm reset) read value: previous value written write value: modify value
idt ddr controller ddr registers 79rc32438 user reference manual 7 - 12 november 4, 2002 notes figure 7.4 ddr0 al ternate address mapping ddr [0|1] base register figure 7.5 ddr [0|1] base register (ddr[0|1]base) baseaddr description: base address. this 16-bit field specifies the upper 16 bits of the ddr base address. initial value: 0x0 (this field is not modified due to a warm reset) read value: previous value written write effect: modify value ddr0base ddr0abase ddr0mask ddr0amask ddr0 ddr0 alternate ph ys i ca l add ress physical memory ddrcsn[0] ddr0 ddr0 ddr0 & ddr0 alt overlap region ddr0amap mapping notes: 1. register ddr0amap controls the location of the overlap region within ddr0 space. the mapping logic substitutes address bits that logic participate in address comparison (i.e., non-masked bits) with the corresponding bits in the ddr0amap register. 2. only ddr chip-select 0 (ddrcsn[0]) supports alternate mapping. ddr[0|1]base 0 31 16 16 baseaddr 0
idt ddr controller ddr registers 79rc32438 user reference manual 7 - 13 november 4, 2002 notes ddr [0|1] mask register figure 7.6 ddr [0|1] mask register (ddr[0|1]mask) ddr 0 alternate base register figure 7.7 ddr 0 alternate base register (ddr0abase) mask description: address mask. this field determines which bits of the upper 16-bits of the address participate in address comparisons. when a bit is set in this field, then the corresponding address bit partici- pates in address comparisons. when a bit is cleared in this field, then the corresponding address bit is masked and does not participate in address comparisons. when the mask field is zero, the ddr space is disabled and does not appear in the memory map. initial value: 0x0 (this field is not modified due to a warm reset) read value: previous value written write effect: modify value baseaddr description: base address. this 16-bit field specifies the upper 16 bits of the alternate ddr 0 base address. initial value: 0x0 (this field is not modified due to a warm reset) read value: previous value written write effect: modify value ddr[0|1]mask 0 31 16 mask 16 0 ddr0abase 0 31 16 16 baseaddr 0
idt ddr controller ddr registers 79rc32438 user reference manual 7 - 14 november 4, 2002 notes ddr 0 alternate mask register figure 7.8 ddr 0 alternate mask register (ddr0amask) ddr 0 alternate mapping register figure 7.9 ddr 0 alternate mapping register (ddr0amap) ddr data bus multiplexing the ddr controller supports data bus multiplexing when the data bus multiplexing (dbm) bit is set in the ddrc register. data bus multiplexing allows the rc32438?s 16-bit or 32-bit data bus 1 to interface to ddr memory systems having a data bus width of 64-bits. this is nec essary when interfacing the rc32438 to standard ddr memory modules such as ddr dimms and sodimms. to support data bus multiplexing, external bus switches must be placed between the rc32438 and external ddr memory banks. these bus switches are used to isolate unused data bits and strobes from the rc32438 allowing 16-bit or 32-bit data quantit ies to be read from a 64-bit bus. the rc32438 ddroen[3:0] pins are output enabled for these buffers. mask description: address mask. this field determines which bits of the upper 16-bits of the address participate in address comparisons. when a bit is set in this field, then the corresponding address bit partici- pates in address comparisons. when a bit is cleared in this field, then the corresponding address bit is masked and does not participate in address comparisons. when the mask field is zero, the alternate dd r space is disabled and does not appear in the memory map. initial value: 0x0 (this field is not modified due to a warm reset) read value: previous value written write effect: modify value map description: map address. this field contains the ddr mapping address for transactions mapped to ddr chip select zero using the alternate address mapping range. address bits that participated in address comparison are substituted with values in this field. initial value: 0x0 (this field is not modified due to a warm reset) read value: previous value written write effect: modify value 1. mode is determined by the state of the data bus width (dbw) bit in the ddrc register. ddr0amask 0 31 16 mask 16 0 ddr0amap 0 31 16 16 map 0
idt ddr controller ddr registers 79rc32438 user reference manual 7 - 15 november 4, 2002 notes when data bus multiplexing is enabled, the address range allocated to a ddr chip select should be expanded to twice the space allocated in a 32-bit mode sys tem or four times the space allocated in a 16-bit mode system by programming the corresponding base and mask registers. the 32-bit mode section in figure 7.10 illustrates this addre ss range expansion for a 32-bit mode system using 32m x 8 x 4 bank (i.e., 1gb) ddrs. eight of these ddrs create a 64-bit data bus that interf aces to the rc32438?s 32-bit ddr data bus through external bus switches as shown in fi gure 7.11. the total space allocated for the ddr chip select is 1gb. when an access is made to the lower 512 mb, the ddroen[1:0] signals are asserted. during writes to this region, the ddrdm[3:0] signals are used to select enabled byte lanes. when an access is made to the upper 512 mb, the ddroen[3:2] signals are asserted and ddrdm[7:4] are used to select enabled byte lanes during writes. memory range memory range figure 7.10 ddr data bus mult iplexing address range expansion figure 7.11 32-bit bank ddr data bus multiplexing operation in 16-bit mode parallels that in 32-bit mode. using the same ddr devices as in the above example, a 16-bit mode system with data bus multiplexi ng has 4 regions per chip select as shown in the 16- bit mode section of figure 7.10. ei ght of these ddrs create a 64-bit data bus that interfaces to the rc32438?s 16-bit ddr data bus through external bus swit ches as shown in figure 7.12. when an access is made to the lower 256 mb, ddroen[0] is asserted and d drdm[1:0] are used to select byte lanes during writes. when an access is made to the next 256 mb, ddroen[1] is asserted and ddrdm[3:2] are used to select byte lanes during writes. the pattern continues for the upper two memory regions. 256 mb ddrdm[1:0] ddroen[0] 256 mb ddrdm[3:2] ddroen[1] 256 mb ddrdm[5:4] ddroen[2] 256 mb ddrdm[7:6] ddroen[3] 512 mb ddrdm[3:0] ddroen[1:0] 512 mb ddrdm[7:4] ddroen[3:2] 32-bit mode 16-bit mode external ddr bank (32-bits) dm dqs d bus switch oe bus switch oe rc32438 4 4 32 4 ddrdm[3:0] ddrdqs[3:0] ddrdata[31:0] ddrdm[7:4] ddroen[1:0] ddroen[3:2] 2 2 cs external ddr bank (32-bits) dm dqs d cs ddrcsnx
idt ddr controller ddr initialization 79rc32438 user reference manual 7 - 16 november 4, 2002 notes figure 7.12 16-bit bank ddr data bus multiplexing ddr initialization ddr sdrams must be powered up and initialized in a predefined manner before they may be used. see the ddr data sheet for power sequencing and timing initialization requirements. during a cold reset, the rc32438 maintains ddrcke at an lvcmos low level to ensure that the dq and dqs outputs of any connected ddrs are tri-stated. cke will remain at a lv cmos low level until the first ddr custom transac- tion is performed at which point cke will take on the appropriate sstl_2 low or high value or until the first normal ddr transaction at which point cke will take on an sstl_2 high value. note cke will take on a sstl_2 high value whenever a non-custom ddr transaction is executed. each ddr contains two mode register s that define the specific mode of operation for the ddr. the first mode register selects: the burst length, the burst type, cas latency, and operating mode. the second, or extended, mode register is used to reset the dll with in the ddr and to configure its operating parameters. both mode registers are programmed usi ng a ddr load mode register command. note: care should be taken when programming these r egisters. if not properly programmed, the ddr sdram chips may inhibit the assertion of the ddrdqs signal, causing the rc32438 device to lock-up. in order to support compatibility with a wide r ange of devices, the ddr controller does not directly support ddr load mode register commands. instead, this command must be synthesized using a ddr custom transaction. to initiate a ddr custom tr ansaction, one or both chip selects in the cs field of the ddrcust register are sele cted. the desired ddr command is then programmed by setting the ba, cke, cas, ras, we, and cs fields to the desired state in the ddrcust register. on the next decoded ddr memory cycle, a transaction will be issued to the ddr with the command programmed in the bus switch oe bus switch oe rc32438 2 2 16 2 ddrdm[1:0] ddrdqs[1:0] ddrdata[15:0] ddrdm[3:2] ddroen[0] ddroen[1] bus switch oe bus switch oe ddroen[2] ddroen[3] 2 2 ddrdm[5:4] ddrdm[7:6] external ddr bank (16-bits) dm dqs d cs external ddr bank (16-bits) dm dqs d cs external ddr bank (16-bits) dm dqs d cs external ddr bank (16-bits) dm dqs d cs ddrcsnx
idt ddr controller ddr initialization 79rc32438 user reference manual 7 - 17 november 4, 2002 notes ddrcust register. the chip select signals selected in the cs field are asserted for one clock cycle but the state of the other control si gnals ? ddrrasn, ddrcasn , ddrcken, and ddrwen ? reflect the state programmed in the ddrcust register until a new transaction is issued by the ddr controller. the ddr address ddr bus (i.e., ddraddr[13:0]) is driven with the cpu address bits (i .e., a[15:2]) that generated the ddr custom transaction. using this mec hanism, most ddr commands, including load mode register, may be synthesized by the cpu. note that during a ddr custom transaction, no data is read from or written do the ddr (i.e., the ddr data bus re mains tri-stated). after the ddr custom transaction completes, the value of the cs field in the dd rcust register is automatically reset to zero. ddr custom transaction register figure 7.13 ddr custom transaction register (ddrcust) cs description: ddr chip select. this field is used to enable a ddr custom transaction and specifies which chip select(s) should be asserted during the transaction. after the ddr custom transaction com- pletes, the value of this field is automatically reset to zero. 0 neither ddrcsn[0] or ddrcsn[1] are asserted 1 ddrcsn[0] is asserted 2 ddrcsn[1] is asserted 3 ddrcsn[0] and ddrcsn[1] are both asserted initial value: 0x0 (this field is not modified due to a warm reset) read value: previous value written (or zero after a ddr custom transaction completes) write effect: modify value we description: ddr write enable. this field specifies the state of the ddrwen signal during a ddr custom transaction. initial value: 0x1 (this field is not modified due to a warm reset) read value: previous value written write effect: modify value ras description: ddr ras status. this field specifies the state of the ddrrasn signal during a ddr custom transaction. initial value: 0x1 (this field is not modified due to a warm reset) read value: previous value written write effect: modify value cas description: ddr cas status. this field specifies the state of the ddrcasn signal during a ddr custom transaction. initial value: 0x1 (this field is not modified due to a warm reset) ddrcust 0 31 24 0 cke cas ras 1 we cs 2 ba 2 111
idt ddr controller ddr refresh timer 79rc32438 user reference manual 7 - 18 november 4, 2002 notes ddr refresh timer the ddr controller contains a refresh timer whic h may be used to automatically issue ddr refresh transactions. the ddr refresh timer is a 16-bit timer which uses the ipbus clock (iclk) as its time base. when enabled, the counter begins count ing up from zero. the current value of the counter may be deter- mined by reading the count field in the rcount register. when the value in this count field is equal to the compare field of the rcompare register, the refr esh timer expires. this causes the to bit in the rtc register to be set, an ddr refresh transaction to be queued if the re bit in the ddrc register is set, and the counter to reset and begin counting up from zero. when a refresh transaction is queued, the ddr contro ller waits for the ddr bus to become available (i.e., current transaction to complete). a refresh transaction is then issued with both ddr chip selects asserted. the ddr refresh timer may queue up to a ma ximum of eight refresh transactions. if the ddr refresh timer attempts to queue more than eight re fresh transactions, the refresh queue exceeded (rqe) bit is set in the rtc register and the refresh transac tion is discarded. when automatic generation of ddr re fresh transactions is not requir ed, the ddr refresh timer may be used as a general purpose timer. this is done by setting the re bit in the ddrc register to zero which disables the queueing of ddr refresh tr ansactions. the to sticky bit in the rtc register is an input to the interrupt controller. refresh timer count register figure 7.14 refresh timer count register (rcount) read value: previous value written write effect: modify value cke description: ddr clock enable. this field specifies th e state of the ddrcke sign al during a ddr custom transaction. initial value: 0x1 (this field is not modified due to a warm reset) read value: previous value written write effect: modify value ba description: ddr bank address. this field specifies the state of the ddrba[1:0] signals during a ddr cus- tom transaction. initial value: 0x3 (this field is not modified due to a warm reset) read value: previous value written write effect: modify value count description: current count. this 16-bit field contains the current refresh timer count value. initial value: 0x0000 (this field is not modified due to a warm reset) rcount 0 31 16 16 0 count
idt ddr controller ddr refresh timer 79rc32438 user reference manual 7 - 19 november 4, 2002 notes refresh timer compare register figure 7.15 refresh timer compare register (rcompare) refresh timer control register figure 7.16 refresh timer control register (rtc) read value: current refresh timer count write effect: read-only compare description: compare value. this 16-bit field contains the maximum refresh timer count value. when the value in the rcount register equals this value, the refresh timer expires. when the refresh timer is enabled, writing to this register causes the refresh timer to abort its current count and begin counting from zero. initial value: 0xffff (this field is not modified due to a warm reset) read value: previous value written write effect: modify value ce description: counter enable. when this bit is set to a zero the refresh timer is disabled. setting this bit to a one enables the refresh timer. when enabled the refresh timer begins counting up from zero. initial value: 0x0 (this field is not modified due to a warm reset) read value: previous value written write effect: modify value to description: time-out. this bit is set to a one to indicate that the refresh timer has expired. once this bit is set it will remain set until a zero is written into this field by the cpu. this bit is not automatically cleared when the ce bit is cleared. if both the counter timer and the cpu attempt to update this field concurrently, the counter timer will take precedence. initial value: 0x0 (this field is not modified due to a warm reset) read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) rcompare 0 31 16 16 0compare rtc 0 31 29 0 to ce 1 1 rqe 1
idt ddr controller ddr read transaction 79rc32438 user reference manual 7 - 20 november 4, 2002 notes ddr read transaction this section describes the ddr read transaction. al l ddr read transactions consist of a burst read of an even number of 16-bit/32-bit data quantities. the transaction involves f our programmable parameters: ? active to read or write delay ( rcd ). rcd may be programmed to be any value between 1 and 4 ddr clock cycles. ? cas latency (cl). cl may be programmed to values between 2 and 4 ddr clock cycles. ? precharge delay ( rp ). rp may be programmed to be any value between 1 and 4 ddr clock cycles. ? active to precharge (atp). atp may be program med to be any value between 5 and 8 ddr clock cycles. when the auto precharge bit (ap) in the ddrc register is set, only t he last read operation in the transac- tion has the auto precharge address bit (i.e., ddraddr[10] or ddra ddr[8] depending on the ddr type and organization) address bit set. that is, only the last read operation perfo rms an automatic precharge. figure 7.17 ddr sdram read transaction with wrong page active in bank (bank page miss) 1 rqe description: refresh queue exceeded. this bit is set to a one to indicate that the refresh queue limit of eight refresh transactions has been exceeded and that a ddr refresh transaction has been discarded. this bit should never be set under normal operation. initial value: 0x0 (this field is not modified due to a warm reset) read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) 1. the programmable parameters shown in figure 7.17 are for illustrative purposes only and may vary. row a col a0 col a2 nop prechg nop actv nop rd rd nop nop nop nop prechg nop bnkx bnkx bnkx bnkx bnkx d0 d1 d2 d3 ddrckpx ddrcknx ddrcsnx ddraddr[13:0] ddrcmd ddrcke ddrba[1:0] ddrdm[7:0] ddr oen[3:0] ddrdqsx ddrdata[y:0] rp = 2 rcd = 2 cl = 2 atp = 8 notes: 1. y = 31 in 32-bit mode, 15 in 16-bit mode. refer to dbw bit in ddrc register for details. 2. ddrcmd represents the concatenat ion of ddrrasn, ddrcasn, and ddrwen. transaction read transaction ap = 0 next transaction
idt ddr controller ddr write transaction 79rc32438 user reference manual 7 - 21 november 4, 2002 notes a ddr sdram read transaction in which the wrong page is active in a bank is shown in figure 7.17. if no pages had been active, then the transaction woul d have started with the active command (i.e., step three below). if the correct page had been active (bank page hit), then the transaction would have started with the read command (i.e., step five below). a ddr sdram read transaction in which the wrong page is active in a bank consists of the following steps. 1. the rc32438 asserts the appropriate ddr sdram ch ip select (ddrcsnx), drives the bank select pins (ddrba[1:0]) with the value of the bank to be precharged, drives t he ap address bit low (see tables 7.3 and 7.4) to indicate that only that bank is to be precharged, and drives the precharge command (see table 7.5) on the rising edge of ddrc kpx. this indicates the start of a transaction. 2. one clock cycle after step #1, the rc32438 drives the nop command (see table 7.5). 3. rp clock cycles after step #1, the rc32438 drives the bank select pins (ddrba[1:0]) with the value of the bank to be accessed, drives the address bus (ddraddr[13:0]) with the ddr sdram row address, and drives the active command (see table 7.5) on the rising edge of ddrckpx. note that step #2 is skipped if the val ue of rp = 1 (see ddrc register). 4. one clock cycle after step #1, the rc32438 drives the nop command (see table 7.5). 5. rcd clock cycles after step #3, the rc32438 dr ives the address bus (ddraddr[13:0]) with the ddr sdram column address, and drives the read command (see table 7.5). note that step #4 is skipped if the value of rcd = 1 (see ddrc register). 6. one clock cycle after step #5, the rc32438 may drive the nop or read command depending on the amount of data to be read. figure 7.17 shows a read of four words, and thus two read commands are issued (each read command returns a pair of data). during the last read command issued, the rc32438 may assert the auto-precharge (ap) bit of the address bus (see tables 7.3 and 7.4) depending on the state of the ap field in the ddrc register. 7. one clock cycle after step #6, the rc32438 drives the nop command. 8. cl clock cycles after step #5, the rc32438 opens its input buffers and accepts the read data from the data bus (ddrdata[31:0]) as well as the ddr read data strobes (ddrdqs[3:0]). the input buffers remain open until the data and strobes corresponding to the last read command reach the rc32438. 1 9. one clock cycle after the data and strobes fo r the last read command are accepted into the rc32438, the appropriate ddrcsnx is negated, the tr ansaction is completed, and a new transac- tion may begin. ddr write transaction this section describes t he ddr write transaction. al l ddr write transactions c onsist of a burst write of an even number of 16-bit/32-bit data quantities. t he ddr byte write masks (ddrdm[7:0]) are used to mask bytes which should not be modified. the transaction involves f our programmable parameters: ? active to read or write delay ( rcd ). rcd may be programmed to be any value between 1 and 4 ddr clock cycles. ? precharge delay ( rp ). rp may be programmed to be any value between 1 and 4 ddr clock cycles. ? write recovery ( wr ). wr may be programmed to any value between 1 and 4 ddr clock cycles. ? active to precharge ( atp ). atp may be programmed to be any value between 5 and 8 ddr clock cycles. when the auto precharge bit (ap) in the ddrc register is set, only the last write operation in the trans- action has the auto precharge address bit (i.e ., ddraddr[10] or ddraddr[8] depending on the ddr type and organization) addres s bit set. that is, only the last write operation performs an automatic precharge. 1. the input buffers remain open for a maximum of (cl+ 2) ddrckp cycles after the last read command is issued. this puts an upper time limit on the read data access loop (ddrckpx -> ddrdata) of a system.
idt ddr controller ddr write transaction 79rc32438 user reference manual 7 - 22 november 4, 2002 notes figure 7.18 ddr sdram write transaction with wrong page active in bank (bank page miss) 1 a ddr sdram write transaction in which the wrong page is active in a bank is shown in figure 7.18. if no pages had been active, then the transaction woul d have started with the active command (i.e., step three below). if the correct page had been active (bank page hit), then the transaction would have started with the write command (i.e., step five below). a ddr sdram write transaction in which the wrong page is active consists of the following steps. 1. the rc32438 asserts the appropriate ddr sdram ch ip select (ddrcsnx), drives the bank select pins (ddrba[1:0]) with the value of the bank to be precharged, drives t he ap address bit low (see tables 7.3 and 7.4) to indicate that only that bank is to be precharged, and drives the precharge command (see table 7.5) on the rising edge of ddrc kpx. this indicates the start of a transaction. 2. one clock cycle after step #1, the rc32438 drives the nop command (see table 7.5). 3. rp clock cycles after step #1, the rc32438 drives the bank select pins (ddrba[1:0]) with the value of the bank to be accessed, drives the address bus (ddraddr[13:0]) with the ddr sdram row address, and drives the active command (see table 7.5) on the rising edge of ddrckpx. note that step #2 is skipped if the val ue of rp = 1 (see ddrc register). 4. one clock cycle after step one, the rc 32438 drives the nop command (see table 7.5). 5. rcd clock cycles after step #3, the rc32438 dr ives the address bus (ddraddr[13:0]) with the ddr sdram column address, and drives the writ e command (see table 7.5). at this time the rc32438 may also assert the appropriate buffer out put enables (ddroen[3:0]) if the dbm bit in the ddrc register is set. note that step #4 is ski pped if the value of rcd = 1 (see ddrc register). 6. one clock cycle after step #5, the rc32438 may drive the nop or write command depending on the amount of data to be written. figure 7.18 show s a write of four words, and thus two write commands are issued (each write command writes a pair of data). during the last write command issued, the rc32438 may assert the auto-precharge ( ap) bit of the address bus (see tables 7.3 and 7.4) depending on the state of the ap field in the ddrc register. 1. the programmable parameters shown in figure 7.18 are for illustrative purposes only and may vary. rp = 2 rcd = 2 wr = 3 atp = 8 row a col a0 col a2 nop prechg nop actv nop wr wr nop nop nop nop prechg nop bnkx bnkx bnkx bnkx bnkx ff dm0 dm1 dm2 dm3 ff d0 d1 d2 d3 ddrckpx ddrcknx ddrcsnx ddraddr[13:0] ddrcmd ddrcke ddrba[1:0] ddr oen[3:0] ddrdm[7:0] ddrdqsx ddrdata[y:0] write transaction transaction next transaction
idt ddr controller ddr refresh transaction 79rc32438 user reference manual 7 - 23 november 4, 2002 notes 7. a half clock cycle after step #6, the rc32438 st arts driving the ddr data bus (ddrdata[31:0]) as well as the ddr data strobes (ddrdqs[3:0]). this ensures that the rc32438 meets the ddr sdram?s write-preamble requirement. 8. a half clock cycle after step #7, the rc32438 star ts to toggle the ddr data strobes (ddrdqs[3:0]). for each write command issued, each strobe is toggled twice (first low to high and then high to low). in figure 7.18, two write commands are issued and thus each strobe is toggled four times. note that at this time the rc32438 also drives the ddr data bus (ddrdata[31:0]) and ddr data masks (ddrdm[7:0]) in such a way that for each data t he ddr strobes toggle at the center of the data window. 9. a half clock cycle after the rc32438 stops toggl ing the ddr data strobes, the rc32438 starts its write recovery count (wr field of the ddrc register). 10. a full clock cycle after the rc32438 stops toggl ing the ddr data strobes, the rc32438 stops driving the strobes and data bus. this ensures that the rc32438 meets the ddr sdram?s write-post- amble requirement. 1 11. wr-2 clock cycles after step #9, the rc32438 negates all buffer output enables (ddroen[3:0]), negates the appropriate ddrcsnx, the transacti on is completed, and a new transaction may begin. ddr refresh transaction this section describes the ddr refresh transaction. the transacti on involves three programmable parameters: ? precharge delay ( rp ). rp may be programmed to be any value between 1 and 4 ddr clock cycles ? refresh clock cycles ( rfc ). rfc may be programmed to be any value between 1 and 15 ddr clock cycles. figure 7.19 ddr sdram refresh transaction with active pages 2 1. the rc32438 meets the minimum write postamble requirement set by the ddr sdram specification. the maximum limit for this parameter is not required to be met, even though ddr sdram specification has a value for it. not meeting this requirement does not affect the ddr sdram chip nor the rc32438?s bus turn-around time. 2. the programmable parameters shown in figure 7.18 are for illustrative purposes only and may vary. rp = 2 rfc = 7 ap=1 nop prechg nop ar nop nop nop nop nop nop nop actv nop bnkx ddrckpx ddrcknx ddrcsn[1:0] ddraddr[13:0] ddrcmd ddrcke ddrba[1:0] ddrdm[7:0] ddr oen[3:0] ddrdqs[3:0] ddrdata[31:0] transaction refresh transaction next transaction
idt ddr controller d dr custom transaction 79rc32438 user reference manual 7 - 24 november 4, 2002 notes a ddr sdram refresh transaction is queued for exec ution whenever the ddr refresh timer expires and the refresh enable bit (re) in the ddrc register is set. if no acti ve pages exists in any of the ddr sdram banks, then the refresh transaction simply c onsists of an auto refresh command followed by rfc clock cycles (i.e., the transaction starts with step th ree below). if there exists an active page in any of the ddr sdrams, then a precharge-all co mmand is first issued to deactivate all banks in all of the ddrs. this is then followed by an auto-refresh command followed by rfc clock cycles. a ddr sdram refresh trans- action with active pages is shown in figur e 7.19 and consists of the following steps. 1. the rc32438 asserts both ddr sdram chip sele cts (ddrcsn[1:0]), drives the ap address bit high (see tables 7.3 and 7.4) to indicate that all banks are to be pr echarged, and drives the precharge command (see table 7.5) on the rising edge of ddrckpx. this indicates the start of a transaction. 2. one clock cycle after step #1, the rc32438 drives the nop command (see table 7.5). 3. rp clock cycles after step #1, the rc32438 dr ives the auto-refresh command (see table 7.5). note that step two is skipped if the value of rp = 1 (see ddrc register). 4. one clock cycle after step #3, the rc32438 drives the nop command (see table 7.5). 5. rfc clock cycles after step #4, the rc32438 negates the ddr sdram chip selects (ddrcsn[1:0]), the transaction is co mpleted, and a new transaction may begin. ddr custom transaction this section describes the sdram custom transacti on. the transaction involves seven programmable parameters: ? ddr chip select ( cs ). cs may be programmed to select ddrcsn[0], ddrdcsn[1] or both ? ddr write enable status ( we ). we specifies the state of the ddrwen pin during a ddr custom transaction ? ddr ras status ( ras ). ras specifies the state of the ddr rasn pin during a ddr custom trans- action ? ddr cas status ( cas ). cas specifies the state of the ddrcasn signal during a ddr custom transaction ? ddr clock enable status ( cke ). cke specifies the state of the ddrcke signal during a ddr cus- tom transaction. ? ddr bank address status ( ba ). ba specifies the state of t he ddrba[1:0] signals during a ddr custom transaction. ? ddr auto precharge enable ( ap ). ap specifies the state of the auto precharge address bit during a ddr custom transaction.
idt ddr controller example of ddr sdram initialization 79rc32438 user reference manual 7 - 25 november 4, 2002 notes figure 7.20 ddr sdram custom transaction a ddr sdram custom transaction is shown in figure 7.20 and cons ists of the following steps. 1. the cpu configures the programmable paramet ers in the ddrcust regi ster for the desired ddr sdram custom transaction. 2. the cpu performs a write operation to ddr sdra m space. this causes the rc32438 to assert the chip selects (ddrcsnx) programmed in the cs fi eld of the ddrcust register, drive the address bus (ddraddr[13:0]) with the cpu address bits [ 15:2], drive the bank select pins (ddrba[1:0]) with the value programmed in the ba field of the ddrcust register, drive the ddrcke pin with the value programmed in the cke field of the dd rcust register, and drive the ddr sdram custom command programmed in the ras, cas, and we fiel ds of the ddrcust register. note that the ddrdm[7:0] and ddroen[3:0] pins are automat ically negated during custom transactions, and that the ddrdata[31:0] and ddrdq s[3:0] pins are not driven. 3. one clock cycle after step #2, the rc32438 negates all of the asserted chip selects and clears the address and bank select pins. the ddr sdra m custom command programmed in the ddrcust register continues to be driven until the next ddr transaction. at this point the transaction is completed and a new transaction may begin. 4. note that step #2 must be a write operation to ddr sdram space. still, the write data for this oper- ation is meaningless. only the address bits [15:2] of the transac tion are meaningful as they are driven onto the ddraddr[13:0] pins. example of ddr sdram initialization the idt79eb438 board uses two micron mt46v16m 16 (4 meg x 16 x 4 banks) ddr sdram devices tied to ddrcsn[0]. the specifics of this ddr s dram devices are listed below: a). configuration : 4 mb x 16 x 4 banks b). refresh count : 8 k c). row addressing : 8 k (a0-a12) d). bank addressing : 4 ( ba0, ba1) e). column addressing : 512 (a0-a8) a[15:2] nop nop nop custom custom custom custom custom custom custom custom actv nop custom bnkx ddrckpx ddrcknx ddrcsnx ddraddr[13:0] ddrcmd ddrcke ddrba[1:0] ddrdm[7:0] ddr oen[3:0] ddrdqs[3:0] ddrdata[31:0] transaction custom trans next transaction
idt ddr controller example of ddr sdram initialization 79rc32438 user reference manual 7 - 26 november 4, 2002 notes f). cas latency : 2 - 2.5 g). page size : 9 bits h). write recovery time twr : 15 nsec ( 3 clock cycles @ 133 mhz ) i). auto refresh command period trfc : 75 ns ( 10 clock cycles @ 133 mhz ) j). precharge delay trp : 20 nsec ( 3 clock cycles @ 133 mhz ) k). active to read or write delay trcd : 20 nsec ( 3 clock cycles @ 133 mhz) l). active to active/auto refresh period trc : 65 nsec ( 9 clock cycles @133 mhz) m). active to precharge tras : 40 nsec ( 6 clock cycles @ 133 mhz ) ddr control register settings: assuming ddr controller clock frequency is 133 mhz ddrc.ata [ 7-5] : 100b ( 9 clock cycles ) ddrc.dbw[8] : 1 ( 32 bits ) ddrc.wr[10-9] : 00b ( 3 clock cycles ) ddrc.dtype[15-11] : 01001b ( 256mb, 4mx16x4 ddr ) ddrc.rfc[19-16] : 1010b ( 10 clock cycles ) ddrc.rp[21-20] : 10b ( 3 clock cycles ) ddrc.ap[22] : 0 note-1 ddrc.rcd[24-23] : 10b ( 3 clock cycles ) ddrc.cl[26-25] : 01b ( 2.5 clock cycles ) ddrc.dbm[27] : 0 ( no data bus multiplexing ) ddrc.sds[28] : 0 ddrc.atp[30:29] : 01b ( 6 clock cycles ) ddrc.re[31] : 1 ( refresh enabled after initialization ) note-1: to facilitate the logic analyzer debug, it is recommended to enable the auto precharge. if auto precharge is enabled, the row being accessed is prechar ged at the completion of a read or write transac- tion.this would force row and column addres s on the bus for every read and write. please note that ap may need to be set if both the chip selects are being used. this may be required to preclude a scenario where accesses to the same ro w of the ddr bank is made for the two chip selects concurrently. prior to the completing the initialization of the ddr sdram, the program disables the refresh enable in the ddr controller. after completion of the initializati on, the refresh enable bit is set during the normal oper- ation of the ddr sdram. #define ddrc_val_at_init 0x232a4980 #define ddrc_val_normal 0xa32a4980 /* for 64mb ddr the address range for cs0 is 0x0000 0000 - 0x03ff ffff. the mask register for cs0 uses upper 6 bits: fc00_0000 for address comparison */ #define ddr0_base_val 0x00000000 #define ddr0_mask_val 0xfc000000
idt ddr controller example of ddr sdram initialization 79rc32438 user reference manual 7 - 27 november 4, 2002 notes /* since the cs1 is not used, disable it by writing 0x0 to its mask register */ #define ddr1_base_val 0x04000000 #define ddr1_mask_val 0x00000000 /* disable the alternate base register for now. this may be initialized during pci initialization */ #define ddr0_amask_val 0x00000000 the ddr refresh timer count value is det ermined by using the following equation: count x ddr_sdramrows x ticlk = < tref where ticlk is the ip bus clock peri od and tref is the ddr refresh timer. therefore, count = [tref ] / ( ddr_sdramrows x ticlk ). for mt46v16m16 device, periodic refresh interval per row is 7.8 microseconds. for 133 mhz ip bus clock speed ticlk = 1 / ( 133 x 10 6 ) = 7.51 nanoseconds. count = 7.8 x 10 -6 / ( 7.51 x 10 -9 ) =1038 (0x40e) #define ddr_ref_cmp_fast 0x100 /* initial refresh count value */ #define ddr_ref_cmp_val 0x40e /* final refresh count value */ #define ddr_ref_contl_val 0x1 /* enable counter */ on referring to the ddr device specification for mt46v16m16, followi ng defines are obtained to generate the various commands: #define ddr_cust_nop 0xfc #define ddr_cust_precharge 0xf1 #define ddr_cust_refresh 0xe5 #define ddr_ld_mode_reg 0x21 #define ddr_ld_emode_reg 0x61 #define ddr_emode_val 0x00 #define ddr_dll_res_mode_val 0x0161 #define ddr_dll_mode_val 0x0061 #define delay_200usec 25000
idt ddr controller example of ddr sdram initialization 79rc32438 user reference manual 7 - 28 november 4, 2002 notes during the first phase of the ddr sdram initializa tion, the rc32438 ddr contro ller registers are set. the code is as given below: /* load the ddr controller base address */ li t0, ddrbase /* store ddr0base */ li t1, ddr0_base_val sw t1, 0x0(t0) /* store ddr0mask */ li t1, ddr0_mask_val sw t1, 0x4(t0) /* load ddr1mask to disable cs1 */ li t1, ddr1_mask_val sw t1, 0x0c(t0) /* load ddr0amask to disable alternate mapping */ li t1, ddr0_amask_val sw t1, 0x18(t0) /* load the ddrc, reset refresh enable */ li t1, ddrc_val_at_init sw t1, 0x10 ( t0 ) /* read back the ddrc to flush cpu write buffers */ lw t1, 0x10 ( t0 ) during the second phase of the ddr initialization code, the sequence of commands suggested in the micron mt46v16m16 ddr sdram are executed as described below: 1. after power sequencing the dd ram power supply (vdd, vddq applied simultaneously following which vref and system vtt applied) , a delay of 200 microseconds has to be given prior to applying any command to the ddram. /* add 200 microseconds of delay */ li t1, 0x0 li t2, delay_200usec /* delay_200usec = 25000 */ 1:
idt ddr controller example of ddr sdram initialization 79rc32438 user reference manual 7 - 29 november 4, 2002 notes add t1, 1 bne t1, t2, 1b nop 2. apply a deselect or nop co mmand and cke should be brought high. /* register t0 carries pointer to the ddr_base: 0xb8018000 */ li t1, ddr_cust_nop sw t1, 0x20 ( t0 ) /* writ e to ddr custom transaction register */ /* perform a write to ddr s pace to register the command */ li t2, data_pattern li t1, 0xa0000000 sw t2, 0x0(t1) /* perform dummy read to flush cpu write buffer s. when executed from the uncached space such as eprom, flush cpu write buffer may not be needed. */ lw t1, 0x20 ( t0) 3. a precharge all command should be applied. /* register t0 carries pointer to the ddr_base: 0xb8018000 */ li t1, ddr_cust_precharge sw t1, 0x20 ( t0 ) /* writ e to ddr custom transaction register */ /* read it back to flush cpu write buffers */ lw t1, 0x20 ( t0) /* generate a10 high to pre-charge both the ban ks, data_pattern could have any value. */ li t2, data_pattern li t1, 0xa0000400 | ddr0_base_val sw t2, 0x0(t1) 4. issue a load mode register command to extended mode register to enable the dll. /* register t0 carries pointer to the ddr_base: 0xb8018000 */ li t1, ddr_ld_emode_reg sw t1, 0x20 ( t0 ) /* writ e to ddr custom transaction register */ /* generate emode register cont ents on address bus lines a12-a0 */ li t2, data_pattern li t1, 0xa0000000 | ddr_emode_val
idt ddr controller example of ddr sdram initialization 79rc32438 user reference manual 7 - 30 november 4, 2002 notes sw t2, 0x0(t1) /* perform a dummy read to flush cpu write buffers */ lw t1, 0x20 ( t0) 5. issue a load mode register command to m ode register to reset the dll and to program operating parameters such as burst length , burst type, cas latency, operating mode. /* register t0 carries pointer to the ddr_base: 0xb8018000 */ li t1, ddr_ld_mode_reg sw t1, 0x20 ( t0 ) /* writ e to ddr custom transaction register */ /* perform a dummy read to flush cpu write buffers */ lw t1, 0x20 ( t0 ) /* generate mode register content s on the address bus a12-a0 */ li t2, data_pattern li t1, 0xa0000000 | ddr_dll_res_mode_val sw t2, 0x0(t1) 6. a delay of 200 clock cycles is injected to allow dll reset to complete. /* delay of 1.6 microseconds ~ 300 delay iteration value */ li t1, 0x0 li t2, 300 1: add t1, 1 bne t1, t2, 1b nop 7. a precharge all command is applied to ddr sdram placing all banks in idle state. /* register t0 carries pointer to the ddr_base: 0xb8018000 */ li t1, ddr_cust_precharge sw t1, 0x20 ( t0 ) /* writ e to ddr custom transaction register */ /* read it back to flush cpu write buffers */ lw t1, 0x20 ( t0) /* generate a10 high to pre-charge both the banks */
idt ddr controller example of ddr sdram initialization 79rc32438 user reference manual 7 - 31 november 4, 2002 notes li t2, data_pattern li t1, 0xa0000400 | ddr0_base_val sw t2, 0x0(t1) 8. the ddr device requires at least two auto re fresh cycles to be perfo rmed prior to proceeding further. the code implements 9 cycles of auto refresh allowing sufficient margin. li t2, 9 li t3, 0 1: li t1, ddr_cust_refresh sw t1, 0x20 ( t0 ) /* writ e to ddr custom transaction register */ /* read it back to flush cpu write buffers */ lw t1, 0x20 ( t0) /* perform a write to ddr s pace to register the command */ li t2, data_pattern li t1, 0xa0000000 sw t2, 0x0(t1) add t3, 1 bne t3, t2, 1b nop 9. load mode register command is issued to deactivate the dll reset bit. /* register t0 carries pointer to the ddr_base: 0xb8018000 */ li t1, ddr_ld_mode_reg sw t1, 0x20 ( t0 ) /* writ e to ddr custom transaction register */ /* read it back to flush cpu write buffers */ lw t1, 0x20 ( t0) /* generate mode register contents on the address bus a12-a0 */ li t2, data_pattern li t1, 0xa0000000 | ddr_dll_mode_val sw t2, 0x0(t1)
idt ddr controller example of ddr sdram initialization 79rc32438 user reference manual 7 - 32 november 4, 2002 notes once the ddr device is initialized, the refres h timer needs to be programmed appropriately as step wise listed below: 1. initialize the refresh timer with fast refresh count li t0, rcount /* rcount= 0xb8028024 */ li t1, ddr_ref_cmp_fast /* set the rcompare regi ster, this zeroes rcount register */ sw t1, 0x4(t0) /* enable the refresh timer */ li t1, 0x1 /* ce set to enabled the refresh counter */ sw t1, 0x08(t0) 2. enable the refresh in the ddr controller register /* enable re-refresh enable in the ddrc register */ li t0, ddr_base li t1, ddrc_val_normal sw t1, 0x10(t0) /* read it back to flush the cpu write buffer */ lw t1, 0x10(t0) 3. add some delay to allow the ddr sdram to stabilize /* add 200 microseconds of delay */ li t1, 0x0 li t2, delay_200usec /* delay_200usec = 25000 */ 1: add t1, 1 bne t1, t2, 1b nop 4. change the refresh timer compare value to normal refresh rate: li t0, rcount
idt ddr controller example of ddr sdram initialization 79rc32438 user reference manual 7 - 33 november 4, 2002 notes /* disable the refresh counter bef ore changing the compare value */ li t1, 0x0 sw t1, 0x8(t0) /* set the rcompare register */ li t1, ddr_ref_cmp_val sw t1, 0x4(t0) /* enable the refresh timer */ li t1, 0x1 /* ce set to enabled the refresh counter */ sw t1, 0x08(t0) 5. add some delay for the ddr sdram to stabilize /* add 200 microseconds of delay */ li t1, 0x0 li t2, delay_200usec /* delay_200usec = 25000 */ 1: add t1, 1 bne t1, t2, 1b nop the ddr sdram is ready for use at this point.
idt ddr controller example of ddr sdram initialization 79rc32438 user reference manual 7 - 34 november 4, 2002 notes
notes 79rc32438 user reference manual 8 - 1 november 4, 2002 chapter 8 interrupt controller introduction this chapter describes the operation of the interr upt controller which multiplexes all the interrupt sources from on-chip modules and the gpio pins onto the five available interrupt sources of the cpu (ip[6:2]). these interrupt inputs correspond to the ip[6:2 ] bits of the cpu cp0 cause register. (ip[1:0] are software interrupts, and ip[7] is used by the counter timer in the cpu.) each of the ip[6:2] bits in the cpu cause regist er has three corresponding registers in the interrupt controller: ? the interrupt pending register, a 32-bit register that indicates the source of the interrupt. ? the interrupt mask register, a 32-bit register. each bit in the interrupt mask register corresponds to the equivalent bit in the interrupt pending regi ster. setting a bit in the interrupt mask register masks the generation of an interrupt for this source. ? the interrupt test register, a 32-bit register. each bi t in the interrupt test register corresponds to a bit in the interrupt pending register. setting a bit in the interrupt test register causes the same behavior as an interrupt request from the corres ponding interrupt source in the interrupt pending register. this register may be used to test so ftware interrupt handlers without the need to actually generate the condition required to produce an interrupt request. the interrupt controller has no prio rity levels. all sources have the sa me priority. if multiple interrupts are pending, it is the responsibility of the software to assign any priority. the interrupt controller multiplexes the interrupt sour ces to the cpu. the interrupt clearing or assertion may take several clock cycles to show up in the in terrupt pending register, depend ing on the source of the interrupt. to clear the interrupt, the software must clear the source. features ? allows status of all interrupt sources to be read ? each interrupt source may be masked ? provides interrupt test capability
idt interrupt controller block diagram 79rc32438 user reference manual 8 - 2 november 4, 2002 notes block diagram figure 8.1 mapping of interrupts to the cpu cause register interrupt controller register description register offset 1 1. the address of the register is equal to the regi ster offset added to the base value of 0x1800_0000. register name register function size 0x03_8000 ipend2 interrupt pending 2 32-bit 0x03_8004 itest2 interrupt test 2 32-bit 0x03_8008 imask2 interrupt mask 2 32-bit 0x03_800c ipend3 interrupt pending 3 32-bit 0x03_8010 itest3 interrupt test 3 32-bit 0x03_8014 imask3 interrupt mask 3 32-bit 0x03_8018 ipend4 reserved 32-bit 0x03_801c itest4 reserved 32-bit 0x03_8020 imask4 reserved 32-bit 0x03_8024 ipend5 interrupt pending 5 32-bit 0x03_8028 itest5 interrupt test 5 32-bit 0x03_802c imask5 interrupt mask 5 32-bit 0x03_8030 ipend6 interrupt pending 6 32-bit 0x03_8034 itest6 interrupt test 6 32-bit 0x03_8038 imask6 interrupt mask 6 32-bit 0x03_803c nmips non-maskable interrupt pin status 32-bit 0x03_8040 through 0x03_ffff reserved table 8.1 interrupt controller register map ipend2 ipend3 ipend4 ipend5 ipend6 imask2 imask3 imask4 imask5 imask6 ip[2] ip[3] ip[4] ip[5] ip[6] 31 0 ... 31 0 ... 31 0 ... 31 0 ... 31 0 ... rc32438 mips32 cpu interrupt controller registers cause register
idt interrupt controller interrupt controller register description 79rc32438 user reference manual 8 - 3 november 4, 2002 notes interrupt pending [2..6] register note: ipend4 is reserved. use only ipend2, ipend3, ipend5, and ipend6. figure 8.2 interrupt pending [2..6] register (ipend[2..6]) interrupt test [2..6] register note: itest4 is reserved. do not use. figure 8.3 interrupt test [2..6] register (itest[2..6]) ipend description: interrupt pending. each bit in this field corresponds to an interrupt source. when a bit is set the corresponding interrupt source is requesting service. note that this register shows interrupts which are currently requesting service but may be ?masked? from actually generating an interrupt exception. initial value: undefined read value: status write effect: read-only itest description: interrupt test. each bit in this field corresponds to an interrupt source in the corresponding inter- rupt pending (ipend) register. when a bit in this field is set, it appears to the interrupt controller that the corresponding interrupt source in the ipend register is requesting service. initial value: 0x0 read value: previous value written write effect: modify value ipend[2..6] 0 31 32 ipend itest[2..6] 0 31 32 itest
idt interrupt controller int errupt status description 79rc32438 user reference manual 8 - 4 november 4, 2002 notes interrupt mask [2..6] register note: imask4 is reserved. do not use. figure 8.4 interrupt mask [2..6] register (imask[2..6]) interrupt status description imask description: interrupt mask. each bit in this register masks the corresponding interrupt source in the ipendx register. when a bit in this field is set, the corresp onding interrupt source (as well as interrupt test bit) is masked from generating an interrupt exception. initial value: bits that correspond to an interrupt source in the ipendx register are initialized to 0x1. reserved bits are initialized to 0x0 and cannot be modified. read value: previous value written write effect: modify value bit interrupt/status description refer to 0 counter timer 0. corresponds to the to bit in the ctc0 register. chapter 14 1 counter timer 1. corresponds to the to bit in the ctc1 register. chapter 14 2 counter timer 2. corresponds to the to bit in the ctc2 register. chapter 14 3 refresh timer. corresponds to to bit in the rtc register. chapter 7 4 watchdog timer time-out. corresponds to to bit in the wtc register. chapter 4 5 undecoded cpu write. corresponds to ucw bit in the errcs register. chapter 4 6 undecoded cpu read. corresponds to ucr bit in the errcs register. chapter 4 7 undecoded pci write. corresponds to upw bit in the errcs register. chapter 4 8 undecoded pci read. corresponds to upr bit in the errcs register. chapter 4 9 undecoded dma write. corresponds to udw bit in the errcs register. chapter 4 10 undecoded dma read. corresponds to udr bit in the errcs register. chapter 4 11 ipbus slave acknowledge error. corresponds to sae bit in the errcs register. chapter 4 12 ipbus monitor final trigger event . corresponds to ft bit in ipbmtcfg register. chapter 18 13 ipbus monitor recording completed . corresponds to rc bit in ipbmtcfg register. chapter 18 14 event monitor 0 triggered event . corresponds to t bit in em0compare register. chapter 18 15-31 reserved table 8.2 ipend2 interrupt source description imask[2..6] 0 31 32 imask
idt interrupt controller int errupt status description 79rc32438 user reference manual 8 - 5 november 4, 2002 notes bit interrupt/status description refer to 0 dma channel 0. or of the bits in the dma0s not masked by dma0sm. chapter 9 1 dma channel 1. or of the bits in the dma1s not masked by dma1sm. chapter 9 2 dma channel 2. or of the bits in the dma2s not masked by dma2sm. chapter 9 3 dma channel 3. or of the bits in the dma3s not masked by dma3sm. chapter 9 4 dma channel 4. or of the bits in the dma4s not masked by dma4sm. chapter 9 5 dma channel 5. or of the bits in the dma5s not masked by dma5sm. chapter 9 6 dma channel 6. or of the bits in the dma6s not masked by dma6sm. chapter 9 7 dma channel 7. or of the bits in the dma7s not masked by dma7sm. chapter 9 8 dma channel 8. or of the bits in the dma8s not masked by dma8sm. chapter 9 9 dma channel 9. or of the bits in the dma9s not masked by dma9sm. chapter 9 10 - 31 reserved table 8.3 ipend3 interrupt source description bit interrupt/status description refer to 0 uart general interrupt 0 . chapter 13 1 uart txrdy 0 interrupt . chapter 13 2 uart rxrdy 0 interrupt . chapter 13 3 uart general interrupt 1 . chapter 13 4 uart txrdy 1 interrupt . chapter 13 5 uart rxrdy 1 interrupt . chapter 13 6 pci interrupt . or of bits in pcis not masked by pcism. chapter 10 7 pci decoupled access interrupt. or of bits in the pcidas register not masked by pcidasm. chapter 10 8 spi interrupt. corresponds to spif and modf bits in the sps register. chapter 16 9 device decoupled operation done. corresponds to the f bit in the devdacs regis- ter. chapter 6 10 i2c-bus master interface interrupt . or of bits in i2cms not masked by i2cmsm. chapter 15 11 i2c-bus slave interface interrupt . or of bits in i2css not masked by i2cssm. chapter 15 12 ethernet 0 input fifo overflow . corresponds to ovr bit in eth0intfc register. chapter 11 13 ethernet 0 output fifo underflow . corresponds to und bit in eth0intfc register. chapter 11 14 ethernet 0 pause frame done. corresponds to pfd bit in eth0os register. chapter 11 15 ethernet 1 input fifo overflow . corresponds to ovr bit in eth1intfc register. chapter 11 16 ethernet 1 output fifo underflow . corresponds to und bit in eth1intfc register. chapter 11 17 ethernet 1 pause frame done. corresponds to pfd bit in eth1os register. chapter 11 18-31 reserved table 8.4 ipend5 interrupt source description
idt interrupt controller non-maskable interrupts 79rc32438 user reference manual 8 - 6 november 4, 2002 notes non-maskable interrupts ? sources of non-maskable interrupts ? watchdog timer time-out ? setting the nmi bit in the pci management (pmgt) register ? gpio pin(s) programmed to generate an nmi ? the source of an nmi may be determined by checking corresponding status registers bit interrupt/status description refer to 0 gpio 0. corresponds to bit 0 of the gpioistat register. chapter 12 1 gpio 1. corresponds to bit 1 of the gpioistat register. chapter 12 2 gpio 2. corresponds to bit 2 of the gpioistat register. chapter 12 3 gpio 3. corresponds to bit 3 of the gpioistat register. chapter 12 4 gpio 4. corresponds to bit 4 of the gpioistat register. chapter 12 5 gpio 5. corresponds to bit 5 of the gpioistat register. chapter 12 6 gpio 6. corresponds to bit 6 of the gpioistat register. chapter 12 7 gpio 7. corresponds to bit 7 of the gpioistat register. chapter 12 8 gpio 8. corresponds to bit 8 of the gpioistat register. chapter 12 9 gpio 9. corresponds to bit 9 of the gpioistat register. chapter 12 10 gpio 10. corresponds to bit 10 of the gpioistat register. chapter 12 11 gpio 11. corresponds to bit 11 of the gpioistat register. chapter 12 12 gpio 12. corresponds to bit 12 of the gpioistat register. chapter 12 13 gpio 13. corresponds to bit 13 of the gpioistat register. chapter 12 14 gpio 14. corresponds to bit 14 of the gpioistat register. chapter 12 15 gpio 15. corresponds to bit 15 of the gpioistat register. chapter 12 16 gpio 16. corresponds to bit 16 of the gpioistat register. chapter 12 17 gpio 17. corresponds to bit 17 of the gpioistat register. chapter 12 18 gpio 18. corresponds to bit 18 of the gpioistat register. chapter 12 19 gpio 19. corresponds to bit 19 of the gpioistat register. chapter 12 20 gpio 20. corresponds to bit 20 of the gpioistat register. chapter 12 21 gpio 21. corresponds to bit 21 of the gpioistat register. chapter 12 22 gpio 22. corresponds to bit 22 of the gpioistat register. chapter 12 23 gpio 23. corresponds to bit 23 of the gpioistat register. chapter 12 24 gpio 24. corresponds to bit 24 of the gpioistat register. chapter 12 25 gpio 25. corresponds to bit 25 of the gpioistat register. chapter 12 26 gpio 26. corresponds to bit 26 of the gpioistat register. chapter 12 27 gpio 27. corresponds to bit 27 of the gpioistat register. chapter 12 28 gpio 28. corresponds to bit 28 of the gpioistat register. chapter 12 29 gpio 29. corresponds to bit 29 of the gpioistat register. chapter 12 30 gpio 30. corresponds to bit 30 of the gpioistat register. chapter 12 31 gpio 31. corresponds to bit 31 of the gpioistat register. chapter 12 table 8.5 ipend6 interrupt source description
idt interrupt controller non-maskable interrupts 79rc32438 user reference manual 8 - 7 november 4, 2002 notes non-maskable interrupt pin status register figure 8.5 non-maskabl e interrupt pin status gpio description: gpio non-maska ble interrupt. a gpio non-maskable interrupt causes this sticky bit to be set. a gpio non-maskable interrupt occurs when a bit in gpiostat register is set and the corre- sponding bit is set in gpionmien register (see chapter 12). the assertion of this bit results in a non-maskable interrupt. initial value: 0x0 read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) nmips 0 31 0 31 gpio 1
idt interrupt controller non-maskable interrupts 79rc32438 user reference manual 8 - 8 november 4, 2002 notes
notes 79rc32438 user reference manual 9 - 1 november 4, 2002 chapter 9 dma controller introduction the dma controller consists of 10 independent dma c hannels, all of which operate in exactly the same manner. all dma channels support fly-by dma oper ations between memory and a peripheral device. 1 a single dma channel may be multiplexed among two different devices using the device select (ds) field in a dma descriptor (refer to table 9.2). the exter nal dma channels (i.e., dma channels 0 and 1) use the device select field to determine the direction of the dm a transfer (memory to exter nal peripheral or external peripheral to memory). the ds field is unused by the other dma channels and must be set to zero. features ? 10 dma channels ? two channels for pci (pci to memory and memory to pci) ? four ethernet channels ? two for each et hernet interface (transmit/receive) ? two dma channels for memory to memory dma operations ? two dma channels for external dma operations ? provides flexible des criptor based operation ? supports external peripheral dma operations ? supports unaligned transfers (i.e ., source or destination addres s may be on any byte boundary) with arbitrary byte length dma registers 1. dma operations are automatically supported across memory regions (for example, across ddr bank 0 and ddr bank 1) as long as the physical addresses are contiguous and the memory regions have a size which is greater than 64 kb. register offset 1 register name register function size 0x04_0000 dma0c dma 0 control 32-bit 0x04_0004 dma0s dma 0 status 32-bit 0x04_0008 dma0sm dma 0 status mask 32-bit 0x04_000c dma0dptr dma 0 descriptor pointer 32-bit 0x04_0010 dma0ndptr dma 0 next descriptor pointer 32-bit 0x04_0014 dma1c dma 1 control 32-bit 0x04_0018 dma1s dma 1 status 32-bit 0x04_001c dma1sm dma 1 status mask 32-bit 0x04_0020 dma1dptr dma 1 descriptor pointer 32-bit 0x04_0024 dma1ndptr dma 1 next descriptor pointer 32-bit 0x04_0028 dma2c dma 2 control 32-bit 0x04_002c dma2s dma 2 status 32-bit table 9.1 dma register map (part 1 of 3)
idt dma controller dma registers 79rc32438 user reference manual 9 - 2 november 4, 2002 notes 0x04_0030 dma2sm dma 2 status mask 32-bit 0x04_0034 dma2dptr dma 2 descriptor pointer 32-bit 0x04_0038 dma2ndptr dma 2 next descriptor pointer 32-bit 0x04_003c dma3c dma 3 control 32-bit 0x04_0040 dma3s dma 3 status 32-bit 0x04_0044 dma3sm dma 3 status mask 32-bit 0x04_0048 dma3dptr dma 3 descriptor pointer 32-bit 0x04_004c dma3ndptr dma 3 next descriptor pointer 32-bit 0x04_0050 dma4c dma 4 control 32-bit 0x04_0054 dma4s dma 4 status 32-bit 0x04_0058 dma4sm dma 4 status mask 32-bit 0x04_005c dma4dptr dma 4 descriptor pointer 32-bit 0x04_0060 dma4ndptr dma 4 next descriptor pointer 32-bit 0x04_0064 dma5c dma 5 control 32-bit 0x04_0068 dma5s dma 5 status 32-bit 0x04_006c dma5sm dma 5 status mask 32-bit 0x04_0070 dma5dptr dma 5 descriptor pointer 32-bit 0x04_0074 dma5ndptr dma 5 next descriptor pointer 32-bit 0x04_0078 dma6c dma 6 control 32-bit 0x04_007c dma6s dma 6 status 32-bit 0x04_0080 dma6sm dma 6 status mask 32-bit 0x04_0084 dma6dptr dma 6 descriptor pointer 32-bit 0x04_0088 dma6ndptr dma 6 next descriptor pointer 32-bit 0x04_008c dma7c dma 7 control 32-bit 0x04_0090 dma7s dma 7 status 32-bit 0x04_0094 dma7sm dma 7 status mask 32-bit 0x04_0098 dma7dptr dma 7 descriptor pointer 32-bit 0x04_009c dma7ndptr dma 7 next descriptor pointer 32-bit 0x04_00a0 dma8c dma 8 control 32-bit 0x04_00a4 dma8s dma 8 status 32-bit 0x04_00a8 dma8sm dma 8 status mask 32-bit 0x04_00ac dma8dptr dma 8 descriptor pointer 32-bit 0x04_00b0 dma8ndptr dma 8 next descriptor pointer 32-bit 0x04_00b4 dma9c dma 9 control 32-bit 0x04_00b8 dma9s dma 9 status 32-bit 0x04_00bc dma9sm dma 9 status mask 32-bit register offset 1 register name register function size table 9.1 dma register map (part 2 of 3)
idt dma controller data flow within the rc32438 79rc32438 user reference manual 9 - 3 november 4, 2002 notes data flow within the rc32438 the rc32438 is primarily an engine designed to effi ciently move data between interfaces. data is received from one of the interfaces, stored in the ma in memory, then transferred out on another interface. thus, understanding the operation data flow within t he rc32438 is very important in understanding the behavior of the device and how to optimize the internal resources to meet the needs of the various applica- tions. the ipbus? the internal ipbus in the rc32438 is the backbone of the device and is connected to every module in the rc32438. it is used to transfer all the data within the device and to make the connection between the external main memory and the on-chip peripherals. t here are two potential bus masters on the ipbus: the cpu core and the dma controller (through one of it s dma channels). the processor core and the dma controller must arbitrate to acquire ownership of the ipbus (as described in chapter 5, bus arbitration). once the ipbus is granted to a master, data can be transferred within the rc32438. all other interfaces connected to the ipbus are slaves, including the device controller. to transfer data, one of the bus masters must request data from or send data to the slave. none of the on-chip peripherals on the rc32438 have i pbus mastership capability. rather, each has its internal fifo to buffer the incoming and the outgoi ng data. the peripheral receives output data from the ipbus (either dma or cpu) in its transmit fifo and sends it out the interface bus. or it receives input data from the interface bus in its receive fifo and requests service from an ipbus master through an interrupt or status flag to the cpu or a request to the dma cont roller. the internal fifos are only used to compensate for the ipbus arbitration and access latency. the ex ternal memory (ddr or memory/io) is used as the primary storage location for the incoming and outgoing data. thus, all the data movement within the rc32438 must pass through the memory ? either ddr through the ddr controller, or sram / dual port through the device controller. the dma controlle r can transfer data between peripherals via external memory. as an example, input data from the ethernet port will be stored in external memory first. the cpu will then process the data for appropriate protocol c onversion. the data will then be transferred from the ddr memory to the pci interface. the cpu core can access any of the on-chip peri pherals for data transfer and reception. some periph- erals, like the ethernet interface and pci interfac e, have associated dma channels that can be used to transfer and receive data. 4kc core as bus master when the 4kc processor core is the ipbus master, it can read and write data from or to any peripheral to transmit and receive the data. this is accomplis hed through the execution of the standard load and store instructions of the 4kc core. this usually includes several steps: the 4kc core loads the data from main memory into one of its internal registers and then writes it to the peripherals for transmission. the reverse occurs for the reception of data. usually, the inter nal peripherals will be accessed as non-cached entries by the processor core. however, the use of the prefetch -with-ignore-hit instruction enables the processor core to treat some of the peripherals as cached entries, t hus speeding up the processing of the data by the 4kc core. this usually is used when the 4kc core needs to process the header of a packet for decision making. for most of the slow peripherals (like i 2 c), using the processor core is more than adequate to maintain the 0x04_00c0 dma9dptr dma 9 descriptor pointer 32-bit 0x04_00c4 dma9ndptr dma 9 next descriptor pointer 32-bit 0x04_00c8 through 0x04_3fff reserved 1. the address of the register is e qual to the register offset added to the base value of 0x1800_0000. register offset 1 register name register function size table 9.1 dma register map (part 3 of 3)
idt dma controller data flow within the rc32438 79rc32438 user reference manual 9 - 4 november 4, 2002 notes speed requirements of the interface. however, for fast in terfaces like ethernet, using the core to transfer the data is not recommended. rather, the associated dm a channels should be used to maintain the wire speed of these interfaces. dma controller as mentioned above, a dma channel should be used with a fast peripheral to maintain the wire speed on the interface. the dma controller plays a critic al role in the data movement within the rc32438 and in maintaining the wire speed on the various interfaces . the dma controller is one of the most complex blocks on the rc32438 and offers a number of capabilit ies tailored to enhance data movement capabilities. understanding the operation of the dma controller is critical to unde rstanding the operation and the data movement within the rc32438. the dma controller is tightly coupled to the internal ipbus and to the various on chip peripherals to enable the rc32438 to meet the wire speed of the various interfaces. figure 9.1 illustrates a simplified block diagram of the dma controller and the internal ipbus on the rc32438. figure 9.1 dma block diagram the dma controller supports ten dma channels. these dma channels can be grouped into two catego- ries: dedicated channels and multiplexed channels. ea ch of the dedicated dma channels service only one peripheral in one direction (input or output). as an example, dm a channel 2 services the ethernet controller in the input direction only. the multip lexed dma channels service more than one peripheral in both directions. the dma controller implements fl y-by dma operations. a fly-by operation transfers data between an on-chip peripheral and memory using a single transaction. non-fly-by op erations require two transactions: ? one to move data between an on-chip peripheral and an internal buffer ? another to move the data from the internal buffer to memory. the dma controller arbitrates for the ipbus and then monitors the fly-by transfer of data between the memory controller and the on-chip peripheral. the fly-by implementation enhances the bandwidth of the dma because it eliminates the extra clock cycles that would be needed to temporarily store the data. the dma controller supports any length of packet trans fer. each packet is divided into bursts of up to 16 words maximum. some interfaces can generate smaller bursts. the dma controller re-arbitrates for the ipbus at the end of each burst transfer. the maximum burst size of 16 words enables the software to main- tain a balance between the dma transfers and the 4kc core instruction fetches and data transfers. no alignment restrictions to support the needs of most data communication protocols and standard data communication drivers, the dma controller does not impose any alignment rest rictions on the data. the data in memory to be transferred by the dma controller can be located any where in the main memory and start on any byte boundary. for example, the data to be transferred can start at byte 2 within a word and be 1000 bytes long. dma state machine ipbus channel 0 channel 9 ddr controller ddr on-chip peripherals device controller other memory rc32438 external systems pmbus
idt dma controller data flow within the rc32438 79rc32438 user reference manual 9 - 5 november 4, 2002 notes similarly, the received data can be stored anywhere in the main memory without any byte alignment or length restrictions. further, there is no relationship required between the alignment or length of the trans- mitted data and the received data. for example, the received data can start at byte 3 within the word and be 561 bytes long. data flow using the dma controller the reception and transmission of data using the dma co ntroller follows a series of standard steps. for the data reception, the following steps highli ght the data and control flow within the rc32438. 1. the 4kc processor core initializes the dma channel for the desired peripheral. 2. the peripheral starts receiving the data in its input fifo. depending on the peripheral used, once the required number of bytes are received in the fi fo or when an ?end of packet? is received, the peripheral places a dma request with its associated dma channel. 3. the dma channel transfers the dat a from the peripheral to memory. 4. the dma controller can be configured to generate an interrupt to the 4kc core when it completes transferring a packet to memory. this signals t he 4kc core to begin executing software for higher level protocol processing. the transmission of the data follows the same steps in reverse order. the following steps highlight the data and control flow within the rc32438 when data is transmitted. 1. the upper layer software stacks ready the data for transmission. 2. the 4kc core sets up the dma channel for transmission. 3. the dma channel transfers the data from me mory to the output fifo of the peripheral. 4. the peripheral transmi ts the data on its bus. 5. the operation continues until the end of the packet. this usually triggers an interrupt to the 4kc core which ends the dma operation. figure 9.2 illustrates the simplified dat a movement operation within the rc32438. figure 9.2 anatomy of dma operations memory-to-memory transfer the dma controller has a 16-word internal fifo t hat is only used during memo ry-to-memory transfers. this fifo is needed to temporarily store the data between transfers. to do a memory-to-memory dma operation, the data is read from the source memory, stored in the dma fifo, then written in the destination memory. only dma channels 6 and 7 can be us ed for memory-to-memory dma operations. note: memory-to-memory dma operations using c hannel 6 will not start until channel 7 is started. the maximum burst size is limited by the dma fifo size and is fixed at 16 words. source and destination memories can be any ty pe of memory or device connected to the ddr controller or the device controller. endianness swapping is not supported during memory-to-memory dma. dma state machine ipbus channel 0 channel 9 ddr controller ddr on-chip peripherals 1. issue request to transfer data 2. appropriate channel is 3. load descriptor from ddr 4. transfer data 5. store descriptor to memory and end the transfer selected
idt dma controller dma channels 79rc32438 user reference manual 9 - 6 november 4, 2002 notes memory-to-memory dma is illustrated in figure 9.3. figure 9.3 memory to memory dma transfers dma channels dma channel device select device description channel 0 0 external dma channel 0 (external peripheral to memory) 1 external dma channel 0 (memory to external peripheral) 2 reserved 3 reserved channel 1 0 external dma channel 1 (external peripheral to memory) 1 external dma channel 1 (memory to external peripheral) 2 reserved 3 reserved channel 2 0 ethernet channel 0 receive 1 reserved 2 reserved 3 reserved channel 3 0 ethernet channel 0 transmit 1 reserved 2 reserved 3 reserved channel 4 0 ethernet channel 1 receive 1 reserved 2 reserved 3 reserved channel 5 0 ethernet channel 1 transmit 1 reserved 2 reserved 3 reserved table 9.2 dma channels and device selects (part 1 of 2) dma state machine ipbus channel 6 channel 9 ddr controller ddr on-chip peripherals on-chip dma 16 word fifo no endianness swapping supported source/destination can be memory, io, ddr 1. channel 6 reads the data. 2. channel 7 writes the data.
idt dma controller internal dma operation 79rc32438 user reference manual 9 - 7 november 4, 2002 notes internal dma operation all dma operations are performed by reading dma descr iptors from memory. a dma descriptor is read from memory to determine control information when a dma descriptor operation begins, and is written back to memory with updated status information when a dma descriptor operation completes. as shown in figure 9.4, a dma descriptor consists of four words and must be word aligned. 1 the first word of a descriptor contains general dma cont rol and status information, such as the count field which holds the number of bytes to transfer. 2 the three bit device command (devcmd) field is used to pass device specific control information to a peripheral at the start of a dma descriptor operation, and to record peripheral status information at the end of a dma descriptor operat ion. when a dma descriptor operation begins, devcmd is read from memory and transferred to the select ed device. when a dma descriptor operation completes, updated status information is read from the selected device and written back to the devcmd field of the dma descriptor in memory. the device select (ds) fi eld selects the peripheral device to be used during the dma descriptor operation. the encoding of this field for each of the ten dma channels is shown in table 9.2. the second word of a dma descriptor, the current addres s (ca) field, is initialized with the address of a data buffer to which data dmaed from a peripheral is written, or from which data dmaed to a peripheral is read. when a dma descriptor operation begins, the st arting address is loaded into a current address register in the dma controller. after each dma data trans fer, the current address register is modified by the size of the data transfer. thus, when a dma descrip tor operation completes, the ca field of the dma descriptor in memory contains the address of the next data quantity to be transferred had the dma descriptor operation not completed. for example, if ca is initialized to x and count is initialized to y during a dma operation from a peri pheral to memory, then the first data quantity from the peripheral would be written to physical address x . assuming the dma descriptor operati on runs until the count field reaches zero, the value of the ca field in memory when the dma operation completes would be x + y . the third word of a dma descriptor, the device cont rol and status (devcs) field, is used to pass device specific control information to a peripheral at the st art of a dma descriptor operation, and to record periph- eral status information at the end of a dma descrip tor operation. when a dma des criptor operation begins, channel 6 0 memory to memory (memory to holding fifo) 1 reserved 2 reserved 3 reserved channel 7 0 memory to memory (holding fifo to memory) 1 reserved 2 reserved 3 reserved channel 8 0 pci (pci to memory) 1 reserved 2 reserved 3 reserved channel 9 0 pci (memory to pci) 1 reserved 2 reserved 3 reserved 1. the address 0x0000_0000 is used to indicate the end of a dma descriptor list. therefore, a dma descriptor may begin at any word address except 0x0000_0000. 2. the dma controller supports zero length dma operations (i.e., descriptors with the count field equal to zero). zero length dma operations result in the transfer of devcmd and devcs as well as the updating of the dma descriptor but cause no data to be transferred. dma channel device select device description table 9.2 dma channels and device selects (part 2 of 2)
idt dma controller internal dma operation 79rc32438 user reference manual 9 - 8 november 4, 2002 notes devcs is read from memory and transferred to t he selected device. when a dma descriptor operation completes, updated status information is read from the selected device and written back to the devcs field of the dma descriptor in memory. the fourth word of a dma descriptor, the link (link) field, contains the physical address of the next dma descriptor in a descripto r list (i.e., the next dma descriptor in a linked list of dma descriptors).the link field is set to zero in the last descriptor within a descriptor list. dma descriptor register figure 9.4 dma descriptor register f finished. this bit is set when the dma controller finishes descriptor processing due to a finished event (count equal to zero). note that this bit is not cleared if the condition did not occur. if this bit is initially set in the descriptor register and the condition causing the dma transaction to stop is not related to this bit, then this bit will remain set in the dma descriptor written back to memory. d done. this bit is set when the dma controller finishes descriptor processing due to a done event (selected device generates done). note that this bit is not cleared if the condition did not occur. if this bit is initially set in the descriptor register and the condition causing the dma transaction to stop is not related to this bit, then this bit will remain set in the dma descriptor written back to memory. t terminated. this bit is set when dma descriptor processing is abnormally terminated. this occurs when the run bit in the dma control register is cleared during a dma operation, or when the bus transaction timer times-out during a dma bus transaction. note that this bit is not cleared if the condi- tion did not occur. if this bit is initially set in the descriptor register and the condition causing the dma transaction to stop is not related to this bit, then this bit will remain set in the dma descriptor written back to memory. iod interrupt on done. when this bit is set, and the dma controller finishes descriptor processing due to a done event, then the d bit in the dmaxs register is set. iof interrupt on finished. when this bit is set, and the dma controller finishes descriptor processing due to a finished event, then the f bit in the dmaxs register is set. cod chain on done. when this bit is set, and the dma controller finishes descriptor processing due to a done event, then the dma controller loads the next descriptor pointed to by the dmaxndptr register. cof chain on finished. when this bit is set and the dma controller finishes descriptor processing due a finished event, then the dma controller loads the next descriptor pointed to by the dmaxndptr reg- ister. devcmd device command. this field is a device specific command field which is passed to the selected device at the start of a dma operation. ds device select. this field selects the peripheral device used during the dma descriptor operation. see table 9.2 on page 9-6 for the encoding of this field. count byte count. this field specifies the number of bytes to transfer during the dma descriptor operation. ca current address. this 32-bit field is initialized with the dma starting address at the start of a dma operation and is updated when descriptor processing is completed. ca f d iod iof cod cof 1 1 1111 devcmd ds count devcs link t 1 18 32 reserved 2
idt dma controller internal dma operation 79rc32438 user reference manual 9 - 9 november 4, 2002 notes dma registers each dma channel has five registers. a channel is controlled by a dma contro l (dma[0..9]c) register, and the status of a dma channel is reported in a dm a status (dma[0..9]s) register. the bits in a dma status register, which are not masked by the corres ponding dma status mask (dma[0..9]sm) register, are ored together and presented to the interrupt controll er. a dma operation is begun by writing the starting address of the first descriptor in a descriptor list into the dma descript or pointer (dma[0..9]dptr) register of a dma channel. as a side effect of writing this register, a dma operation begi ns and the run (run) bit in the corresponding dmaxc register is set. the dma channel performs dm a descriptor processing, executing the dictated dma descriptor operations until a dma descriptor is reached with a zero in its link field. this signals the completion of dma operation and causes the run bit in the dmaxc register to be cleared and the halt (h) bit in the dmaxs register to be set. during dma descriptor processing, the dmaxdptr register may be read to determine the addr ess of the descriptor currently being processed. dma stopping conditions a dma descriptor operation has three stopping conditions: finished, done , and terminated . the stopping conditions which cause a descriptor operation to comp lete is recorded in the finished (f), done (d), and terminated (t) bits of the first word in a descripto r. when the dma controller updates the first word of a descriptor, only the f, d, and t bits ar e set. for example, if the t bit was initially set in the descriptor and the dma stopping condition was finished , the t bit would remain set in the descriptor written back to memory. finished condition: when a dma operation begins, the count field is loaded from the descriptor in memory into a byte counter associated with the dma channel. the byte counter is decremented by the dma transfer size after each data transfer. the fi nished stopping condition occu rs when the byte counter reaches zero (i.e., there are no more bytes to transfer) . this causes the f bit in the dma descriptor to be set. if the interrupt on finished (iof) bit in the descriptor has been initialized to a one, then the f bit in the dmaxs register is also set. if the chain on finished (cof) bit in the de scriptor has been initialized to a one, then a dma chaining operation takes place. done condition: the done stopping condition occurs when the selected device signals a done event. done events allow a selected peripheral to terminate a dma operation at an arbitrar y point (for example, at the end of packet). the done stopping condition occurs when a done event is signalled by the selected peripheral device. this causes the d bit in the dma descriptor to be set. if the interrupt on done (iod) bit in the descriptor has been initialized to a one, then the d bit in the dmaxs register is also set. if the chain on done (cod) bit in the descriptor has been initialized to a one, then a dma chaining operation takes place. it is possible for a dma descriptor operation to complete due to multiple stopping conditions. for example, it is possible to have a simultaneous fi nished and done stopping condition which causes both the f and d bits in the dma descriptor to be set. terminated condition: a dma operation is halted when the run bit in the dmaxc register is cleared. a halted dma operation results in a terminated st opping condition for the descriptor being processed and causes the dma operation to complete. when this occurs, the dma controller performs the following: discontinues the current dma descriptor operation, sets the t bit, and updates all other status information in the descriptor. the descriptor contents are then wr itten back to memory. when the descriptor write completes, the halt (h) bit in the dmaxs register is set to acknowledge that the dma operation has been halted. when a dma operation is halted by clearing the run bit, writes to the dmaxdptr and dmax- ndptr should not be performed unt il the halt (h) bit is set. note: under certain conditions the terminated status bit is not set. an example is when a zero length dma operation is performed. devcs device control and status. this 32-bit field is initialized with peripheral device specific control infor- mation. when descriptor processing completes, this field is updated with peripheral specific status information. link link. this 32-bit field points to the next descriptor in the descriptor list.
idt dma controller internal dma operation 79rc32438 user reference manual 9 - 10 november 4, 2002 notes the dma controller may be incorrectly programm ed with an address which does not map to a valid device. when this occurs, the address space monitor reports an error to the dma controller. if the dma controller attempts to read a dma descriptor from an un-decoded address, the dma operation is terminated causing the error (e) bit and the halt (h) bit to be se t in the dmaxs register and the run bit to be cleared the dmaxc register. if the dma controller attempts to read or write a dma data buffer that corresponds to an undecoded address, then the dma oper ation is terminated. this resu lts in the dma discontinuing the current dma descriptor operation, clearing the run bi t in the dmaxs register, setting the t bit in the descriptor, and updating all other status information in the descriptor. once the descriptor contents are written back to memory, the halt (h) bit and er ror (e) bit in the dmaxs register are set. clearing the run bit in the dmaxc register prov ides a means of orderly halting a dma operation but sometimes a need exists to abort a dma operation wit hout cooperation from the peripheral. for example, resetting a peripheral during a dma operation may make it impossible to halt a dma operation since the dma will wait indefinitely for the peripheral to supply updated devcs and devcmd values. a dma opera- tion may be aborted without cooperation fr om a peripheral by writing a one to the abort (a) bit in the dmaxc register. this causes the dma channel to complete the current dma transaction on the bus if one is in progress, write back the descriptor 1 with the terminated (t) bit set, set the halt (h) bit in the dmaxs register, and clear the run bit. if a dm a operation is aborted while the dma is in the process of following a link or performing a chaining operation, the term inated bit will not be set in any descriptor. dma request event a dma request event causes a data quantum to be transferred by the dma c ontroller between a periph- eral device and memory. the amount of data contained in a dma quantum is defined by the dma transfer size. the dma transfer size is specified for each per ipheral device and is the amount of data transferred by the dma controller when it gains ownership of the ip bus. the mode field in the dmaxc regi ster allows the dma to be configured to operate in one of three modes: auto request, burst request, and transfer reques t. in auto request mode, dma request events generated by the selected peripheral device are ignored, and the dma controller generates internal request events at the maximum possible rate. this causes a bl ock of data to be transferred by the dma controller without the need for dma request events to be generated by the peripheral device. in burst request mode, a dma request event signalled by the selected peripheral device causes the dma controller to begin internally generating reques t events until the dma operation completes. thus, in this mode the first request event generated by the peripher al signals the start of a burst transfer. this mode allows the peripheral device to externally signal the beginning of a burst dma operation. in transfer request mode, a dma request event signall ed by the selected peripheral device causes the dma controller to transfer a single data quantum between the peripheral device and memory. thus, for each data quantum of a dma operation, the peripheral must signal to the dma controller when the transfer should take place. all of the dm a peripheral devices internal to the rc32438 operate in transfer request mode. configuring an internal per ipheral device for auto request or burst request modes will produce unde- sirable consequences. external dma operations, described later in this chapter, support all three modes. dma descriptor list and chaining a dma descriptor list consists of a linked list of dm a descriptors, with the link field of each descriptor pointing to the next descriptor in the list. the link fiel d of the last descriptor in a descriptor list is zero. descriptor list processing begins when the address of a dma descrip tor is written to the dmaxdptr register. this causes the dma c ontroller to read a descriptor from memory, performs the specified dma operation, update the descriptor status information, and follows the link field to the next descriptor in the descriptor list. the dmaxdptr r egister may be read at any time to determine the currently active descriptor in the descriptor list. dma chaining is enabled by initializing the dma next descriptor pointer (dmaxndptr) with the starting address of a dma descriptor list. when the dma contro ller completes the operation associated with the last descriptor in a descriptor list, and dma chaining is not enabled (that is, dmaxndptr is zero), then the halt 1. aborting a dma operation may result in undefined values in the devcs and devcmd fields.
idt dma controller internal dma operation 79rc32438 user reference manual 9 - 11 november 4, 2002 notes (h) bit in the dmaxs register is set and the dma hal ts. if dma chaining is enabled, then the dma controller loads the address in the dmaxndptr into the dmaxdp tr register, sets the value of the dmaxndptr register to zero, sets the chain (c) bit in the dm axs register, and begins proc essing the descriptor pointed to by dmaxdptr. the dma controlle r continues processing descriptors until it once again reaches the end of a descriptor list, at which point the above process repeats. an example of dma chaining is show n in figure 9.5. in this example dmaxdptr is initialized with the starting address of the descriptor list abc, and dmaxndp tr is initialized with a pointer to the starting address of descriptor list xyz. when the dma controll er completes the operation associated with descriptor c, the value in dmaxndptr is loaded into dmaxdptr , dmaxndptr is set to zero, the c bit in the dmaxs register is set, and the dma continues with the dma operation s pecified by descriptor x. if the dmaxndptr register is not updated by the cpu duri ng the processing of descriptor list xyz, then the completion of the dma operation associated with descripto r z causes the h bit in the dma status register to be set and the dma to halt. figure 9.5 dma chaining example dma chaining may be initiated in the middle of a descriptor list based on the descriptor stopping condi- tion. if the chain on done (cod) bit is set in a des criptor and the dma stopping c ondition for the descriptor is due to a done event, dma chaining takes place. th is causes the dma controller to stop processing descriptors in the current descriptor list and to continue with those in the descrip tor list pointed to by dmax- ndptr. if dmaxndptr is zero, the dma halts. fini shed events may also be programmed to cause dma chaining. if the chain on finished (cof) bit is set in a descriptor and the dma stopping condition for the descriptor is due to a finis hed event, dma chaining occurs. writing to the dmaxndptr register while the dma is running (i.e., the run bit is set) simply modifies the value of the register. writing to the dmaxndptr r egister while the dma is not running (i.e., the run bit is cleared) not only modifies the va lue of dmaxndtpr but also causes a chaining operation to take place. this causes: dmaxndptr to be loaded into dmaxdptr, the value of dmaxndptr to be set to zero, the chain (c) bit to be set, the run bit to be set, and a dma operation to begin. dmaxndptr a dmaxdptr data buffer b data buffer c data buffer x data buffer y data buffer z data buffer
idt dma controller internal dma operation 79rc32438 user reference manual 9 - 12 november 4, 2002 notes dma [0..9] control register figure 9.6 dma [0..9] cont rol register (dma[0..9]c) run description: run. this bit is automatically set to a one when a dma operation begins (i.e., when a value is written into the dmaxdptr register). if this bit is set, writing a zero into it halts dma descriptor processing. the halting of dma descriptor processing is acknowledged when the h bit in the dmaxs register is set. when the run bit is cleared, writes should not be performed to the dmaxdptr and dmaxndptr registers until the h bit is set. initial value: 0x0 read value: previous value written write effect: writing a one has no effect; writing a zero clears the bit if it is set. r description: reserved. this bit performs no function. initial value: undefined. must be set to zero. read value: na write effect: na mode description: dma mode. this field controls the operating mode of external dma operations. all other dma operations ignore this field and use transfer request mode. 0 auto request mode . in this mode, dma request events from the selected device are ignored and the dma controller automatically generates a continuous request event. 1 burst request mode . in this mode, a dma request event from the selected device initiates a burst transfer (i.e., the transfer automatically progresses until a done or finished event). when the dma controller observes a request event, it automatically generates a continuous request event for the remainder of the dma operation. 2 transfer request mode . in this mode, a dma request event signals that a dma transfer is requested. the amount of data moved by the dma is defined by the dma transfer size for the selected device. 3 reserved initial value: undefined read value: previous value written write effect: modify value abort dma[0..9]c 0 31 27 0 r 1 run 1 2 mode abort 1
idt dma controller internal dma operation 79rc32438 user reference manual 9 - 13 november 4, 2002 notes dma [0..9] status register figure 9.7 dma [0..9] status register (dma[0..9]s) description: abort. writing a one to this field causes the dma controller to abort the current dma operation if one is in progress. the aborting of a dma operation is acknowledged when the h bit in the dmaxs register is set. when a dma operation is in the process of being aborted, writes should not be performed to the dmaxdptr and dmaxndptr registers until the h bit is set. aborting a dma operation may result in an undefined value in the devcs and devcmd fields of the descriptor currently being processed. in addition, the associated peripheral may be left in an undefined state. therefore, the corresponding peripheral should always be reset following the abortion of a dma operation. 1 initial value: undefined read value: 0x0 write effect writing a one to this field causes the dma controller to abort the current dma operation. 1. following the abortion of a memory to memory dma operation, the dma holding fifo may contain undefined data. this data must be emptied by initiating dm a operations to empty the fifo. f description: finished. this bit is set when a descriptor with the iof bit set completes due to a finished event. initial value: undefined read value: status write effect: sticky bi t (a sticky bit is set by the hardware and can only be cleared by the cpu) d description: done. this bit is set when a descriptor with the iod bit set completes due to a done event. initial value: undefined read value: status write effect: sticky bi t (a sticky bit is set by the hardware and can only be cleared by the cpu) c description: chain. this bit is set when a descriptor chaining operation takes place. initial value: undefined read value: status write effect: sticky bi t (a sticky bit is set by the hardware and can only be cleared by the cpu) e description: error. this bit is set when an error is detected by the dma during descriptor processing. initial value: undefined d dma[0..9]s 0 31 27 0 f 11 c 1 e 1 h 1
idt dma controller internal dma operation 79rc32438 user reference manual 9 - 14 november 4, 2002 notes dma [0..9] status mask register figure 9.8 dma [0..9] status mask register (dma[0..9]sm) read value: status write effect: sticky bi t (a sticky bit is set by the hardware and can only be cleared by the cpu) h description: halt. this bit is set when the dma halts descriptor processing and is idle. initial value: undefined read value: status write effect: sticky bi t (a sticky bit is set by the hardware and can only be cleared by the cpu) f description: finished. when this bit is set, the f bit in the dmaxs register is masked from generating an interrupt. initial value: 0x1 read value: previous value written write effect: modify value d description: done. when this bit is set, the d bit in the dmaxs register is masked from generating an inter- rupt. initial value: 0x1 read value: previous value written write effect: modify value c description: chain. when this bit is set, the c bit in the dmaxs register is masked from generating an inter- rupt. initial value: 0x1 read value: previous value written write effect: modify value e description: error. when this bit is set, the e bit in the dmaxs register is masked from generating an inter- rupt. initial value: 0x1 dma[0..9]sm d 0 31 27 0 f 11 c 1 e 1 h 1
idt dma controller internal dma operation 79rc32438 user reference manual 9 - 15 november 4, 2002 notes dma [0..9] descriptor pointer register figure 9.9 dma [0..9] descriptor pointer register (dma[0..9]dptr) dma [0..9] next descriptor pointer register figure 9.10 dma [0..9] next descript or pointer register (dma[0..9]ndptr) read value: previous value written write effect: modify value h description: halt. when this bit is set, the h bit in the dmaxs register is masked from generating an interrupt. initial value: 0x1 read value: previous value written write effect: modify value dptr description: descriptor pointer. this 32-bit field is written with the ph ysical address of th e first descriptor in a descriptor list. writing a value to this register automatically starts dma descriptor processing and causes the run bit in the dmaxc register to be set. this register should not be modified while the dma is active (i.e., the run bit is set). the value read from this register is the address of the currently active dma descriptor if the dma is running or the address of the last descriptor processed if the dma has halted. writing a zero to this field modifies its contents but does not cause dma descriptor processing to start. the ndptr field in the dmaxndptr register should be initialized to zero prior to initializing the dptr field since writing a descriptor address to dptr will start dma descriptor processing. initial value: undefined read value: physical address of currently active descriptor or last descriptor processed write effect: modify value and start dma operation dma[0..9]dptr 0 31 32 dptr dma[0..9]ndptr 0 31 32 ndptr
idt dma controller external dma operations 79rc32438 user reference manual 9 - 16 november 4, 2002 notes external dma operations an external dma operation is one in which the dm a controller is used to transfer data between an external peripheral and memory. the dma controller supports two exte rnal dma channels: external dma channel 0 (uses dma channel 0) and exter nal dma channel one (uses dma channel 1). the dma descriptor ds field is used to select the di rection of the dma transfer. when ds is zero, data is transferred from the external peripheral to memory. when the ds fi eld is one, data is transferred from memory to the external peripheral. the dma descriptor devcs field, shown in figure 9. 11, holds the address of the external dma periph- eral. the dma descriptor devc md field, shown in figure 9.12, cont ains a transfer size (ts) field that specifies the dma transfer burst size for external perip herals. the width of the ts field must be greater than or equal to the width of the external dma peripher al. during dma burst transactions on the memory and peripheral bus, the address field remains constant throughout the entire transaction and is equal to the value in the peripheral address (addr) field. device control and status field for external dma figure 9.11 device control and status value for external dma descriptors device command field for external dma figure 9.12 device command fiel d for external dma descriptors ndptr description: next descriptor pointer. this 32-bit field contains the address of the first descriptor in the descriptor list to be used for chaining. if this field is a zero, dma chaining is disabled. writing to this register when the dma is not running causes the dma to start and a chaining operation to take place. writing a zero to this field modifies its contents but does not cause dma descriptor processing to start. initial value: undefined read value: address of next descriptor in descriptor chain write effect: modify value addr peripheral address. this 32-bit field specifies the address of the external dma peripheral. the address must map to a device on the memory and peripheral bus. the address should be aligned to the size of the external dma peripheral (e.g., address bit zero must be zero for a 16-bit external dma peripheral). devcs 0 31 32 addr devcmd 2 3 ts 0
idt dma controller external dma operations 79rc32438 user reference manual 9 - 17 november 4, 2002 notes an external peripheral generates a dma request event by asserti ng a dma request (dmareqnx) input. the dmareqnx inputs are gpio alte rnate functions (see chapter 12, g eneral purpose i/o controller). transfer request: when the dma is configured to operate in transfer request mode, a dma request instructs the dma controller to perform one burst trans action to the external peripheral address in devcs. the size of the burst transfer is selected in the ts field. the assertion of chip select to the external per ipheral acknowledges the dm a request and causes the external peripheral to negate dmareqnx. when the external peripheral samples chip select negated, it may once again assert dmareqnx. an example of a peripheral-to-me mory external dma operation in transfer request mode is shown in figure 9.13 figure 9.13 external dma op eration (transfer request mode) burst request: when the dma is configured to operate in burst request mode, then the first dma request initiates the entire dma transfer between the external peripheral and me mory. an example of a peripheral-to-memory dma operation in bur st request mode is shown in figure 9.14. ts transfer size. this field specifies the dma burst transfer size used to access the external peripheral. 0 - byte 1 - halfword 2 - word 3 - 2 words 4 - 4 words 5 - 6 words 6 - 8 words 7 - 16 words dma request event assertion of dmareqnx pin. dma done event assertion of dmadonenx pin. dma terminated event an external device cannot signal a terminated event. dma transfer size value programmed in the transfer size (ts) field of devcmd. limitations the width of the ts field must be greater than or equal to the width of the external dma peripheral. table 9.3 external dma operations extclk dmareqnx csnx transaction transaction to memory transaction to external peripheral transaction to external peripheral 1 2 3 4 5 6 7 1. dma requests data transfer by asserting dmareqnx 2. the rc32438 acknowledges dma request by asserting chip select (csnx) to external peripheral. dma control- ler reads a transfer size data quantity from the external peripheral 3. external peripheral reacts to acknowledgment of dm a request (i.e., assertion of chip select) by negating dmareqnx 4. dma controller writes data quantity read from external peripheral to memory 5. dma requests next data tran sfer by asserting dmareqnx 6. the rc32438 acknowledges next dma request by asserti ng chip select and reading a transfer size data quan- tity from the external peripheral 7. external peripheral reacts to acknowledgem ent of dma request by negating dmareqnx.
idt dma controller external dma operations 79rc32438 user reference manual 9 - 18 november 4, 2002 notes figure 9.14 external dma operation (burst request mode) the dma done (dmadonenx) inputs are gpio alternat e functions (see chapter 12, general purpose i/o controller) may be asserted by an external peripher al to signal a done event to the dma controller. as shown in figure 9.15, during exte rnal peripheral read operations, dm adonenx is sampled on the same clock edge as the data. as shown in figure 9.16, dur ing external peripheral wr ite operations, dmadonenx is sampled on the same clock edge as the byte wr ites are negated. the dmadonex inputs are only sampled in the last data transfer on the memory and peri pheral bus of a burst transfer. in other words, if the specified transfer size results in multiple memory and peripheral bus data transfe rs, the external peripheral can only signal a done event during the last data transfer of the burst. figure 9.15 sampling of dmadonenx duri ng external peripheral read transactions figure 9.16 sampling of dmadonenx during external peripheral write transactions the dma finished (dmafinnx) outputs are gpio al ternate functions (see table 12.1 in chapter 12, general purpose i/o controller). a dma finished output is asserted by the dma controller to signal a finished event to an external peri pheral. during a read transaction, dm afinnx is asserted for one clock extclk dmareqn csnx transaction transaction to memory transaction to external peripheral transaction to external peripheral 1 2 3 4 5 1. dma requests data transfer by asserting dmareqnx 2. the rc32438 acknowledges dma request by asserting chip select (csnx) to external dma peripheral and per- forming the burst transfer specified in the ts field. 3. external peripheral reacts to acknowledg ment of dma request by negating dmareqnx 4. dma controller writes data quantity read from external peripheral to memory 5. dma controller performs remaining transfers in dma operation without further dma requests. a dma operation is completed when the byte count reaches zero or dmadonenx is asserted. extclk maddr[25:0] rwn csnx bwen[1:0] oen mdata[15:0] address valid data valid dmadonenx dma samples dmadonenx extclk maddr[25:0] rwn csnx bwen[1:0] oen mdata[15:0] address valid data valid dmadonenx dma samples dmadonenx
idt dma controller memory to memory dma operations 79rc32438 user reference manual 9 - 19 november 4, 2002 notes cycle corresponding to a clock edge during which the fina l data quantity is read (i.e., the data quantity that causes the byte counter to reach zero). this is shown in figure 9.17 for a non-burst read transaction. during a write transaction, dmafinnx is asserted throughout the entire transaction in which the byte counter reaches zero. this is shown in figure 9.18. figure 9.17 assertion of dmafinnx during external peripheral read transactions figure 9.18 assertion of dmafinnx during external peripheral write transactions memory to memory dma operations a fifo between dma channels six and seven allows th e dma controller to be used for memory to memory dma transfers. when dma channel six device ze ro is selected, data is read from memory and written into a dma fifo. when dma channel seven devic e zero is selected, data is read from the dma fifo and written to memory. thus, by using these dma channels together, data may be dmaed from memory to memory. the dma fifo allows burst transfers of up to 16 words (64-bytes) to be buffered between dma chan- nels six and seven. the dma channel six and seven descriptor devcmd field, shown in figure 9.12, contains a transfer size (ts) field that specifies the dma transfer burst size. the dma transfer burst size for the two dma channels need not be the same values. figure 9.19 device command field for memory to memory dma descriptors extclk maddr[25:0] rwn csnx bwen[1:0] oen mdata[15:0] address valid data valid dmafinnx extclk maddr[25:0] rwn csnx bwen[1:0] oen mdata[15:0] address valid data valid dmafinnx devcmd 2 3 ts 0
idt dma controller examples 79rc32438 user reference manual 9 - 20 november 4, 2002 notes the devcs field is not used during memory to me mory dma operations. table 9.4 summarizes the memory to dma fifo dma operations and table 9.5 summarizes dma fifo to memory dma operations. examples example 1: dma operation using one descriptor list (program dmaxdptr register) set up interrupt controller set up descriptor dmaxndptr = 0 dmaxdptr = starting address of the descriptor list while (dma done or finis hed interrupt is not detected) { perform dma descriptor operation dma updates descriptor status ts transfer size. this field specifies the dma burst transfer size used to access memory during memory to memory dma operations. 0 - reserved 1 - reserved 2 - word 3 - 2 words 4 - 4 words 5 - 6 words 6 - 8 words 7 - 16 words dma request event dma fifo has room for a burst transfer of the size specified by the ts field. dma done event dma done event is never generated. dma terminated event dma terminated event is never generated by the fifo. dma transfer size the dma controller will attempt to transfer a burst of the size specified in the ts field from memory to the dma fifo. fewer words will be transferred if the byte count reaches zero. limitations none. a dma operation may start and end on any byte boundary and may contain any number of words. table 9.4 memory to dma fifo dma operations dma request event dma fifo contains enough data for a burst transfer of the size specified by the ts field, or the last word of a dma operation has been transferred to the fifo. dma done event dma done event is never generated. dma terminated event dma terminated event is never generated. dma transfer size the dma controller will attempt to transfer a burst of the specified size in the ts field from the dma fifo to memo ry. fewer words will be transferred if the byte count reaches zero, or the last word of a dma operation has been transferred to the fifo. limitations none. a dma operation may start and end on any byte boundary and may contain any number of words. table 9.5 dma fifo to memory dma operations
idt dma controller examples 79rc32438 user reference manual 9 - 21 november 4, 2002 notes dma follows link field to next dma descriptor } read the status from dmaxs register and descriptors example 2: dma operation using one descriptor list (program dmaxndptr register) set up interrupt controller set up descriptor dmaxndptr = starting address of the descriptor list while (dma done or finis hed interrupt is not detected) { perform dma descriptor operation dma updates descriptor status dma follows link field to next dma descriptor } read the status from dmaxs register and descriptors example 3: dma operation using multiple descriptor lists (program dmaxndptr register) set up interrupt controller set up descriptors dmaxndptr = starting address of the first descriptor list while (dma transfer is not completed) { while (dma chain interrupt is not detected) { prepare the next descriptor list } clear the chain bit in dmaxs register dmaxndptr = starting address of the next descriptor list } example 4: dma operation using multiple descriptor lists (program dmaxdptr & dmaxndptr register) set up interrupt controller set up descriptors dmaxndptr = 0 dmaxdptr = starting address of the first descriptor list
idt dma controller examples 79rc32438 user reference manual 9 - 22 november 4, 2002 notes dmaxndptr = starting addres s of the second descriptor list while (dma transfer is not completed) { while (dma chain interrupt is not detected) { prepare the next descriptor list } clear the chain bit in dmaxs register dmaxndptr = starting address of the next descriptor list }
notes 79rc32438 user reference manual 10 - 1 november 4, 2002 chapter 10 pci bus interface introduction pci bus interface complies with pci local bus sp ecification revision 2.2 and provides a bus bridge between the rc32438?s internal ipbus and the pci bus. the pci bus interface may be configured to operate in host or satellite mode. th is is controlled by the pci mode se lected during boot configuration. the operating mode can be determined by reading the pci mode (pcim) field in the pcic register. the pci clock is always an input and may be asynchronous to the master clock input. the pci interface supports operation at frequencies from 16 mhz to 66 mhz; however, the pci operating frequency must be less than or equal to half of the ipbus clock fr equency. the pci clock may be stopped and there is no minimum master clock to pci clock ratios. the inte rface implements 3.3v pci compliant pads. the pci bus interface never merges separate writes into a single transaction. figure 10.1 shows a block diagram of the pci bus interface. figure 10.1 pci interface block diagram features ? 32-bit pci revision 2.2 compliant ? supports host or satellite operation in both master and target modes ? pci clock ? supports pci clock frequencies from 16 mhz to 66 mhz ? pci clock may be asynchronous to master clock (clk) ? pci arbiter in host mode ? supports 6 external masters ? fixed priority or ro und robin arbitration ? bus parking ? i 2 o ?like? pci messaging unit pci bus pci dma output fifo pci dma input fifo pci regs. pci config. regs pci messaging unit cpu master output fifo cpu master input fifo pci ta rge t output fifo pci ta rge t input fifo pci master interface pci target interface pci arbiter ipbus fly-by dma interface ipbus slave interface ipbus master interface ipbus pci serial eeprom
idt pci bus interface use of decoupled pci transactions 79rc32438 user reference manual 10 - 2 november 4, 2002 notes use of decoupled pci transactions the pci portion of the system controller sits on t he ipbus. therefore, read and write transactions to and from this block consume some of the available ipbus bandwidth and must be factored into the overall system bus utilization for a given system. to maxi mize performance, the number of local ipbus cycles consumed for a given transaction shou ld be minimized. the pci system controller is designed to automati- cally do this for most types of transactions. in the case of dma operations to or from the pci, t he transaction is initiated by the dma. prior to taking control of the ipbus, the dma automatically waits fo r the data to become available in the master read case or for space to be available in the output fifo fo r the master write case. this prevents the dma from wasting bandwidth sitting on the ipbus waiting for data to become available. in the case of target reads and target writes from an external pci master to the rc32438 as a pci target, data is fetched or queued effi- ciently. no user intervention is required. however, in the case where the cpu core rather than the dma controller initiates a master read or a master write, users must be careful not to monopoliz e the ipbus which will reduce available bandwidth. the rc32438 contains the following mechanism for decoupli ng both cpu master reads and cpu master writes. in the master write case, the cpu core can check t he status of the master write fifo prior to beginning the write via the ofe (output fi fo empty) bit, bit[3], of the pc i decoupled access status register (pcidas). if this bit is set, the fifo is empty. then t he cpu core can safely initiate a master write or a burst of 4 writes, since enough space is guaranteed for the transaction to be queued immediately without stalling the ipbus. in the master read case, the user can enable the decoupled access mode via the den bit in the pci decoupled access control register (pcidac). when the den bit is set, any master read to the pci memory space will return a "0" immediately. the progr am can then either rely on polling or use an interrupt generated from the pci decoupled access status regist er (pcidas) done bit (d) to indicate that the read has been completed. upon completion, the data wi ll be available in the pci decoupled access data register (pcidad). if the user opts not to enable this mode, some amount of efficiency will be lost waiting for cpu-initiated master reads to complete. in most applications, this is probably acceptable as the number of cpu-initiated master reads is generally small. however, in the ca se of pci bridges, failure to use the decoupled master read mechanism could result in the read timing out and causing a bus error. this error occurs when the cpu core attempts a master read while the bridge has data queued in its write fifo and is attempting to initiate target writes to the rc32438 device to clear the queue. the bridge will pass the read to the device on the other side, but when that target pci device re turns the requested read data to the bridge, the bridge will hold the data until the bridge manages to clear its wr ite fifo. however, since the cpu core is not using decoupled reads, the cpu holds the ipbus until the trans action completes. as long as the cpu is sitting on the ipbus, the bridge can only do writes until the tar get write fifo fills up on the rc32438. when the target write fifo is full, the rc32438 refuses to take any further target writes. the rc32438 cannot empty the target write fifo ? the ipbus must do that ? and the cpu continues to wait for the read to complete. because the rc32438 will not take any more target writes and the bridge will not pass the read data through until it completes its writes, t he rc32438 and the bridge ar e now "deadlocked". the deadlock will only be broken when the rc32438 pci master transaction retry counter is exceeded. at that point, the system will generate a bus error. the interrupt handler must correct the problem. this obviously imposes a signi ficant performance penalty. therefore, idt strongly recommends the use of dec oupled master reads and checking the status of the output fifo empty bit prior to generating cpu-initiat ed master reads or master writes, especially when the rc32438 is being used with a pci bridge. ipbus access access to the ipbus is determined by the ipbus arbiter.
idt pci bus interface pci register description 79rc32438 user reference manual 10 - 3 november 4, 2002 notes the pci interface contains six fifos. the pci dm a output fifo is used for memory to pci dma oper- ations. the pci dma input fifo is used for pci to memory dma operations. the ipbus master output fifo is used for ipbus master (e.g., cpu) pci write operations while the ipbus master input fifo is used for ipbus master pci read operations. the pci target out put fifo is used for external pci master reads of the rc32438 local address space while the pci target input fifo is used for external pci master writes to the rc32438 local address space. pci register description fifo size pci dma output fifo 64 words pci dma input fifo 64 words cpu master output fifo 4 words cpu master input fifo 8 words pci target output fifo 64 words pci target input fifo 64 words table 10.1 pci bus interface fifo sizes register offset 1 register name register function size pci bus interface 0x08_0000 pcic pci control 32-bit 0x08_0004 pcis pci status 32-bit 0x08_0008 pcism pci status mask 32-bit 0x08_000c pcicfga pci configuration address 32-bit 0x08_0010 pcicfgd pci configuration data 32-bit 0x08_0014 pcilba0 pci local base address 0 32-bit 0x08_0018 pcilba0c pci local base address 0 control 32-bit 0x08_001c pcilba0m pci local base address 0 mapping 32-bit 0x08_0020 pcilba1 pci local base address 1 32-bit 0x08_0024 pcilba1c pci local base address 1 control 32-bit 0x08_0028 pcilba1m pci local base address 1 mapping 32-bit 0x08_002c pcilba2 pci local base address 2 32-bit 0x08_0030 pcilba2c pci local base address 2 control 32-bit 0x08_0034 pcilba2m pci local base address 2 mapping 32-bit 0x08_0038 pcilba3 pci local base address 3 32-bit 0x08_003c pcilba3c pci local base address 3 control 32-bit 0x08_0040 pcilba3m pci local base address 3 mapping 32-bit 0x08_0044 pcidac pci decoupled access control 32-bit 0x08_0048 pcidas pci decoupled access status 32-bit table 10.2 pci register map (part 1 of 2)
idt pci bus interface pci register description 79rc32438 user reference manual 10 - 4 november 4, 2002 notes pci control register figure 10.2 pci control register (pcic) 0x08_004c pcidasm pci decoupled access status mask 32-bit 0x08_0050 pcidad pci decoupled access data 32-bit 0x08_0054 pcidma8c pci dma channel 8 configuration 32-bit 0x08_0058 pcidma9c pci dma channel 9 configuration 32-bit 0x08_005c pcitc pci target control 32-bit 0x08_0060 through 0x08_7fff reserved pci messaging uni t 0x08_8000 through 0x08_800c reserved 0x08_8010 pciim0 pci inbound message 0 32-bit 0x08_8014 pciim1 pci inbound message 1 32-bit 0x08_8018 pciom0 pci outbound message 0 32-bit 0x08_801c pciom1 pci outbound message 1 32-bit 0x08_8020 pciid pci inbound doorbell 32-bit 0x08_8024 pciiic pci inbound interrupt cause 32-bit 0x08_8028 pciiim pci inbound interrupt mask 32-bit 0x08_802c pciod pci outbound doorbell 32-bit 0x08_8030 pcioic pci outbound interrupt cause 32-bit 0x08_8034 pcioim pci outbound interrupt mask 32-bit 0x08_8038 through 0x8_ffff reserved 1. the address of the register is equal to the regi ster offset added to the base value of 0x1800_0000. en description: enable. when this bit is set, the pci bus interface is enabled. when this bit is cleared, the pci bus interface is disabled and enters a benign low power mode. disabling and then re-enabling the pci bus interface resets all of the logic associated with the pci bus interface. initial value: the enable bit is set when the pci mode boot configuration selects a pci satellite mode. in all other modes, the enable bit is cleared. see pci mode boot configuration in table 3.3 of chapter 3. (a warm reset does not modify this field except under the following conditions: the warm reset occurs as a result of the assertion of the pci reset signal and the rc32438 is operat- ing in pci satellite mode. when a warm reset occurs under the above conditions, this field takes on its initial value.) register offset 1 register name register function size table 10.2 pci register map (part 2 of 2) pcic 0 31 0 22 en 1 3 pcim tnr 1 sce 1 ien 1 aaa 1 eap 1 igm 1
idt pci bus interface pci register description 79rc32438 user reference manual 10 - 5 november 4, 2002 notes read value: previous value written write effect: modify value tnr description: target not ready. when this bit is set, the pci bus interfac e issues a retry to all target transac- tions. when this bit is set, delayed reads are never performed. 0x0 - normal operation 0x1 - target not ready (retry all target transactions) initial value: see pci mode boot configuration intable 3.3 of chapter 3. read value: previous value written write effect: modify value sce description: suspend cpu execution . when this bit is set, cpu execution is suspended. note: software should never set this bit because it may cause the system to lock-up. initial value: see pci mode boot configuration in table 3.3 of chapter 3. (a warm reset does not modify this field except under the following conditions: the warm reset occurs as a result of the assertion of the pci reset signal and the rc32438 is operat- ing in pci satellite mode. when a warm reset occurs under the above conditions, this field takes on its initial value.) read value: previous value written write effect: modify value ien description: ipbus error enable . when this bit is set, the pci interface will signal ipbus slave acknowledge errors during cpu master read transactions when an error occurs. when this bit is cleared, ipbus slave acknowledge errors are masked. initial value: 0x1 (a warm reset does not modify this field except under the following conditions: the warm reset occurs as a result of the assertion of the pci reset signal and the rc32438 is operat- ing in pci satellite mode. when a warm reset occurs under the above conditions, this field takes on its initial value.) read value: previous value written write effect: modify value aaa description: arbiter arbitration algorithm . when the pci bus interface is configured to operate in pci host with internal arbiter mode, this bit selects the arbitration algorithm used by the internal arbiter. this bit has no effect in pci satellite mode or in pci host mode using an external arbiter. 0x0 - round robin arbitration algorithm 0x1 - fixed priority arbitration algorithm initial value: see pci mode boot configuration in table 3.3 of chapter 3. (a warm reset does not modify this field except under the following conditions: the warm reset occurs as a result of the assertion of the pci reset signal and the rc32438 is operat- ing in pci satellite mode. when a warm reset occurs under the above conditions, this field takes on its initial value.)
idt pci bus interface pci register description 79rc32438 user reference manual 10 - 6 november 4, 2002 notes read value: previous value written write effect: modify value eap description: enable arbiter parking . when this bit is set and the pci bus interface is configured to operate in pci host mode with an internal arbiter, then pci bus parking is enabled. enabling bus parking causes the internal pci arbiter to ?park? the bus on the last master granted the bus as long as no other master requests the bus. initial value: 0x0 (a warm reset does not modify this field except under the following conditions: the warm reset occurs as a result of the assertion of the pci reset signal and the rc32438 is operat- ing in pci satellite mode. when a warm reset occurs under the above conditions, this field takes on its initial value.) read value: previous value written write effect: modify value pcim description: pci mode . this field indicates the pci operating mode selected during boot configuration. 0x0 - disabled (en bit in pcic register is cleared) 0x1 - pci satellite mode with pci target not ready 0x2 - pci satellite mode with suspended cpu execution 0x3 - pci host mode with external arbiter 0x4 - pci host mode with internal arbiter using fixed priority arbitration algorithm 0x5 - pci host mode with internal arbiter using round robin arbitration algorithm 0x6 - reserved 0x7 - reserved initial value: see pci mode boot configuration in table 3.3 of chapter 3. read value: status write effect: read-only igm description: idle grant mode . this bit controls the operation of the internal arbiter when the pci interface is configured to operate in a pci host mode with internal arbiter. when the internal arbiter is used and this bit is cleared, the arbiter operates in a static idle grant mode. this means that once a grant is asserted when the pci bus is idle, the grant will remain asserted until the requested transaction completes or 16 pci clock cycles have elapsed. when the internal arbiter is used and this bit is set, the arbiter operates in a dynamic idle grant mode. this means that while the pci bus is idle, the arbiter may take away a grant from one master and pass it to another. initial value: 0x0 read value: previous value written write effect: modify value
idt pci bus interface pci register description 79rc32438 user reference manual 10 - 7 november 4, 2002 notes pci status register figure 10.3 pci status register (pcis) eed description: pci serial eeprom done. this bit is set while the pci bus interface has completed using the pci serial eeprom interface. afte r a cold reset in pci satellit e mode with suspended cpu exe- cution, this bit is cleared and remains cleared until the pci interface completes loading configu- ration information from the pci serial eeprom. this bit is always set in the other pci modes. initial value: 0x0 read value: status write effect: read only wr description: warm reset. this bit is set when a pci master or the cpu writes a one to the warm reset (wr) bit in the pci management (pmgt) register. the state of this bit is preserved across warm resets. initial value: 0x0 (this field takes on its initial value when a warm reset occurs as a result of the assertion of the pci reset signal when the rc32438 is operating in pci satellite mode. read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) nmi description: non-maskable interrupt. this bit is set when a pci master or the cpu writes a one to the non- maskable interrupt (nmi) bit in the pci management (pmgt) register. initial value: 0x0 read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) ii description: inbound interrupt. this bit represents the or of all of the bits in the pci inbound interrupt cause (pciic) register which are not masked in the pci inbound interrupt mask (pciim) regis- ter. initial value: 0x0 pcis 16 31 0 14 0 15 nmi wr 1 sta mdpe rma rta pe sse 1 1 1 1 1 1 1 ii 1 eed 1 tae 1 rle 1 bme 1 cwe 1 cre 1 prd 1 rip 1 ose 1
idt pci bus interface pci register description 79rc32438 user reference manual 10 - 8 november 4, 2002 notes read value: status write effect: read only cwe description: cpu write error. this bit is set if a cpu pci write transaction experienced an error. initial value: 0x0 read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) cre description: cpu read error. this bit is set if a cpu pci read transaction experienced an error and the ien bit is set. initial value: 0x0 read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) mdpe description: master data parity error detected. this bit is set whenever the mdpe bit in the pci configura- tion status register is set. initial value: 0x0 read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) sta description: signalled target abort status. this bit is set whenever the sta bit in the pci configuration status register is set. initial value: 0x0 read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) rta description: received target abort status. this bit is set whenever the rta bit in the pci configuration status register is set. initial value: 0x0 read value: status write effect: sticky bit. when set, this bit cannot be cleared until the corresponding bit in the status register is cleared. rma description: received master abort status. this bit is set whenever the rma bit in the pci configuration status register is set. initial value: 0x0
idt pci bus interface pci register description 79rc32438 user reference manual 10 - 9 november 4, 2002 notes read value: status write effect: sticky bit. when set, this bit cannot be cleared until the corresponding bit in the status register is cleared. sse description: signalled system error. this bit is set whenever the sse bi t in the pci configuration status register is set. initial value: 0x0 read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) ose description: observed system error. this bit is set whenever a system error is observed on the pci bus (i.e., the serrn pin is asserted). initial value: 0x0 read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) pe description: parity error. this bit is set whenever the pe bit in the pci configuration status register is set. initial value: 0x0 read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) tae description: target address error. this bit is set if the pci bus interface terminates a target transaction with a target abort due to an invalid transaction local address reported by the address space moni- tor. initial value: 0x0 read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) rle description: retry limit exceeded. this bit is set if the pci bus interface terminated a master transaction with an error because the retry limit specified in the retry_limit register in pci configuration space was exceeded. initial value: 0x0 read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) bme description: bus master error. this bit is set if the pci bus interface terminated a master transaction with an error because the transaction could not be completed since the bus master enable (bm) bit in the command register in pci configuration space was not set.
idt pci bus interface pci register description 79rc32438 user reference manual 10 - 10 november 4, 2002 notes pci status mask register figure 10.4 pci status mask register (pcism) initial value: 0x0 read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) prd description: pending read discarded. this bit is set if a pending read was discarded because the discard timer expired. initial value: 0x0 read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) rip description: reset in progress. when the en bit is cleared, the pci interface is reset (note that this does not result in a pci reset). this bit is set to indicate that a pci interface reset is in progress. this reset may take several clock cycles to complete due to the crossing of clock domains. when the pci interface reset has completed, this bit is cleared and the pci interface may be re-enabled by setting the en bit. initial value: 0x0 read value: status write effect: read-only eed description: pci serial eeprom done. when this bit is set, the eed bit in the pcis register is masked from generating an interrupt. initial value: 0x1 read value: previous value written write effect: modify value wr description: warm reset. when this bit is set, the wr bit in the pcis register is masked from generating an interrupt. initial value: 0x1 pcism 16 31 0 14 0 15 nmi wr 1 sta mdpe rma rta pe sse 1 1 1 1 1 1 1 ii 1 eed 1 tae 1 rle 1 bme 1 cwe 1 cre 1 prd 1 rip 1 ose 1
idt pci bus interface pci register description 79rc32438 user reference manual 10 - 11 november 4, 2002 notes read value: previous value written write effect: modify value nmi description: non-maskable interrupt. when this bit is set, the nmi bit in the pcis register is masked from generating an interrupt. initial value: 0x1 read value: previous value written write effect: modify value ii description: inbound interrupt. when this bit is set, the ii bit in the pcis register is masked from generating an interrupt. initial value: 0x1 read value: previous value written write effect: modify value cwe description: cpu write error. when this bit is set, the cwe bit in th e pcis register is masked from generat- ing an interrupt. initial value: 0x1 read value: previous value written write effect: modify value cre description: cpu read error. when this bit is set, the cre bit in th e pcis register is masked from generat- ing an interrupt. initial value: 0x1 read value: previous value written write effect: modify value mdpe description: master data parity error. when this bit is set, the mdpe bit in the pcis register is masked from generating an interrupt. initial value: 0x1 read value: previous value written write effect: modify value sta description: signalled target abort. when this bit is set, the sta bit in the pcis register is masked from generating an interrupt. initial value: 0x1
idt pci bus interface pci register description 79rc32438 user reference manual 10 - 12 november 4, 2002 notes read value: previous value written write effect: modify value rta description: received target abort. when this bit is set, the rta bit in the pcis register is masked from generating an interrupt. initial value: 0x1 read value: previous value written write effect: modify value rma description: received master abort status. when this bit is set, the rma bit in the pcis register is masked from generating an interrupt. initial value: 0x1 read value: previous value written write effect: modify value sse description: signalled system error. when this bit is set, the sse bit in the pcis register is masked from generating an interrupt. initial value: 0x1 read value: previous value written write effect: modify value ose description: observed system error. when this bit is set, the ose bit in the pcis register is masked from generating an interrupt. initial value: 0x1 read value: previous value written write effect: modify value pe description: parity error. when this bit is set, the pe bit in the pcis register is masked from generating an interrupt. initial value: 0x1 read value: previous value written write effect: modify value tae description: target address error. when this bit is set, the tae bit in the pcis register is masked from gen- erating an interrupt. initial value: 0x1
idt pci bus interface reset 79rc32438 user reference manual 10 - 13 november 4, 2002 notes reset upon assertion of the pci reset, either a warm or cold reset causes all of the pci interface pins to be tri- stated during the reset condition. 1 this reaction is asynch ronous to the pci clock or master clock input (clk) and is immediate. a warm or cold reset and the subsequent enabling of the pci interface may result in the pci bus inter- face being enabled during an active bus (e.g., in the mi ddle of a burst transfer bet ween two other devices). this may also occur due to the delay in locking the pll following a pci reset when the rc32438 is used in satellite mode. the pci bus interface handles this condition. if the rc32438 becomes active during a pci transaction, the rc32438 will ignore events on the pci bus until the transaction is completed. for additional information, refer to the reset implementation not e in section 4.3.2 of the pci 2.2 specification. read value: previous value written write effect: modify value rle description: retry limit exceeded. when this bit is set, the rle bit in the pcis register is masked from gen- erating an interrupt. initial value: 0x1 read value: previous value written write effect: modify value bme description: bus master error. when this bit is set, the bme bit in the pcis register is masked from generat- ing an interrupt. initial value: 0x1 read value: previous value written write effect: modify value prd description: pending read discard. when this bit is set, the prd bit in the pcis register is masked from generating an interrupt. initial value: 0x1 read value: previous value written write effect: modify value rip description: reset in progress. when this bit is set, the rip bit in the pcis register is masked from generat- ing an interrupt. initial value: 0x1 read value: previous value written write effect: modify value 1. an exception to this is the pci reset signal pcirstn. when the rc32438 is configured to operate in pci host mode, pcirstn will be asserted whenever the en bit is cleared (set to zero).
idt pci bus interface disabled mode 79rc32438 user reference manual 10 - 14 november 4, 2002 notes during a cold reset, the rc32438?s pci reset output is tri-stated since it is not yet known if the rc32438 will be operating in host or satellite mode. therefor e, system designers should pull the pci reset signal down so that it is held low following the application of power to the system. disabled mode when the en bit in the pcic register is cleared, the pci bus interface is disabled. the pci bus interface may be permanently disabled during boot configuration by selecting t he disable pci mode. when disabled, the pci bus interface enters a benign low-power mode. the values on all pci input pins are ignored. the pci clock (pciclk) should be driven to a valid logic level on the board. when the pci bus interface is disabled, all of the pci pins are tri-stated and thus should be held at a valid logic level on the board. the pci bus interface may be disabled at any time after a cold reset by clearing the enable (en) bit in the pc i configuration (pcic) register. disabling and then re-enabling the pci bus interface resets all of the logic associated with the pci bus interface and causes all fifos to be reset. the states of all status registers are reset to their initial values, but the states of all configuration registers are preserved. pci host mode reset and initialization in pci host mode, the pci reset pin (pcirstn) is an output. the pcirstn pin is asserted whenever the en bit in the pcic register is cleared (e.g., as the result of a warm or cold reset). software should ensure that the pcirstn pin is asserted for a minimu m of 1 ms after power has stabilized and 100 s after the pci clock has stabilized. after reset, the rc32438 boots from the boot device. t he pci interface is then enabled, causing the pci reset pin to be de-asserted (i.e., taking the pci bus out of reset). initially, the ta rget not ready (tnr) bit is set in the pcic register. this causes all pci bus inte rface target transactions to be retried and allows the rc32438 to initialize the pci interface and configur ation registers. once the rc32438 device completes the initialization sequence, it clears the target not ready (tnr) bit, allowing pc i masters to access the rc32438. a warm reset may be initiated by writing to t he warm reset (wr) bit in the pci management (pmgt) register in pci configuration space. an nmi to t he cpu core may be initiated by writing to the non- maskable interrupt (nmi) bit in the pmgt register. a pci host may use these features to reset/reboot the rc32438 device. the cpu core may generate a pci reset by clearing the en bit in the pcic regi ster or by initiating a warm or cold reset. note that system designers ma y choose to generate the pci reset signal using external logic rather than the rc32438 pcirstn signal to reset other external devices. in such a configuration, the externally generated reset should be confi gured to generate a warm or cold reset. bus arbitration pci arbitration mode in host mode is determined by the pci mode selected during boot configuration. the pci host can be configured to use an external ar biter or internal arbiter. the function of the pcireqn[5:0] and pcigntn[5:0] signals is determined by the pci mode selected 1 and is dependent on whether the internal arbiter is used or an external arbiter is selected. 1. pcireqn[4] is an alternate function of gpio[24], pcireqn[5] is an alternate function of gpio[27], pcigntn[4] is an alternate function of gpio[26], a nd pcigntn[5] is an alternate function of gpio[28].
idt pci bus interface pci satellite mode 79rc32438 user reference manual 10 - 15 november 4, 2002 notes the internal arbiter supports up to six external dev ices. the default arbitrati on algorithm used by the internal arbiter is selected by the pci mode duri ng boot configuration. the algorithm may be modified through the arbiter arbitration algorithm (aaa) bi t in the pcic register. the two algorithms are: round robin arbitration algorithm - ownership is granted in a fixed rotating sequence (rc32438, pcireqn[0], pcireqn[1], pcireqn[2], pcireqn[3], pcireqn[4], pcireqn[5]). fixed priority arbitrati on algorithm - the priority order (highest to lowest) is rc32438, pcireqn[0], pcireqn[1], pcireqn[2], pcireqn[3], pcireqn[4], pcireqn[5]. the rc32438 internal arbiter will guar antee that the pci ?trhff? (time from reset high-to-first-frame# assertion) specification will be met by not granting the bus for at leas t eight clock cycles after negation of the pci reset or the enabling of the pci interface. interrupts in host mode, the rc32438 does not provide any dedicat ed interrupt inputs. gpio pins may be used as interrupt inputs. although no gpio pins are dedicated for pci interrupts, gpio pins gpio[29:26] have pci buffers (refer to table 1.3 in chapter 1). the pci messaging unit operates in both satellit e and host modes. the pci messaging unit interrupt output (i.e., pcimuintn) is a gpio alternate func tion output (refer to table 12.1 in chapter 12). when configured as an alternate function, this pin is tri- stated when not asserted (i.e., it acts as an open collector output). pci satellite mode reset and initialization in pci satellite mode, the pci reset pin (pcirstn) is an input. assertion of the pci reset pin causes the rc32438 to perform a warm reset and to reset the state of all registers in the pci in terface to their initial value (including pci conf iguration registers). the pci bus interface supports two pci satellit e operating modes. the two satellite operating modes are: pci satellite mode with target not ready, and pci satellite mode with suspended cpu execution. the operating mode is selected by the pc i mode field during boot configuration. pin name type description pcireqn[5:0] i pci request . the assertion of these signals indicates to the internal rc32438 arbiter that an agent desires use of the pci bus. pcigntn[5:0] o pci grant . the assertion of these signals indicates to the agent that the internal rc32438 arbiter has granted the agent access to the pci bus. table 10.3 pci arbitration pin functionality in pci host mode with internal arbiter enabled pin name type description pcireqn[0] o pci request . this signal is asserted by the rc32438 to request use of the pci bus. while pcirstn is asserted, the rc32438 tri-states this signal. pcireqn[5:1] o unused . these signals are unused in this mode and driven high. pcigntn[0] i pci grant . this signal is asserted by an external arbiter to indicate to the rc32438 that access to the pci bus has been granted. while pcir- stn is asserted, the rc32438 ignores the state of this signal. pcigntn[5:1] o unused . these signals are unused in this mode and driven high. table 10.4 pci arbitration pin functionality in pci host mode using external arbiter
idt pci bus interface pci satellite mode 79rc32438 user reference manual 10 - 16 november 4, 2002 notes an rc32438 warm reset may be initiated by writing to the warm reset (wr) bit in the pci management (pmgt) register in pci configurat ion space. a cpu nmi may be initiated by writing to the non-maskable interrupt (nmi) bit in the pmgt register. a pci host may use these features to reset/reboot the rc32438. pci satellite mode with target not ready in this mode, the sequence of events after reset is as follows: the rc32438 boots from the boot device. initially the target not ready (tnr) bit is set in the pcic register. this causes all pci bus interface target transactions to be retried. it also allows the rc32438 to boot, initialize the system, and initialize the pci interface and configuration registers. once the initia lization is completed, it clears the target not ready (tnr) bit, allowing pci masters to access the rc32438. pci satellite mode with suspended cpu execution in this mode, the execution of the rc32438 device is suspended when the system is reset because the suspend cpu execution (sce) bit is set in the pcic register. since execution of the cpu core is suspended in this mode, the watchdog timer should be in itially disabled by setting the disable watchdog timer bit in the boot configuration vector (refer to table 3.3 in chapter 3). in addition, the target not ready (t nr) bit is initially set in the pcic register. the pci serial eeprom loads the pci configuration registers from the pci serial eeprom. once the pci configuration registers are initialized, the tnr bit is aut omatically cleared, allowing pci hosts to access all of the rc32438?s memory mapped registers and local memory. the pci host can configure a signifi cant proportion of the rc32438 device. for example, it can initialize the device controller or ddr controller and load boot co de into memory. the pci host can also change pci and device address mapping, allowing the cpu to boot directly from pci memory. note that there are two address mapping regions fo r ddr0. this allows ddr0 space to be mapped to address 0x0000_0000 using the normal mapping mechanism and it allows the cpu core boot exception vector memory space starting at 0x1fc0_00000 to be mapped to ddr0 using the second mapping region. for more information, refer to chapter 7, ddr controller. when the pci host has completed configuring t he rc32438 device and/or loading boot code, it clears the sce bit, allowing the cpu core to begin execution. the cpu begins executing at the mips reset excep- tion vector whose physical address is 0x1fc0_0000. the cpu core can only boot from a 32-bit wide device on the pci bus. there is no need to disable the bus ti mer in this mode since setting the sce bit disables cpu accesses to the pmbus. since there is no cpu transaction on the pmbus or ipbus, there is no possi- bility of a bus time-out. bus arbitration in satellite mode, the rc32438 device always uses an external arbiter. table 10.5 summarizes the func- tion of the bus arbitration pins in satellite mode. pin name type description pcireqn[0] o pci request . this signal is asserted by the rc32438 to request use of the pci bus. while pcirstn is asserted, the rc32438 tri-states this signal. pcireqn[1] i initialization device select . in satellite mode this signal takes on the alternate function of pciidselp and is used as a chip select during configuration read and write transactions. pcireqn[5:2] o unused . these signals are unused in this mode and driven high. table 10.5 pci arbitration pin functionality in pci satellite mode (part 1 of 2)
idt pci bus interface pci transactions 79rc32438 user reference manual 10 - 17 november 4, 2002 notes interrupts in satellite mode, the rc32438 device does not pr ovide any dedicated interrupt outputs. the pci messaging unit operates in both satellite and host mode s. the pci messaging unit interrupt output (i.e., pcimuintn) is a gpio alternate function output (ref er to table 12.1 in chapter 12). although no gpio pins are dedicated for pci interrupts, gpio pins 29:26 have pci buffers (refer to table 1.3 in chapter 1). pci serial eeprom interface when the rc32438 device is booted in pci satell ite mode with the execution of the cpu core suspended, the pci serial eeprom is used to load pci configuration register s whose addresses are less than 0x80 in pci configuration space. the pci serial eeprom interface provides a national semicon- ductor microwire? compatible serial eeprom inte rface. pci serial eeprom done bit (eed) in the pcis register is set when the loading of configur ation information has been completed and the serial i/o signals have been released. eeproms equal to or greater than 1024-bits in size should be used (0x80 corresponds to 128 8-bit registers). each eeprom address corresponds to a 16-bit data quantity. this is in contrast to pci configuration which correspond to 8-bit quantities. for this re ason, corresponding eeprom addresses are equal to one half of their pci configuration space addresses. u nused eeprom locations (i.e., those whose initial values are don?t care) may be used to store application s pecific information. e eprom addresses which are greater than or equal to 0x40 in eeproms whose size is greater than 1024-bits may be used to store appli- cation specific information. application-specific information may be accessed from the eeprom using the spi interface after the initia lization process is completed. for information on the operation of the pci serial eeprom i/o pins, see chapter 16, serial peripheral interface. pci transactions table 10.6 summarizes the pci command codes suppor ted by the pci bus interface. the sections following this table describe how these transactions are generated for master and target configurations. pcigntn[0] i pci grant . this signal is asserted by an external arbiter to indicate to the rc32438 that access to the pci bus has been granted. while pcir- stn is asserted, the rc32438 ignores the state of this signal. pcigntn[1] o pci eeprom chip select . in satellite mode this signal takes on the alternate function of pcieecs an d is used as a pci serial eeprom chip select. pcigntn[5:2] o unused . these signals are unused in this mode and driven high. cben[3:0] command ipbus master dma ch. 9 pci master dma ch. 8 pci master pci target 0000 interrupt acknowledge no no no ignored 0001 special cycle no no no ignored 0010 i/o read yes yes no yes 0011 i/o write yes no yes yes 0100 reserved no no no ignored table 10.6 supported pci transactions (part 1 of 2) pin name type description table 10.5 pci arbitration pin functionality in pci satellite mode (part 2 of 2)
idt pci bus interface pci master 79rc32438 user reference manual 10 - 18 november 4, 2002 notes pci master the pci master interface, shown in figure 10.1, prov ides the ability for the cpu core to read and write to pci memory and i/o space. in addition, it allows the cpu core to perform pci configuration operations. although the pci master interface is an ipbus slave inte rface, it does not support transactions from masters other than the cpu core itself. a transaction to memory by any ipbus master other than the cpu core that maps to pci space is not acknowledged by the pci interface and results in an undecoded address error. the pci bus interface provides f our mapping regions from an ipbus lo cal address space to the pci bus. each mapping region has a corresponding pci local ba se address (pcilbax) register, pci local base address control (pcilbaxc) register, and pci local base address mapping (pcilbaxm) register. the pcilbax holds the local address space base address. the pcilbaxc register holds the configuration information for the mapping region. the pcilbaxm regi ster holds the base address of pci transactions that map to the pci bus address space through pcilbax. lo cal base addresses in pcilbax registers should be non-overlapping. if they are ov erlapping, one will be chosen. the pci addresses which are mapped by one or more pcilbaxm registers may overlap. the pci master interface does not support pci locki ng and thus will never assert the pcilockn signal. the pci master interface will queue a maximum of f our writes to the pci bus and one read from the pci bus. the pci master interface honor s byte enables, allowing individual bytes to be read and written using i/o and memory pci transactions. when a pci master interface issues a memory re ad, memory read line, or a memory read multiple transaction that is terminated early (e.g., a target disconnect), the pci master may reissue the read using the preferred read transaction. see the pci specificati on 2.2 section 3.1.2 for the definition of preferred read transactions. i/o read all ipbus read transactions whose address matches the base address in a pci local base address (pcilbax) register configured for i/o space (i.e., t he msi bit is set in the corresponding pci local base address control (pcilbaxc) register) result in an i/o read transaction on the pci bus. the value in the corresponding pci local base address map (pcilbaxm) r egister maps the upper bits of the local ipbus address to the pci i/o read address, as indicat ed by the size field of the pcilbaxc register. the byte enables on the pci bus correspond to the si ze/byte enables of the ipbus read operation (i.e., byte, halfword, triple-byte or word). 0101 reserved no no no ignored 0110 memory read yes yes no yes 0111 memory write yes no yes yes 1000 reserved no no no ignored 1001 reserved no no no ignored 1010 configuration read yes no no yes 1011 configuration write yes no no yes 1100 memory read multiple no no yes yes 1101 dual address cycle no no no ignored 1110 memory read line yes yes no yes 1111 memory write-and-invalidate no no yes yes cben[3:0] command ipbus master dma ch. 9 pci master dma ch. 8 pci master pci target table 10.6 supported pci transactions (part 2 of 2)
idt pci bus interface pci master 79rc32438 user reference manual 10 - 19 november 4, 2002 notes all ipbus initiated i/o read transactions translate into single data phase pci transactions even if a burst transaction was generated on the ipbu s (i.e., bursts are not supported). i/o write all ipbus write transactions whos e address matches the base address in a pci local base address (pcilbax) register configured for i/o space (i.e., t he msi bit is set in the corresponding pci local base address control (pcilbaxc) r egister) result in an i/o write transaction on the pci bus. the value in the corresponding pci local base addr ess map (pcilbaxm) regi ster maps the upper bits of the local ipbus address, as indicated by the size field of the pcilbaxc register, to the pci i/o read address. the value written on the pci bus corresponds to the data value of the ipbus write transaction. the byte enables on the pci bus correspond to the size/byte en ables of the ipbus write operation (i.e., byte, half- word, triple-byte, or word). ipbus initiated i/o write transactions may contain one or more data phases (i.e., bursts are supported). memory read an ipbus read transaction will result in a memory read transaction on the pci bus when the following conditions are met: ? the address matches the base address in a pci local base address (pcilbax) register that is configured for memory space (i.e., the msi bit is cleared in the corresponding pci local base address control (pci lbaxc) register) ? read transaction (rt bit in corresponding pcilbaxc ) bit is cleared, resulting in a memory read transaction on the pci bus. the value in the corresponding pci local base addr ess map (pcilbaxm) regi ster maps the upper bits of the local ipbus address, as indicated by the size field of the pcilbaxc register, to the pci memory read address. the byte enables on the pci bus correspond to the si ze/byte enables of the ipbus read operation (i.e., byte, halfword, triple-byte, or word). memory write all ipbus write transactions whos e address matches the base address in a pci local base address (pcilbax) register that is configured for memory s pace (i.e., the msi bit is cleared in the corresponding pci local base address control (pcilbaxc) register) re sult in a memory write transaction on the pci bus. the value in the corresponding pci local base addr ess map (pcilbaxm) regi ster maps the upper bits of the local ipbus address, as indicated by the size field of the pcilbaxc register, to the pci memory write address. the value written on the pci bus corresponds to the data value of the ipbus write transaction. the byte enables on the pci bus correspond to the size/byte en ables of the ipbus write operation (i.e., byte, half- word, triple-byte, or word). the pci bus interface will attempt to perform bur st pci memory write trans actions whenever possible. the pci interface will add a data phase to t he memory write transaction in progress if: ? data exists in the cpu master output fifo w hose address is equal to that of the current data quantity being transferred plus four ? the master latency timer has not expired. configuration read to generate a pci configuration r ead transaction, an ipbus master (e .g., cpu core) writes the desired configuration register addr ess to the pci configuration address (pcicfga) register and performs a read from the pci configuration data (p cicfgd) register. the value returned to the ipbus master will be that
idt pci bus interface pci master 79rc32438 user reference manual 10 - 20 november 4, 2002 notes received from the configuration r ead transaction. during the configurat ion read transaction, the pci byte enables will correspond to the size of the data read from the pcicfgd register (i.e ., byte, halfword, triple- byte, or word). if the bus field in the pci configuration address (p cicfga) register is zero, a type 0 configuration read transaction is performed. if t he bus field is non-zero, a type 1 configuration read transaction is performed. see section 3.2.2.3 of the pc i 2.2 specification for more information. for type 1 configuration transactions, the pciad[30: 2] takes on the value of the corresponding bit posi- tions in the pcicfga register. pciad[1:0] takes on the value 0x01 and pciad[31] takes on the value 0x0. for type 0 configuration transactions, the device fi eld in the pci configuration address (pcicfga) register is used to select the idsel line of the pc i satellite to be configured. the device field to idsel mapping is shown in table 10.7. type 0 configuration transactions with device field equal to zero correspond to the rc32438 device and are handled internally without generating a pci transaction. type 0 configuration transactions have pci address bits 31 through 11 (i.e., pciad[31:11]) set to all ones for device fields 0x1 through 0x15. in addition, pciad[1:0] are both zero. all pci configuration transactions use address stepping to allow for idsel predriving. refer to the pci 2.2 specification section 3.2.2.5 for more information. performing a pci configuration read from a nonexis ting device results in the devseln signal not being asserted by a pci target. this results in a master abort of the transaction and the setting of the receive master abort status (rma) bit in the status regi ster in pci configurati on space, value 0xffff_ffff being returned to the ipbus master, and an ipbus slav e acknowledge error if the ipbus error enable (ien) bit is set in the pcicfg register. the setting of the rma bit may be used to signal a cpu interrupt. the rc32438 does not support the generation of burst c onfiguration read transactions. all configuration read transactions hav e a single data phase. when the pci interface is set to operate in decou pled mode (i.e., the decoupled access enable (den) bit is set in the pci decoupled access control (pcida c) register), then the value read from the pcicfgd is not valid until the done (d) bit is set in the pci decoupled access status (pcidas) register. the error (e) and busy (b) bits in the pcidas register reflect the status of the operation. configuration write to generate a pci configuration writ e transaction, an ipbus master (e .g., cpu core) writes the desired configuration register addr ess to the pci configuration address (pcicfga) register and performs a write to the pci configuration data (pcicfgd) register. the va lue written by the ipbus ma ster will be used for the pci configuration write, and the pci byte enables will co rrespond to the size of the data written (i.e., byte, halfword, triple-byte, or word). device number address line device number address line device number address line 0x00 internal access 0x08 pciad[18] 0x10 pciad[26] 0x01 pciad[11] 0x09 pciad[19] 0x11 pciad[27] 0x02 pciad[12] 0x0a pciad[20] 0x12 pciad[28] 0x03 pciad[13] 0x0b pciad[21] 0x13 pciad[29] 0x04 pciad[14] 0x0c pciad[22] 0x14 pciad[30] 0x05 pciad[15] 0x0d pciad[23] 0x15 pciad[31] 0x06 pciad[16] 0x0e pciad[24] 0x07 pciad[17] 0x0f pciad[25] table 10.7 pci device fields to idsel mapping
idt pci bus interface pci master 79rc32438 user reference manual 10 - 21 november 4, 2002 notes if the bus field in the pci configuration address (p cicfga) register is zero, a type 0 configuration read transaction is performed. if t he bus field is non-zero, a type 1 configuration read transaction is performed. see section 3.2.2.3 of the pc i 2.2 specification for more information. for type 1 configuration transactions, the pciad[30: 2] takes on the value of the corresponding bit posi- tions in the pcicfga register. pciad[1:0] takes on the value 0x01 and pciad[31] takes on the value 0x0. for type 0 configuration transactions, the device field in the pci configuration address (pcicfga) register is used to select the idsel line of the pc i satellite to be configured. the device field to idsel mapping is shown in table 10.7. type 0 configuration transactions with device field equal to ze ro correspond to the rc32438 and are handled internally without generating a pci transac tion. type 0 configuration transactions have pci address bits 31 through 11 (i.e., pciad[31:11]) set to all ones for device fields 0x1 through 0x15. in addi- tion, pciad[1:0] are both zero. all pci configuration transactions use address stepping to allow for idsel predriving. refer to the pci 2.2 specification section 3.2.2.5 for more information. performing a pci configuration write to a nonexis ting device results in the devseln signal not being asserted by a pci target. this results in a master abort of the transaction and the setting of the receive master abort status (rma) bit in the status register in pci configuration space. the setting of the rma bit may be used to signal a cpu interrupt. the rc32 438 does not support generation of burst configuration write transactions. all configuration wr ite transactions have a single data phase. when the pci interface is set to operate in decou pled mode (i.e., the decoupled access enable (den) bit is set in the pci decoupled access control (pcida c) register), then the done (d), error (e), and busy (b) bits in the pci decoupled access status (pcidas) register reflect the status of the operation. memory read line all ipbus read transactions whose address matches the base address in a pci local base address (pcilbax) register that is configured for memory s pace (i.e., the msi bit is cleared in the corresponding pci local base address control (pcilbaxc) register ) and whose read transaction (rt bit in corresponding pcilbaxc) bit is set result in a memory read li ne transaction on the pci bus. the value in the corre- sponding pci local base address map (pcilbaxm) r egister maps the upper bits of the local ipbus address, as indicated by the size field of th e pcilbaxc register, to the pci memory read address. setting the read transaction (rt) bit in the corresponding pcilbaxc register indicates to the pci inter- face that a memory read line transaction should be used to prefetch data when the read transaction maps to the corresponding pcilbax register. the pci bus inte rface will supply the data quantity requested by the ipbus master read and will queue prefetch data in the ipbus master pci input fifo. subsequent sequen- tial reads that map to pcilbax wi ll result in queued data being returned. the memory read line is used when a pci master will read more than one word but no more than a cache line. memory read line transacti ons resulting from ipbus master read transactions will cause the pci bus interface to issue a memory read line burst transac tion that transfers either an entire cache line or eight words, whichever is smaller. the 8 word limit allows the cache_line_size register in pci configuration space to be set larger than the size of the ipbu s master pci input fifo. for example, setting the cache_line_size register to 16 words still results in only 8 words being transferred. prefetch data in the cpu master input fifo is fl ushed when an ipbus write transaction maps to the pci bus. error handling ipbus master fatal errors are: target timeout error, pci target terminates with a target abort, transaction could not be completed because the retry_limit was exceeded, parity error, and the transaction could not be completed because the bm bit is not set in the command register. an ipbus master fatal error is not propagated to the ipbus on prefetched data that is not subsequently read by an ipbus master (i.e., if the error occurs on pr efetched data, it is ignored unless the data is actually used). if a cpu generated pci master read transaction experiences a fatal error, the cpu master input
idt pci bus interface pci master 79rc32438 user reference manual 10 - 22 november 4, 2002 notes fifo is flushed and an ipbus slave acknowledge error is generated if the ipbus error enable (ien) bit is set in the pci control (pcic) register. when a sl ave acknowledge error is generated, the cpu read error (cre) bit is set in the pci status (pcis) r egister. if ien is not set, the error is ignored. if a cpu generated pci master write transaction experi ences a fatal error, an ipbus slave acknowledge error is generated and the cpu write error (cwe) bit is set in the pcis register . a slave acknowledge error is not generated. pci configuration address register figure 10.5 pci configuration address register (pcicfga) reg description: register. this field specifies the pci register address (i.e., the address of a 32-bit quantity within the target function?s configuration space). initial value: 0x0 read value: previous value written write effect: modify value func description: function. this field specifies the pci function number. initial value: 0x0 read value: previous value written write effect: modify value dev description: device. this field specifies the pci device numb er. pci address bits 31 through 11 (i.e., pciad[31:11]) are all set to one for device numbers 0x1 through 0x15. pci device number 0 refers to the rc32438?s host device (i.e., itself). initial value: 0x0 read value: previous value written write effect: modify value bus description: bus. this field specifies the pci bus number. initial value: 0x0 read value: previous value written write effect: modify value pcicfga 0 31 8 0 7 en 1 2 0 bus 5 dev 3 func 6 reg
idt pci bus interface pci master 79rc32438 user reference manual 10 - 23 november 4, 2002 notes pci configuration data register figure 10.6 pci configuratio n data register (pcicfgd) pci local base address [0|1|2|3] register figure 10.7 pci local base address [0|1|2|3] register (pcilba[0|1|2|3]) en description: enable. when this bit is set, accesses to the pci configuration data (pcicfgd) register are translated into pci configuration accesses. since there is no analogous pc-at i/o address space in the mips architecture, this bit cannot be cleared and is read-only. initial value: 0x1 read value: 0x1 write effect: read-only data description: data. reading this register results in a pci configuration read transaction using the information in the pci configuration address (pcicfga) register. the value returned to the processor is the result of the read. writing this register results in a pci configuration write transaction using the data value written to this register. initial value: 0x0 read value: previous value written write effect: modify value baddr description: base address. this field specifies the local address bits to use for decoding ipbus transactions to pci transactions. all of the local address bits that are active (i.e., those whose bit position is greater than or equal to size) are compared to the corresponding bits in this field. if they all match, then the corresponding transaction is mapped to the pci bus. initial value: 0x0 read value: previous value written write effect: modify value pcicfgd 0 31 32 data pcilba[0|1|2|3] 0 31 24 baddr 0 8
idt pci bus interface pci master 79rc32438 user reference manual 10 - 24 november 4, 2002 notes pci local base address [0|1|2|3] control figure 10.8 pci local ba se address [0|1|2|3] control (pcilba[0|1|2|3]c) msi description: memory space indicator. the value of this bit determines the type of transaction issued on the pci bus for local transactions that map to the pci bus through pcilbax. 0x0 - memory transactions 0x1 - i/o transactions initial value: 0x0 read value: previous value written write effect: modify value size description: address space size. this field indicates the size (in bits) of the address space for the corre- sponding local base address register. a size value less than eight disables the address space (i.e., no addresses will match). initial value: 0x0 read value: previous value written write effect: modify value sb description: swap bytes. this bit controls byte swapping for local transactions that map to the pci bus through the pcilbax register. 0x0 - no byte swapping 0x1 - swap bytes initial value: 0x0 read value: previous value written write effect: modify value rt description: read transaction. this bit controls the type of pci transaction(s) issued in response to ipbus master reads that map through pcilbax to the pci bus when the msi bit configures pcilbax to use memory transactions. when the msi bit is set, ipbus read operations use pci i/o read transactions regardless of the state of this bit. 0x0 - issue memory read transaction(s) on pci bus and pass data to ipbus as it becomes avail- able. 0x1 - issue memory read line transaction(s) on the pci bus and prefetch entire cache lines in anticipation of future ipbus reads. initial value: 0x0 read value: previous value written write effect: modify value pcilba[0|1|2|3]c 0 31 1 msi 1 0 size 5 1 sb 1 rt 23 0
idt pci bus interface decoupled pci master transactions 79rc32438 user reference manual 10 - 25 november 4, 2002 notes pci local base address [0|1|2|3] mapping register figure 10.9 pci local base address [0|1 |2|3] mapping register (pcilba[0|1|2|3]m) decoupled pci mast er transactions cpu core accesses to the pci bus may take a signifi cantly longer time to complete than normal ipbus transactions. one reason for this is the fact that the pci bus can run at one quarter the frequency of the ipbus. other reasons are: pci arbitration delay s, retried pci transactions, and pci wait states. reads from the cpu core to the pci bus will lock up the ipbus until the transaction completes. writes from the cpu core to the pci bus when the cpu master output fifo is full will also lock up the ipbus until a write transaction completes and space becomes ava ilable in the fifo. locking up the ipbus may have adverse affects on the real-time performance of the system. for example, it may lead to ethernet fifo overflows and underflows. the programmer may avoid locking up the ipbus due to cpu core-initiated writes to the pci bus by making sure that the cpu master output fifo is not fu ll prior to performing a wr ite. this may be determined by observing the state of the output fifo full (o ff) bit in the pci decoupled access status (pcidas) register. since the ipbus does not support split transac tions, there is no way to avoid locking up the ipbus using traditional cpu r eads of the pci bus. to overcome this difficulty, the pci bus inte rface supports decoupled r ead accesses. decoupled read accesses are enabled when the decoupled access enabl e (den) bit is set in the pci decoupled access control (pcidac) register. when the den bit is set, any cpu core-initiated read of an address that maps to pci space is completed immediately with a value of zero being returned to the cpu core. the pci bus interface then performs the read operation on the pci bus. while a decoupled access is in progress, the busy (b) bit is set in the pcidas register. when the r ead operation completes, the done (d) bit is set in the pcidas register, the b bit is cleared, and the value r ead from the pci bus is available in the pci decoupled access data (pcidad) register. the cpu may read this value, thus completing the decoupled pci read operation. if an error was detected while performing the pc i read, the error (e) bit is set and the value in the pcidad register is undefined. note that the d bit will not be set under this condition. the state of the pci cpu input and output fifos may be determined by examining the state of the ofe, off, ife, and iff bits in the pci decoupled access status register. all of the bits in the pcidas register not masked by the pci dec oupled access status mask regist er are ored together and presented to the interrupt controller as the pci decoupled access interrupt. note that when the den bit is set in the pcidac register, configuration r ead and write transactions to devices other than the rc32438 are also performed in a decoupled manner. configuration read and writes to internal rc32438 configuration regist ers are never performed in a decoupled manner. maddr description: mapping address. this field contains the pci base address for local transactions mapped to the pci bus through the pcilbax register. local transaction address bits 31 through the value of the size field in the pcilbaxc register are replaced by corresponding bits in this field for local transactions that map to the pci bus through the pcilbax register. initial value: 0x0 read value: previous value written write effect: modify value pcilba[0|1|2|3]m 0 31 24 maddr 0 8
idt pci bus interface decoupled pci master transactions 79rc32438 user reference manual 10 - 26 november 4, 2002 notes also note that ipbus bursts from the cpu core do not translate into pci bus burst transactions. in general, ipbus burst transactions are split into a series of pci transactions. the exception to this is when a decoupled transaction maps to a pci r egion that is configured to perform prefetching (i.e., a memory read line transaction). when this occurs, a pci burst transaction is generated to prefetch the data. pci decoupled access control register figure 10.10 pci decoupled ac cess control register (pcidac) pci decoupled access status register figure 10.11 pci decoupled acc ess status register (pcidas) den description: decoupled access enable. when this bit is set, pci decoupled mode is enabled and all cpu pci read transactions are decoupled. this mode affects all ipbus read transactions that map to the ipbus including those generated by the dma. initial value: 0x0 read value: previous value written write effect: modify value d description: done. this bit is set when a decoupled cpu pci read operation has completed and a valid value may be read from the pcidad register. initial value: 0x0 read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) b description: busy. this bit is set while a decoupled cpu pci read operation is being processed. initial value: 0x0 read value: status write effect: read only e description: error. this bit is set if an error was detected while performing a decoupled access pci read. pcidac 0 31 0 31 den 1 pcidas 0 31 0 25 d 1 b 1 ofe 1 off 1 ife 1 iff 1 e 1
idt pci bus interface decoupled pci master transactions 79rc32438 user reference manual 10 - 27 november 4, 2002 notes pci decoupled access status register figure 10.12 pci decoupl ed access status mask register (pcidasm)) initial value: 0x0 read value: status write effect: sticky bit ofe description: output fifo empty. this bit is set while the cpu master output fifo is empty. initial value: 0x1 read value: status write effect: read only off description: output fifo full. this bit is set while the cpu master output fifo is full. initial value: 0x0 read value: status write effect: read only ife description: input fifo empty. this bit is set while the cpu master input fifo is empty. initial value: 0x1 read value: status write effect: read only iff description: input fifo full. this bit is set while the cpu master input fifo is full. initial value: 0x0 read value: status write effect: read only d description: done. when this bit is set, the d bit in the pcid as register is masked from generating a pci decoupled access interrupt. initial value: 0x1 pcidasm 0 31 0 25 d 1 b 1 ofe 1 off 1 ife 1 iff 1 e 1
idt pci bus interface decoupled pci master transactions 79rc32438 user reference manual 10 - 28 november 4, 2002 notes read value: previous value written write effect: modify value b description: busy. when this bit is set, the b bit in the pcidas register is masked from generating a pci decoupled access interrupt. initial value: 0x1 read value: previous value written write effect: modify value e description: error. when this bit is set, the e bit in the pcidas register is masked from generating a pci decoupled access interrupt. initial value: 0x1 read value: previous value written write effect: modify value ofe description: output fifo empty. when this bit is set, the ofe bit in the pcidas register is masked from generating a pci decoupled access interrupt. initial value: 0x1 read value: previous value written write effect: modify value off description: output fifo full. when this bit is set, the off bit in the pcidas register is masked from gen- erating a pci decoupled access interrupt. initial value: 0x1 read value: previous value written write effect: modify value ife description: input fifo empty. when this bit is set, the ife bit in the pcidas register is masked from gen- erating a pci decoupled access interrupt. initial value: 0x1 read value: previous value written write effect: modify value iff description: input fifo full. when this bit is set, the iff bit in the pcidas register is masked from generat- ing a pci decoupled access interrupt. initial value: 0x1
idt pci bus interface pci master?p ci to memory dma (dma channel 8) 79rc32438 user reference manual 10 - 29 november 4, 2002 notes pci decoupled access data register figure 10.13 pci decoupled a ccess data register (pcidad) pci master?pci to memo ry dma (dma channel 8) dma channel 8 allows dma operations to be performed that transfer data from the pci bus to either the ddr or local memory. pci dma operations do not us e local mapping registers. the starting pci address for a dma operation is specified in the devcs field of the dma descriptor. this starting address is used for i/o as well as memory pci transactions. the pci starting address in devcs and the local starting address (specified in the ca field of the descriptor) may start on any byte boundary and the dma operation may transfer no more than 16k bytes. the pt field in the devcmd field of the dma descriptor specifies the type of pci transaction to use for the dma operation. the sb field indicates whet her bytes read from the pci bus should be swapped or passed unmodified into the pci dma input fifo. the pc i bus interface will begin issuing pci bus transac- tions based on the type specified in the pt field of t he dma descriptor?s devcmd field, starting at the address specified in the devcs field. data will be read from the pci bus whenever there is space for at least 16 words in the pci dma input fifo. the pci bus interface will attempt to burst as much data from the pci bus as possible during a transac- tion. the pci burst length is deter mined by system conditions. the transac tion will continue as long as the following conditions exist: ? it is not terminated by the pci target ? there exists at least one free word in the pci dma input fifo ? the byte count specified in the count fi eld of the dma descriptor has not reached zero ? the number of data phases has not exceeded that specified in the maximum burst size (mbs) field of the pcidma8c register, and t he master latency timer has not expired. the dma controller transfers data from the pci dm a input fifo to memory whenever a dma request event is generated. the pci bus interface generates a dma request event to the dma controller for dma channel 8 whenever there are 16 words of data or data corresponding to the end of a dma operation in the pci dma input fifo. read value: previous value written write effect: modify value data description: data field. this register contains the return value of a decoupled pci cpu read operation. initial value: 0x0 read value: return value of previously initiated decoupled pci cpu read operation write effect: modify value pcidad 0 31 data 32
idt pci bus interface pci master?p ci to memory dma (dma channel 8) 79rc32438 user reference manual 10 - 30 november 4, 2002 notes \ figure 10.14 device command field for pci to memory dma descriptors figure 10.15 device control and status value for pci to memory dma descriptors event description dma request event a request event is generated whenever 16 words of data or data corre- sponding to the end of a dma operation are present in the pci dma input fifo. pci to memory dma operations will generate dma request events during ipbus transactions as long as the above conditions are met for subsequent data in the fifo. dma done event a dma done event is never generated. dma terminated event a dma terminated event is generated if any of the following occur: pci master terminates transaction with a master abort (i.e., no target responds to transaction), pci target terminates transaction with a tar- get abort, transaction could not be completed because the retry_limit was exceeded, the transaction could not be completed because the bm bit is not set in the command register, and detection of a pci parity error. dma transfer size 16 words. limitations none. a dma operation may start and end on any local address or pci address byte boundary and may contain any number of bytes table 10.8 pci to memory dma operations pt pci transaction. this field specifies the pci transaction to use to read data from the pci bus. 0x0 memory read 0x1 memory read line 0x2 memory read multiple 0x3 i/o read sb swap bytes. this field control byte swapping for data read from the pci bus during a pci to memory dma operation. pciaddr pci address. this field specifies the starting pci address for pci to memory dma operations. devcmd 2 2 pt 0 1 sb devcs 0 31 32 pciaddr
idt pci bus interface pci master?p ci to memory dma (dma channel 8) 79rc32438 user reference manual 10 - 31 november 4, 2002 notes memory read pci memory read transactions are generated during pci to memory dma operations if the pci transac- tion (pt) field in the devcmd field of the dma descriptor is set to memory read. the pci bus interface will attempt to generate a burst transaction when possible. memory read multiple pci memory read transactions are generated during pci to memory dma operations if the pci transac- tion (pt) field in the devcmd field of the dma descriptor is set to memory read multiple. the pci bus inter- face will attempt to generate a burst transaction when possible. after a pci disconnect, the pci to memory dma operation may generate a ?preferred? memory r ead transaction (i.e., a memory read line or memory read transaction). for a definition of preferr ed memory, refer to pci specification 2.2. memory read line pci memory read transactions are generated during pci to memory dma operations if the pci transac- tion (pt) field in the devcmd field of the dma descriptor is set to memory read line. the pci bus interface will attempt to generate a burst transaction when possibl e. after a pci disconnect, the pci to memory dma operation may generate a preferred memory read transaction (i.e., a memo ry read transaction.) i/o read pci/io read transactions are generat ed during pci to memory dma oper ations if the pci transaction (pt) field in the devcmd field of the dma descriptor is set to i/o read. the pci bus interface will attempt to generate a burst transaction when possible. error handling pci to memory fatal errors are: ? pci target terminates with a target abort ? transaction could not be completed because the retry_limit was exceeded ? transaction could not be completed because the bm bit is not set in the command register ? detection of a pci parity error. if any of the above fatal errors are detected during a dma operation, the dma operation is halted with a terminated condition (i.e., the t bit is set in the descriptor) and the dma descriptor?s devcs field is updated with the address of the error. the dma descr iptor?s current address (ca) field contains the address to which the data (where the error occurred ) should have been written. note that no write actually takes place. the count field contai ns the actual number of bytes transferred. all data queued in the pci dma input fifo before the error occurred is wri tten to memory before the dma operation is halted. pci dma channel 8 configuration register figure 10.16 pci dma channel 8 c onfiguration register (pcidma8c) mbs description: maximum burst size. this field specifies the maximum number of words allowed in a pci to memory dma operation. a value of 0x0 corresponds to 0x1000 (i.e., 4k word transfer). initial value: 0x8 pcidma8c 0 31 12 mbs 19 0 1 our
idt pci bus interface pci master ? memory to pci dma (dma channel 9) 79rc32438 user reference manual 10 - 32 november 4, 2002 notes pci master ? memory to pci dma (dma channel 9) dma channel 9 allows dma operations to be performed that transfer data from either the ddr or local memory to the pci bus. pci dma operations do not us e local mapping registers. the starting pci address for a dma operation is specified in the devcs field of the dma descriptor. this starting address is used for i/o as well as memory pci transactions. the pci starting address in devcs and the local starting address (specified in the ca field of the descriptor) may start on any byte boundary and the dma operation may transfer any number of bytes (i.e., there are no restri ctions on the count field of the dma descriptor). the pt field in the devcmd field of the dma descriptor specifies the type of pci transaction to use for the dma operation. the sb field indi cates whether bytes read from the rc32438 memory and written to the pci bus should be swapped or passed unm odified. the pci bus interface w ill begin issuing pci bus trans- actions of the type specified in the pt field of the dma descriptor?s devcmd field and starting at the address specified in the devcs fiel d. data will be written to the pc i bus whenever there are at least 16 words in the pci dma output fifo or the pci dma outpu t fifo contains the last word of a dma transfer. the pci bus interface will attempt to burst as much data to the pci bus as possible during a transaction. for memory write, memory write and invalidate, and i/o write transactions, the pci burst transaction length is determined by system conditions. the transaction will continue as long as the following conditions exist: ? it is not terminated by the pci target ? there exists at least one available word in the pci dma output fifo ? the byte count specified in the count fi eld of the dma descriptor has not reached zero ? the number of data phases has not exceeded that specified in the maximum burst size (mbs) field of the pcidma9c register ? the master latency timer has not expired. the dma controller transfers dat a from the rc32438 memory to the pci dma output fifo whenever a dma request event is generated. the pci bus interf ace generates a dma request event to the dma controller for dma channel 9 whenever there are 16 free words available in the pci dma output fifo. read value: previous value written write effect: modify value our description: optimize unaligned burst reads. when this bit is cleared, the pci interface honors byte enables at the start and end of unaligned pci burst read transfers generated by the dma control- ler. this results in the pci interface potentially generating three separate transactions for a sin- gle unaligned dma burst read transfer; one pci transaction for the partial byte transfer at the start of the burst, one pci transaction for the a ligned portion of the burst transfer, and one pci transaction for the partial byte transfer at the end of the burst transfer. these three transactions are treated by the pci interface as three independent transactions. in most cases, byte enables generated during partial word pci memory transactions are irrele- vant as they have no side effect. thus, entire words could simply have been read from memory and unneeded data discarded. when this bit is set during a dma read transfer that is pro- grammed to generate memory read, memory read line, or memory read multiple transactions, then the pci interface will read complete words and discard unneeded data. this improves unaligned pci burst read transfer performance as it allows an entire burst read transfer gener- ated by the dma controller to be serviced as one pci transaction. initial value: 0x0 read value: previous value written write effect: modify value
idt pci bus interface pci master ? memory to pci dma (dma channel 9) 79rc32438 user reference manual 10 - 33 november 4, 2002 notes figure 10.17 device command field for memory to pci dma descriptors figure 10.18 device control and status value for memory to pci dma descriptors event description dma request event a request event is generated whenever 16 free words are available in the pci dma output fifo. memory to pci dma operations will gener- ate dma request events during ipbus transactions as long as the above conditions are met for subsequent data in the fifo. dma done event a dma done event is never generated. dma terminated event a dma terminated event is generated if any of the following occur: pci master terminates transaction with a master abort (i.e., no target responds to transaction), pci target terminates with a target abort, transaction could not be completed because the retry_limit was exceeded, the transaction could not be completed because the bm bit is not set in the command register, and detection of a pci parity error. dma transfer size 16 words. limitations none. a dma operation may start and end on any local address or pci address byte boundary and may contain any number of bytes table 10.9 memory to pci dma operations pt pci transaction. this field specifies the pci transactio n to use to write data to the pci bus. 0x0 memory write 0x1 memory write and invalidate 0x2 reserved 0x3 i/o write sb swap bytes. this field control byte swapping for data written to the pci bus during a memory to pci dma operation. pciaddr pci address. this field specifies the starting pci address for memory to pci dma operations. devcmd 2 2 pt 0 1 sb devcs 0 31 32 pciaddr
idt pci bus interface pci master ? memory to pci dma (dma channel 9) 79rc32438 user reference manual 10 - 34 november 4, 2002 notes memory write pci memory write transactions ar e generated during memory to pci dm a operations if the pci transac- tion (pt) field in the devcmd field of the dma descripto r is set to memory write. the pci bus interface will attempt to generate a burst transaction when possible. memory write and invalidate pci memory write and invalidate transactions are generated during memory to pci dma operations if the pci transaction (pt) field is set to memory wr ite and invalidate and the mwi bit is set in the command register in pci configuration spac e. if the memory write and invalidate enable (mwi) bit is not set in the command register in pci configur ation space and the pt field indicates memory write and invalidate transactions, the dma will perform the operation using memory write transactions. it is the responsibility of software to make sure that memory to pci dma operations that use memory write and invalidate transactions start on a cache line boundary and transfer an integral number of cache lines. to ensure this, the pci bus interface will wait until the required number of words for a cache line are present in the pci dma output fifo before initiati ng a memory write and invalidate transaction on the pci bus. if the starting address for a dma transfer is not on a cache line boundary or does not contain the number of words required for a complete cache line, the pci bus interface will use memory write transac- tions. if the mwi bit is not set in the command regist er in pci configuration s pace, the pci bus interface will use memory write transactions. if a target disconnects before a complete cache line is transferred, the pci bus interface will complete the remainder of the transfer using memo ry write transaction(s). i/o write pci i/o write transactions are generated during memory to pci dma operations if the pci transaction (pt) field in the devcmd field of t he dma descriptor is set to i/o write. the pci bus interface will attempt to generate a burst transaction when possible. error handling memory to pci fatal errors are: ? pci target terminates with a target abort ? transaction could not be completed because the retry_limit was exceeded ? transaction could not be completed because the bm bit is not set in the command register ? detection of a pci parity error. if any of the above fatal errors are detected during a dma operation, the dma operation is halted with a terminated condition (i.e., the t bit is set in the descriptor) and the dma descriptor?s devcs field is updated with the approximate address of the error. t he address is approximate as it may be off by several words. the dma descriptor?s current address (ca) field contains the address of the last data quantity transferred to the pci dma output fifo and not the corresponding address of where the pci error occurred. similarly, the count fiel d contains the number of bytes transferred to the pci dma output fifo and not the number of bytes written to the pci bus. all data queued in the pci dma output fi fo is discarded (i.e., the fifo is flushed) when a fatal error is detected.
idt pci bus interface pci target 79rc32438 user reference manual 10 - 35 november 4, 2002 notes pci dma channel 9 configuration register figure 10.19 pci dma channel 9 c onfiguration register (pcidma9c) pci target pci target mode will support up to 11 queued co mmands. these commands can be either 11 queued writes or 10 queued writes and one queued read. exceeding t hese queue limits will result in the pci host transaction being retried until the command can be accepted. the pci target interface, shown in figure 10.1, allows an external pci master to read and write any rc32438 local memory address in the same manner as t he cpu core. this allows a pci master to access the rc32438 memory (i.e., ddr or a device) or any inter nal register. the pci target interface allows pci masters to access 8/16/32-bit memory . the pci target interface will aut omatically perform byte scattering (writes) and gathering (reads) for devices on the me mory and peripheral bus and ddr sdram. the pci target interface is expected to obey the same ac cess and alignment rules as the cpu for accesses to internal rc32438 registers. the pci bus interface provides four mapping r egions from the pci space to the rc32438?s local address space. each mapping region has a corres ponding pci base address (pbax) register, pci base address control (pbaxc) register, and pci base a ddress mapping (pbaxm) regist er. these registers are all part of the pci configuration. the pbax register co rresponds to the bar register s in the pci 2.2 specifi- cation. their initial values and configuration howev er is controlled by t he pbaxc register. the pbaxc register holds the configuration information for the mapping region. the memory space indicator (msi) field in a pbaxc c ontrols how space is advertised (i/o or memory). if the space is advertised by the msi as memory, the pr efetchable (p) bit controls prefetching. if the space is advertised as i/o, the prefetchable bit is inactive. the swap bytes (sb) field in a pbaxc controls whether bytes are swapped or passed unmodified between the i pbus and the pci bus when the pci bus interface is accessed as a target. the pbaxm register holds t he local address space base address of pci transactions that map to the local address space through pbax. the local address mapped by a pbaxm register may be any valid local address. these local addresses are decoded in the same manner as cpu physical addr esses. the local addresses mapped by one or more pbaxm registers may be overlapping. pci base addre sses in pbax registers should be non-overlapping. if they are overlapping, one will be chosen. pci target burst transactions which attempt to bur st data beyond the address space allocated to a pbax will terminate with a target disconnect without data. the pci address spaces mapped by two pbax regis- ters may be contiguous. pci target burst transactions which attempt to burst data across adjacent address spaces mapped by pbax registers will terminate with a target disconnect without data. the pci target control register (pcitc) contains fields which control the behavior of the pci bus interface when acting as a pci target. mbs description: maximum burst size. this field specifies the number the maximum number of words allowed in a memory to pci dma operation. a value of 0x0 corresponds to 0x1000 (i.e., 4k word transfers). initial value: 0x8 read value: previous value written write effect: modify value pcidma9c 0 31 12 mbs 20 0
idt pci bus interface pci target 79rc32438 user reference manual 10 - 36 november 4, 2002 notes the retry timer controls the number of pci clock cycles the pci interface will wait for the first data of an access before issuing a retry. this is used duri ng read operations (i.e., memory read, memory read multiple, memory read line, and i/o read) to specify t he number of pci clock cycles the pci bus interface is allowed (delay supplying the first data quantity of a transaction) before the transaction must be retried. during write operations (i.e., memory write, memory wr ite and invalidate, and i/o write), this field specifies the number of pci clock cycles the pci bus interface is allowed to wait for space to appear in the pci target input fifo before a transaction must be retried. the initial value for the retry timer is specified in the retry timer (rtimer) fi eld of the pcitc register. pci 2.2 specification sets the maximum to 16 pci cl ock cycles, but the rc32438 allows this limit to be extended to 255 clock cycles. the disc onnect timer controls the number of pci clock cycles the pci inter- face will wait for between data transfers. if the pci bus interface is unable to accept data before the timer expires, it issues a disconnect. pci 2.2 specificati on sets the maximum to 8 pci clock cycles, but the rc32438 allows this limit to be extended to 255 clock cycles. the pci bus interface supports target delayed r eads. the pci bus interface supports only one pending delayed read. if a read is attempted while a delay ed read is pending, the transaction is retried and a delayed read is not initiated for the transaction. the pci master that initiates a delayed read is expected to retry the transaction until the read completes. the pci bus interface contains a discard timer. if the master does not repeat a delayed read request within 2 15 clock cycles, the discard timer will expire and discard the pending read. this is necessary to ensure that a malfunctioning pci master (e.g., one which has a pending delayed read) does not cause the rc32438 to deadlock. if the discard timer expi res and a pending read is discarded, the pending read discarded (prd) bit is set in the pcis register. the discard timer may be disabled by setting the disable discard timer (ddt) bit in the pcitc register. the pci transaction ordering constrai nts may be viewed as favoring tar get write operations since only a single delayed read is allowed when ther e are posted writes. by contrast, mu ltiple posted writes are allowed when there is a delayed read. in an effort to provide some level of fairness, the pci bus interface supports a mode in which all transactions are retried when t here is a delayed read. when the retry when delayed read (rdr) bit is set in the pcitc r egister, all pci target transactions are retired as long as there is a pending delayed read. the pci bus interface allows normal pci target transaction ordering constr aints to be overridden for improved efficiency in some system scenarios. for more information, see the transaction ordering section later in this chapter. the pci bus interface supports target locking. once a lock has been established, all pci target transactions to the rc32438 are retried until the lock has been released. the rc32438 does not implement locked operations on the ipbus. therefore, lock operations are only useful for creating atomic sequences as seen by masters on the pci bus. the rc32438 does not support ipbus master accesses to pci addresses that map to its pci target interface. an ipbus master access to a pci addre ss that maps to the rc32438?s pci target interface results in a master abort. also, the rc32438 does not support pci bus master accesses to the rc32438?s local memory that maps to pci space. these oper ations do not damage hardware, but their results are undefined. i/o read pci i/o read transactions that map to a pci base addr ess (pbax) register are converted to local ipbus read operations. data from an i/o read transaction is tr anslated using the pbaxm register into a local ipbus address. pci i/o read transactions are not allowed to burst. the pci memory write maximum completion time limi t of 10 microseconds (see section 3.5.3 in the pci 2.2 specification) is met under nor mal system conditions, but this limit may be violated in some system configurations. for example, setting the rdr bit may violate this specif ication. another example is when pci target bus requests are masked in the ipbus arbite r. it is the responsibility of the system designer (hardware and software) to guarant ee adherence to this requirement.
idt pci bus interface pci target 79rc32438 user reference manual 10 - 37 november 4, 2002 notes i/o write pci i/o write transactions that map to a pci base a ddress (pbax) register are converted to local ipbus write operations and posted to the pci target input fi fo. pci i/o write transacti ons are posted to the pci target input fifo and are not allowed to burst. memory read pci memory read transactions that map to a pci base address (pbax) register are mapped to local ipbus read operation(s). the behavior of pci target me mory read operations is determined by the state of the memory read behavior (mr) field in the corres ponding pbaxc register. if mr field is 0x0, the memory read behaves as described below. if the mr field is 0x1, the memory read transaction behaves in the same manner as a memory read line transac tion. if the mr field is 0x2, th e memory read transaction behaves in the same manner as a memory read multiple transaction. pci memory read transactions that map to a pci ba se address (pbax) register are mapped to a local ipbus word read operation. pci memory read transactions are not allowed to burst unless the memory read is mapped to a memory read line or memory read multiple. memory write pci memory write transactions that map to a pci base address (pbax) register are mapped to a local ipbus write operation(s) and posted into the pci target input fifo. the pci bus interface will attempt to extend memory write burst transaction for as long as possible. a burst transaction will be retried by the rc32438 if the pci target input fifo is full for a period of time which exceeds the programmed rtimer/ dtimer value in the pcitc register. configuration read pci configuration read transactions return the value of the register in pci configuration space with address pciad[7:2]. the pci bus interface does not s upport target burst configur ation read transactions. if a configuration read transaction cons ists of more than a single data phase, the target will terminate the transaction with a disconnect. configuration write pci configuration write tr ansactions return the value of the regi ster in pci configuration space with address pciad[7:2]. the pci bus interface will use the byte enables to determine which bytes of the word address by pciad[7:2] are being modified. the pci bus interface does not support target burst configura- tion write transaction. if a configur ation write transaction consists of more than a single data phase, the target will terminate the transaction with a disconnect. memory read multiple pci memory read multiple transactions that map to a pci base address (pbax) register are mapped to local ipbus read operations. memory read multiple tran sactions fetch not only the data requested by the data phase of the transaction but cause the pci bus in terface to prefetch additional data. the prefetching behavior is controlled by the memory read multiple prefetching behavior (mrm) bit. if cleared, the pci bus interface performs conservative prefetching. ot herwise, the pci bus interface performs aggressive prefetching. in conservative prefetching, the pci bus interf ace will prefetch 16 words whenever a memory read multiple transaction is in progress and there are less t han 8 words available in the pci target output fifo. in aggressive prefetching, the pci bus interface wi ll continue prefetching bursts of 16 words as long as room exists in the pci target output fifo. the pci target output fifo will discard prefetched data in the fifo when a memory read line multiple burst transaction completes.
idt pci bus interface pci target 79rc32438 user reference manual 10 - 38 november 4, 2002 notes memory read line pci memory read multiple transactions that map to a pci base address (pbax) register are mapped to local ipbus read operations. the prefetching behavior is controlled by the memory read line prefetching behavior (mrl) bit. if cleared, the pci bus interface wi ll prefetch data to the end of the cache line. if the mrl bit is set, the pci bus interfac e will translate a memory read line transaction to a memory read multiple transaction. memory write and invalidate pci memory write and invalidate transactions that map to a pci base address (pbax) register are translated into memory write transactions. error handling data parity errors detected during ta rget transactions are handled as def ined in the pci 2.2 specification (i.e., the pe bit in the status register is set and pe rrn is asserted if the pen bit is set in the command register) and the transaction is completed as though no error was detected (i.e., writes are performed and reads deliver possi bly corrupted data). address parity errors detected during target read trans actions result in termination of the transaction with a target abort. an ipbus transaction is not gener ated when an address parity error is detected during a target read transaction. address parity errors detected during target write transacti ons result in termination of the transaction with a target abort. an ipbus tr ansaction is not generated when an address parity error is detected during a target write transaction. the pci bus interface terminates a target read or write transaction with a target abort if the address space monitor detects a pci master attempting to ac cess an invalid local address range. for more informa- tion, refer to the address space monitor section in c hapter 4, system integrity functions. if the transaction was a delayed read, a target abort is signaled when the transaction is retried. if the pci transaction was a posted write, the transaction is viewed as completed by the pci bus master and results in the pci bus inter- face signalling a pci system error by asserting serrn for one pci clock cycle if the system error enable (sen) and parity error enable (pen) bits are set in the command register. an address space monitor error detected during servic ing of a posted target write transaction may result in multiple assertions of serrn. data for a posted write transaction is queued in the pci target input fifo and segmented into one or more ipbus transactions. each ipbus transaction is treated independently. if an undecoded address is detected in an ipbus transaction, the remaining ipbus transaction data in the input fifo is discarded and serrn is asserted for one pci cl ock cycle if the sen and pen bits are set. since a posted pci write transaction may result in multiple ipbu s transactions, this may result in multiple assertions of serrn. pci target control register figure 10.20 pci target control register (pcitc) rtimer description: retry timer. this field specifies the number of pci clock cycles the pci interface will wait for the first data of an access before issuing a retry. the pci 2.2 specification sets the maximum limit of this timer at 16 pci clock cycles, but in some systems it may be necessary to extend this limit. the minimum retry timer value is eight. values less than eight are aliased to eight. initial value: 0x10 pcitc 0 31 12 0 rtimer 8 dtimer 8 ddt 1 rdr 1 2 0
idt pci bus interface transaction ordering 79rc32438 user reference manual 10 - 39 november 4, 2002 notes transaction ordering ipbus master (i.e., cpu) reads and writes to the pci bus maintain the total ordering defined by the ordering of transactions on the ipbus. ipbus master pci read transactions are given precedence over pci dma read and write operations. ipbus master pci wr ite operations are given precedence over pci dma read and write operations. pci dma read and write operations are given fair acce ss to the pci bus. this means that if pci to memory and memory to pci dma operations are in progr ess, access to the pci bus will alternate between pci dma reads and pci dma writes. pr efetched data in the cpu master input fifo is flushed if an ipbus master write is performed that maps to the pci bus. ipbus master writes may be posted in the cpu master output fifo. a ipbus master read from the pci bus cannot complete until all posted writes in the cpu master output fifo have completed. read value: previous value written write effect: modify value dtimer description: disconnect timer. this field specifies the number of pci clock cycles the pci interface will wait between data phases in an access before issuing a disconnect. the pci 2.2 specification sets the maximum limit of this timer at 8 pci clock cycl es, but in some systems it may be necessary to extend this limit. the minimum disconnect timer value is four. values less than four are aliased to four. initial value: 0x8 read value: previous value written write effect: modify value rdr description: retry when delayed read. when this bit is set, all transactions are retried as long as there is an uncompleted delayed read. w arning: setting this bit may violate the pci 2.2 specification -- see implementation note in the pci 2.2 specification section 3.3.3.3.4. 0x0 - post writes 0x1 - retry writes when delayed read initial value: 0x0 read value: previous value written write effect: modify value ddt description: disable discard timer. when a master does not repeat a delayed read request within 2 15 pci clock cycles the pci interface discards the delayed completion. when this bit is set, delayed completions are never discarded. 0x0 - discard timer enabled 0x1 - discard timer disabled initial value: 0x0 read value: previous value written write effect: modify value
idt pci bus interface pci messaging unit 79rc32438 user reference manual 10 - 40 november 4, 2002 notes software may use the ipbus master (i.e., cpu) read/ write ordering constraints to flush the cpu master output fifo. a cpu read will not complete until all wr ites in the cpu master output fifo have completed. no ordering constraints are enforced between cpu and dma transactions. no or dering constraints are enforced between pci to memory and memory to pci dma operations. a pci to memory dma operation completes when the last data quantity of the dma operation is written to the rc32438?s local memory (i.e., ddr or device). a memory to pci dma operation completes when the last data quantity of the dma operation is written to t he pci. this implies that the pci dma output fifo can only contain data associated with one dma operation at a time. target writes which are posted by the pci bus inte rface must complete in the order in which they occurred on the pci bus. no ordering constraints ar e enforced between writes posted by an ipbus master (i.e., cpu core) and by an external pci master to the rc32438?s pci target interface. due to transaction ordering constraint s, a pci target read is not allowed to complete as long as there are posted writes in the pci target input fifo. t he rc32438 will retry the read if it cannot be completed in the allotted time. the pci target interface suppor ts one delayed read. the delayed read cannot complete until all previous posted writes have completed. the pci transaction ordering constrai nts may be viewed as favoring tar get write operations since only a single delayed read is allowed when t here are posted writes, while multip le posted writes are allowed when there is a delayed read. in an effort to provide some level of fairness, the pci bus interface supports a mode in which all transactions are retried when there is a delayed read. when the retry when delayed read (rdr) bit is set in the pcitc register, all pci target transactions are retired as long as there is a pending delayed read. in some system scenarios, it may be desirable to vi olate pci target transacti on ordering constraints in order to improve performance. normal ly, a pci target read is not allowed to complete until all previously posted writes to the target have completed. in situations where one can guarantee that input and output buffers never overlap, this cons traint may be overly restrictive. when the target read priority (trp) bit is set in a pci base address contro l (pbaxc) register, target read transactions that map to the rc32438?s local addr ess space using that pci base address are allowed to complete even if there are posted targeted write tr ansactions. since the trp bit only affects target reads that map using that pci base address, a synchroni zation barrier may be impl emented by performing a target read to a different pci base address that does not have the trp bit set. pci messaging unit the rc32438 provides message and doorbell registers to facilitate efficient communication between pci agents and the cpu. the messaging unit is a subset of the i 2 o messaging unit as well as that imple- mented by the intel i960rx. there ar e different behaviors for some of the registers depending on if they are written by the cpu or by a pci master. all of the bi ts in the pci inbound interrupt cause (pciiic) register which are not masked by the pci inbound interrupt ma sk (pciiim) register are ored and result in the status of the inbound interrupt (ii) bit in the pci status (pcis) register. all of the bits in the pci outbound interrupt cause (pcioic) register which are not masked by the pci outbound interrupt mask (pcioim) register are ored together. if this ored value is a one, the pci messaging unit interrupt (pcimuintn) signal is driven low. otherwise, if the ored value is a zero, the pcimuintn signal is tri-stated. the pcimuintn signal is a gpio alternat e function output (for more information, refer to chapter 12, general purpose i/o controller).
idt pci bus interface pci messaging unit 79rc32438 user reference manual 10 - 41 november 4, 2002 notes pci inbound message [0|1] register figure 10.21 pci inbound message [0|1] register (pciim[0|1]) pci outbound message [0|1] register figure 10.22 pci outbound message [0|1] register (pciom[0|1]) msg description: message. when written, the value of the register is modified and the corresponding message bit (im0 or im1) is set in the pci inbound interrupt cause (pciiic) register. this register is intended for passing messages from the pci bus to the cpu and thus can only be written by pci bus masters. the cpu may read this register, but cpu writes are ignored. initial value: 0x0 read value: previous value written write effect: modify value (cpu writes are ignored) msg description: message. when written, the value of the register is modified and the corresponding message bit (om0 or om1) is set in the pci outbound interr upt cause (pcioic) register. this register is intended for passing messages from the cpu to the pci bus and thus may only be written by the cpu. pci bus masters may read this register, but pci bus master writes are ignored. initial value: 0x0 read value: previous value written write effect: modify value (pci bus master writes are ignored) pciim[0|1] 0 31 32 msg pciom[0|1] 0 31 32 msg
idt pci bus interface pci messaging unit 79rc32438 user reference manual 10 - 42 november 4, 2002 notes pci inbound doorbell register figure 10.23 pci inbound d oorbell register (pciid) pci inbound interrupt cause register figure 10.24 pci inbound interrupt cause register (pciiic) indoor description: inbound doorbell. writing a one to a bit in this field by a pci bus master causes the bit to be set. writing a one to a bit in this field by the cpu clears the bit if it was set. the inbound doorbell (id) bit in the pci inbound interrupt cause (pciiic) regi ster is set if any of the bits in this register are set. initial value: 0x0 read value: previous value written write effect: modify value (pci bus master writes one to set bit, cpu writes one to clear bit) im0 description: inbound message 0. this bit is set when the pci inbound message 0 (pciim0) register is writ- ten by a pci bus master. initial value: 0x0 read value: status write effect: sticky, writing a one clears this bit im1 description: inbound message 1. this bit is set when the pci inbound message 1 (pciim1) register is writ- ten by a pci bus master. initial value: 0x0 read value: status write effect: sticky, writing a one clears this bit id description: inbound doorbell. this bit is set when any bit in the pci inbound doorbell (pciid) register is set. this bit is read-only and simply represents the or of all the bits in the pciid register. initial value: 0x0 pciid 0 31 32 indoor pciiic 0 31 29 0 1 im0 1 im1 1 id
idt pci bus interface pci messaging unit 79rc32438 user reference manual 10 - 43 november 4, 2002 notes pci inbound interrupt mask register figure 10.25 pci inbound interrupt mask register (pciiim) read value: status write effect: read-only im0 description: inbound message 0. when this bit is set, the im0 bit in th e pciic register is masked from set- ting the inbound interrupt (ii) bit in the pci status (pcis) register. initial value: 0x1 read value: previous value written write effect: modify value im1 description: inbound message 1. when this bit is set, the im1 bit in th e pciic register is masked from set- ting the inbound interrupt (ii) bit in the pci status (pcis) register. initial value: 0x1 read value: previous value written write effect: modify value id description: inbound doorbell. when this bit is set, the id bit in the pciic register is masked from setting the inbound interrupt (ii) bit in the pci status (pcis) register. initial value: 0x1 read value: previous value written write effect: modify value pciiim 0 31 29 0 1 im0 1 im1 1 id
idt pci bus interface pci messaging unit 79rc32438 user reference manual 10 - 44 november 4, 2002 notes pci outbound doorbell register figure 10.26 pci outbound d oorbell register (pciod) pci outbound interrupt cause register figure 10.27 pci outbound interr upt cause register (pcioic) outdoor description: outbound doorbell. writing a one to a bit in this field by the cpu causes the bit to be set. writ- ing a one to a bit in this field by a pci master clears the bit if it was set. the outbound doorbell (od) bit in the pci outbound interrupt cause (pcioic) register is set if any of the bits in this reg- ister are set. initial value: 0x0 read value: previous value written write effect: modify value (cpu writes one to set bit, pci bus master writes one to clear bit) om0 description: outbound message 0. this bit is set when the pci outbound message 0 (pciom0) register is written by the cpu. initial value: 0x0 read value: status write effect: sticky, writing a one clears this bit om1 description: outbound message 1. this bit is set when the pci outbound message 1 (pciom1) register is written by the cpu. initial value: 0x0 read value: status write effect: sticky, writing a one clears this bit od description: inbound doorbell. this bit is set when the od bit in the pcioic register is masked from gener- ating a pci interrupt output. initial value: 0x0 pciod 0 31 32 outdoor pcioic 0 31 29 0 1 om0 1 om1 1 od
idt pci bus interface pci configuration registers 79rc32438 user reference manual 10 - 45 november 4, 2002 notes pci outbound interrupt mask register figure 10.28 pci outbound interrupt mask register (pcioim) pci configuration registers the registers in this section are not memory mapped in the rc32438?s memory space. they may be read and written by the cpu core or the ethernet pci master using pci configuration read and write opera- tions.table 10.10 shows the pci configuration space registers. addresses between 0x00 and 0x3f follow the type 00h configuration space header defined by the pci 2.2 specification. addresses between 0x40 and 0x 7f contain device dependent registers. addresses between 0x80 and 0xff are not used. shaded fields are read-only to an external pci bus master. the cpu core may read and modify any pci configuration regi ster or field in either host or satellite mode. read value: status write effect: read-only om0 description: outbound message 0. this bit is set when the om0 bit in the pcioic register is masked from generating a pci interrupt output. initial value: 0x0 read value: previous value written write effect: modify value om1 description: outbound message 1. this bit is set when the om1 bit in the pcioic register is masked from generating a pci interrupt output. initial value: 0x0 read value: previous value written write effect: modify value od description: inbound doorbell. this bit is set when the od bit in the pcioic register is masked from gener- ating a pci interrupt output. initial value: 0x0 read value: previous value written write effect: modify value pcioim 0 31 29 0 1 om0 1 om1 1 od
idt pci bus interface pci configuration registers 79rc32438 user reference manual 10 - 46 november 4, 2002 notes the pci serial eeprom interface loads the initial va lue of all pci configuration registers, shown as shaded in table 10.10. values shown as ?xxxxxxxx? are don?t care values. registers in pci configuration space are unaffected by a warm reset except when the warm reset was the result of the assertion of the pci reset signal when operating in pci satellite mode. w hen this occurs, all pci registers are set to their initial values. address 31 0 0x00 device_id vendor_id 0x04 status command 0x08 class _code revision_id 0x0c bist header_type master_latency cache_line_size 0x10 pba0 0x14 pba1 0x18 pba2 0x1c pba3 0x20 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0x24 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0x28 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0x2c subsystem_id subsystem_vendor_id 0x30 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0x34 reserved 1 1. writes to reserved fields are i gnored. reserved fields always retu rn a value of zero when read. 0x38 reserved 0x3c max_lat min_gnt interrupt_pin interrupt_line 0x40 reserved retry_limit trdy_timeout 0x44 pba0c 0x48 pba0m 0x4c pba1c 0x50 pba1m 0x54 pba2c 0x58 pba2m 0x5c pba3c 0x60 pba3m 0x64 pmgt 0x68 - 0x7f reserved 0x80 - 0xff reserved (not loaded from pci serial eeprom) table 10.10 pci configuration registers
idt pci bus interface pci configuration registers 79rc32438 user reference manual 10 - 47 november 4, 2002 notes vendor id register figure 10.29 vendor id register (vendor_id) device id register figure 10.30 device id register (device_id) command register figure 10.31 command register (command) id description: id. this field specifies the vendor of the device. it should be initialized to 0x111d which corre- sponds to the vendor idt. initial value: 0x111d or value initialized from pci serial eeprom read value: previous value written write effect: cpu can modify value, read-only from pci bus id description: id. this field specifies the device id. initialize this field to: 0x0207 ? rc32438 initial value: 0x0 or value init ialized from pci serial eeprom read value: previous value written write effect: cpu can modify value, read-only from pci bus i/o description: i/o enable. when this bit is set the device responds to i/o space accesses. initial value: 0x0 vendor_id 0 15 16 id device_id 0 15 16 id command 1 io 1 mem 1 bm 1 0 1 mwi 1 0 1 pen 1 0 1 sen 1 fbb 0 15 6 0
idt pci bus interface pci configuration registers 79rc32438 user reference manual 10 - 48 november 4, 2002 notes read value: previous value written write effect: modify value mem description: memory enable. when this bit is set the device responds to memory space accesses. initial value: 0x0 read value: previous value written write effect: modify value bm description: bus master enable. when this bit is set, the device is allowed to act as a pci master. initial value: 0x0 read value: previous value written write effect: modify value mwi description: memory write and invalidate enable. when this bit is set, the pci bus interface may generate memory write and invalidate transactions on the pci bus. initial value: 0x0 read value: previous value written write effect: modify value pen description: parity error enable. when this bit is set, the device must take its normal action when a parity error is detected (see pci 2.2 specification). when this bit is cleared, the devices sets its parity error (pe) bit in the pci status register, does not assert perrn, and continues normal oper- ation. initial value: 0x0 read value: previous value written write effect: modify value sen description: system error enable. when this bit is set, the serrn drive is enabled. when this bit is cleared, the serrn driver is disabled. this bit and the pen bit must be set to report address phase parity errors. initial value: 0x0 read value: previous value written write effect: modify value fbb description: fast back to back enable. when this bit is set, the pci bus interface is allowed to generate fast back-to-back transactions to different agents as described in pci 2.2 specification, section 2.4.2. when this bit is cleared, fast back-to-back transactions are only performed to the same agent. note : rc32438 never generates fast back-to-back transactions.
idt pci bus interface pci configuration registers 79rc32438 user reference manual 10 - 49 november 4, 2002 notes status register figure 10.32 status register (status) initial value: 0x0 read value: previous value written write effect: modify value m66 description: 66 mhz capable. when this bit is set, it indicates that the device pci bus interface can be oper- ated at 66 mhz. initial value: 0x1 read value: current value write effect: no effect, this bit is hardwired to a one. fbb description: fast back-to-back capable. when this bit is set it indicates the target is capable of accepting fast back-to-back transactions when the transactions are not to the same agent. initial value: 0x1 read value: current value write effect: no effect, this bit is hardwired to a one. mdpe description: master data parity error detected. this bit is set when three conditions are met: (1) the bus agent asserted perrn on a read or observed perrn asserted on a write; (2) the agent setting the bit acted as the bus master for the operation in which the error occurred; and (3) the pen bit is set in the command register. initial value: 0x0 read value: status write effect: pci sticky bit (set by hardware: writ e of one clears bit, write of zero has no effect). dst description: device select timing. this field indicates the slowest timing of pcidevseln when the pci bus interface responds to a pci transaction as a target. initial value: 0x1 read value: 0x1 write effect: no effect, this field is hardwired to a 0x1. status 5 0 1 m66 1 0 1 fbb 1 mdpe 2 dst 1 sta 1 rta 1 rma 1 sse 0 15 1 pe
idt pci bus interface pci configuration registers 79rc32438 user reference manual 10 - 50 november 4, 2002 notes sta description: signalled target abort status. this bit is set by the pci bus interface whenever it acts as a pci target and terminates a transaction with a target-abort. initial value: 0x0 read value: status write effect: pci sticky bit (set by hardware: writ e of one clears bit, write of zero has no effect). rta description: received target abort status. this bit is set by the pci bus interface whenever it acts as a master and a transaction is terminated with a target-abort. initial value: 0x0 read value: status write effect: pci sticky bit (set by hardware: writ e of one clears bit, write of zero has no effect). rma description: received master abort status. this bit is set by the pci bus in terface whenever it acts as a pci master and terminates a host-to-pci transaction with a master abort. initial value: 0x0 read value: status write effect: pci sticky bit (set by hardware: writ e of one clears bit, write of zero has no effect). sse description: signaled system error. this bit is set by the pci bus interface whenever it asserts pciserrn. initial value: 0x0 read value: status write effect: pci sticky bit (set by hardware: writ e of one clears bit, write of zero has no effect). pe description: parity error. this bit is set by the device whenever it detects a parity error, even if parity error handling is disabled. initial value: 0x0 read value: status write effect: pci sticky bit (set by hardware: writ e of one clears bit, write of zero has no effect).
idt pci bus interface pci configuration registers 79rc32438 user reference manual 10 - 51 november 4, 2002 notes device revision id register figure 10.33 device revision id register (revision_id) class code register figure 10.34 class code register (class_code) cache line size register figure 10.35 class code register (class_code) id description: id. this register contains the current revision identifier for the device. initial value: 0x0 or value init ialized from pci serial eeprom read value: previous value written write effect: cpu can modify value, read-only from pci bus ccv description: class code value. this field identifies the function of the device. see appendix d in the pci 2.2 specification for a complete list of class codes. initial value: 0x0 or value init ialized from pci serial eeprom read value: previous value written write effect: cpu can modify value, read-only from pci bus cls description: cache line size. this field specifies the size of a cache line in 32-bit words. this field may only be initialized to the following values: 0, 1 2, 4, 8, 16, 32, 64, 128. initializing this field to an unsup- ported value results in the same behavior as initializing this field to zero. initial value: 0x0 revision_id 0 7 8 id class_code 0 23 24 ccv cache_line_size 0 7 8 cls
idt pci bus interface pci configuration registers 79rc32438 user reference manual 10 - 52 november 4, 2002 notes master latency register figure 10.36 master laten cy register (master_latency) header type register figure 10.37 header type register (header_type) read value: previous value written write effect: modify value ml description: master latency. this field specifies the minimum time the pci bus interface, when operating as a pci bus master, is allowed to retain ownership of the bus after it has acquired bus ownership and initiated a transaction. in the rc32438, the minimum value is four pci bus clock cycles. initial value: 0x0 read value: previous value written write effect: modify value ht description: header type. this field identifies the layout of the second part of the predefined header (begin- ning at byte 0x10 in pci configuration space). see section 6.2.1 of the pci 2.2 specification for information on this field. initial value: 0x0 or value init ialized from pci serial eeprom read value: previous value written write effect: cpu can modify value, read-only from pci bus master_latency 0 7 6 ml 2 0 header_type 0 7 8 ht
idt pci bus interface pci configuration registers 79rc32438 user reference manual 10 - 53 november 4, 2002 notes bist register figure 10.38 header type register (bist) pci base address [0|1|2|3] register figure 10.39 pci base address [0|1|2|3] register (pba[0|1|2|3]) bist description: built in self test. the rc32438 does not implement this optional pci register and functionality. thus, the value of this field should be zero. initial value: 0x0 or value init ialized from pci serial eeprom read value: current value write effect: no effect, this bit is hardwired to a 0x0. msi description: memory space indicator. this bit determines if the base address register maps into memory or i/o space. 0x0 - memory space 0x1 - i/o space initial value: 0x0 read value: value in msi fiel d of correspondi ng pbaxc register write effect: read only p description: prefetchable. when the msi field indicates that the base address register maps into memory space, this bit indicates if the memory is prefetchable. 0x0 - non-prefetchable 0x1 - prefetchable (no side effect on reads and write merging is allows) initial value: 0x0 read value: value in p field of corresponding pbaxc register write effect: read only bist 0 7 8 bist pba[0|1|2|3] 0 31 24 baddr 1 msi 0 2 1 p 0 4
idt pci bus interface pci configuration registers 79rc32438 user reference manual 10 - 54 november 4, 2002 notes subsystem vendor id figure 10.40 subsystem ve ndor id register (svi) subsystem id register figure 10.41 subsystem id register (subsystem_id) baddr description: base address. this field specifies the pci address bits to use for decoding a pci transaction to a local transaction. see the pci specification for more information. the value of the size field in t he corresponding pbaxc register cont rols which bits in this field may be modified by a pci master or the cpu. bits that cannot be modified are always zero. initial value: 0x0 read value: previous value written write effect: modify value svi description: subsystem vendor id. this field identifies the vendor of the pci device subsystem. initial value: 0x0 or value init ialized from pci serial eeprom read value: previous value written write effect: cpu can modify value, read-only from pci bus si description: subsystem id. this field identifies the subsystem of the pci device subsystem. initial value: 0x0 or value init ialized from pci serial eeprom read value: previous value written write effect: cpu can modify value, read-only from pci bus. subsystem_vendor_id 0 15 16 svi subsystem_id 0 15 16 si
idt pci bus interface pci configuration registers 79rc32438 user reference manual 10 - 55 november 4, 2002 notes interrupt line register figure 10.42 interrupt line register (interrupt_line) interrupt pin register figure 10.43 interrupt pin register (interrupt_pin) minimum grant register figure 10.44 minimum grant register (min_gnt) il description: interrupt line. the value of this field identifies the system controller(s) input to which the inter- rupt pin of the device is connected. initial value: 0x0 read value: previous value written write effect: modify value ip description: interrupt pin. this field identifies the interrupt pin the device (or device function) uses. initial value: 0x0 or value init ialized from pci serial eeprom read value: previous value written write effect: cpu can modify value, read-only from pci bus min_gnt description: minimum grant. this field identifies how long of a burst period is needed. units are in 0.25 sec increments assuming a 33 mhz pci clock. a value of 0 indicates no restriction is needed. see pci 2.2 specification section 6.2.4 for details and a fifo resource example. initial value: 0x0 or value init ialized from pci serial eeprom interrupt_line 0 7 8 il interrupt_pin 0 7 8 ip min_gnt 0 7 8 min_gnt
idt pci bus interface pci configuration registers 79rc32438 user reference manual 10 - 56 november 4, 2002 notes maximum latency register figure 10.45 maximum latency register (max_lat) target ready time-out register figure 10.46 target time-out register (trdy_timeout) read value: previous value written write effect: cpu can modify value, read-only from pci bus max_lat description: maximum latency. this field identifies how often access to the pci bus are needed. units are in 0.25 sec increments assuming a 33 mhz pci clock. a value of 0 indicates no restriction is needed. see pci 2.2 specification section 6.2.4 for details and a fifo resource example. initial value: 0x0 or value init ialized from pci serial eeprom read value: previous value written write effect: cpu can modify value, read-only from pci bus tt description: target time-out. this field indicates how many pci clock cycles the pci bus interface will wait as a master for the assertion of trdyn. setting this field to zero results in an infinite time-out period (i.e., no time-out). initial value: 0x80 read value: previous value written write effect: modify value max_lat 0 7 8 max_lat trdy_timeout 0 7 8 tt
idt pci bus interface pci configuration registers 79rc32438 user reference manual 10 - 57 november 4, 2002 notes retry limit register figure 10.47 retry limit register (retry_limit) pci base address [0|1|2|3] control figure 10.48 pci base address [0 |1|2|3] control (pba[0|1|2|3]c) rl description: retry limit. this field indicates how many times the pci bus interface will retry a transaction. setting this field to zero results in an infinite retry limit (i.e., no limit). initial value: 0x80 read value: previous value written write effect: modify value msi description: memory space indicator. the value of this bit determines the value advertised in the msi bit of the corresponding pbax register. 0x0 - memory space 0x1 - i/o space initial value: 0x0 read value: previous value written write effect: modify value p description: prefetchable. the value of this bit determines the value advertised in the p bit of the corre- sponding pbax register. this bit does not affect operat ion of the pci interf ace (i.e., it may not actually perform pefetching). prefetching operation for pci parx mapped transactions is con- trolled by the perform prefetch (pp) bit in this register. 0x0 - non-prefetchable 0x1 - prefetchable initial value: 0x0 read value: previous value written write effect: modify value retry_limit 0 7 8 rl pba[0|1|2|3]c 0 31 1 msi 1 p size 5 1 sb 1 pp 1 mrl 1 mrm 2 mr 18 0 1 trp
idt pci bus interface pci configuration registers 79rc32438 user reference manual 10 - 58 november 4, 2002 notes size description: address space size. this field indicates the size of the address space for the corresponding pci base address register. all bits greater than or equal to size in pbax may be modified. bits less than size and greater than or equal to bit four always return a value of zero when read and cannot be modified. setting the size field to a value less than eight results in all bits in the corre- sponding pbax register to take on the val ue zero. this effectively di sables the pc i base address register. initial value: 0x0 read value: previous value written write effect: modify value sb description: swap bytes. this bit controls byte swapping for pci transactions that map to the local bus through the pbax register. 0x0 - no byte swapping 0x1 - swap bytes initial value: 0x0 read value: previous value written write effect: modify value pp description: perform prefetching. this bit controls the prefetching behavior for pci read transactions that map to the local bus through pbax. 0x0 - do not perform prefetching for any transactions 0x1 - perform prefetching as indicated by the mr, mrl, and mrm fields in this register initial value: 0x1 read value: previous value written write effect: modify value mr description: memory read behavior. this bit controls the behavior of pci memory read transactions. 0x0 - read data indicated by transaction (no prefetching) 0x1 - treat memory read transactions as memory read line transaction 0x2 - treat memory read transactions as memory read multiple transaction 0x3 - reserved initial value: 0x0 read value: previous value written write effect: modify value mrl description: memory read line prefetching behavior. this bit controls the behavior of pci memory read line transactions. 0x0 - prefetch data to end of cache line 0x1 - treat memory read line transactions as memory read multiple transactions initial value: 0x0
idt pci bus interface pci configuration registers 79rc32438 user reference manual 10 - 59 november 4, 2002 notes pci base address [0|1|2|3] mapping register figure 10.49 pci base address [0|1|2 |3] mapping register (pba[0|1|2|3]m) read value: previous value written write effect: modify value mrm description: memory read multiple prefetching behavior. this bit controls the behavior of pci memory read multiple transactions on the local bus. 0x0 - conservative prefetching. prefetch a 16 word burst from local address space whenever there are less than 8 words in the pci target output fifo. 0x1 - aggressive prefetching. keep prefetching 16 word bursts from local address space as long as room exists for them in the pci target output fifo. initial value: 0x0 read value: previous value written write effect: modify value trp description: target read priority. when this bit is set, pci target read transactions that map to the rc32438?s local address space using the corresponding base address are given priority over posted writes in the pci target input buffer. w hen this bit is set, pci transaction ordering con- straints are violated. for more information, see section ?transaction ordering? on page 10-39. warning: setting this bit will violate the pci 2.2 specification since read transactions will be completed before pos ted write transactions. initial value: 0x0 read value: previous value written write effect: modify value maddr description: mapping address. this field contains the local base address for pci transactions mapped to the local bus through the pbax register. pci transa ction address bits 31 through the value of the size field in the pbaxc register are replaced by corresponding bits in this field for pci transac- tions that map to the local bus through the pbax register. initial value: 0x0 read value: previous value written write effect: modify value pba[0|1|2|3]m 0 31 24 maddr 0 8
idt pci bus interface pci configuration registers 79rc32438 user reference manual 10 - 60 november 4, 2002 notes pci management register figure 10.50 pci manage ment register (pmgt) wr description: warm reset. writing a one to this register generates a warm reset. initial value: 0x0 read value: current warm reset state 0x0 - normal operation 0x1 - warm reset write effect: writing a one generates a warm reset. nmi description: non-maskable interrupt. writing a one to this register causes the nmi bit to be set in the pci status (pcis) register and results in a cpu non-maskable interrupt. initial value: 0x0 read value: 0x0 write effect: writing a one generates a non-maskable interrupt. pmgt 0 31 1 wr 30 0 1 nmi
notes 79rc32438 user reference manual 11 - 1 november 4, 2002 chapter 11 ethernet interfaces introduction this chapter describes the two ethernet interf aces on the rc32438 device. both channels are nearly identical (ethernet 0 channel has mii managem ent functions; ethernet 1 channel does not). features ? 10 and 100 mb/s iso/iec 8802-3:1996 compliant ? two ieee 802.3u compatible media independent interf aces (mii) with serial management interface ? mii supports ieee 802.3u auto-negotiation speed selection ? supports 64 entry hash table bas ed multicast address filtering ? 512 byte transmit and receive fifos ? supports flow control functions outlined in ieee std. 802.3x-1997 block diagram figure 11.1 ethernet interf ace with management feature functional overview the rc32438 contains two nearly i dentical 10/100 mb/s iso/iec 8802-3:1996 compliant ethernet inter- faces (only 0 channel has mii managem ent functions). figure 11.1 show s a block diagram with a manage- ment function. an external ethernet physical laye r device (phy) connects to each ethernet interface through an ieee std 802.3u-1995 media independent interface (mii). this allows each ethernet interface to be used with a multitude of physical layers such as: 10base-t, 100base-tx, and 100base-fx. each ethernet interface is capable of performing cont rol flow functions outlined in ieee std 802.3x-1997. management mii logic csma/cd mac dma interface ipbus? media independent interface ethernet mac address recognition logic
idt ethernet interfaces input and output fifos 79rc32438 user reference manual 11 - 2 november 4, 2002 notes since both ethernet interfaces are nearly identical, t he remainder of this chapter describes the function- ality of a single interface. it should be understood that there are two copies of all ethernet registers, one for ethernet interface zero (denoted by the prefix et h0 or mii0) and one for interface one (denoted by the prefix eth1 or mii1). as illustrated in figure 11.1, an ethernet in terface consists of five major blocks: ? an ethernet mac (medium access controller), which includes a csma/cd mac, a management interface, and a mii pin level interface ? a 512 byte input fifo connected to the mac ? a 512 byte output fifo connected to the mac ? address recognition logic, which determines if an ethernet frame received on the mii should be passed to the input fifo ? dma interface, which allows the input and output fifos to be read and written by the dma controller. the ethernet interface is enabled by setting the en bit in the ethernet interface control (eth[0|1]intfc) register. input and output fifos the input and output fifos are not intended to hold entire packets, but merely to compensate for latency in accessing data by the dma controller. each 512 byte fifo is organized as 128 32-bit words. during boot configuration, the system may be confi gured to operate in either big endian or little endian mode. although ethernet packet data is packed into word s in the fifos, packet data is referenced as bytes (also called octets) by the cpu core and ethernet mac. data is always stored in big endian format within fifo data words, with endianness conversion taking place as data is transferred between the ipbus and the fifos. thus, data stored in the fifos always appears to the programmer in the endianness selected during boot configuration. packet data to be transmitted is written by the dma controller into the output fifo. when the amount of packet data in the output fifo exceeds the threshol d programmed in the transmit threshold (tth) field of the ethernet fifo transmit threshold register (eth[0|1]f ifott), or when the last byte of a packet is written to the output fifo, the mac will check if the line is busy. if the line is not busy, the mac will begin transmit- ting the preamble, start of frame delimiter, and the packet data. if a collision is detected during the collision window, the mac will back off and attempt to retransmit the frame. attempts are made to retransmit the frame unt il the collision threshold specified in the maximum retransmissions (maxret) field of the eth[0|1]clrt register is reached. when this occurs, the excessive collisions (ec) bit is set in the devcs field of the dma descriptor. for correct operation, the transmit threshold (tth) must be set to a value equal to or greater than the value selected for the collision window size in the colwin field of the ethernet collision window and retry (eth[0|1]clrt) register minus tw o words or eight bytes (the collision window size includes the preamble and sfd which are generated by the mac and are not part of a packet). ethernet register description register offset 1 register name register function size 0x05_8000 eth0intfc ethernet 0 interface control 32-bit 0x05_8004 eth0fifott ethernet 0 fifo transmit threshold 32-bit 0x05_8008 eth0arc ethernet 0 address recognition control 32-bit 0x05_800c eth0hash0 ethernet 0 hash table 0 32-bit 0x05_8010 eth0hash1 ethernet 0 hash table 1 32-bit 0x05_8014 through 0x05_8020 reserved table 11.1 ethernet register map (part 1 of 4)
idt ethernet interfaces ethernet register description 79rc32438 user reference manual 11 - 3 november 4, 2002 notes 0x05_8024 eth0pfs ethernet 0 pause frame status 32-bit 0x05_8028 ethmcp ethernet management clock prescalar 32-bit 0x05_802c through 0x05_80ff reserved 0x05_8100 eth0sal0 ethernet 0 station address 0 low 32-bit 0x05_8104 eth0sah0 ethernet 0 station address 0 high 32-bit 0x05_8108 eth0sal1 ethernet 0 station address 1 low 32-bit 0x05_810c eth0sah1 ethernet 0 station address 1 high 32-bit 0x05_8110 eth0sal2 ethernet 0 station address 2 low 32-bit 0x05_8114 eth0sah2 ethernet 0 station address 2 high 32-bit 0x05_8118 eth0sal3 ethernet 0 station address 3 low 32-bit 0x05_811c eth0sah3 ethernet 0 station address 3 high 32-bit 0x05_8120 eth0rbc ethernet 0 receive byte count 32-bit 0x05_8124 eth0rpc ethernet 0 receive packet count 32-bit 0x05_8128 eth0rupc ethernet 0 receive undersized packet count 32-bit 0x05_812c eth0rfc ethernet 0 receive fragment count 32-bit 0x05_8130 eth0tbc ethernet 0 transmit byte count 32-bit 0x05_8134 eth0gpf ethernet 0 generate pause frame 32-bit 0x05_8138 through 0x05_81ff reserved 0x05_8200 eth0mac1 ethernet 0 mac configuration 1 32-bit 0x05_8204 eth0mac2 ethernet 0 mac configuration 2 32-bit 0x05_8208 eth0ipgt ethernet 0 back-to-back inter-packet gap 32-bit 0x05_820c eth0ipgr ethernet 0 non back-to-back inter-packet gap 32-bit 0x05_8210 eth0clrt ethernet 0 collision window retry 32-bit 0x05_8214 eth0maxf ethernet 0 maximum frame length 32-bit 0x05_8218 reserved 0x05_821c eth0mtest ethernet 0 mac test 32-bit 0x05_8220 miimcfg mii management configuration 32-bit 0x05_8224 miimcmd mii management command 32-bit 0x05_8228 mimmaddr mii management address 32-bit 0x05_822c miimwtd mii management write data 32-bit 0x05_8230 miimrdd mii management read data 32-bit 0x05_8234 miimind mii management indicators 32-bit 0x05_8238 through 0x05_823c reserved 0x05_8240 eth0cfsa0 ethernet 0 control frame station address 0 32-bit 0x05_8244 eth0cfsa1 ethernet 0 control frame station address 1 32-bit 0x05_8244 eth0cfsa2 ethernet 0 control frame station address 2 32-bit register offset 1 register name register function size table 11.1 ethernet register map (part 2 of 4)
idt ethernet interfaces ethernet register description 79rc32438 user reference manual 11 - 4 november 4, 2002 notes 0x05_824c through 0x05_ffff reserved 0x06_0000 eth1intfc ethernet 1 interface control 32-bit 0x06_0004 eth1fifott ethernet 1 fifo transmit threshold 32-bit 0x06_0008 eth1arc ethernet 1 address recognition control 32-bit 0x06_000c eth1hash0 ethernet 1 hash table 0 32-bit 0x06_0010 eth1hash1 ethernet 1 hash table 1 32-bit 0x06_0014 through 0x06_0020 reserved 0x06_0024 eth1pfs ethernet 1 pause frame status 32-bit 0x06_0028 through 0x6_00ff reserved 0x06_0100 eth1sal0 ethernet 1 station address 0 low 32-bit 0x06_0104 eth1sah0 ethernet 1 station address 0 high 32-bit 0x06_0108 eth1sal1 ethernet 1 station address 1 low 32-bit 0x06_010c eth1sah1 ethernet 1 station address 1 high 32-bit 0x06_0110 eth1sal2 ethernet 1 station address 2 low 32-bit 0x06_0114 eth1sah2 ethernet 1 station address 2 high 32-bit 0x06_0118 eth1sal3 ethernet 1 station address 3 low 32-bit 0x06_011c eth1sah3 ethernet 1 station address 3 high 32-bit 0x06_0120 eth1rbc ethernet 1 receive byte count 32-bit 0x06_0124 eth1rpc ethernet 1 receive packet count 32-bit 0x06_0128 eth1rupc ethernet 1 receive undersized packet count 32-bit 0x06_012c eth1rfc ethernet 1 receive fragment count 32-bit 0x06_0130 eth1tbc ethernet 1 transmit byte count 32-bit 0x06_0134 eth1gpf ethernet 1 generate pause frame 32-bit 0x06_0138 through 0x06_01ff reserved 0x06_0200 eth1mac1 ethernet 1 mac configuration 1 32-bit 0x06_0204 eth1mac2 ethernet 1 mac configuration 2 32-bit 0x06_0208 eth1ipgt ethernet 1 back-to-back inter-packet gap 32-bit 0x06_020c eth1ipgr ethernet 1 non back-to-back inter-packet gap 32-bit 0x06_0210 eth1clrt ethernet 1 collision window retry 32-bit 0x06_0214 eth1maxf ethernet 1 maximum frame length 32-bit 0x06_0218 reserved 0x06_021c eth1mtest ethernet 1 mac test 32-bit 0x06_0220 through 0x06_023c reserved 0x06_0240 eth1cfsa0 ethernet 1 control frame station address 0 32-bit register offset 1 register name register function size table 11.1 ethernet register map (part 3 of 4)
idt ethernet interfaces ethernet register description 79rc32438 user reference manual 11 - 5 november 4, 2002 notes ethernet interface control register figure 11.2 ethernet interface control register (eth[0|1]intfc) 0x06_0244 eth1cfsa1 ethernet 1 control frame station address 1 32-bit 0x06_0248 eth1cfsa2 ethernet 1 control frame station address 2 32-bit 0x06_024c through 0x06_ffff reserved 1. the address of the register is equal to the regi ster offset added to the base value of 0x1800_0000. en description: enable. when this bit is set to 1, the ethernet interface is enabled. when this bit is set to 0, the ethernet interface is disabled. disabling and then re-enabling the ethernet interface initializes all of the ethernet interface logic to its initial default state (i.e., all registers are set to their initial val- ues and input and output fifos are empty. initial value: 0x0 read value: previous value written write effect: modify value its description: ignore transmit status. when this bit is set to 1, multiple ethernet packets may be queued by the dma controller in the output fifo. in this mo de, control bits in the devcs field of the dma descriptor should be initialized to 0, and status information is not written back to the devcs field when a packet is transmitted. when this bit is set to 0, the output fifo can only hold one packet. the dma controller will update the status information in the devcs field after the packet has been transmitted. initial value: 0x0 read value: previous value written write effect: modify value rip description: reset in progress. when the en bit is cleared to 0, an ethernet interface reset is generated, and this bit is set to indicate that an ethernet interface reset is in progress. the reset may take several clock cycles to complete due to the crossing of multiple clock domains. when the reset has completed, this bit is cleared to 0 and the ethernet interface may be re-enabled by setting the en bit to 1. initial value: 0x0 read value: status write effect: read-only register offset 1 register name register function size table 11.1 ethernet register map (part 4 of 4) eth[0|1]intfc 0 31 en 1 0 26 its 1 1 rip 1 jam 1 ovr 1 und
idt ethernet interfaces ethernet register description 79rc32438 user reference manual 11 - 6 november 4, 2002 notes because the packet portion of the collision window fo r a frame to be transmitted fits entirely in the output fifo, and remains there until it is transmitted wi thout collision, there is never a need to re-fetch data to be transmitted. when an output fifo underflow occurs during packet transmission, then the un d bit is set in the eth[0|1]intfc register and also in the devcs field of the dma descriptor if the its bit is not set in the eth[0|1]intfc register. the state of t he und bit in the eth[0|1]intfc register is presented to the interrupt controller as an interrupt source. when the mac observes a valid preamble and start of frame delimiter, it begins receiving an ethernet frame. if the destination address in the packet is not rejected by the address recognition logic, the packet data is written by the mac into the input fifo. once data beyond the collision window is received without error, the dma controller is signalled that valid packet data exists in the input fifo. if a collision is detected within the collision window programmed in the colwin field, the resulting runt frame is automatically flushed from the input fifo by the mac. note: collision frames, runt frames, and frames whose destination addresses are not accepted by the address recognition logic are never passed to the dma controller. when an input fifo overflow occurs during packet rec eption, the ovr bit is set in the eth[0|1]intfc register. if less than 64-bytes of the packet have been written into the fifo, then the packet is discarded from the input fifo. if 64-bytes or more have been writt en into the fifo, the remaining bytes of the packet are discarded but data already written to the fifo is not flushed. when the dma transfers a packet in which an overflow occurred to memory, the ovr bit is set in the devcs field of the dma descriptor. the state of the ovr bit in the eth[0|1]intfc register is presented to the interrupt controller as an interrupt source. jam description: transmit half duplex flow control. when this bit is set to 1, the ethernet mac transmits a preamble on the wire causing other macs to defer. this may be used as a means of achieving half duplex flow control. when this bit is set to 0, the preamble is not transmitted. initial value: 0x0 read value: previous value written write effect: modify value ovr description: input fifo overflow. this bit is set to 1 when the input fifo overflows. if the overflow occurs before 64-bytes of a packet are received and written into the input fifo, then the entire contents of the packet are discarded. if more than 64-bytes of the packet are received and written into the input fifo and an overflow occurs, then the remaining bytes of the packet are discarded and the ovr bit is set in the dma descriptor when the packet is transferred to memory. once the input fifo overflows, all subsequent packets are discarded until space becomes available in the input fifo. note that for all other errors, packets are received. initial value: 0x0 read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) und description: output fifo underflow. this bit is set to 1 if frame transmission is aborted due to an output fifo underflow. an output fifo underflow condit ion would typically be due to latencies within the system and should not occur under normal operating conditions. when this condition occurs, the remainder of the data for the current frame is discarded. however, subsequent frames are transmitted properly. initial value: 0x0 read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu)
idt ethernet interfaces address recognition logic 79rc32438 user reference manual 11 - 7 november 4, 2002 notes ethernet fifo transmit threshold register figure 11.3 ethernet fifo transmit threshold register (eth[0|1]fifott) address recognition logic ethernet frames contain the address of the source and of the destination. both addresses are 48-bits in length and are typically represented as a series of six bytes separated by hyphens in the order that they are transmitted (left to right) on the wire. the bits within bytes are transmitted on the wire from right to left (that is, least significant bit first and most significant bit last). these addresse s are referred to as medium access control (mac) addresses. an example of a mac address, and the order in whic h its bits are transmitted on the wire, is shown in figure 11.4. figure 11.4 representation of mac address based on the destination address in a received ether net frame, the address recognition logic deter- mines if the packet should be accepted by the ethernet in terface and passed to the dma controller or if the frame should be rejected. tth description: transmit threshold. this field contains the number of words which must be present in the ethernet output fifo in order for the mac to start transmitting the frame. the mac will begin transmitting the frame before the threshold is reached if the last byte of a packet is written into the fifo. for correct operation of the ethernet interface, this field should be set to a value greater than or equal to the number of words programmed in t he colwin field in the eth[0|1]clrt register minus two words (that is, do not count sfd or preamble). care should be exercised in determining the value selected for the transmit threshold, since mis- configuration could lead to a deadlock. for example, if this field is set to 125 words and the trans- mit fifo contains 120 words, then further dma transmit requests will not be generated since the remaining space in the transmit fifo is not at least 16 words. in addition, the ethernet mac will not start transmitting the frame since the transmit threshold has not been reached, thus resulting in a deadlock. initial value: undefined read value: previous value written write effect: modify value eth[0|1]fifott 0 31 tth 25 7 0 byte 0 ac byte 1 de byte 2 48 byte 3 00 byte 4 00 byte 5 80 binary representation: 0011 0101 0111 1011 0001 0010 0000 0000 0000 0000 0000 0001 universally/locally administered address bit (2nd bit on the wire) individual/group address bit (1st bit on the wire) mac address: ac-de-48-00-00-80
idt ethernet interfaces address recognition logic 79rc32438 user reference manual 11 - 8 november 4, 2002 notes there are two types of destination addresses, in dividual addresses and group addresses. an individual address is associated with a particular station on the network, while a group address is associated with one or more stations on the network. a group address can be further classified as either a multicast address (an address associated by a higher level convention with a group of logically related stations) or a broadcast address (an address that denotes the set of all stations on a given lan). the ethernet interface supports up to four station addresses. a station address is a 48-bit mac address stored in a station address low and high register pair. there are four station address register pairs: eth[0|1]sal[0|1|2|3] eth[0|1]sah[0|1|2|3] these are programmed with the four individual stat ion addresses of the ethernet interface. the destina- tion address of an ethernet packet is compared to all four station addresses. if the destination address of the packet matches any one of the four stati on addresses, the ethernet packet is accepted. applications that do not require al l four station addresses may program the same address into multiple station address register pairs. for ex ample, if an application requires t he ethernet interface to have only a single station address, all four st ation address register pairs can be assigned the same station address value. the mac address used for control frames is c ontained in the eth[0|1]cfsa[0|1|2] registers. using another example, if an application requires two a ddresses, one address would be assigned to station one and the other address would be assigned to stations two, three, and four. a hash table approach is used to determine if mult icast group destination address packets should be accepted. 1 when a packet with a multicast group destinati on address is received, a 6-bit hash value is computed by passing the 48-bit destination address through the frame check sequence crc calculator. the hash value, consisting of bits 26 through 31 of t he computed crc, is used as an index into a 64 bin hash table in which each bin is represented by a singl e bit. if the selected bit in the hash table is a one and the accept filtered multicast packets (afm) bit in the ethernet address recognition control (eth[0|1]arc) register is set, the packet is accepted. the 64-bit hash table is stored in the hash[0|1] regi sters. hash0 contains bits 0 through 31 of the hash table, while hash1 contains bits 32 through 63 of the hash table. the hash table filtering algorithm is not perfect, and therefore packets must be further filtered by soft- ware to determine if they do, in fact, match a mult icast address that should be ac cepted. if the accept all multicast packets (am) bit in the eth[0|1]arc register is set, all multicast packe ts are accepted regardless of whether or not they pass the hash table filtering algorithm. a broadcast address is a mac address consisting of all ones (that is, ff-f f-ff-ff-ff-ff). if the accept broadcast packets (ab) bit in the eth[0|1]ar c register is set, all broadcast packets are accepted by the ethernet interface. when this bit is cleared, all broadcast packets are rejected. when a packet is accepted by the ethernet interface, three bits ar e updated in the devcs field of a dma descriptor. the filter match (fm) bit is set when one of the following conditions occurs: ? the packet matches an individual station address ? the packet passes the hash table fi ltering algorithm described above ? the packet is a multicast packet and was acc epted because the am bit in the eth[0|1]arc register was set ? the packet is a broadcast packet and was accept ed because the ab bit in the eth[0|1]arc register was set. the multicast packet (mp) bit is set when the ac cepted packet is a multicast packet, and the broadcast packet (bp) bit is set when the a ccepted packet is a broadcast packet. the ethernet interface has a promiscuous mode which is enabled by setting the promiscuous mode (pro) bit in the eth[0|1]arc regi ster. in this mode, the address recognition logic accepts all incoming packets regardless of their destination address. while in this mode, the filter matc h (fm) bit in the devcs field of a dma descriptor is still set only in the c onditions outlined above. the addr ess filtering algorithm is summarized in figure 11.6. 1. the only exception to this is the multicast address 01-80-c2-00-00-01 which is always received regardless of the setting of the corresponding ethernet hash table entry.
idt ethernet interfaces address recognition logic 79rc32438 user reference manual 11 - 9 november 4, 2002 notes ethernet address recognition control register figure 11.5 ethernet a ddress recognition control register (eth[0|1]arc) pro description: promiscuous mode. when this bit is set to 1, all incoming packets are received regardless of their destination address and other address registers are overridden. when this bit is set to 0, this function is disabled. initial value: undefined read value: previous value written write effect: modify value am description: accept all multicast packets. when this bit is set to 1, all incoming packets with a multicast destination address are accepted. when this bit is set to 0, this function is disabled. initial value: undefined read value: previous value written write effect: modify value afm description: accept filtered multicast packets. when this bit is set to 1, multicast packets which pass address filtering are accepted. when this bit is set to 0, this function is disabled. initial value: undefined read value: previous value written write effect: modify value ab description: accept broadcast packets. when this bit is set to 1, all incoming packets with a broadcast des- tination address are received. when this bit is set to 0, this function is disabled. initial value: undefined read value: previous value written write effect: modify value eth[0|1]arc 0 31 28 0pro 1 am 1 afm 1 ab 1
idt ethernet interfaces address recognition logic 79rc32438 user reference manual 11 - 10 november 4, 2002 notes match = false if (da == individual address) { if ( da == local station address 1 or da == local station address 2 or da == local station address 3 or da == local station address 4 ) { accept packet set fm bit in descriptor/status register match = true } } else { if (da == broadcast address ) { if (ab bit set in ethxarc ) { accept packet set fm bit in descriptor/status register set bp bit in descriptor/status register match = true } } else if ( afm bit set in ethxarc && hash_table[hash(da)] == 1 ) { accept packet set fm bit in descriptor/status register set mp bit in descriptor/status register match = true } else if ( am bit set in ethxarc ) { accept packet clear fm bit in descriptor/status register set mp bit in descriptor/status register match = true } } if ( pro bit set in ethxarc and match == false ) { accept packet clear fm bit in descriptor/status register if ( da == broadcast address ) { set bp bit in descriptor/status register } else if ( da == multicast address ) { set mp bit in descriptor/status register } } figure 11.6 ethernet a ddress filtering algorithm
idt ethernet interfaces address recognition logic 79rc32438 user reference manual 11 - 11 november 4, 2002 notes ethernet hash table [0|1] register figure 11.7 ethernet hash table [0|1] register (eth[0|1]hash[0|1]) ethernet station address [0|1|2|3] low register figure 11.8 ethernet stati on address [0|1|2|3] low regi ster (eth[0|1]sal[0|1|2|3]) hash description: hash table bit vector. this 32-bit field contains a hash table used for multicast address filter- ing. the hash table is 64 bits in size with the lower 32 bits stored in hash0 and the upper 32 bits stored in hash1. bit x in the hash y register corresponds to bit 32 y + x in the hash table. initial value: undefined read value: previous value written write effect: modify value byte5 description: byte five. this field contains byte five of the 48-bit mac address. for example, for the mac address ac-de-48-00-00-80, this field holds the value 80. initial value: undefined read value: previous value written write effect: modify value byte4 description: byte four. this field contains byte four of the 48-bit mac address. for example, for the mac address ac-de-48-00-00-80, this field holds the value 00. initial value: undefined read value: previous value written write effect: modify value byte3 description: byte three. this field contains byte three of the 48-bit mac address. for example, for the mac address ac-de-48-00-00-80, this field holds the value 00. initial value: undefined eth[0|1]hash[0|1] 0 31 32 hash eth[0|1]sal[0|1|2|3] 0 31 8 byte4 8 byte3 8 byte2 8 byte5
idt ethernet interfaces dma interface 79rc32438 user reference manual 11 - 12 november 4, 2002 notes ethernet station address [0|1|2|3] high register figure 11.9 ethernet station address [0|1 |2|3] high register (eth[0|1]sah[0|1|2|3]) dma interface an ethernet interface supports dma operations fr om the input fifo to memory, and dma operations from memory to the output fifo (see chapter 9, dm a controller). ethernet dma operations do not use the dma descriptor device command (devcmd) field. ethernet input dma operations table 11.2 summarizes ethernet interface input dm a operations. as shown in figure 11.10, the dma descriptor device control and status (d evcs) field is used to record status information for received packets. a dma request event is generated whenever 16 full fifo data words exist in the input fifo or when a fifo data word tagged as an end-of-packet is present in the input fifo. this causes the dma to transfer data from the input fifo to memory. read value: previous value written write effect: modify value byte2 description: byte two. this field contains byte two of the 48-bit mac address. for example, for the mac address ac-de-48-00-00-80, this field holds the value 48. initial value: undefined read value: previous value written write effect: modify value byte1 description: byte one. this field contains byte one of the 48-bit mac address. for example, for the mac address ac-de-48-00-00-80, this field holds the value de. initial value: undefined read value: previous value written write effect: modify value byte0 description: byte zero. this field contains byte zero of the 48-bit mac address. for example, for the mac address ac-de-48-00-00-80, this field holds the value ac. initial value: undefined read value: previous value written write effect: modify value eth[0|1]sah[0|1|2|3] 0 31 16 0 8 byte0 8 byte1
idt ethernet interfaces dma interface 79rc32438 user reference manual 11 - 13 november 4, 2002 notes a dma done event is generated whenever a fifo data word tagged as an end-of-packet is transferred from the input fifo to memory. the first descriptor (fd) bit in the devcs field is set in the first descriptor of a dmaed packet, while the last descriptor (ld) bit in the devcs field is set in the last descriptor of a dmaed packet (that is, one in which a done event was generat ed). note that it is possible for a packet to be both the first and last descriptor of a packet and t herefore have both the fd and ld bits set. it is also possible for a descriptor to contain data in the mi ddle of a packet and therefore have neither bit set. the remaining status fields in t he devcs field are updated in the last dma descriptor of a packet (i.e., the ld bit is set to 1). all other dma descripto rs of a packet contain zeros in these fields. device control and status value for ethernet receive descriptors figure 11.10 device control and status value for ethernet receive descriptors dma request event a request event is generated whenever 16 full fifo data words are present in the input fifo, or when less than 16 full fifo data words are present in the input fifo but one exists which is tagged as an end-of-packet. dma done event a dma done event is generated after an end-of-packet tagged fifo data word has been transferred. dma terminated event a dma terminated event is never generated. dma transfer size the dma controller usually transfers 16 fifo data words from the input fifo to mem- ory. fewer fifo data words are transferred if a fifo data word tagged as an end-of- packet is reached or if the byte count reaches zero. limitations none. a dma operation may start and end on any byte boundary and may contain any number of bytes. table 11.2 ethernet interface input dma operations fd first descriptor. this bit is set to 1 if this descrip tor is the first descriptor of a packet. ld last descriptor. this bit is set to 1 if this descript or is the last descriptor of a packet. rok received ok. this bit is set to 1 if the packet was received without error. this bit is set if and only if the ovr, crc, cv, and le bits are all cleared to 0. this field is valid only in the last descriptor of a packet. fm filter match. this bit is set to 1 if the packet passed address recognition filtering. this field is valid only in the last descriptor of a packet. mp multicast packet. this bit is set to 1 when the packet has a multicast address. this field is valid only in the last descriptor of a packet. bp broadcast packet. this bit is set to 1 when the packet has a broadcast address. this field is valid only in the last descriptor of a packet. vlt vlan tag detected. this bit is set to 1 when the packet is a vlan tagged packet. this field is valid only in the last descriptor of a packet. devcs 16 31 16 length 0 15 fd 1 ld 1 rok 1 fm 1 mp 1 bp 1 vlt 1 cf 1 ovr 1 crc 1 cv 1 db 1 le 1 lor 1 ces 1 0 1
idt ethernet interfaces dma interface 79rc32438 user reference manual 11 - 14 november 4, 2002 notes ethernet output dma operations table 11.3 summarizes ethernet interface output dm a operations. as shown in figure 11.11, the dma descriptor devcs field is used to record status information for transmitted packets. a dma request event is generated w henever 16 free fifo data words exist in the output fifo. this causes the dma to transfer data from memory to the output fifo. a dma done event is never generated during ethernet ou tput dma operations. the first descriptor (fd) bit in the devcs field is set in the first descriptor of a packet while the last descriptor (ld) bit in the devcs field is set in the last descriptor of a packet. note that it is possible for a packet to be both the first and last descriptor of a packet and, therefore, have both the fd and ld bits set. it is also possible for a descriptor to contain data in the middle of a packet and, therefore, have neither bit set. cf control frame. this bit is set to 1 to indicate that the packet was recognized as a control frame. received control frames are normally discarded unless the paf bit is set in the eth[0|1]mac1 register. this field is valid only in the last descriptor of a packet. ovr receive fifo overflow. this bit is set to 1 when the input fifo overflowed during packet recep- tion. once an overflow occurs, the remaining contents of the packet are discarded. crc crc error. this bit is set to 1 when the received packet has a crc error. this field is valid only in the last descriptor of a packet. crc error packets are not discarded. cv code violation. this bit is set to 1 when a coding violation was detected somewhere in the packet. this field is valid only in the last descriptor of a packet. code violation error packets are not discarded. db dribble bits detected. this bit is set to 1 when between one and seven dribbling bits are detected at the end of the packet. this field is valid only in the last descriptor of a packet. dribble bit error packets are not discarded le length error. this bit is set to 1 when the packet length field does not match the actual length of the packet. this field is valid only in the last descriptor of a packet. length error packets are not discarded. lor length out of range. this bit is set to 1 when the packet type/length field is larger than 1518. this field is valid only in the last descriptor of a packet. if this bit is set, type/length field is used as type field. length out of range error packets are not discarded. ces carrier event seen. this bit is set to 1 to indicate that something less than a well formed pream- ble or start of frame delimiter has been received (as s pecified in ieee 802.3 clause 24.2.4.4.2). this field is valid only in the last descriptor of a packet. carrier error packets are not discarded. length length. this 16-bit field contains the length of the received frame. this field is valid only in the last descriptor of a packet. dma request event a request event is generated whenever 16 free fifo data words are present in the out- put fifo. dma done event a dma done event is never generated. dma terminated event a dma terminated event is never generated. dma transfer size the dma controller usually transfers 16 fifo data words from memory to the output fifo. fewer words are transferred if the byte count reaches zero. limitations none. a dma operation may start and end on any byte boundary and may contain any number of bytes. table 11.3 ethernet interface output dma operations
idt ethernet interfaces dma interface 79rc32438 user reference manual 11 - 15 november 4, 2002 notes when the byte count in a dma descriptor reaches zero , a finished event is generated. this causes the fifo data word associated with the last byte trans ferred prior to the finished event to be tagged as an end- of-packet in the output fifo if this descriptor is t he last descriptor of the packet. because the number of bytes in a packet need not be an integer multiple of four, the fifo data word tagged with an end-of-packet need not have all bytes valid. the fd, ld, oen, pen, cen, and hen fields of the devcs field are packet cont rol bits initialized by the cpu prior to an ethernet output dma operation. the remaining bits of the devcs field are status bits which are zero for all dma descriptors except the last one of a packet. the packet override enable bit (oen) allows mac c ontrol settings to be overridden on a per packet basis. this bit is examined in t he first dma descriptor of a packet, one in which the fd bit has been set in the descriptor. if the oen bit is set, then t he pad enable (pe), crc enable (ce), and huge frame enable (hfe) bits in the ethernet mac conf iguration register #2 (eth[0|1]mac2) are overridden by the values in the pen, cen, and hen fields in the devcs field for the entire packet. the packet padding enable (pen) field controls whether or not s hort frames are padded by the mac. the packet crc enable (cen) field controls whether or not the crc is comput ed and appended by the mac. the huge frame enable (hen) field controls if large ethernet frames are transmitted by the mac. the status information contained in the devcs fiel d of the last dma descriptor in a packet is updated when the ethernet packet is transmitted by the mac, or when transmission of the packet is aborted. this allows only a single packet to be buffered in the transmi t fifo at a time, since a dma operation for the next packet cannot begin until the last descriptor of the previous packet has been written to memory. some applications may not require the status val ues contained in the devcs field. setting the ignore transmit status (its) bit in the eth[ 0|1]intfc register causes the status fields of the devcs field in the descriptor to always be written back to memory with zeros and allows multiple packets to be queued by the dma controller in the output fifo. this implies that t he status information for the last descriptor of a packet may not be updated for quite some time after the data has been transferred from memory to the output fifo. figure 11.11 device control and status value for ethernet transmit descriptors fd first descriptor. this bit is set to 1 if this descriptor is the first descriptor of a packet. this bit is exam- ined in every descriptor and is initialized by the cpu prior to an ethernet output dma operation. ld last descriptor. this bit is set to 1 if this descriptor is the last descriptor of a packet. this bit is examined in every descriptor and is initialized by the cpu prior to an ethernet output dma operation. oen override enable. when this bit is set to 1, pen, cen, and hen are enabled. this bit is examined in the first packet descriptor and is initialized by the cpu prior to a ethernet output dma operation. pe packet padding enable. when the oen bit is set to 1, this bit controls whether short ethernet packets are padded. when pen is set, short packets are padded. when pen is cleared, short packets are not padded. this bit is examined in the first packet descriptor and is initialized by the cpu prior to an ether- net output dma operation. fd devcs 16 31 11 0 0 15 1 tok 1 mp 1 bp 1 und 1 of 1 ed 1 ec 1 lc 1 td 1 crc 1 le 1 ld 1 oen 1 pen 1 cen 1 hfe 1 cc 4
idt ethernet interfaces ethernet statistics 79rc32438 user reference manual 11 - 16 november 4, 2002 notes ethernet statistics the ethernet interface contains five 32-bit count ers which may be used to gather statistics. each counter increments by one each time the specified receive or transmi t event occurs. the cpu may read these counters at any time, provided that the mii cl ocks are supplied and the rip bit in the eth[0|1]intfc register is not set to 1. the act of reading a counter causes its value to be reset to zero as an atomic opera- tion. this prevents the loss of events due to non-atomic read and clear operations. cen packet crc enable. when the oen bit is set to 1, it controls whether the mac appends an crc to the ethernet packet. if cen is set, then the crc is appended to the packet. when cen is cleared, crc is not appended to the packet. this bit is examined in the first packet descriptor and is initialized by the cpu prior to an ethernet output dma operation. hfe huge frame enable. when the oen bit is set to 1, this bit controls whether large ethernet packets (that is, packets that exceed the value in the eth[0|1]maxf register) are transmitted. when hfe is set, then large ethernet frames are transmitted. if hfe is cleared to 0, then transmission is aborted after the length in eth[0|1]maxf has been reached and the remainder of the frame is discarded. this bit is examined in the first packet descriptor and is initialized by the cpu prior to an ethernet output dma operation. tok transmit ok. this bit is set to 1 when the packet is transmitted without error. this bit is set if and only if the und, of, ed, ec, and lc bits are all cleared. this field is valid only in the last descriptor of a packet. mp multicast packet. this bit is set to 1 when the transmitted packet has a multicast address. this field is valid only in the last descriptor of a packet. bp broadcast packet. this bit is set to 1 when the transmitted packet has a broadcast address. this field is valid only in the last descriptor of a packet. und transmit fifo underflow. this bit is set to 1 if frame transmission was aborted due to an output fifo underflow. this field is valid only in the last descriptor of a packet. of oversized frame. this bit is set to 1 if transmission was aborted due to an attempt to transmit a frame larger than the value in the eth[0|1]maxf regist er. the contents of the frame beyond eth[0|1]maxf are discarded. this field is valid only in the last descriptor of a packet. ed excessive deferral. this bit is set to 1 if t ransmission was aborted due to excessive deferrals. this field is valid only in the last descriptor of a packet. ec excessive collisions. this bit is set to 1 if transmission was aborted due to excessive collisions. this field is valid only in the last descriptor of a packet. lc late collision. this bit is set to 1 if transmission was aborted due to a collision beyond the collision win- dow. this field is valid only in the last descriptor of a packet. td transmit deferred. this bit is set to 1 if transmission of the frame was deferred on the first transmission attempt. this field is valid only in the last descriptor of a packet. crc crc error. this bit is set to 1 if the crc in the trans mitted frame does not match the crc computed by the mac. if the mac is configured to automatically compute and append the crc to transmitted frames, then the value of this bit should be ignored. this field is valid only in the last descriptor of a packet. le length error. this bit is set to 1 if the value of the length field of the transmitted frame does not match the actual length. this field is valid only in the last descriptor of a packet. cc collision count. this 4-bit field indicates the number of collisions that the successfully transmitted frame experienced. this field is not valid if frame transmission was aborted due to excessive collisions. this field is valid only in the last descriptor of a packet.
idt ethernet interfaces ethernet statistics 79rc32438 user reference manual 11 - 17 november 4, 2002 notes ethernet receive byte count register figure 11.12 ethernet receive byte count (eth[0|1]rbc) ethernet receive packet count register figure 11.13 ethernet receiv e packet count (eth[0|1]rpc) ethernet receive undersized packet count register figure 11.14 ethernet receive undersized packet count (eth[0|1]rupc) ethrbc description: ethernet receive byte count. total number of bytes in all packets received by the ethernet interface (including bad packets, packets discarded by hardware, and control frames). this value does not include sfd or preamble bytes. reading this register atomically clears its value to zero. initial value: undefined read value: return value and reset field to zero write effect: read-only ethrpc description: ethernet receive packet count. total number of ethernet packets received (including packets discarded by hardware as well as control packets). reading this register atomically clears its value to zero. initial value: undefined read value: return value and reset field to zero write effect: read-only eth[0|1]rbc 0 31 32 eth[0|1]rbc eth[0|1]rpc 0 31 32 ethrpc eth[0|1]rupc 0 31 32 ethrupc
idt ethernet interfaces ethernet statistics 79rc32438 user reference manual 11 - 18 november 4, 2002 notes ethernet receive fragment count register figure 11.15 ethernet receive fragment count (eth[0|1]rfc) ethernet transmit byte count register figure 11.16 ethernet transm it byte count (eth[0|1]tbc) ethrupc description: ethernet receive undersize packet count . total number of ethernet packets discarded by hardware since they were less than 64 bytes in size but were otherwise well formed. reading this register atomically clears its value to zero. initial value: undefined read value: return value and reset field to zero write effect: read-only ethrfc description: ethernet receive fragment count . total number of ethernet packets discarded by hardware since they were less than 64 bytes in size and had either a crc error or an alignment error (that is, not an integral number of bytes). reading this register atomically clears its value to zero. initial value: undefined read value: return value and reset field to zero write effect: read-only ethtbc description: ethernet transmit byte count. total number of bytes transmitted by the ethernet interface (includes control frames and retransmissions). this value does not include sfd, preamble, or jam bytes. reading this register atomically clears its value to zero. initial value: undefined read value: return value and reset field to zero write effect: read-only eth[0|1]rfc 0 31 32 ethrfc eth[0|1]tbc 0 31 32 ethtbc
idt ethernet interfaces pause control frames 79rc32438 user reference manual 11 - 19 november 4, 2002 notes pause control frames the ethernet interface supports pause control fr ames as defined by ieee std 802.3x-1997. received pause control frames are h andled by the ethernet mac. a control fram e is a frame with a type/length field that identifies a control frame (i.e., 0x88_08). control frames are accepted or rejected in the same manner as all other frames (i.e., using the method specif ied in the address recognition logic section of this chapter). the only exception to this is the multic ast address 01-80-c2-00-00-01 which is always received regardless of the setting of the corresponding ethernet hash table entry. a pause control frame is a cont rol frame with a multicast addr ess of 01-80-c2-00-00-01 and an opcode field that corresponds to a pause frame (i.e., 0x 00_01). the mac normally processes pause control frames but it may be configured to ignore pause cont rol frames by clearing t he receive flow control (rfc) bit in the ethernet mac 1 (eth[0|1]mac1) r egister. control frames ar e normally discarded after required processing by the mac. however, if the pass all frames (paf) bit is set in the eth[0|1]mac register, all frames (i.e., normal frames and control frames) are pass ed to the ethernet input fifo. when the mac is configured to ignore control frames, they ar e still passed to the ethernet input fifo if the paf bit is set. a pause control frame may be generated either by tr ansferring the contents of such a frame to the output fifo using the dma or by writing to the et hernet generate pause frame (eth[0|1]gpf) register. a write to the eth[0|1]gpf register causes the mac to transmit a pause control frame with the pause timer value set to the value written to the pause ti mer value (ptv) field of the eth[0|1]gpf register. the source address (sa) of the mac generated pause frame is equal to that specified by eth[0|1]cfsa0, eth[0|1]cfsa1, and eth[0|1]cfsa2. when the mac completes transmission of a pause control frame, the pause frame done (pfd) bit is set in the ethernet pause frame status (eth[0|1]pfs) register. the pfd bit is presented to the interrupt handler as an interrupt source. writes to the eth[0|1]pgf register before the ma c has completed transmitting a pause control frame due to a prior write are ignored (that is, they neither modify the register?s contents nor result in the genera- tion of a pause control frame). t he mac may be blocked from generati ng pause control frames by clearing the transmit flow control (tfc) bi t in the eth[0|1]mac1 register. ethernet generate pause frame register figure 11.17 ethernet generate pa use frame register (eth[0|1]gpf) ptv description: pause timer value. writing any value into this register causes a pause control frame to be generated by the mac. the value written to this field (ptv) is used as the pause timer value for the generated frame. once the mac has completed transmitting the pause control frame, the pause frame done (pfd) bit is set in the eth[0|1]pfs register. writes to this register before the mac has completed transmitting a pause control frame due to a prior write are ignored (that is, they neither modify the register?s contents nor result in the gen- eration of a pause control frame). initial value: 0x0 read value: previous value written write effect: modify value and generate pause control frame eth[0|1]gpf 0 15 ptv 16 0 16
idt ethernet interfaces pause control frames 79rc32438 user reference manual 11 - 20 november 4, 2002 notes ethernet pause frame status register figure 11.18 ethernet pause fram e status register (eth[0|1]pfs) ethernet control frame station address 0 register figure 11.19 ethernet control fram e station address 0 (eth[0|1]cfsa0) pfd description: pause frame done. this bit is set to 1 when the mac completes pause control frame trans- mission. the state of this bit is presented to the interrupt handler as an interrupt source. initial value: undefined read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) cfsa4 description: control frame station address 4. this field holds byte 4 of the station address used for control frames. for example, for the mac address ac-de-48-00-00-80, this field holds the value 00. initial value: 0x0 read value: previous value written write effect: modify value cfsa5 description: control frame station address 5. this field holds byte 5 of the station address used for control frames. for example, for the mac address ac-de-48-00-00-80, this field holds the value 80. initial value: 0x0 read value: previous value written write effect: modify value eth[0|1]pfs 0 31 31 0 pfd 1 eth[0|1]cfsa0 0 15 16 31 16 0 88 cfsa5 cfsa4
idt ethernet interfaces pause control frames 79rc32438 user reference manual 11 - 21 november 4, 2002 notes ethernet control frame station address 1 register figure 11.20 ethernet control fram e station address 1 (eth[0|1]cfsa1) ethernet control frame station address 2 register figure 11.21 ethernet control fram e station address 2 (eth[0|1]cfsa2) cfsa2 description: control frame station address 2. this field holds byte 2 of the station address used for control frames. for example, for the mac address ac-de-48-00-00-80, this field holds the value 48. initial value: 0x0 read value: previous value written write effect: modify value cfsa3 description: control frame station address 3. this field holds byte 3 of the station address used for control frames. for example, for the mac address ac-de-48-00-00-80, this field holds the value 00. initial value: 0x0 read value: previous value written write effect: modify value cfsa0 description: control frame station address 0. this field holds byte 0 of the station address used for control frames. for example, for the mac address ac-de-48-00-00-80, this field holds the value ac. initial value: 0x0 eth[0|1]cfsa1 0 15 16 31 16 0 88 cfsa3 cfsa2 eth[0|1]cfsa2 0 15 16 31 16 0 88 cfsa1 cfsa0
idt ethernet interfaces etherne t medium access controller (mac) 79rc32438 user reference manual 11 - 22 november 4, 2002 notes ethernet medium access controller (mac) this section describes the configurable parameters fo r the ethernet mac. the function of the control bits in the mac configuration registers are self-explanatory. ethernet mac configuration register #1 figure 11.22 ethernet mac confi guration register #1 (eth[0|1]mac1) read value: previous value written write effect: modify value cfsa1 description: control frame station address 1. this field holds byte 1 of the station address used for control frames. for example, for the mac address ac-de-48-00-00-80, this field holds the value de. initial value: 0x0 read value: previous value written write effect: modify value re description: receive enable. when this bit is set to 1, the mac is enabled to receive ethernet frames. when this bit is set to 0, this function is disabled and all incoming traffic is discarded. initial value: 0x0 read value: previous value written write effect: modify value paf description: pass all frames. when this bit is set to 1, the mac passes all frames to the input fifo regard- less of the frame type (i.e., normal frame or cont rol frame). when this bit is set to 0, control frames are discarded and only normal frames are written to the input fifo. initial value: 0x0 read value: previous value written write effect: modify value rfc description: receive flow control. when this bit is set to 1, the mac will act upon received pause flow control frames. when this bit is set to 0, pause flow control frames are ignored. eth[0|1]mac1 paf 0 15 re 11 tfc rfc 11 lb 1 mr 1 0 10 16 31 16 0
idt ethernet interfaces etherne t medium access controller (mac) 79rc32438 user reference manual 11 - 23 november 4, 2002 notes ethernet mac configuration register #2 figure 11.23 ethernet mac confi guration register #2 (eth[0|1]mac2) initial value: 0x0 read value: previous value written write effect: modify value tfc description: transmit flow control. when this bit is set to 1, the mac will transmit pause flow control frames. when this bit is set to 0, pause flow control frames are blocked. initial value: 0x0 read value: previous value written write effect: modify value lb description: loopback. when this bit is set to 1, the mac transmit interface is looped back to the mac receive interface. when this bit is set to 0, the mac is in its normal operation mode. initial value: 0x0 read value: previous value written write effect: modify value mr description: mac reset. when this bit is set to 1, the mac logic is reset. when this bit is set to 0, the mac is in its normal operation mode. initial value: 0x0 read value: previous value written write effect: modify value fd description: full duplex. when this bit is set to 1, the mac is selected to operate in full-duplex mode. when this bit is set to 0, the mac is selected to operate in half-duplex mode. initial value: 0x0 read value: status write effect: modify value eth[0|1]mac2 flc 0 15 fd 11 dc hfe 11 pe 1 ed 1 ape vpe 11 ppe 1 nb lpe 11 bp 1 0 1 0 2 16 31 16 0 cen 1
idt ethernet interfaces etherne t medium access controller (mac) 79rc32438 user reference manual 11 - 24 november 4, 2002 notes flc description: frame length checking. when this bit is set to 1, both transmit and receive frame lengths are compared to the length/type field. if the length/type field represents a length, a check is per- formed. when this bit is set to 0, frame length checking is disabled. initial value: 0x0 read value: status write effect: modify value hfe description: huge frame enable. when this bit is set to 1, frames of any length may be transmitted and received. when this bit is set to 0, transmission is aborted after the length in eth[0|1]maxf has been reached and the remainder of the frame is discarded. initial value: 0x0 read value: status write effect: modify value dc description: delayed crc. when this bit is set to 1, a four byte proprietary header exists on the front of all ieee 802.3 frames. crcs are not computed over the proprietary header. thus, when this bit is set to 1, crc calculations are delayed by four bytes. when this bit is set to 0, delayed crc is disabled. initial value: 0x0 read value: previous value written write effect: modify value cen description: crc enable. when this bit is set to 1, the mac pads all short frames and appends a crc to every frame. when this bit is cleared to 0, frames passed to the mac are assumed to have a valid length and crc (that is, these operations are performed in software). refer to table 11.4. initial value: 0x0 read value: previous value written write effect: modify value pe description: pad enable. when this bit is set to 1, the mac pads short transmit frames and computes and appends a crc on all transmit frames. when this bit is set to 0, frames are padded prior to being passed to the mac (i.e., padding operation is performed by software). refer to table 11.4. initial value: 0x0 read value: previous value written write effect: modify value vpe description: vlan pad enable. when this bit is set to 1 and padding is enabled, short transmit frames are padded to 64 bytes. if padding is enabled and this bit is cleared to 0, short transmit frames are padded to 60 bytes. refer to table 11.4. initial value: 0x0
idt ethernet interfaces etherne t medium access controller (mac) 79rc32438 user reference manual 11 - 25 november 4, 2002 notes read value: previous value written write effect: modify value ape description: auto pad enable. when this bit is set to 1 and padding is enabled, the mac automatically detects the frame type, either tagged or untagged, by comparing the two bytes following the source address with 0x1800 (vlan protocol id) and pads accordingly. untagged frames are padded to 60 bytes while tagged frames are padded to 64 bytes. when this bit is set to 0, the auto padding function is disabled. refer to table 11.4. initial value: 0x0 read value: previous value written write effect: modify value ppe description: pure preamble enforcement. when this bit is set to 1, the mac will verify the content of the preamble to ensure it contains 0x55 and is error-free. a frame with an error in the preamble is discarded. when this bit is cleared, no preamble checking is performed. initial value: 0x0 read value: previous value written write effect: modify value lpe description: long preamble enforcement. when this bit is set to 1, th e mac only allows receive frames which contain preamble fields less than 12 bytes in length. when this bit is cleared to 0, the mac allows any length preamble. initial value: 0x0 read value: previous value written write effect: modify value nb description: no backoff. when this bit is set to 1, the mac will immediately retransmit following a collision rather than using the binary exponential backoff algorithm. when this bit is set to 0, the mac will use the binary exponential backoff algorithm. initial value: 0x0 read value: previous value written write effect: modify value bp description: back pressure / no backoff. when this bit is set to 1, after incidentally causing a collision dur- ing back pressure, the mac will immediately retr ansmit without backoff. this reduces the chance of further collisions and ensures that transmit frames get sent. initial value: 0x0 read value: previous value written write effect: modify value
idt ethernet interfaces etherne t medium access controller (mac) 79rc32438 user reference manual 11 - 26 november 4, 2002 notes ed description: excess defer. when this bit is set to 1, the mac will defer indefinitely. when this bit is set to 0, the mac will abort when the excess deferral limit is reached. initial value: 0x0 read value: previous value written write effect: modify value ape vpe pe cen result 0 0 0 0 no pad or crc appended. 0 0 0 1 crc appended. 0 0 1 0 pad to 60 bytes (if necessary), append crc (min size = 64) with crc error. 0 0 1 1 pad to 60 bytes (if necessary), append crc (min size = 64). 0 1 0 0 no pad or crc appended. 0 1 0 1 crc appended. 0 1 1 0 pad to 64 bytes (if necessary), append crc (min size = 68) with crc error. 0 1 1 1 pad to 64 bytes (if necessary), append crc (min size = 68). 1 0 0 0 no pad or crc appended. 1 0 0 1 crc appended. 1 0 1 0 if untagged, pad to 60 by tes, add crc with crc error. if tagged, pad to 64 bytes, add crc with crc error. 1 0 1 1 if untagged, pad to 60 bytes, add crc. if tagged, pad to 64 bytes, add crc. 1 1 0 0 no pad or crc appended. 1 1 0 1 crc appended. 1 1 1 0 if untagged, pad to 60 by tes, add crc with crc error. if tagged, pad to 64 bytes, add crc with crc error. 1 1 1 1 if untagged, pad to 60 bytes, add crc. if tagged, pad to 64 bytes, add crc. table 11.4 padding operation
idt ethernet interfaces etherne t medium access controller (mac) 79rc32438 user reference manual 11 - 27 november 4, 2002 notes ethernet back-to-back inter-packet gap register figure 11.24 ethernet back-to-back inter-packet gap register (eth[0|1]ipgt) ethernet non back-to-back inter-packet gap register figure 11.25 ethernet non back-to-back inter-packet gap register (eth[0|1]ipgr) ipgt description: inter-packet gap. this is a programmable field representing the nibble time offset of the mini- mum possible period between the end of any transmitted packet to the beginning of the next. in full-duplex mode, the register value should be the desired period in nibble times minus 3. in half-duplex mode, the register value should be the desired period in nibble times minus 6. in full-duplex mode, the recommended setting is 0x15 (21d), which represents the minimum ipg of 0.96 s (in 100 mb/s) or 9.6 s (in 10 mb/s). in half-duplex the recommended setting is 0x12 (18d), which also represents the minimum ipg of 0.96 s (in 100 mb/s) or 9.6 s (in 10 mb/s). initial value: 0x0 read value: previous value written write effect: modify value ipgr2 description: non back-to-back inter-packet gap part 2. this field contains a field which represents the non back-to-back inter-packet gap. the default value of 0x12 represents a minimum value of 0.96 s at 100 mb/s or 9.6 s at 10 mb/s. initial value: 0x0 read value: previous value written write effect: modify value eth[0|1]ipgt 0 15 ipgt 7 0 9 16 31 16 0 eth[0|1]ipgr 0 15 ipgr2 7 0 1 0 1 ipgr1 7 16 31 16 0
idt ethernet interfaces etherne t medium access controller (mac) 79rc32438 user reference manual 11 - 28 november 4, 2002 notes ethernet collision window and retry register figure 11.26 ethernet collision window and retry register (eth[0|1]clrt) ipgr1 description: non back-to-back inter-packet gap part 1. this field contains the field which represents the optional carrier sense window referenced in ieee 802.3/4.2.3.2.1 ?carrier deference.? if carrier is detected during the timing of ipgr1, the mac defers to carrier. if carrier becomes active after ipgr1, the mac continues timing ipgr2 and transmits, knowingly causing a collision, thus ensuring fair access to the medium. its range of values are 0x0 to ipgr2. initial value: 0x0 read value: previous value written write effect: modify value maxret description: maximum retransmissions. this field specifies the number of retransmission attempts follow- ing a collision before transmission of the frame is aborted due to excessive collisions. initial value: 0xf read value: previous value written write effect: modify value colwin description: collision window. this field represents the slot time or collision window during which collisions occur in properly configured networks. since the collision window starts at the beginning of trans- mission, the preamble and sfd are included. its default value of 0x37 corresponds to the count of frame bytes at the end of the window. initial value: 0x37 read value: previous value written write effect: modify value eth[0|1]clrt 0 15 maxret 4 0 2 0 4 colwin 6 16 31 16 0
idt ethernet interfaces etherne t medium access controller (mac) 79rc32438 user reference manual 11 - 29 november 4, 2002 notes ethernet maximum frame length register figure 11.27 ethernet maximum fr ame length register (eth[0|1]maxf) ethernet mac test register figure 11.28 ethernet mac test register (eth[0|1]mtest) maxf description: maximum frame length. this field contains the maximum frame length supported by the mac. the default value 0x0600 represents a maximum receive frame of 1536 bytes. the maximum untagged ethernet frame size is 1518 bytes. a tagged frame adds four bytes for a total of 1522 bytes. initial value: 0x0600 read value: previous value written write effect: modify value tb description: test back pressure. when this bit is set to 1, the mac asserts back pressure on the link. back pressure causes the preamble to be transmitted, ra ising carrier sense. when this bit is set to 0, the test back pressure function is disabled. initial value: 0x0 read value: previous value written write effect: modify value eth[0|1]maxf 0 15 16 maxf 16 31 16 0 0 eth[0|1]mtest 0 15 2 tb 1 0 13 16 31 16 0
idt ethernet interfaces ethernet mii management interface 79rc32438 user reference manual 11 - 30 november 4, 2002 notes ethernet mii management interface the mii management interface provides a simple seri al interface for controlling phys and for gathering status from phys. both ethernet interfaces shar e a single mii management interface. the interface consists of two pins for readi ng and writing registers in a phy: clock pin (miimdc) bidirectional data pin (miidio) the clock for the management inte rface is generated by the cpu core and driven on the miimdc pin. the clock frequency driven on this pin is based on the ethernet management clock generated by the ethernet clock prescalar. the ethernet clock presca lar value should be selected such that the minimum high and low times for the miimdc pin are at least 160 ns, and the minimum period is 400 ns. a phy register is read by first writing the desired phy address into the phy address (phyaddr) field of the mii management address (miim addr) register and writing the desired register address in the register address (regaddr) field of the miimaddr register. one of two operations can then be selected: setting the read (rd) bit in the mii management command (miicmd) register causes a single read operation to be performed. setting the scan (scn) bit in the miicmd register causes repeated reads to be performed from the selected phy register. once the read data not valid (nv) bit in the mii m anagement indicators regist er (miimind) is cleared to 0, the value read from the selected phy register ma y be read from the mii management read data register (miimrdd) by the cpu core. a phy register may be written by writing the desired phy address into the phy address (phyaddr) field of the miimaddr register, and then writing the data to the mii management write data (miiwtd) register. a side effect of writing into the miiwtd regi ster is that a write is performed by the mii management interface to the selected phy register. the phy write operation is completed when the busy (bsy) bit in the miimind register is cleared. mii management configuration register figure 11.29 mii management c onfiguration register (miimcfg) rsv description: reserved. any value may be written to this field. initial value: undefined read value: previous value written write effect: modify value miimcfg 0 15 0 2 r 1 0 11 rsv 2 16 31 16 0
idt ethernet interfaces ethernet mii management interface 79rc32438 user reference manual 11 - 31 november 4, 2002 notes mii management command register figure 11.30 mii management command register (miimcmd) r description: reset mii management logic. when this bit is set to 1, the ethernet mii management logic is reset. when this bit is set to 0, the ethernet mii management logic is in normal operational mode. initial value: 0x1 read value: previous value written write effect: modify value rd description: read. when this bit is set to 1, the mii management interface performs a single read operation. the data read is returned in the mii management read data (miimrdd) register. initial value: 0x0 read value: previous value written write effect: modify value scn description: scan. when this bit is set to 1, the mii management interface performs continuous read opera- tions. this is useful for monitoring status. initial value: 0x0 read value: previous value written write effect: modify value nv (read data not valid) read scan operation 1 1 1 single read 1 0 1 multiple read 1 0 0 no operation x 1 1. x = don?t care. 1 1 not valid 0xxbusy miimcmd 0 15 0 14 rd 1 scn 1 16 31 16 0
idt ethernet interfaces ethernet mii management interface 79rc32438 user reference manual 11 - 32 november 4, 2002 notes mii management address register figure 11.31 mii management address register (miimaddr) mii management write data register figure 11.32 mii management write data register (miimwtd) regaddr description: register address. this field contains the 5-bit register address used for mii management oper- ations. initial value: 0x0 read value: previous value written write effect: modify value phyaddr description: phy address. this field contains the 5-bit phy address used for mii management operations. initial value: 0x0 read value: previous value written write effect: modify value wdata description: write data. when this field is written, a mii management write cycle is performed using the 16- bit data value written and the pre-configured phy and register address from the mii manage- ment address (miimaddr) register. initial value: 0x0000 read value: previous value written write effect: modify value and initiate a mii management write cycle miimaddr 0 15 regaddr 5 0 3 phyaddr 5 0 3 16 31 16 0 miimwtd 0 15 16 wdata 16 31 16 0
idt ethernet interfaces ethernet mii management interface 79rc32438 user reference manual 11 - 33 november 4, 2002 notes mii management read data register figure 11.33 mii management re ad data register (miimrdd) mii management indicators register figure 11.34 mii ma nagement indicators register (miimind) rdata description: read data. following a mii management read cycle, this field contains the data read. the nv bit is set to 0 when data is valid following the read operation. initial value: 0x0000 read value: data read from mii management interface write effect: read-only bsy description: busy. when this bit is set to 1, a mii management read cycle or write cycle is in progress and subsequent reads or writes are ignored until this bit is cleared to 0. initial value: 0x0 read value: status write effect: read-only scn description: scan. when this bit is set to 1, a mii management scan operation is in progress. initial value: 0x0 read value: status write effect: read-only miimrdd 0 15 16 rdata 16 31 16 0 miimind 0 15 0 13 bsy 1 scn 1 nv 1 16 31 16 0
idt ethernet interfaces ethernet clock prescalar 79rc32438 user reference manual 11 - 34 november 4, 2002 notes ethernet clock prescalar the ethernet interfaces share an 8-bit clock pres calar which is used to generate the ethernet manage- ment clock for shared mii management interface. the ethernet management clock is the media indepen- dent interface management data clock on the miimdc pin. the ethernet management clock is equal to the ipbus clock (iclk) frequency divided by the clock pres calar divisor (div) field in the ethernet management clock prescalar register (ethmcp). figure 11.35 ethernet management clock prescalar register (ethmcp) programming example disclaimer: code examples provided by idt are for illu strative purposes only and should not be relied upon for developing applications. idt does not assume li ability for any loss or damage that may result from the use of this code. */ #define ethipgt_half_duplex 0x12 #define ethipgt_full_duplex 0x15 int reginit( void ) ; int io_fifo( void ) ; int addr_rec( void ) ; int cpu_infc( void ) ; int eth_mac( void ) ; int eth_prescale( void ) ; nv description: read data not valid. when this bit is set to 1, a mii management read operation has not com- pleted and the value in the mii management read data (miimrdd) register is not valid. initial value: 0x0 read value: status write effect: read-only div description: clock prescalar divisor. when the div field equals zero, one, two, or three, the internally gen- erated ethernet management clock is equal to the system clock divided by four. for all other even values of the div field up to 255, the ethernet management clock is equal to the system clock divided by the div field. bit zero of the div field is always assumed to be zero. initial value: 0x0 read value: previous value written write effect: modify value ethmcp 0 31 div 0 24 8
idt ethernet interfaces programming example 79rc32438 user reference manual 11 - 35 november 4, 2002 notes int eth_mii( void ) ; int reginit( void ) { addr_rec(); eth_mac(); io_fifo(); eth_prescale(); reset_phy(); return( 0 ); } /* set up the four physical station addresses for the mac */ int addr_rec( void ) { /* accept only packets destined fo r this ethernet device address */ ethernet.etharc = 0x0; /* set all ethernet address registers to the same initial values */ /* set all four addresses to 66-88-aa-cc-dd-ee */ ethernet.ethsal0 = 0xaaccddee; ethernet.ethsah0 = 0x00006688; ethernet.ethsal1 = 0xaaccddee; ethernet.ethsah1 = 0x00006688; ethernet.ethsal2 = 0xaaccddee; ethernet.ethsah2 = 0x00006688; ethernet.ethsal3 = 0xaaccddee; ethernet.ethsah3 = 0x00006688; return( 0 ); } int eth_mac( void ) { /* receive is enabled */ ethernet.ethmac1 = ethermac1_re; /* enable full duplex */ ethernet.ethmac2 = ethermac2_fd; /* back-to-back inter-packet-gap, full-duplex */ ethernet.ethipgt = ethipgt_full_duplex; /* none back-to-back inter-packet-gap, ipgr2 */ ethernet.ethipgr = 0x12; return( 0 ); } int eth_prescale( void )
idt ethernet interfaces programming example 79rc32438 user reference manual 11 - 36 november 4, 2002 notes { /* system clock divisor for mii bus */ ethernet.ethmcp = 0x28; /* 50 mhz / 40 = 1.25 mhz */ return( 0 ); } int io_fifo( void ) { unsigned int i, xthres; ethernet.ethintfc = 0; /* reset ethernet interfce */ i = ethernet.ethintfc; printf("intfc = %x\n",i); for(i=0xffff;i>0;i--){ if(!(ethernet.ethintfc & etherintfc_rip)) break; } /* enable ethernet interface */ ethernet.ethintfc = etherintfc_en; v /* fifo tx threshold level */ ethernet.ethfifott = 0x40; return( 0 ); } /* reset ethernet phy chip */ int reset_phy(void) { unsigned int tmp,i; ethernet.miimcfg = 0x8000; /* set mii reset bit */ for(i=0;i<0xffff;i++);/* allow for slow mii clock */ ethernet.miimcfg = 0;/* clear reset bit */ /* phy default is 10/100 full duplex mode */ tmp = read_phy_reg(0); printf("read phy reg 0 = %x\n",tmp); tmp = read_phy_reg(0); printf("read phy reg 0 = %x\n",tmp); tmp = read_phy_reg(1); printf("read phy reg 1 = %x\n",tmp); while(!(tmp& 0x04))/* link is down */ tmp = read_phy_reg(1); printf("read phy reg 1 = %x\n",tmp); /* link is up */ return(0); }
idt ethernet interfaces programming example 79rc32438 user reference manual 11 - 37 november 4, 2002 notes #define mii_timeout 0xf000 int write_phy_reg(int reg, int data) { int i; i=mii_timeout; while((ethernet.miimind & ethermiimind_bsy) && i) i--; if(i == 0){ printf("write phy reg timed out waiting for mii busy\n"); return (1); } ethernet.miimaddr = reg; i=mii_timeout; while((ethernet.miimind & ethermiimind_bsy) && i) i--; if(i == 0){ printf("write phy reg timed out waiting for mii busy\n"); return (2); } ethernet.miimwtd = data; i=mii_timeout; while((ethernet.miimind & ethermiimind_bsy) && i) i--; if(i == 0){ printf("write phy reg timed out waiting for mii busy\n"); return (3); } return(0); } int read_phy_reg(int reg) { int i, data; i=mii_timeout; while((ethernet.miimind & ethermiimind_bsy) && i) i--; if(i == 0){ printf("read phy reg timed out waiting for mii busy\n"); return (0x1); } ethernet.miimaddr = reg; i=mii_timeout; while((ethernet.miimind & ethermiimind_bsy) && i)
idt ethernet interfaces programming example 79rc32438 user reference manual 11 - 38 november 4, 2002 notes i--; if(i == 0){ printf("read phy reg timed out waiting for mii busy\n"); return (0x1); } ethernet.miimcmd = ethermiimcmd_rd; i=mii_timeout; while((ethernet.miimind & ethermiimind_bsy) && i) i--; if(i == 0){ printf("read phy reg timed out waiting for mii busy\n"); return (0x2); } if(ethernet.miimind & ethermiimind_nv){ printf("read phy reg fail ed, data not valid\n"); return(0x3); } data = ethernet.miimrdd; ethernet.miimcmd = 0;/* clear read bit */ return(data); } int scan_phy_reg(int reg) { int i, data; i=mii_timeout; while((ethernet.miimind & ethermiimind_bsy) && i) i--; if(i == 0){ printf("read phy reg timed out waiting for mii busy\n"); return (0x1); } ethernet.miimaddr = reg; i=mii_timeout; while((ethernet.miimind & ethermiimind_bsy) && i) i--; if(i == 0){ printf("read phy reg timed out waiting for mii busy\n"); return (0x1); } ethernet.miimcmd = ethermiimcmd_scn; while(1){ i=mii_timeout; while((ethernet.miimind & ethermiimind_nv) && i) i--;
idt ethernet interfaces programming example 79rc32438 user reference manual 11 - 39 november 4, 2002 notes if(i == 0){ printf("read phy reg timed out waiting for mii not vaild\n"); return (0x2); } data = ethernet.miimrdd; printf("reg %d = %x\r",reg,data); if(data == 0x782d) break; } ethernet.miimcmd = 0;/* clear scan bit */ return(data); }
idt ethernet interfaces programming example 79rc32438 user reference manual 11 - 40 november 4, 2002 notes
notes 79rc32438 user reference manual 12 - 1 november 4, 2002 chapter 12 general purpose i/o controller introduction this chapter describes the operation of the gener al purpose i/o (gpio) controller and the operation of the general purpose i/o pins. this chapter also descri bes how the gpio controller and pins are configured to operate as a general purpose i/o or as an alternate function. functional overview the general purpose i/o controller provides 32 general purpose i/o pins which may be individually configured as: ? general purpose input ? general purpose output ? alternate functions when configured as general purpose i nput, each pin can be used as an acti ve high or active low level interrupt input. as shown in table 12.1, each general purpose i/o (gpi o) bit is shared with another on-chip function. the gpio function (gpiofunc) fiel d in the general purpose i/o functi on (gpiofunc) register controls whether a gpio bit operates as a general purpose i/o or as the specified alternate function. gpio pin alternate function pin name alternate function description alternate function pin type 0 u0sout uart channel 0 serial output (see chapter 13) output 1 u0sinp uart channel 0 serial input (see chapter 13) input 2 u0rin uart channel 0 ring indicator (see chapter 13) input 3 u0dcdn uart channel 0 data carrier detect (see chapter 13) input 4 u0dtrn uart channel 0 data terminal ready (see chapter 13) output 5 u0dsrn uart channel 0 data set ready (see chapter 13) input 6 u0rtsn uart channel 0 request to send (see chapter 13) output 7 u0ctsn uart channel 0 clear to send (see chapter 13) input 8 u1sout uart channel 1 serial output (see chapter 13) output 9 u1sinp uart channel 1 serial input (see chapter 13) input 10 u1dtrn uart channel 1 data terminal ready (see chapter 13) output 11 u1dsrn uart channel 1 data set ready (see chapter 13) input 12 u1rtsn uart channel 1 request to send (see chapter 13) output 13 u1ctsn uart channel 1 clear to send (see chapter 13) input 14 dmareqn0 external dma channel 0 request (see chapter 9) input 15 dmareqn1 external dma channel 1 request (see chapter 9) input table 12.1 general purpose i/o pi n alternate function (part 1 of 2)
idt general purpose i/o controller theory of operation 79rc32438 user reference manual 12 - 2 november 4, 2002 notes theory of operation after reset, all gpio pins default to the gpio input function. when a gpio pin is configured for use as a gpio pin, the alternate function associ ated with that pin is held in an inac tive state by internal logic. care should be exercised when configuri ng gpio pins as outputs because an incorrect configuration (for example, mistakenly configuring an input pin as an output pin) coul d cause damage to external components as well as to the rc32438 device itself. each gpio pin is controlled by its corresponding bit in each gpio register. for example, gpio bit [0] is controlled by gpiofunc[0], gpiocfg[0], gpiod[0], gpioilevel[0], gpioistat[0], and gpionmien[0]. in another example, gpio bit [2] is controlled by gpiofunc[2 ], gpiocfg[2], gpiod[2], gpioilevel[2], gpioistat[2], and gpionmien[2]. all gpio pins except gpio[24] and gpio[30:26] have lvttl i/o buffers. gpio pins 24 and 26 through 30 have pci i/o buffers which allow these pins to be used for pci interrupts. gpio pin configured as input when configured as an input in the gpio configurat ion register (gpiocfg) and as a gpio function in the gpio function register (gpiofunc), the gpio pin value will be sampled and registered in the gpio data register (gpiod) each master clock cycle (after double registering to prevent metastability). the value of the input pin can be determined at any time by reading gpiod. 16 dmadonen0 external dma channel 0 done (see chapter 9) input 17 dmadonen1 external dma channel 1 done (see chapter 9) input 18 dmafinn0 external dma channel 0 finished (see chapter 9) output 19 dmafinn1 external dma channel 1 finished (see chapter 9) output 20 maddr[22] memory and peripheral bus address (see chapter 6) output 21 maddr[23] memory and peripheral bus address (see chapter 6) output 22 maddr[24] memory and peripheral bus address (see chapter 6) output 23 maddr[25] memory and peripheral bus address (see chapter 6) output 24 pcireqn[4] pci request 4 (see chapter 10) input 25 afspare1 reserved input 26 pcigntn[4] pci grant 4 (see chapter 10) output 27 pcireqn[5] pci request 5 (see chapter 10) input 28 pcigntn[5] pci grant 5 (see chapter 10) output 29 ipbmtriginp ipbus monitor trigger input (see chapter 19) input 30 pcimuintn 1 pci messaging unit interrupt output (see chapter 10) output 31 reserved 1. when acting as the alternate function pcimuintn, this pin is tr i-stated when it is not asserted (i.e., it acts as an open colle ctor output when configured as an alternate function). gpio pin alternate function pin name alternate function description alternate function pin type table 12.1 general purpose i/o pin alternate function (part 2 of 2)
idt general purpose i/o controller theory of operation 79rc32438 user reference manual 12 - 3 november 4, 2002 notes gpio pin configured as output when configured as an output in gpiocfg and as a gpio function in gpiofunc, the value written into gpiod will be output at the pin. the value of the output pin can be determi ned at any time by reading gpiod. gpio pin configured as an alternate function when configured as an alternate function in gpiofu nc register, the pin behaves as described in each chapter associated with that functi on. the value of the alternate func tion pin can be determined at any time by reading gpiod. gpio pins as interrupt sources each pin can also generate an interrupt to the interr upt controller, regardless of the configuration in gpiofunc or gpiocfg. this allows an alternate func tion, a write to gpiod, or a gpio input from an external device, to generate an interrupt. interrupt generation is controlled using the gpio inte rrupt level register (gpioilevel) and gpio inter- rupt status register (gpioistat). gpioilevel describes the interrupt level (either active high or low) of the signal that will cause the interrupt. when the value of a pin matches the level in gpioilevel, the corre- sponding bit in the gpio interrupt status register (g pioistat) will be set high. once set, the bit in gpio- istat will remain set even if the value of the gpio pin changes. all gpioistat bits are sent to the interrupt controller to request interrupt servicing. to clear the interrupt, the source of the interrupt must be cleared or serviced. (this could be an alternate function service or clearing of gpiod.) then the bit in gpioistat must also be cleared. note that if an interrupt is not wanted from a gpio pin, it must be masked in the interrupt controller interrupt mask 6 register (imask6). see chapter 8, interrupt controller. gpio pins as non-maskable interrupt sources each gpio pin can also be programmed to generate a non-maskable interrupt (nmi) to the cpu regard- less of the configuration in gpiofunc or gpiocfg. gpioilevel and gpioistat must be set up to generate an interrupt as described in the previous section. the gpio non- maskable interrupt enable register (gpionmien) enables the co rresponding bit in the gpioistat register to generate an nmi. all enabled nmi sources are logically combined to gener ate a single nmi to the cpu core. the gpiostat register can be read to determine the cause of the nmi. note that in addition to the generation of the nm i, an interrupt is also generated unless masked in the interrupt controller. gpiofunc gpiocfg pin function 0 0 gpio input 0 1 gpio output 1 don?t care alternate 1 function table 12.2 possible gpio configurations
idt general purpose i/o controller g eneral purpose i/o register description 79rc32438 user reference manual 12 - 4 november 4, 2002 notes general purpose i/o register description gpio function register figure 12.1 gpio f unction register (gpiofunc) gpio configuration register figure 12.2 gpio configuration register (gpiocfg) register offset 1 1. the address of the register is equal to the regi ster offset added to the base value of 0x1800_0000. register name register function size 0x04_8000 gpiofunc gpio function 32-bit 0x04_8004 gpiocfg gpio configuration 32-bit 0x04_8008 gpiod gpio data 32-bit 0x04_800c gpioilevel gpio interrupt level 32-bit 0x04_8010 gpioistat gpio interrupt status 32-bit 0x04_8014 gpionmien gpio nonmaskable interrupt enable 32-bit 0x04_8018 through 0x04_ffff reserved table 12.3 ethernet register map gpiofunc description: gpio function. each bit in this field controls its corresponding gpio pin. when a bit is set to a one, the corresponding gpio pin operates as the alternate 1 function as defined in table 12.1. when a bit is set to a zero, the corresponding gpio pin operates as a general purpose i/o pin. initial value: 0x0 read value: current value write effect: modify value gpiocfg description: gpio configuration. each bit in this field controls its corresponding gpio pin. when a bit is configured as a general purpose i/o pin and the corresponding bit in this field is set, then the pin is configured as an output. when a bit is configured as a general purpose i/o pin and the corre- sponding bit in this field is a zero, the pin is configured as in input. when the pin is configured as an alternate function, the behavior of the pin is defined by the alternate 1 function. gpiofunc 0 31 32 gpiofunc gpiocfg 0 31 32 gpiocfg
idt general purpose i/o controller g eneral purpose i/o register description 79rc32438 user reference manual 12 - 5 november 4, 2002 notes gpio data register figure 12.3 gpio data register (gpiod) gpio interrupt level register figure 12.4 gpio interrupt level register (gpioilevel) gpio interrupt status register figure 12.5 gpio interrupt status register (gpioistat) initial value: 0x0 read value: current value write effect: modify value gpiod description: gpio data. each bit in this field controls its corresponding gpio pin. reading this field returns the current value of each gpio pin. writing a value to this field causes the corresponding pins which are configured as gpio outputs to change state to the value written. initial value: undefined read value: gpio pin status write effect: modify gpio output pin status gpioilevel description: gpio interrupt level. when the value of a gpio pin matches the value of the corresponding bit in this field, then the corresponding bit is set in the gpioistat field is set. initial value: undefined read value: current value write effect: modify value gpiod 0 31 32 gpiod gpioilevel 0 31 32 gpioilevel gpioistat 0 31 32 gpioistat
idt general purpose i/o controller g eneral purpose i/o register description 79rc32438 user reference manual 12 - 6 november 4, 2002 notes gpio non-maskable interrupt enable register figure 12.6 gpio non-maskable in terrupt enable register (gpionmien) gpioistat description: gpio interrupt status. each bit in this field controls its corresponding gpio pin. when a bit in this field is set to 1, the gpio pin value matche s that of the correspondi ng bit in the gpioilevel field. each bit in this field is presented to the inte rrupt controller as an interrupt input. bits in this field are typically cleared by an interrupt service routine. initial value: undefined read value: status write effect: sticky bit 1 1. a sticky bit is set by the hardwar e and can only be cleared by the cpu. nmien description: gpio non-maskable interrupt enable. when a bit in the gpioistat register is set to 1 and the corresponding bit in the nmien field of the gpionmien register is set to 1, a gpio non- maskable interrupt request is generated. this results in the gpio bit being set in the nmips reg- ister (see chapter 8, general purpose i/o controller) which causes a non-maskable interrupt exception. initial value: 0x0000_0000 read value: previous value written write effect: modify value gpionmien 0 31 32 nmien
notes 79rc32438 user reference manual 13 - 1 november 4, 2002 chapter 13 uart controller introduction the rc32438 contains two completely separate but identical serial channels (uarts). each uart is compatible with the industry standard 16550 1 uart. the two uarts (referred to as channel 0 and channel 1) are functionally identic al, except uart channel 1 does not use all the available modem control pins. features ? compatible with the 16550 and 16450 uarts ? two completely separate serial channels ? modem control functions (cts, rts, dsr, dtr, ri, dcd) ? 16-byte transmit and receive buffers ? programmable baud rate generator der ived from the system clock ? fully programmable seri al characteristics: ? 5, 6, 7, or 8 bit characters ? even, odd or no parity bit generation and detection ? 1, 1-1/2 or 2 stop bit generation ? line break generation and detection ? false start bit detection ? internal loopback mode functional overview the 16550 uart is an enhanced version of the 16450 uart. upon power-up, each uart defaults to the 16450 mode. the 16550 contains two 16-byte buffers: one in the receive data path and one in the transmit data path. the buffers reduce the overhead on the cpu core in managing the data flow. the 16450 does not use the buffers in the data path. the cpu core can read the status of either uart channel at any time during operation. status informa- tion that is available includes the ty pe and condition of the transfer operati on, as well as any error condition (parity, overrun, framing, or break interrupt). the baud rate generator divides down the ipbus clock and provides a 16x clock for driving the transmitter and receiver logic. the uart pins shown in table 13.1 are multiplex ed with the gpio pins as shown in table 12.1. 1. pc 16550d dual universal asynchronous receiver/transmitter with fifos , june 1995, national semicon- ductor . signal description direction u0sout uart channel 0 serial output output u0sinp uart channel 0 serial input input u0rin uart channel 0 ring indicator input u0dcrn uart channel 0 data carrier detect input u0dtrn uart channel 0 data terminal ready output u0dsrn uart channel 0 data set ready input table 13.1 uart input/output pins (part 1 of 2)
idt uart controller uar t register description 79rc32438 user reference manual 13 - 2 november 4, 2002 notes the uart must be configured before operat ion may begin. to configure the uart: 1. set up the transmit and receive parameters in the line control (uartxlc) register. 2. program the baud rate in the divisor latch lo w (uartdll) and divisor la tch high (uartdlh) regis- ters. 3. enable, if desired, the 16550 buffer mode in the fifo control (uartxfc) register. the general purpose i/o controller must be configured to use the desired uart pins as alternate func- tion gpio pins. the uart contains a baud rate generator which is used to operate the transmit and receive logic at the baud rate determined by the divisor latches. uart register description in order to maintain full compatibility with the 16550, all registers in the uart are 8-bits in size and have the addressing architecture of the 16550. despite the fact that the registers are 8-bits in size, they are word aligned. as in the 16550, the exact register which is selected when accessing the uart is dependent on the divisor latch access bit (dlab) in the line cont rol (uartxlc) register and on whether a read or write operation is performed. table 13.2 lists the uart registers. u0rtsn uart channel 0 request to send output u0ctsn uart channel 0 clear to send input u1sout uart channel 1 serial output output u1sinp uart channel 1 serial input input u1dtrn uart channel 1 data terminal ready output u1dsrn uart channel 1 data set ready input u1rtsn uart channel 1 request to send output u1ctsn uart channel 1 clear to send input register offset register name register function size dlab = 0 dlab = 1 0x05_0000 uart0rb (read) uart0th (write) uart0dll uart 0 receive buffer / uart 0 trans- mit holding / uart 0 divisor latch low 32-bit 0x05_0004 uart0ie uart0dlh uart 0 interrupt enable / uart 0 divi- sor latch high 32-bit 0x05_0008 uart0ii (read) uart0fc (write) none uart 0 interrupt identification / uart 0 fifo control 32-bit 0x05_000c uart0lc uart 0 line control 32-bit 0x05_0010 uart0mc uart 0 modem control 32-bit 0x05_0014 uart0ls uart 0 line status 32-bit 0x05_0018 uart0ms uart 0 modem status 32-bit 0x05_001c uaart0s uart 0 scratch 32-bit 0x05_0020 uart1rb (read) uart1th (write) uart1dll uart 1 receive buffer / uart 1 trans- mit holding / uart 1 divisor latch low 32-bit 0x05_0024 uart1ie uart1dlh uart 1 interrupt enable / uart 1 divi- sor latch high 32-bit table 13.2 uart register map (part 1 of 2) table 13.1 uart input/output pins (part 2 of 2)
idt uart controller baud rate selection 79rc32438 user reference manual 13 - 3 november 4, 2002 notes baud rate selection the baud rate is determined by a two-byte divisor that divides down the ipbus cl ock (iclk). the divisor, in binary, is loaded into the uartdll and uartdlh regist ers. a divisor value of zero or one is interpreted as a divisor of 32 decimal ( 0020 hex) by the baud rate generator. to calculate the baud rate, use the following formul a (the constant, 16, is used in the formula because the output frequency of the baud rate generator is 16 times the baud): baud rate = (system frequency) / (divisor * 16) or, to calculate the divisor to load into the divisor latches, use the following formula: divisor = system frequency / (baud rate * 16) as an example, for a system frequency of 66 mhz and a baud rate of 9600 (values shown are decimal), calculate the divisor as follows: divisor = 66,000,000 / (9600 * 16) = 429.6875 round off the ideal divisor to the nearest whole number, 430, to load into the divisor latches. load 0000_0001_1010_1110 into the divisor latches: 0000_0001 into uartdlh and 1010_1110 into uartdll. some divisors and system frequencies will give a more accurate baud rate than others. to calculate the percent error of the divisor, use this formula: % error = ((difference of the whole divisor and the ideal fractional divisor) / ideal fractional divisor) * 100. in this example, the error is ((430 - 429.6875) / 429.6875) * 100 = 0.073%. divisor values for typical baud rates and system clock frequencie s are provided in table 13.3. 0x05_0028 uart1ii (read) uart1fc (write) none uart 1 interrupt identification / uart 1 fifo control 32-bit 0x05_002c uart1lc uart 1 line control 32-bit 0x05_0030 uart1mc uart 1 modem control 32-bit 0x05_0034 uart1ls uart 1 line status 32-bit 0x05_0038 uart1ms uart 1 modem status 32-bit 0x05_003c uaart1s uart 1 scratch 32-bit 0x05_0040 uart0rr uart 0 reset 32-bit 0x05_0044 uart1rr uart 1 reset 32-bit 0x05_0048 through 0x05_7fff reserved ipbus clock frequency baud rate divisor (decimal) 133 mhz 19200 433 116.5 mhz 19200 379 100 mhz 9600 651 66 mhz 19200 214 table 13.3 divisor values for typical baud rates and ipbus clock frequencies (part 1 of 2) register offset register name register function size dlab = 0 dlab = 1 table 13.2 uart register map (part 2 of 2)
idt uart controller uart interrupts 79rc32438 user reference manual 13 - 4 november 4, 2002 notes uart interrupts the uart generates six interrupt r equests to the interrupt controller: ? general interrupt 0 . activated when one of the conditions in the uart0ie register is enabled and the necessary condition has occurred. this is bit (0) in the uart0ii register, inverted, and sent to the interrupt controller. ? txrdy 0 interrupt. activated depending on the dma mode set in the fifo control register for channel 0. an interrupt request is generated under the same conditions that the txrdy pin for channel 0 would be asserted. (refer to industry standard 16550 uart specification.) 1 ? rxrdy 0 interrupt . activated depending on the dma mode set in the fifo control register for channel 0. an interrupt request is generated under the same conditions that the rxrdy pin for channel 0 would be asserted. (refer to industry standard 16550 uart specification.) 1 ? general interrupt 1 . activated when one of the conditions in the uart1ie register is enabled and the necessary condition has occurred. this is bit (0) in the uart1ii register, inverted, and sent to the interrupt controller. ? txrdy 1 interrupt. activated depending on the dma mode set in the fifo control register for channel 1. an interrupt request is generated under the same conditions that the txrdy pin for channel 1 would be asserted. (refer to industry standard 16550 uart specification.) 1 ? rxrdy 1 interrupt . activated depending on the dma mode set in the fifo control register for channel 1. an interrupt request is generated under the same conditions that the rxrdy pin for channel 1 would be asserted. (refer to industry standard 16550 uart specification.) 1 uart channel reset the uart provides two independent serial channel s. when switching a uart channel between 16550 and 16450 modes, the internal uart fifos are not cleared. to support clean switching between modes, a uart reset register (uart[0|1]rr) is added to the standard 16550 uart register definition for each channel. the standard 16550 uart registers are described in the functional overview section at the beginning of this chapter. uart registers this section describes the uart registers. for additional information on configuring and operating the uart, see the 16550 data sheet 2 . 66mhz 9600 430 66mhz 2400 1719 50mhz 9600 326 40mhz 9600 260 33mhz 9600 215 25mhz 9600 163 1. pc 16550d dual universal asynchronous receiver/transmitter with fifos , june 1995, national semicon- ductor . 2. pc 16550d dual universal asynchronous receiver/transmitter with fifos , june 1995, national semicon- ductor. ipbus clock frequency baud rate divisor (decimal) table 13.3 divisor values for typical baud rates and ipbus clock frequencies (part 2 of 2)
idt uart controller uart registers 79rc32438 user reference manual 13 - 5 november 4, 2002 notes reset register figure 13.1 uart [0|1] reset register receive buffer register figure 13.2 uart [0|1] receive buffer register (uart[0|1]rb) transmit holding register figure 13.3 uart [0|1] transmit holding register (uart[0|1]th) r description: reset. a write of any value to this register causes the corresponding uart channel to be reset. initial value: undefined read value: undefined write effect: write of any value causes uart channel reset data description: data. reading this field returns a byte from the uart receive buffer. initial value: undefined read value: byte from uart receive buffer write effect: read-only data description: data. writing a byte to this field places the byte into the uart transmit buffer. initial value: undefined uart[0|1]rr 0 31 32 r 31 uart[0|1]rb 0 8 data 24 0 uart[0|1]th 0 8 data 31 24 0
idt uart controller uart registers 79rc32438 user reference manual 13 - 6 november 4, 2002 notes interrupt enable register figure 13.4 uart [0|1] interrupt enable register (uart[0|1]ie) read value: write-only write effect: write byte into uart transmit buffer rda description: enable receive data available interrupt. when set to 1, this bit enables receiver data available interrupts and time-out interrupts in fifo mode. initial value: 0x0 read value: previous value written write effect: modify value the description: enable transmitter holding register empty interrupt. when set to 1, this bit enables transmit- ter holding register empty interrupts. initial value: 0x0 read value: previous value written write effect: modify value rls description: enable receiver line status interrupt. when set to 1, this bit enables receiver line status inter- rupts. initial value: 0x0 read value: previous value written write effect: modify value ems description: enable modem status interrupt. when set to 1, this bit enables modem status interrupts. initial value: 0x0 read value: previous value written write effect: modify value uart[0|1]ie 0 4 0 1 rda 1 the 1 rls 1 ems 31 24 0
idt uart controller uart registers 79rc32438 user reference manual 13 - 7 november 4, 2002 notes interrupt identification register figure 13.5 uart [0|1] interrupt id entification register (uart[0|1]ii) pi description: pending interrupt. when this bit is set to 1, no interrupt request is pending. when this bit is cleared, an interrupt request is pending. initial value: 0x1 read value: status write effect: read-only iid description: interrupt id. these bits identify the highest priority pending interrupt. 0x0 modem status . clear to send, data set ready, ring indicator or data carrier detect. 0x1 transmitter holding register empty. writing to uartxth will reset this interrupt. 0x2 received data available. rx data is available to read or the specified trigger level is reached. reading either uartxrb or if the buffer level drops below the trigger point resets the interrupt. 0x3 receiver line status . occurs during an overrun error, parity error, framing error or break interrupt. reading uartxls resets the interrupt. 0x4 reserved 0x5 reserved 0x6 character time-out indication . no characters have been removed from or input to the receiver buffer during the last four character times and there is at least 1 character in it during this time. 0x7 reserved initial value: 0x0 read value: status write effect: read-only fifoen description: fifo enables. these two bits are set when fifo mode is enabled. initial value: 0x0 read value: status write effect: read-only uart[0|1]ii 0 2 0 1 pi 3 iid 2 fifoen 31 24 0
idt uart controller uart registers 79rc32438 user reference manual 13 - 8 november 4, 2002 notes fifo control register figure 13.6 uart [0|1] fifo control register (uart[0|1]fc) en description: fifo enable. when this bit is set, the transmit and receive fifos are enabled for 16550 mode. when switching between 16550 and 16450, always reset the buffers. initial value: 0x0 read value: write-only write effect: modify value rr description: reset receive fifo. writing a 1 into this bit position resets the receive fifo. initial value: 0x0 read value: write-only write effect: modify value tr description: reset transmit fifo. writing a 1 into this bit position resets the transmit fifo. initial value: 0x0 read value: write-only write effect: modify value dms description: dma mode select. writing a 1 into this bit position changes the dma mode. the txrdy and rxrdy signals of the 16550 go to the interrupt controller as an interrupt source. (refer to indus- try standard 16550 uart specification.) 1 initial value: 0x0 read value: write-only write effect: modify value rt description: receiver trigger. this field designates the interrupt trigger level. when the number of bytes in the receive fifo equals the designated interrupt level, a receive data available interrupt is acti- vated. 0x0 1-byte in the receive buffer 0x1 4-bytes in the receive buffer 0x2 8-bytes in the receive buffer 0x3 14-bytes in the receive buffer initial value: 0x0 uart[0|1]fc 0 2 0 1 en 2 rt 1 rr 1 tr 1 dms 31 24 0
idt uart controller uart registers 79rc32438 user reference manual 13 - 9 november 4, 2002 notes line control register figure 13.7 uart [0|1] line control register (uart[0|1]lc) read value: write-only write effect: modify value 1. pc 16550d dual universal asynchronous receiver/transmitter with fifos , june 1995, national semiconductor . wls description: word length select. this field specifies the number of data bits in transmit and receive serial characters. 0x0 5-bits 0x1 6-bits 0x2 7-bits 0x3 8-bits initial value: 0x0 read value: previous value written write effect: modify value stb description: number of stop bits. this bit specifies the number of stop bits transmitted with each serial character. 0x0 one stop bit generated 0x1 5-bit word length: 1.5 stop bits generated. 6, 7 or 8-bit word length: 2 stop bits generated initial value: 0x0 read value: previous value written write effect: modify value pen description: parity enable. when this bit is set to 1, parity is generated on transmit data and checked on receive data. initial value: 0x0 read value: previous value written write effect: modify value eps description: even parity select. when parity is enabled and this bit is set to 1, an odd number of logic 1s is transmitted or checked. when parity is enabled and this bit is cleared, an even number of 1s is transmitted or checked. 0x1 even parity 0x0 odd parity initial value: 0x0 uart[0|1]lc 0 2 wls 1 stb 1 pen 1 eps 1 sp 1 sb 1 dlab 31 24 0
idt uart controller uart registers 79rc32438 user reference manual 13 - 10 november 4, 2002 notes modem control register figure 13.8 uart[0|1] modem control register (uart0mc) read value: previous value written write effect: modify value sp description: stick parity. when parity is enabled, this bit is used in conjunction with eps to select mark or space parity. initial value: 0x0 read value: previous value written write effect: modify value sb description: set break. when this bit is set to 1, a break is transmitted. initial value: 0x0 read value: previous value written write effect: modify value dlab description: divisor latch access bit. this bit must be set to access the divisor latches of the baud rate generator or the alternate functions register. when th is bit is cleared, access to other registers is enabled. initial value: 0x0 read value: previous value written write effect: modify value dtr description: data terminal ready. when this bit is set to 1, the dat a terminal ready output (uxdtrn) is asserted. initial value: 0x0 read value: previous value written write effect: modify value rts description: request to send. when this bit is set to 1, the reques t to send output (uxrtsn) is asserted. initial value: 0x0 read value: previous value written write effect: modify value uart0mc 0 1 o1 1 o2 1 lp 3 0 1 dtr 1 rts 31 24 0
idt uart controller uart registers 79rc32438 user reference manual 13 - 11 november 4, 2002 notes line status register figure 13.9 uart [0|1] line st atus register (uart[0|1]ls) o1 description: out 1. in local loopback mode this bit controls bit 2 of the modem status register. no connection to pin. initial value: 0x0 read value: previous value written write effect: modify value o2 description: out 2. in local loopback mode this bit controls bit 3 of the modem status register. no connection to pin. initial value: 0x0 read value: previous value written lp description: loop. this bit provides a local loopback feature for diagnostic testing of the associated serial channel. 0x0 loopback disabled 0x1 loopback enabled initial value: 0x0 read value: previous value written write effect: modify value dr description: data ready. this bit is set whenever a character has been received and may be read from the receive buffer. initial value: undefined read value: status write effect: modify value oe description: overrun error. this bit is set whenever a receiver overrun occurs. initial value: undefined read value: status write effect: modify value uart[0|1]ls 0 1 pe 1 fe 1 bi 1 dr 1 oe 1 thr 1 te 1 rfe 31 24 0
idt uart controller uart registers 79rc32438 user reference manual 13 - 12 november 4, 2002 notes pe description: parity error. this bit is set when a character with incorrect parity is received. initial value: undefined read value: status write effect: modify value fe description: framing error. this bit is set whenever a received character does not have a valid stop bit. initial value: undefined read value: status write effect: modify value bi description: break interrupt. this bit is set when a break is received. initial value: undefined read value: status write effect: modify value thr description: transmitter holding register. this bit is set to indicate that the serial channel is ready to accept a new character for transmission. initial value: undefined read value: status write effect: read-only te description: transmitter empty. this bit is set when both the transmitter holding register and the transmitter shift register are empty. initial value: undefined read value: status write effect: modify value rfe description: receive fifo error. this bit is set when there is a character with a parity error or a framing error, or there is a break indication in the fifo. initial value: undefined read value: status write effect: read-only
idt uart controller uart registers 79rc32438 user reference manual 13 - 13 november 4, 2002 notes modem status register figure 13.10 uart[0|1] modem status register (uart0ms) dcts description: delta clear to send. when this bit is set to 1, it indicates that the clear to send input has changed since the last time it was read by the cpu. initial value: undefined read value: status write effect: modify value ddsr description: delta data set ready. when this bit is set to 1, it indicates that the data set ready input has changed since the last time it was read by the cpu. initial value: undefined read value: status write effect: modify value teri description: trailing edge ring indicator. this bit is set when the ring indicator input changes from a low to a high state. initial value: undefined read value: status write effect: modify value ddcd description: delta data carrier detect. when this bit is set to 1, it indicates that the data carrier detect input has changed since the last time it was read by the cpu. initial value: undefined read value: status write effect: modify value cts description: clear to send. this bit is the complement of the clear to send (uxctsn) input. initial value: undefined read value: status write effect: read-only dsr description: data set ready. this bit is the complement of the data set ready (uxdsrn) input. uart0ms 0 1 teri 1 ddcd 1 cts 1 dcts 1 ddsr 1 dsr 1 ri 1 dcd 31 24 0
idt uart controller uart registers 79rc32438 user reference manual 13 - 14 november 4, 2002 notes scratch register figure 13.11 uart [0|1] scratch register (uart[0|1]s) divisor latch low register figure 13.12 uart [0|1] divisor latch low regist er (uart[0|1]dll) initial value: undefined read value: status write effect: read-only ri description: ring indicator. the bit is the complement of the ring indicator (u0rin) input for uart channel 0. uart channel 1 does not implement a ring indicator input. thus, this field is undefined for uart channel 1. initial value: undefined read value: status write effect: read-only dcd description: data carrier detect. this bit is the complement of the data carrier detect (u0dcrn) input for uart channel 0. uart channel 1 does not implement a data carrier detect input. thus, this field is undefined for uart channel 1. initial value: undefined read value: status write effect: read-only data description: data. this register may be used by the programmer to hold temporary data and does not con- trol the serial channel in any way. initial value: undefined read value: previous value written write effect: modify value uart[0|1]s 0 8 data 31 24 0 uart[0|1]dll 0 8 data 31 24 0
idt uart controller uart registers 79rc32438 user reference manual 13 - 15 november 4, 2002 notes divisor latch high register figure 13.13 uart [0|1] divisor la tch high register (uart[0|1]dlh) data description: data. this field contains the lower 8-bits of the 16-bit baud rate divisor. see table 13.3 for addi- tional baud rate information. initial value: undefined read value: previous value written write effect: modify value data description: data. this field contains the upper 8-bits of the 16-bit baud rate divisor. see table 13.3 for additional baud rate information. initial value: undefined read value: previous value written write effect: modify value uart[0|1]dlh 0 8 data 31 24 0
idt uart controller uart registers 79rc32438 user reference manual 13 - 16 november 4, 2002 notes
notes 79rc32438 user reference manual 14 - 1 november 4, 2002 chapter 14 counter/timers functional overview the rc32438 contains three general purpose 32-bit counter/timers that operate at the ipbus clock (iclk) frequency. each timer/counter is com posed of three registers: ? the count register, which is a 32- bit register that holds the curr ent value of timers. it is incre- mented on every clock iclk clock cycle. ? the compare register, which is a 32- bit register that holds the value to which the count register is compared. ? the control register, which holds the stat us and control information of the counter. counter/timers register description theory of operation a counter timer is enabled by setting the enable bit (en) in the corresponding counter timer [0|1|2] control (ctc[0|1|2]) register. when this occurs, t he counter timer begins incr ementing its current counter timer count value with each ipbus (iclk) clock c ycle. the cpu may determine the current timer count value by reading the corresponding c ounter timer [0|1|2] count (count[0 |1|2]) register. writing to this register modifies the counter timer count value. for normal operation, th is register should be initialized to zero prior to enabling a counter timer. register offset register name register function size 0x02_8000 count0 counter timer 0 count 32-bit 0x02_8004 compare0 counter timer 0 compare 32-bit 0x02_8008 ctc0 counter timer 0 control 32-bit 0x02_800c count1 counter timer 1 count 32-bit 0x02_8010 compare1 counter timer 1 compare 32-bit 0x02_8014 ctc1 counter timer 1 control 32-bit 0x02_8018 count2 counter timer 2 count 32-bit 0x02_801c compare2 counter timer 2 compare 32-bit 0x02_8020 ctc2 counter timer 2 control 32-bit 0x02_8024 rcount refresh timer count 32-bit 0x02_8028 rcompare refresh timer compare 32-bit 0x02_802c rtc refresh timer control 32-bit 0x02_8030 through 0x02_ffff reserved
idt counter/timers theory of operation 79rc32438 user reference manual 14 - 2 november 4, 2002 notes when the counter timer count value matches the value in the corresponding counter timer [0|1|2] compare register (compare[0|1|2]), the timer expires 1 . when this occurs: the time-out (to) bit in ctcx register is set, the counter timer count value is re set to zero, and the counter begins incrementing at the master clock frequency. the to bit is presented as an in terrupt source to the interrupt controller. the oper- ation of the timer/counter can be stopped at any time by writing 0 to the enable bit [en]. counter timer [0|1|2] count register figure 14.1 counter timer [0|1|2 ] count register (count[0|1|2]) counter timer [0|1|2] compare register figure 14.2 counter timer [0|1|2] compare register (compare[0|1|2]) 1. the counter timer expires at the point when the value in the countx register first equals the value in the comparex register (that is, countx == comparex) or when the counter timer is first enabled with countx equal to comparex. count description: current count. this field contains the current counter timer count value. initial value: 0x0000_0000 read value: current counter timer count value write effect: set counter timer count value compare description: compare value. this 32-bit field contains the maximum counter timer count value. when the value in the corresponding countx register equals this value, the counter timer expires. initial value: 0xffff_ffff read value: previous value written write effect: modify value count[0|1|2] 0 31 32 count compare[0|1|2] 0 31 32 compare
idt counter/timers theory of operation 79rc32438 user reference manual 14 - 3 november 4, 2002 notes counter timer [0|1|2] control register figure 14.3 counter timer [0|1|2 ] control register (ctc[0|1|2]) en description: enable. when this bit is set the counter timer is enabled. clearing this bit disables the counter timer. neither enabling nor disabling the counter timer affects the counter timer count value. initial value: 0x0 read value: previous value written write effect: modify value to description: time-out. this bit is set to a one to indicate that the counter timer has expired. once this bit is set, it will remain set until a zero is written into this field. writing 0 to this value will to clear the source of the interrupt. initial value: 0x0 read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) ctc[0|1|2] 0 31 30 0to en 11
idt counter/timers theory of operation 79rc32438 user reference manual 14 - 4 november 4, 2002 notes
notes 79rc32438 user reference manual 15 - 1 november 4, 2002 chapter 15 i 2 c bus interface introduction this chapter describes the standard i 2 c bus interface that is implemented on the rc32438 device. the i 2 c bus interface allows the rc32438 device to connect to a number of standard ex ternal peripherals. the i 2 c implementation on the rc32438 device supports both master and slave operations, allowing it to be used in a variety of applications. features ? supports standard 100 kbps mode as well as 400 kbps fast mode ? supports 7-bit and 10-bit addressing ? supports four modes: ? master transmitter ? master receiver ? slave transmitter ?slave receiver block diagram figure 15.1 i 2 c bus interface block diagram functional overview an d theory of operation the rc32438 contains an i 2 c bus interface and supports both master and slave modes. 1 figure 15.1 shows a block diagram of the i 2 c bus interface. the interface has three major components: ?i 2 c bus master interface ?i 2 c bus slave interface ?i 2 c bus interface common logic. the i 2 c bus interface connects to an external i 2 c bus using two pins: an i 2 c bus clock pin (scl), and an i 2 c bus data pin (sda). the i 2 c bus interface is controlled by the i 2 c bus control (i2cc) register. if the bus prescalar clock is running, setting the master enabl e (men) bit in this register enables the i 2 c bus master interface. likewise, if the bus pr escalar clock is running, setting t he slave enable (sen) bit enables the i 2 c bus slave interface.the i 2 c bus interface contains a 16-bit cloc k prescalar which is used to generate an 1. for a reference work on the i 2 c bus, see the i 2 c-bus specification, version 2.0 , december 1998, philips semi- conductor. ip bus i 2 c bus master interface i 2 c bus slave interface sda scl i 2 c bus interface common logic
idt i2c bus interface i2c register description 79rc32438 user reference manual 15 - 2 november 4, 2002 notes internal i 2 c bus prescalar clock (i2cpclk) that is used as a time base by the master and slave inter- faces. 2 the internally generated i 2 c bus prescalar clock is equal to t he ipbus clock input divided by the clock prescalar divisor (div) field in the i 2 c bus clock prescalar (i2ccp) register. 2 the master and slave interfaces may be independently enabled and disabled at any point in time, 2 allowing the interface to operate as an i 2 c bus master, an i 2 c bus slave, or concurrently as master and slave. 2 when configured to operate concurrently as a master and slave, it is possible for the master inter- face to initiate transactions to the slave interface 2 (that is, 2 it is possible to perform loop-back operations). 2 a central part of the i 2 c bus interface common logic is the i 2 c bus data input (i2cdi) and i 2 c bus data output (i2cdo) registers. 2 the i2cdi register is used by both the master and slave interfaces to receive data from the i 2 c bus. during the data phase of any i 2 c bus operation, data present on the sda pin is shifted into this register. thus, at the end of each i 2 c bus data transfer, this regi ster contains the data byte present on the i 2 c bus. data to be driven onto the i 2 c bus is written to i2cdo register by the cpu. during the data phase of an i 2 c bus transmit operation, the contents of this register are shifted out a bit at a time on the sda pin. 2 i 2 c register description i 2 c bus control register figure 15.2 i 2 c bus control register (i2cc) register offset register name register function size 0x7_0000 i2cc i 2 c bus control 32-bit 0x7_0004 i2cdi i 2 c bus data input 32-bit 0x7_0008 i2cdo i 2 c bus data output 32-bit 0x7_000c i2ccp i 2 c bus clock prescalar 32-bit 0x7_0010 i2cmcmd i 2 c bus master command 32-bit 0x7_0014 i2cms i 2 c bus master status 32-bit 0x7_0018 i2cmsm i 2 c bus master status mask 32-bit 0x7_001c i2css i 2 c bus slave status 32-bit 0x7_0020 i2cssm i 2 c bus slave status mask 32-bit 0x7_0024 i2csaddr i 2 c bus slave address 32-bit 0x7_0028 i2csack i 2 c bus slave acknowledge 32-bit 0x7_002c through 0x7_7fff reserved table 15.1 i2c register map i2cc 0 31 men 0 29 1 sen 1 iom 1
idt i2c bus interface i2c register description 79rc32438 user reference manual 15 - 3 november 4, 2002 notes i 2 c bus data input register figure 15.3 i 2 c bus data input register (i2cdi) men description: master enable. when the bus prescalar clock is running and this bit is set, the i 2 c bus master interface is enabled. when this bit is cleared, the i 2 c bus master interface is disabled and all commands written to the i2cmcmd register are ignored. when disabled, the slc and sda pins are tri-stated by the i 2 c bus master interface. disabling and then enabling the master interface causes all logic associated with the master interface to be reset. initial value: 0x0 read value: previous value written write effect: modify value sen description: slave enable. when the bus prescalar clock is running and this bit is set, the i 2 c bus slave inter- face is enabled. when this bit is cleared, the slave is disabled. when disabled, the slave does not respond to any operations and the slc and sda pins are tri-stated. disabling and then enabling the slave interface causes all logic associated with the slave interface to be reset. initial value: 0x0 read value: previous value written write effect: modify value iom description: ignore other masters. when this bit is set, the i 2 c bus master interface will arbitrate for the i 2 c bus but will assume that it always wins arbitration. this mode is used for testing and may be set in single master systems. when this bit is cleared, the i 2 c bus master will arbitrate for the i 2 c bus, as outlined in the i 2 c- bus specification, version 2.0 , december 1998, philips semiconductor. initial value: 0x0 read value: previous value written write effect: modify value data description: data. this field is used to receive data from the i 2 c bus and always contains the last byte present on the i 2 c bus. the most significant bit of this field contains the first bit received from the i 2 c bus. initial value: undefined i2cdi 0 31 data 0 24 8
idt i2c bus interface i2c bus clock prescalar 79rc32438 user reference manual 15 - 4 november 4, 2002 notes i 2 c bus data output register figure 15.4 i 2 c bus data output register (i2cdo) i 2 c bus clock prescalar the i 2 c bus interface contains a 16-bit clock presca lar which is used to generate an internal i 2 c bus prescalar clock (i2cpclk) that is used as a time base by the master and slave interfaces. 2 the internally generated i 2 c bus prescalar clock is equal to the ipbus cl ock frequency (iclk) divi ded by the clock pres- calar divisor (div) field in the i 2 c bus clock prescalar (i2ccp) register. the generated clock may not be symmetric, but is guaranteed to meet i 2 c bus tolerances. the i 2 c bus prescalar clock is stopped and the master and slave interfaces are held in reset w hen the div field is set to zero or one. 2 2 the i 2 c bus interface operates at the i 2 c bus prescalar clock divided by eight. therefore, the i 2 c data transfer rate may be calculated as follows: 2 i 2 c transfer rate = iclk i2ccp 8 figure 15.5 i 2 c bus clock prescalar register (i2ccp) read value: previous value received from i 2 c bus write effect: read-only data description: data. this field is used to transmit data onto the i 2 c bus. during i 2 c bus transmit operations the first bit to be transmitted is in the most significant bit of this field. initial value: undefined read value: previous value written write effect: modify value i2cdo 0 31 data 0 24 8 i2ccp 0 31 div 0 16 16
idt i2c bus interface i2c bus master interface 79rc32438 user reference manual 15 - 5 november 4, 2002 notes i 2 c bus master interface the i 2 c bus master interface operates by having the cpu issue commands to the i 2 c bus master command (i2cmcmd) register and obtaining status from the i 2 c bus master status register (i2cms). all of the bits in the i2cms register, which are not masked by the i 2 c bus master status mask (i2cmsm) register, are ored together and presented as the i 2 c bus master interface interrupt. i 2 c bus master commands are summarized in table 15.2. 2 each command in this table consists of a simple action performed on the i 2 c bus. commands may be composed sequentially to perform complex i 2 c bus transactions. 2 div description: clock prescalar divisor. the internally generated i 2 c bus prescalar clock is equal to the ipbus clock divided by the div field. the i 2 c data transfer rate may be calculated as follows: i2c transfer rate = ipbus clock frequency i2ccp 8 when the div field is equal to zero or one, the i 2 c bus prescalar clock is stopped, and both the master and slave interfaces are held in reset. starting or stopping the clock always occurs cleanly, but the clock may glitch when the period is modified. therefore, the clock should be stopped before modifying the period. initial value: 0x0 read value: previous value written write effect: modify value command encoding mnemonic description 0000 nop no operation . release i 2 c bus and put master transmitter into idle state. when this command is issued the sda and scl signals are tri-stated. this command completes when a new command is written to the i2cmcmd register. 0001 start start . wait for any alternate bus master transaction to complete, then generate a start condition on the i 2 c bus. when this command completes the d bit is set. for more information on the d bit, refer to the i2c bus master status register section later in this chapter. 0010 stop stop . generate a stop condition on the i 2 c bus. when this command com- pletes, the d bit is set. unlike other commands which suspend the i 2 c bus when the d bit is set, the completion of the stop command sets the 2 d bit but does not suspend the i 2 c bus. the completion of the stop command is automatically fol- lowed by a nop command. 0011 reserved same effect as nop. 0100 rd read data . receive 8-bits of data from the i 2 c bus and store it in the i2cdi reg- ister. when this command completes the d bit is set and the na, la, and err status bits are valid. 0101 rdack read data and acknowledge . receive 8-bits of data from the i 2 c bus and store it in the i2cdi register. after data has been received, generate an acknowledge. when this command completes the d bit is set and the na, la, and err status bits are valid. table 15.2 i2c bus master interface commands (part 1 of 2)
idt i2c bus interface i2c bus master interface 79rc32438 user reference manual 15 - 6 november 4, 2002 notes the i 2 c bus scl and sda signals are wired-and, allowi ng the clock signal to be used as a synchroni- zation mechanism. a device on the i 2 c bus can slow down, or stop, the i 2 c bus clock at any point by extending the low period of the clock. 2 this can be done after each bit, or after a complete operation is performed. 2 thus, the speed of the master is automatically adapted to the operating rate of the slowest device. this is illustrated in figure 15.6. 2 figure 15.6 using the i 2 c bus clock (scl) to adapt the operating rate when a command is written to the i2cmcmd regist er, the specified action is initiated on the i 2 c bus. for commands other than nop, this consists of generating the i 2 c bus clock (scl) and pos sibly driving the i 2 c bus data pin (sda). 2 the completion of the command is signaled to the cpu by setting the done (d) bit in the i2cms register. 2 depending on the command, other status bits in this register may also become valid. 2 when the done bit is set, the master interface hol ds the scl signal low, allowing the cpu core to respond to the received status information and issue the next command 1 . all of the status bits in the i2cms register, 2 including the done bit, 2 are automatically cleared and scl si gnal is released when a command is written to the i2cmcmd 2 register. 2 the 2 read data (rd), read data with acknowledge (r dack), write data (wd), and write data with acknowledge (wdack) commands all participate in i 2 c bus arbitration. when one of these commands is issued, the master interface observes the state of sda. arbitration is lost when a master i 2 c bus interfaces transmits a high value but observes a low value on the sda signal. when this occurs the master i 2 c bus 0110 wd write data . transmit 8-bits of data from the i2cdo register onto the i 2 c bus. when this command completes the d bit is set and the na, la, and err status bits are valid. 0111 wdack write data and acknowledge. (thi s command is for debug purposes only.) transmit 8-bits of data from the i2cdo register onto the i 2 c bus. after the data has been transmitted, generate an acknowledge. when this command com- pletes the d bit is set and the na, la, and err status bits are valid. 1000 through 1111 reserved same effect as nop. 1. this is true for all commands except the stop command. at the completion of the stop command, the d bit is set, the i 2 c bus is released by tri-stating the sda and scl signals, and the master goes into an idle state. command encoding mnemonic description table 15.2 i2c bus master interface commands (part 2 of 2) i2cpclk scl 1 5 6 1. a slave becomes not-ready, so it pulls scl low. since scl is wired-and, it is held low as long as the slave is not-ready. the i 2 c bus master is suspended. 2. slave becomes ready and releases scl. this allows the clock to progress. 3. a device may pull scl low even before i2cpclk (the internally generated i 2 c bus prescalar clock) goes low. this may occur for example during i 2 c bus arbitration when multiple masters drive the bus. 4. an external device can release scl at any point. the master interface must make sure that ?runt? clocks are not gener- ated which have a period smaller than that programmed in the i2ccp register. this may mean that the master interface stretches the clock and waits for the next rising edge of i2cpclk. 5. a slave becomes not-ready. 6. a slave becomes ready. 2 3 4
idt i2c bus interface i2c bus master interface 79rc32438 user reference manual 15 - 7 november 4, 2002 notes interface sets the lost arbitration (la) and the done (d) 2 bits in the i2cms register and tri-states the scl and sda signals. 2 the master interface does not automatically re-execute commands for which arbitration is lost; it is the responsibility of the 2 software driver to notice that the la bit is set and re-execute the command. 2 arbitration may be lost while executing t he wd and wdack commands when the 8-bit data quantity is driven on the bus, or during transmission of acknowledgment status. 2 for the rd and rdack commands, arbitration may only be lost duri ng transmission of acknowledgment status. 2 arbitration is lost during the acknowledgment status phase of a command when the i 2 c bus master reports not acknowledge (that is, a logic high) while another i 2 c bus master reports an acknow ledge (that is, a logic low). at the completion of each rd, rdack, wd, and wdack command, the status of the acknowledgment is reported in the no acknowledge (n a) bit of the i2cms register. 2 the error (err) bit in the i2cms register is set whenever an unexpected i 2 c bus start or stop condition is det ected during execution of a command by the i 2 c bus master interface. when this occurs, the master interface immediately sets the d and err bits in the i2cms register, and tr i-states both the scl and sda signals. 2 example i 2 c bus transactions this section illustrates how the i 2 c bus master interface commands shown in table 15.3 may be composed by the cpu to generate complete i 2 c bus transactions. table 15. 3 shows abbreviations used by figures in this section. .2 2 figure 15.7 shows a master transmitter transac tion to a slave with a 7-bit slave address. 2 at the comple- tion of the previous transaction issued by the master interface, 2 or immediately follow ing the enabling of the master interface, a nop command was issued. 2 this caused the master interface to tri-state the scl and sda signals. 2 to begin a transaction, the cpu writes the start command to the i2cmcmd register. this causes the i 2 c bus master interface to wait for any transac tion in progress by an alternate bus master to complete, and for a start condition to be driven on the i 2 c bus. once the start condition has been gener- ated, the command stops causing the 2 d bit in the i2cms register to be set and stops causing the master interface to suspend the i 2 c bus by holding the scl signal low until the next command is written to the i2cmcmd register. 2 abbreviation explanation s start condition sla7 7-bit slave address sla10 8-bits of 10-bit slave address r read bit (high on sda) w write bit (low on sda) a acknowledge bit (low on sda) a not acknowledge bit (high on sda) data 8-bit data byte p stop condition table 15.3 i 2 c bus data transfer abbreviations
idt i2c bus interface i2c bus master interface 79rc32438 user reference manual 15 - 8 november 4, 2002 notes figure 15.7 master operation: master transmi tter addressing a slave receiver (7-bit address) at the completion of the start command, the cpu in itializes the i2cdo register with an 8-bit data quan- tity which consists of the 7-bit slav e address and a read/write bit set to write. 2 the cpu then writes the transfer data (wd) command to the i2cmcmd register. 2 this causes the master interface to release the i 2 c bus and drive the slave addr ess and write bit onto the i 2 c bus. the addressed slave device indicates that it can accept data by generating an acknowledge. 2 at the completion of the wd command, the d bit is set in the i2cms register and the master interface suspends the i 2 c bus. in addition to the d bit being set, the i2cms register contains additional status information. 2 the na bit is cleared if a slave generated an acknowledge. 2 the la bit is set if the master interface lo st an arbitration with an alternate bus master. finally, the err bit is set if an unexpected start or stop condition was detected on the i 2 c bus during execu- tion of the command. 2 continuing the example shown in fi gure 15.7, the cpu transmits data to the addressed slave by writing the 8-bit data quantity to be transmitted to t he i2cdo register and issuing a wd command. 2 at the comple- tion of each command, the status bits in the i2cms register become valid and the i 2 c bus is suspended until the next command is issued. 2 when the cpu wishes to end the transaction because it has no more data to transmit, or because no acknowledgment was observed, 2 it issues a stop command. 2 this causes a stop condition to be driven on the i 2 c bus. when the command completes, the done bit in the i2cms register is set. at this point, the cpu may begin a new transaction. 2 figure 15.8 shows a master receiver transaction to a slave with a 7-bit slave address. the transaction is similar to the master tr ansmitter transaction shown 2 in figure 15.7 except that data is driven by the slave. 2 to transfer data the cpu issues an rdack command. 2 this causes the master interface to issue clock pulses on the scl signal and the slave transmitter to drive data on the sda signal. 2 the data driven by the slave transmitter is shi fted into the i2cdi register. 2 after the data has been transferred, the master interface generates an acknowledge. 2 this completes the command, causing the d bit to be set, status information in the i2cs register to be valid, and the master interface to suspend the i 2 c bus. the rdack command will always cause the na status bit to be cleared. 2 the master interface signals the end of data to the slave transmitter by not generating an acknowledge. 2 this is done by issuing an rd command rather than an rdack command. 2 figure 15.8 master operation: master receive r addressing a slave transmitter (7-bit address) s sla7 nop start wd w a status: d status: d data a status: d wd wd data a p status: d na stop status: d nop idle bus from master to slave bus suspended by master from slave to master s sla7 nop start wd r a status: d status: d data a status: d rdack rd data a p status: d na stop status: d nop idle bus from master to slave bus suspended by master from slave to master
idt i2c bus interface i2c bus master interface 79rc32438 user reference manual 15 - 9 november 4, 2002 notes a repeated start condition allows a mast er to begin a new transaction on the i 2 c bus without relin- quishing control of the bus. 2 thus, rather than generating a stop condit ion at the end of a transaction, the master generates a start condition and addresses a slave. 2 as shown in figure 15.9, master interface commands may be composed to g enerate a repeated start condition. 2 figure 15.9 master operation: master in terface initiated repeated start condition the i 2 c bus has been extended to support 10-bit slave addressing. as shown in figure 15.10, the master interface commands listed in table 15. 2 may be used to address 10-bit slave devices. 2 following an initial start command, 2 the cpu issues a wd command with the i2 cdo register initialized with the bit address 0b11110xx and the read/write bit set to write. 2 the x?s in the address 0b 11110xx represent the two high order bits of t he 10-bit slave address. 2 more than one slave may match this address, and may thus cpu next issues a wd command, 2 with the low order 8-bits of the 10-bit slave address. 2 only one slave will find a match and generate an acknowledge. at this point the cpu can write data to the addressed slave receiver. 2 if the cpu wants to read data from a 10-bit slave receiver, it must issue a repeated start 2 condition followed by a wd command with the slave address equal to 0b 11110xx as before, but this time with the read/write bit set to read. 2 the matching slave remembers that it was addressed before. 2 this slave checks if the address after the repeated start condition is the same as in the previous transaction and tests if the read/write bit is set to read. 2 if there is a match, the slave declares that it has been addressed as a 10-bit slave tr ansmitter and generates an acknowledge. 2 the cpu is then free to read from the slave 2 using rdack and rd commands as shown in figure 15.8. 2 figure 15.10 master operation: address ing a 10-bit slave as a slave transmitter i 2 c bus master command register figure 15.11 i 2 c bus master command register (i2cmcmd) s sla7 start wd r a status: d status: d rd data a status: d na idle bus from master to slave bus suspended by master from slave to master s sla7 start wd w a status: d status: d data wd s sla7 start wd w a status: d status: d wd status: d idle bus from master to slave bus suspended by master from slave to master s sla7 start wd r a status: d status: d data rdack sla10 a i2cmcmd 0 31 cmd 0 28 4
idt i2c bus interface i2c bus master interface 79rc32438 user reference manual 15 - 10 november 4, 2002 notes i 2 c bus master status register figure 15.12 i 2 c bus master status register (i2cms) cmd description: command. when a value is written into this field, the corresponding command is initiated on the i 2 c bus. completion of the command is signalled when the done (d) bit in the i2cms register is set. initial value: 0x0 (nop) read value: previous command write effect: initiate command on i 2 c bus d description: done. this bit is set when the command written to the i2cmcmd register has been completed and the remaining status bits in this register are valid. at the completion of each command except stop, the i 2 c bus scl signal is held in a low state. this bit is automatically cleared when a com- mand is written to the i2cmcmd register. initial value: 0x0 read value: status write effect: read-only na description: no acknowledge. at the completion of each data transfer initiated by the i 2 c bus master inter- face, if there was a ?no acknowledge? signal, this bit is set to one. if there was an ?acknowledge? signal, this bit is cleared to zero. the absence or presence of the acknowledge signal is recorded in this bit whether the acknowledge signal comes from the i 2 c bus master interface or an external slave. this bit is automatically cleared when a command is written to the i2cmcmd register. initial value: undefined read value: status write effect: read-only la description: lost arbitration. arbitration takes place during each byte transmitted by the i 2 c bus master inter- face. if the i 2 c bus master interface transmits a high level during a bit period while another mas- ter transmits a low level, then the i 2 c bus master interface has lost arbitration. when this occurs, this bit is set and the i 2 c bus master interface tri-states the slc pin for the remainder of the byte transfer. this bit is automatically cleared when a command is written to the i2cmcmd register. initial value: undefined read value: status write effect: read-only i2cms 0 31 d 0 28 1 na 1 la 1 err 1
idt i2c bus interface i2c bus master interface 79rc32438 user reference manual 15 - 11 november 4, 2002 notes i 2 c bus master status mask register figure 15.13 i 2 c bus master status mask register (i2cmsm) err description: error. this bit is set if a misplaced start or stop condition is detected during execution of a command by the i 2 c bus master interface. this bit is automatically cleared when a command is written to the i2cmcmd register. initial value: undefined read value: status write effect: read-only d description: done. when this bit is set, the d bit in the i2cms register is masked from generating an interrupt. initial value: 0x1 read value: previous value written write effect: modify value na description: no acknowledge. when this bit is set, the na bit in the i2cms register is masked from generat- ing an interrupt. initial value: 0x1 read value: previous value written write effect: modify value la description: lost arbitration. when this bit is set, the la bit in the i2cms register is masked from generating an interrupt. initial value: 0x1 read value: previous value written write effect: modify value err description: error. when this bit is set, the err bit in the i2 cms register is masked from generating an inter- rupt. initial value: 0x1 read value: previous value written write effect: modify value i2cmsm 0 31 d 0 28 1 na 1 la 1 err 1
idt i2c bus interface i2c bus slave interface 79rc32438 user reference manual 15 - 12 november 4, 2002 notes i 2 c bus slave interface the i 2 c bus slave interface operates by monitoring the state of the i 2 c bus and suspending the i 2 c bus clock at points where cpu intervention is required. status is reported in the i 2 c bus slave status (i2css) register. all of the bits in this re gister which are not masked by the i 2 c bus slave status mask (i2cssm) register are ored together and presented to the interrupt controller as the i 2 c bus slave interface interrupt. the i 2 c bus is suspended by the slave interface when any of the following bits: read request (rr), write request (wr), or slave addressed (sa) bits in the i2css register are set. 2 the slave interface releases the i 2 c bus when the these bits are cleared by the cpu. the i 2 c bus slave acknowledge (i2csack) register controls how the slave interface responds during acknowledgment phases on the i 2 c bus. if the acknowledge (ack) bit is se t in this register and the slave is addressed, then the slave respon ds with an acknowledge during i 2 c bus acknowledgment phases. other- wise, the slave tri-states the sda pi n during acknowledgment phases (that is, 2 it issues a ?no acknowl- edge?). 2 the i 2 c bus slave interface may be configured to operat e with either a 7-bit or a 10-bit slave address. when the a10 bit is set in the i 2 c bus slave address (i2csaddr) regist er, the slave interface operates using the 10-bit slave address in the address (addr) field of the i2csaddr register. 2 when the a10 bit is cleared, the slave interface operates using the addr ess in the bottom 7-bits of the addr field. 2 the general call enable (gce) bit in the i2csaddr register contro ls whether the slave interface responds to the i 2 c bus general call address. 2 if the gce bit is set, the slave interf ace responds to both the address in the addr field and the general call address. a genera l call address is one in which the 7-bit i 2 c bus address is bit address 0b0000000 and the read/write bit is set to write (that is, low). 2 a general call transaction is similar to a master transmitter tr ansaction in its operation. 2 an i 2 c bus master may generate start byte transactions to allow a microcontroller sampling at a slow sampling rate to detect a start condition 2 a start byte transaction consists of a start condition followed by a 7-bit address equal to 0b0000000 and with the r ead/write bit set to read (that is, high). 2 this is then followed by another start condition and a transac tion with the address of the act ual slave to be addressed. the i 2 c bus slave interface ignores all start byte transactions. 2 example of i 2 c bus transaction figure 15.14 shows a master transmitter transaction with a 7-bit slave address issued to the slave inter- face. 2 the master transmitter generates a st art condition followed by the 7-bit address of the slave and the read/write bit set to write. 2 the slave interface compares the address to the value in its addr field. if the address matches the bottom seven bits of this field 2 and the a10 bit is cleared, then the slave interface is addressed. when this occurs, the slave interface suspends the i 2 c bus and sets the slave addressed (sa) bit in the i2css register. if the address on the i 2 c bus was the general call address and the gce bit was set, then in addition to suspending the i 2 c bus and setting the sa bit, the slave interface sets the general call (gc) bit in the i2css register. 2 the setting of the sa bit indicates to the cpu the beginning of an i 2 c bus transaction addressed to the slave interface. 2 the cpu may examine the address and read/write bit driven by the master by reading the i2cdi register. 2 if the cpu wishes to acknowledge that it has been addressed, it sets the ack bit in the i2csack register. 2 when the cpu clears the sa bit it releases the i 2 c bus and allows the transaction to progress. 2
idt i2c bus interface i2c bus slave interface 79rc32438 user reference manual 15 - 13 november 4, 2002 notes figure 15.14 slave operation: master transmi tter addressing a slave receiver (7-bit address) the master transmitter then drives the 8- bit data quantity to be transmitted on the i 2 c bus. at the completion of the data transfer, the write request (wr) 2 bit in the i2css is set and the slave interface once again suspends the i 2 c bus. the na bit will be cleared to indicate that an acknowledge was observed in the previous acknowledgment phase in wh ich the slave interface was addressed. 2 the cpu may read the value transmitted by the master by reading the i2cdi register. 2 if the cpu wishes to acknowledge the data transfer, it sets the ack bit in the i2csack register. 2 when the cpu clears the wr bit it releases the i 2 c bus and allows the transaction to progress. 2 the master transmitter completes a transaction by generating a stop or repeated start condition. when this occurs while the slave is addressed, the transact ion finished (tf) bit in the i2css register is set. 2 this indicates to the cpu that the current transaction has completed. 2 if an unexpected start or stop condition is detected by the slave interface while it is addressed, 2 then the error (err) bit in the i2css register is set along with the tf bit thus aborting the current transaction. 2 figure 15.15 shows a master receiver transaction with a 7-bit slave address issued to the slave inter- face. after acknowledgment of the save address, the slave interface suspends the i 2 c bus and sets the read request (rr) bit in the i2css register. in response to 2 this bit being set, the cpu writes the 8-bit quan- tity to be transmitted to the master into the i2cdo register and clears the rr bit. 2 this releases the i 2 c bus and allows the data transfer to progress. at the completion of the data transfer the i 2 c bus is once again suspended and the rr bit is set. 2 the acknowledgment status from the master transmitter during the previous data transfer is reported in the na bit. 2 if the na bit is cleared and rr bit is set, the cpu writes the next 8-bit quantity to 2 be transmitted into the i2cdo register and clears the rr bit allowing the transfer to progress. otherwise, 2 if the na bit is set, the master rece iver did not acknowledge the previous data transfer. 2 this indicates the end of data transfer to the sl ave. the cpu clears the na and rr bits allowing the 2 master receiver to generate a stop or repeated start condition. after the stop or repeated start condition, the tf bit is set. 2 this indicates to the cpu that the transaction has completed. 2 figure 15.15 slave operation: master receiver addressing a slave transmitter (7-bit address) figure 15.16 shows a master receiver transaction to the slave interface us ing a 10-bit slave address. the master first generates a start condition followed by 2 a bit address of 0b11110xx and the read/write bit set to write. 2 the x?s in the bit address 0b 11110xx represent the high order two bits of the 10-bit slave address. if the a10 bit is set, the slave interface compares the 2 value in the x?s to the high order two bits of the addr field. if they match, the slave interface automatically generates an acknowledge. 2 the master s sla7 w a status: sa status: wr data a data a p idle bus from master to slave bus suspended by slave from slave to master status: wr status: tf na s sla7 r a status: sa status: rr data a status: rr data a p idle bus from master to slave bus suspended by slave from slave to master status: rr status: tf na
idt i2c bus interface i2c bus slave interface 79rc32438 user reference manual 15 - 14 november 4, 2002 notes then transmits the remaining 8-bi ts of the 10-bit slave address. 2 if these 8-bits match the bottom 8-bits of the addr field, then the slave interface suspends the i 2 c bus and sets the sa bit. at this point the slave is addressed as a slave receiver and the master may write data 2 to the slave interface using the same mecha- nism as shown in figure 15.14 fo r slaves with 7-bit addresses. 2 if the master wishes to read data from a 10- bit slave, it must issue a repeated start condition followed by 2 the same address 0b 11110xx as before, but this time with the read/write bit set to read. 2 the slave interface remembers that it was addressed in the previous transaction. it checks if the addre ss after the repeated start condition is the 2 same as it was in the previous transaction and tests if t he read/write bit is set to read. 2 if there is a match, the slave interface is addressed as a slave transmitter. it suspends the i 2 c bus and set the sa bit. from this point on the transac- tion is the same as that shown in figure 15. 15 for a slave transmitter with a 7-bit address. 2 figure 15.16 slave operation: addressing a 10-bit slave as a slave transmitter i 2 c bus slave status register figure 15.17 i 2 c bus slave status register (i2css) rr description: read request. this bit is set when a master initiates a read request of an 8-bit data quantity from the slave interface. the value to be returned to the master is written to the i2cdo register and this bit cleared. clearing the rr bit causes the slave interface to release the i 2 c bus. initial value: undefined read value: status write effect: clear to release i 2 c bus wr description: write request. this bit is set when a master initiates a write request of an 8-bit data quantity to the slave interface. the value transmitted by the master is written to the i2cdi register. once the value has been read by the cpu the wr bit is cleared. clearing this bit causes the slave inter- face to release the i 2 c bus. initial value: undefined read value: status write effect: clear to release i 2 c bus s sla7 w a idle bus from master to slave bus suspended by slave from slave to master s sla7 r a data sla10 a status: sa status: rr status: sa status: tf i2css 0 31 rr 0 25 1 wr 1 tf 1 na 1 err 1 sa 1 gc 1
idt i2c bus interface i2c bus slave interface 79rc32438 user reference manual 15 - 15 november 4, 2002 notes i 2 c bus slave status mask register figure 15.18 i 2 c bus slave status mask register (i2cssm) sa description: slave addressed. this bit is set when the slave interface determines that it has been addressed by an i 2 c bus master. this occurs when an address on the i 2 c bus matches that in the i2csaddr register, or when the general call address (zero) is observed and the gce bit is set in the i2csaddr register. clearing this bit causes the slave interface to release the i 2 c bus. initial value: undefined read value: status write effect: clear to release i 2 c bus tf description: transaction finished. this bit is set when the slave interface determines that it is no longer addressed by an i 2 c bus master. this occurs as the result of a stop or repeated start condition. initial value: undefined read value: status write effect: clear to release i 2 c bus gc description: general call. this bit is set when the slave interface observes a general call address on the i 2 c bus and the gce bit in the i2csaddr register is set. initial value: undefined read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) na description: no acknowledge. this bit reflects the state of the acknowledgment signal driven during the pre- vious i 2 c bus acknowledge phase in which the slave interface was addressed (that is, it reflects the value of the ack on the wire). initial value: undefined read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) err description: error. this bit is set when a start or stop condition is detected in an illegal position during a i 2 c bus transaction in which the slave interface is addressed. initial value: undefined read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) i2cssm 0 31 rr 0 25 1 wr 1 tf 1 na 1 err 1 sa 1 gc 1
idt i2c bus interface i2c bus slave interface 79rc32438 user reference manual 15 - 16 november 4, 2002 notes rr description: read request. when this bit is set to 1, the rr bit in the i2css register is masked from gener- ating an interrupt. initial value: 0x1 read value: previous value written write effect: modify value wr description: write request. when this bit is set to 1, the wr bit in the i2css register is masked from gener- ating an interrupt. initial value: 0x1 read value: previous value written write effect: modify value sa description: slave addressed. when this bit is set to 1, the sa bit in the i2css register is masked from gen- erating an interrupt. initial value: 0x1 read value: previous value written write effect: modify value tf description: transaction finished. when this bit is set to 1, the tf bit in the i2css register is masked from generating an interrupt. initial value: 0x1 read value: previous value written write effect: modify value gc description: general call. when this bit is set to 1, the gc bit in the i2css register is masked from generat- ing an interrupt. initial value: 0x1 read value: previous value written write effect: modify value na description: no acknowledge. when this bit is set to 1, the na bit in the i2css register is masked from gen- erating an interrupt. initial value: 0x1 read value: previous value written write effect: modify value
idt i2c bus interface i2c bus slave interface 79rc32438 user reference manual 15 - 17 november 4, 2002 notes i 2 c bus slave address register figure 15.19 i 2 c bus slave address register (i2csaddr) err description: error. when this bit is set to 1, the err bit in th e i2css register is masked from generating an interrupt. initial value: 0x1 read value: previous value written write effect: modify value addr description: slave address. this field contains the address of the i 2 c bus slave interface. when the a10 bit is set to 1, the slave interface is configured for a 10-bit address equal to the value in this field. when the a10 bit is cleared, the slave interface is configured for a 7-bit address equal to the value in the bottom seven bits of this field. initial value: undefined read value: previous value written write effect: modify value gc description: general call. when this bit is set to 1, the general call address (0x00) is recognized by the slave; otherwise it is ignored. initial value: undefined read value: previous value written write effect: modify value a10 description: 10-bit slave address. when this bit is set to 1, the slave interface is configured to use 10-bit addressing. in this mode, the ten bit addr field contains the address of the slave. when this bit is cleared, the slave interface is configured to use 7-bit addressing. in this mode, the bottom seven bits of the addr field contains the address of the slave. initial value: undefined read value: previous value written write effect: modify value i2csaddr 0 31 addr 0 20 10 gc 1 a10 1
idt i2c bus interface programming example 79rc32438 user reference manual 15 - 18 november 4, 2002 notes i 2 c bus slave acknowledge register figure 15.20 i 2 c bus slave acknowledge register (i2csack) programming example disclaimer: code examples provided by idt are for illustrative purposes only and should not be relied upon for developing applications. idt does not assume liability for any loss or damage that may result from the use of this code. /* ** this is an example to read/write an i2c eeprom ** using the rc32438 as a master and i2c eeprom as ** a slave.(microchip 24aa64/24lc64) ** ** note: every single variable used is not defined ** here. the emphasis is to get the hardware bit ** setting and the program flow across, and not the ** programming language syntax. the hardware register ** address and values are defined in the following ** header files as are the us ed c data structures. these ** header files can be obtained from idt. */ #include "s364-355.h" #include "i2c.h" unsigned int master_done; unsigned int slave_done; unsigned int num_master_data_bytes_txd; unsigned int num_master_data_bytes_rxd; ack description: acknowledge. when this bit is set to 1, the slave interface returns an acknowledge during the next i 2 c bus acknowledge phase in which the slave interface is addressed. when this bit is cleared, the slave interface returns a not acknowledge during the next i2c bus acknowledge phase in which the slave interface is addressed. initial value: undefined read value: previous value written write effect: modify value i2csack 0 31 ack 0 31 1
idt i2c bus interface programming example 79rc32438 user reference manual 15 - 19 november 4, 2002 notes unsigned int num_master_done_ints; unsigned int num_master_lost_arb_ints; unsigned int num_master_err_ints; unsigned int num_acks; unsigned int num_naks; void i2c_master_isr(void); ///////////////////////////////////////////////////////////////////////// // // handler for master isr // ///////////////////////////////////////////////////////////////////////// void i2c_master_isr (void) { unsigned int master_status; volatile unsigned char temp; printf("\nm isr - \n"); // read the master status regs master_status = i2c.i2cms; if (master_status & i2cms_err) { num_master_err_ints++; printf("\ni2c master err detected!\n"); } if (master_status & i2cms_d) { num_master_done_ints++; } if (master_status & i2cms_la) { num_master_lost_arb_ints++; printf ("\ni2c master la detected!\n"); } // master is done with the current operation. switch (master.state) { case master_idle: // no need to do anything... break; case master_start: // done sending start, begin sending address
idt i2c bus interface programming example 79rc32438 user reference manual 15 - 20 november 4, 2002 notes printf (" start done"); i2c.i2cdo = master.dest_addr[0]; i2c.i2cmcmd = i2cmcmd_cmd(wd); master.state = master_addr; break; case master_addr: printf (" addr done"); // count acks & naks - note, an ack occurs when the ack bit is cleared // (because sda is driven low) if (!(master_status & i2cms_ack)) num_acks++; else num_naks++; if (master_st atus & i2cms_ack) { // no slave acknowledged the address byte, so generate stop if desired if (master.stop_when_done) { i2c.i2cmcmd = i2cmcmd_cmd(stop); master.state = master_stop; } else { // no stop desired, so go to idle and set global variable master.state = master_idle; master_done = true; // mask all master interrupts i2c.i2cmsm = 0xffffffff; } break; } if (master.data_len == 0) { // data length is zero, so skip write / read stage if (master.stop_when_done) { i2c.i2cmcmd = i2cmcmd_cmd(stop); master.state = master_stop; } else { // no stop desired, so go to idle and set global variable master.state = master_idle; master_done = true;
idt i2c bus interface programming example 79rc32438 user reference manual 15 - 21 november 4, 2002 notes // mask all master interrupts i2c.i2cmsm = 0xffffffff; } break; } if (master.transfer_type == master_write) { // done sending address, now send data master.state = master_write_data; num_master_data_bytes_txd++; i2c.i2cdo = *master.data_ptr++; i2c.i2cmcmd = i2cmcmd_cmd(wd); } else { // done sending address, now read data master.state = master_read_data; if (num_master_data_byt es_rxd == (master.data_len - 1)) { // almost done reading data, now send rd (not rdack!) i2c.i2cmcmd = i2cmcmd_cmd(rd); } else { // read another data byte (and ack) i2c.i2cmcmd = i2cmcmd_cmd(rdack); } num_master_data_bytes_rxd++; } break; case master_write_data: printf(" wd done"); // count acks & naks - note, an ack occurs when the ack bit is cleared // (because sda is driven low) if (!(master_status & i2cms_ack)) num_acks++; else num_naks++; if (num_master_data_bytes_txd >= master.data_len) { // done sending data, now send stop if desired. if (master.stop_when_done) { i2c.i2cmcmd = i2cmcmd_cmd(stop);
idt i2c bus interface programming example 79rc32438 user reference manual 15 - 22 november 4, 2002 notes master.state = master_stop; } else { // no stop desired, so go to idle and set global variable master.state = master_idle; master_done = true; // mask all master interrupts i2c.i2cmsm = 0xffffffff; } } else { // send next data byte i2c.i2cdo = *master.data_ptr++; i2c.i2cmcmd = i2cmcmd_cmd(wd); num_master_data_bytes_txd++; } break; case master_read_data: // write incoming read data to buffer printf(" rd done"); *master.data_ptr = (unsigned char)i2c.i2cdi; master.data_ptr++; // count acks & naks - note, an ack occurs when the ack bit is cleared // (because sda is driven low) if (!(master_status & i2cms_ack)) num_acks++; else num_naks++; if (num_master_data_bytes_rxd >= master.data_len) { // done sending data, now send stop if desired. if (master.stop_when_done) { i2c.i2cmcmd = i2cmcmd_cmd(stop); master.state = master_stop; } else { // no stop desired, so go to idle and set global variable master.state = master_idle;
idt i2c bus interface programming example 79rc32438 user reference manual 15 - 23 november 4, 2002 notes master_done = true; // mask all master interrupts i2c.i2cmsm = 0xffffffff; } } else // almost done reading data, now send rd (not rdack!) if (num_master_data_byt es_rxd == (master.data_len - 1)) { // almost done reading data, now send rd (not rdack!) i2c.i2cmcmd = i2cmcmd_cmd(rd); } else { // read another data byte (and ack) i2c.i2cmcmd = i2cmcmd_cmd(rdack); } num_master_data_bytes_rxd++; break; case master_stop: // done with packet, set global variable, write nop command, and go to idle printf(" stop done"); // mask all master interrupts i2c.i2cmsm = 0xffffffff; master.state = master_idle; master_done = true; i2c.i2cmcmd = i2cmcmd_cmd(nop); break; default: printf ("\nerr in default\n"); break; } } void perform_rd_wr_eeprom (unsigned int transfer_type, unsigned int num_data_bytes, unsigned int dest_addr, unsigned int stop_when_done, ) { master.stop_when_done = stop_when_done;
idt i2c bus interface programming example 79rc32438 user reference manual 15 - 24 november 4, 2002 notes num_master_data_bytes_txd = 0; num_master_data_bytes_rxd = 0; master.data_len = num_data_bytes; master_done = false; master.transfer_type = transfer_type; master.state = master_idle; master_done = false; if (transfer_type == master_write) // master write master.dest_addr[0] = (unsig ned char)((dest_addr & 0x7f) << 1); else // master read master.dest_addr[0] = (unsigned char)(((dest_addr & 0x7f) << 1) | 0x1); // initialize slave address / slave control bits i2c.i2csaddr = 0x30; // initialize slave ack register i2c.i2csack = i2csack_ack; // update master state master.state = master_start; // kickoff master operation by writing command start to command reg. i2c.i2cmcmd = i2cmcmd_cmd(start); printf("start read i2c "); while (1) { if (master_done) break; // using polling! if((i2c.i2cms &~i2cms_ack) != 0) i2c_master_isr(); } } ///////////////////////////////////////////////////////////////////////// // // start // ///////////////////////////////////////////////////////////////////////// main()
idt i2c bus interface programming example 79rc32438 user reference manual 15 - 25 november 4, 2002 notes { unsigned int i; unsigned int slave_addr; unsigned int dest_addr; unsigned int divisor; unsigned int num_data_bytes; unsigned char data[1024]; unsigned int prescaler_value; // enable master & slave interfaces i2c.i2cc = i2cc_men; // make sure to mask all unused bits. // prescalar value is programmed for 800khz clock. prescaler_value = 84; i2c.i2ccp = prescaler_value; //i2c bus master status mask register is masked //from generating an interrrupt. i2c.i2cmsm = 0xf; //slave address is set here. slave_addr = 0x30; //i2c bus slave is masked from generating interrupt. i2c.i2cssm = 0x7f; num_data_bytes = 8; // the 1st and 2nd data byte is set to the address // where data is located within the i2c nvram. data[0] = 0; data[1] = 0; for (i = 2; i<8; i++) { data[i] = 0x33; } master.data_ptr = data; printf("\nwrite:"); perform_rd_wr_eep rom (master_write, // trans. type num_data_bytes,
idt i2c bus interface programming example 79rc32438 user reference manual 15 - 26 november 4, 2002 notes // # data bytes slave_addr, // dest. addr. true, // gen. stop when done ? ); // this write is performed to set the address // within i2c nvram to do random read. // the 1st and 2nd byte is the address from where you // want to read within the i2c eeprom. data[0] = 0; data[1] = 0; master.data_ptr = data; num_data_bytes = 2; printf("\nwrite:"); perform_rd_wr_eep rom (master_write, // trans. type num_data_bytes, // # data bytes slave_addr, // dest. addr. false, // gen. stop when done ? ); // initialize data for (i = 0; i<8; i++) { data[i] = 0x0; } master.data_ptr = data; num_data_bytes = 6; printf("\nread /rdack:"); perform_rd_wr_eeprom (master_read, // trans. type num_data_bytes, // # data bytes slave_addr,
idt i2c bus interface programming example 79rc32438 user reference manual 15 - 27 november 4, 2002 notes // dest. addr. true, ); for (i=0; i<6; i++){ if (data[i] != 0x33){ printf("\ndata failed location is %d data is %x\n", i, data[i]); } } }
idt i2c bus interface programming example 79rc32438 user reference manual 15 - 28 november 4, 2002 notes
notes 79rc32438 user reference manual 16 - 1 november 4, 2002 chapter 16 serial peripheral interface functional overview the serial peripheral interface (spi) included on t he rc32438 device supports an spi master interface allowing it to interface to low-cost spi peripherals and memory. the spi interface connects to an external spi device using three signals: ? sdo (serial data output) ? sdi (serial data input) ? sck (serial clock) additional spi functions, such as chip select and write protect, must be implemented by allocating a gpio pin for this purpose and managing the gpio pin?s behavior in software. block diagram figure 16.1 spi and pci serial eeproms interfacing pci serial eeprom and spi interfaces share comm on clock (sck), data input (sdi), and data output (sdo) pins. the behavior of these pins depends on the mode of operation. for detailed information on the pci bus interface, see chapter 10, pci bus interface. when the pci interface is configured to operate in pci satellite mode with suspended cpu execution, the pci interface drives the sck and sdo pins using the national microw ire serial protocol to read pci configuration information from the pci seri al eeprom. data is read in on the sdi pin. the chip select signal for the pci serial eeprom is active high. pcigntn[1] behaves as the pci serial eeprom chip select when the pci interface operates in pci satellite mode with suspended cpu execu- tion. initially, the pcigntn[1] si gnal is driven low following a reset. the signal is driven high when the pci interface begins reading c onfiguration information. microwire cs serial eeprom ck di do rc32438 spi cs serial eeprom sck di do spi cs serial eeprom sck di do pcigntn[1] sck sdo sdi gpio[x] gpio[y] (pci serial eeprom)
idt serial peripheral interface block diagram 79rc32438 user reference manual 16 - 2 november 4, 2002 notes when the pci interface completes reading configurati on information from the pci serial eeprom, it tri- states the sck and sdo pins and drives pcigntn[1] low (i.e., it negates the chip select). this allows the sck, sdo, and sdi pins to be used by the spi interface. after a reset, the spi interface is initially disabl ed. when the pci interface completes reading configura- tion information from the pci serial eeprom, the spi interface may be enabled by setting the spe bit in the spi control register. the spi interface may not be enabled before the pci serial eeprom has completed reading configuration information (i.e., bef ore the pci serial eeprom done (eed) bit is set in the pcis register). attempting to enable the spi interfac e while the interface is in use by the pci interface does not damage the rc32438 (i.e., no dual sourcing), bu t it does produce unpredictable results. when the pci mode is not pci satellite mode with suspended cpu execution, the spi interface may be enabled at any time since the pci interface w ill not read the pci serial eeprom. when the spi interface is enabled, it drives the sc and sdo pins. when an spi transaction is initiated by writing to the spi data register (spd), the sc k, sdo, and sdi signals are used to transfer data. a general purpose i/o pin must be used as the spi ch ip select, and this pin must be managed by software. in systems where multiple spi devices are requir ed, multiple general purpose i/o pins may be used as spi chip selects. in these scenarios, the gpio pins used as chip selects must be managed by software. in cases where the spi interface is not enabled, the serial i/o pins are not used as bit i/o ports and the sck, sdo, and sdi pins are tri-stated after the loading of configuration in formation is complete. pull-ups or pull-downs are necessary on the board. (refer to the second to the last row in table 16.1.) when the spie bit is set in the spc register, the spi interrupts are enabled. an spi interrupt is gener- ated when the modf or spif bits are set in the sps register. pci satellite mode pci serial eeprom loading complete 1 1. pci serial eeprom loading only occurs in pci satellite mode with suspended execution. in pci satellite mode with pci target not ready, the pci serial eeprom loading is effectively always completed. spi interface enabled corresponding spiofunc bit (1=bit i/o) corresponding siocfg bit (1=output) serial i/o pins sck sdo sdi pcigntn[1] no x 2 2. don?t care no 0 x z 3 3. tri-stated zzo 4 4. state determined by pci function in corresponding pci mode no x yes 0 z o 5 5. output oi 6 6. input o 4 noxx10iiio 4 yesyesx10iiii noxx 1 1oooo 4 yesyesx 1 1oooo yesnoxxxoo i o yesyesno0xzzzo 7 7. this signal is driven low (microwire chip select is negated). yes yes yes 0 x o o i o 7 table 16.1 serial i/o pin configuration
idt serial peripheral interface spi clock prescalar 79rc32438 user reference manual 16 - 3 november 4, 2002 notes spi register description spi clock prescalar the spi contains an 8-bit clock pres calar which is used to generate an internal spi prescalar clock. this clock is further divided by the value in the spi clock rate divisor (spr) field of the spi control register (spc) before being used by the spi interface as the time base for all transfers. the internally generated spi prescalar clock is equal to the ipbus clock (iclk) frequency divided by twice t he clock prescalar divisor (div) field value in the spi cloc k prescalar (spcp) register plus one. the generated clock may not be symmetric. the clock used by the spi interface is equal to: clock prescalar register figure 16.2 spi clock prescalar register (spcp) register offset register name register function size 0x07_8000 spcp spi clock prescalar 32-bit 0x07_8004 spc spi control 32-bit 0x07_8008 sps spi status 32-bit 0x07_800c spd spi data 32-bit 0x07_8010 siofunc serial i/o function 32-bit 0x07_8014 siocfg serial i/o configuration 32-bit 0x07_8018 siod serial i/o data 32-bit 0x07_801c through 0x07_ffff reserved table 16.2 spi register map div description: clock prescalar divisor. the internally generated spi prescalar clock is equal to the master clock divided by twice the div field plus one. initial value: 0x0 read value: previous value written write effect: modify value spi clock iclk 2div1 + () spr --------------------------------------------------------- = spcp 0 31 div 0 24 8
idt serial peripheral interface spi clock prescalar 79rc32438 user reference manual 16 - 4 november 4, 2002 notes spi control register figure 16.3 spi control register (spc) spr description: clock divisor. this two bit field specifies the value by which the spi prescalar clock is divided. the resulting clock is used as the time base for all spi operations. 0x0 - divide by 2 0x1 - divide by 4 0x2 - divide by 16 0x3 - divide by 32 initial value: 0x0 read value: previous value written write effect: modify value cpha description: clock phase. this bit together with the cpol bit control the clock and data relationship for serial data clocked out on the sdo pin and clocked in on the sdi pin. 0x0 - data is clocked out/in on the first edge of the clock 0x1 - data is clocked out/in on the second edge of the clock initial value: 0x0 read value: previous value written write effect: modify value cpol description: clock polarity . this bit specifies the polarity of the clock. when this bit is set to zero (cleared), the spi clock (spclk) is held in a low state during spi idle periods (i.e., between transactions when the bus is idle). when this bit is set to one, the spi clock is held in a high state during spi idle periods. initial value: 0x0 read value: previous value written write effect: modify value mstr description: master/slave mode . since the spi interface only supports master mode, this bit should always be set. it is provided for software compatibility only. initial value: 0x1 read value: previous value written write effect: modify value spc 0 31 0 24 spr 2 cpha 1 cpol 1 spe 1 spie 1 0 1 mstr 1
idt serial peripheral interface spi clock prescalar 79rc32438 user reference manual 16 - 5 november 4, 2002 notes figure 16.4 serial peripheral interface (spi) clock/data timing spi status register figure 16.5 spi status register (sps) spe description: enable . when this bit is set to one, the serial peripheral interface is enabled. when this bit is set to zero (cleared), the serial peripheral interface is disabled and held in a low power state. dis- abling and then re-enabling the spi initializes all spi interface logic to a known state. when the spi is disabled, writes to the spd register will produce undefined results. initial value: 0x0 read value: previous value written write effect: modify value spie description: spi interrupt enable . when this bit is set to zero (cleared), spi transfer complete (spif) and master error flag (modf) bits in the sps register are masked from generati ng an interrupt. initial value: 0x0 read value: previous value written write effect: modify value modf description: master error flag. this bit is asserted if a write is performed to the spd register while the spi interface is in non-master mode (i.e., slave mode). this bit is provided for software compatibility. initial value: 0x0 msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb sck (cpol=0) sck (cpol=1) sample input data output (cpha=1) sample input data output (cpha=0) gpio(x) (chip select) sps 0 31 0 24 0 4 wcol 1 spif 1 1 modf 1 0
idt serial peripheral interface spi clock prescalar 79rc32438 user reference manual 16 - 6 november 4, 2002 notes spi data register figure 16.6 spi data register (spd) read value: status write effect: no effect. this bit is au tomatically set to zero when the sps register is r ead and then a write is performed to the spc register with the mstr bit set. wcol description: write collision. this bit is set if a write collision occurs (i.e., the cpu writes to the spd register during an spi transaction). initial value: 0x0 read value: status write effect: no effect. this bit is automatically set to zero when the sps register is read and then the spd register is written. spif description: spi transfer complete. this bit is set when an spi transaction completes. initial value: 0x1 read value: status write effect: no effect. this bit is automatically set to zero when the sps register is read and then the spd register is read. data description: data. a write to this field results in an spi transaction in which the value written to this register is shifted out on the sdo pin while data is simultaneously shifted into this field from the sdi pin. at the completion of the transaction, the spif bit in the sps regi ster is set to one and this field contains the 8-bit quantity read from the sdi pin. initial value: 0x0 read value: value shifted in from sdi pin during the previous transaction write effect: initiate an spi transaction. after an initial transaction, subsequent spi transactions can only be initiated when the spif bit is set in the sps regist er and a read of the register is performed before a write to the spd register. spd 0 31 0 24 data 8
idt serial peripheral interface spi setup 79rc32438 user reference manual 16 - 7 november 4, 2002 notes spi setup the following describes the typical setup of t he spi interface which occurs during boot time: 1. as the spi interface shares data and clock pins with the pci eeprom, the spi module must first poll the pci eeprom eed bit in the pci status r egister of the pci controller to determine if the pci module has finished loading data from t he pci eeprom. the rc32438 device automatically switches the functionality of the pins for use as an spi interface when the loading of configuration data from the pci eeprom is completed. 2. as the spi signal functions ar e routed via the pio controller, the pio controller will generally be initialized to the effect mode and establish the corr ect direction for each spi pin. at reset time, the default effect mode and direction are set up for the pci eeprom and also for the spi. 3. the spi clock prescalar r egister, spcp, is programmed. 4. the spi control register (spc), including the spe enable bit, is programmed. 5. the data being sent to the spi slave is written into the spi data register (spd). 6. the spi controller will initiate the hardwar e protocol on the spi pins. the rc32438 device will receive data from the slave at the same time it is sending data to the slave. 7. system either with: ? wait for an spi interrupt. after receiving an spi interrupt via the interrupt controller, the spi status register spif and modf flags can be read. ? poll the spi status register spif and modf flags. 8. if the spif flag is set, indicating the transaction is complete, reading the spi status register resets the spif flag. 9. read the data from the spi data register. 10. repeat steps 5 through 10, as needed. serial bit i/o pins the serial i/o signals sck, sdo, sdi, and pcignt n[1] may be used as bit i/o ports that operate in basically the same way as gpio pins. for additional information on the gpio pins, refer to chapter 12, general purpose i/o controller. the pci serial eeprom may be read to and written fr om when loading to the pci configuration regis- ters has completed. this is achieved by disab ling the spi interface and synthesizing (via software) microwire transactions on the serial i/o pins. when the pci interface operates in pci satellite m ode, the state of the pcigntn pin may be controlled by writing the desired pin state value into the serial i/o data (siod) register. serial i/o function register figure 16.7 serial i/o function register (siofunc) sdo description: serial data output. when this bit is set to one, the sdo pin operates as a bit i/o port regardless of the state of the spi or pci interfaces. initial value: 0x0 siofunc 0 31 0 28 sdo 1 sdi 1 sck 1 pci 1
idt serial peripheral interface serial bit i/o pins 79rc32438 user reference manual 16 - 8 november 4, 2002 notes serial i/o configuration register figure 16.8 serial i/o conf iguration register (siocfg) read value: previous value written write effect: modify value sdi description: serial data input. when this bit is set to one, the sdi pin operates as a bit i/o port regardless of the state of the spi or pci interfaces. initial value: 0x0 read value: previous value written write effect: modify value sck description: serial clock. when this bit is set to one, the sck pin operates as a bit i/o port regardless of the state of the spi or pci interfaces. initial value: 0x0 read value: previous value written write effect: modify value pci description: pci chip select. when this bit is set to one, the pcigntn[1] pin operates as a bit i/o port regardless of the state of the pci interface if the pci interface is in pci satellite mode. if the pci interface is in host mode, the state of this bit has no effect, and the operating mode of this pin is determined by the pci pin function in that mode. initial value: 0x0 read value: previous value written write effect: modify value sdo description: serial data output. when this bit is set to one and the corresponding pin is configured as a bit i/ o port in the siofunc register, the pin is configured as an output. otherwise, if this bit is reset and the corresponding pin is configured as a bit i/o port in the siofunc register, the pin is con- figured as an input. if the pin is not configured as a bit i/o port, the bit in this register has no effect. initial value: 0x0 read value: previous value written write effect: modify value siocfg 0 31 0 28 sdo 1 sdi 1 sck 1 pci 1
idt serial peripheral interface serial bit i/o pins 79rc32438 user reference manual 16 - 9 november 4, 2002 notes serial i/o data register figure 16.9 serial i/o data register (siod) sdi description: serial data input. when this bit is set to one and the corresponding pin is configured as a bit i/o port in the siofunc register, the pin is configured as an output. otherwise, if this bit is reset and the corresponding pin is configured as a bit i/o port in the siofunc register, the pin is con- figured as an input. if the pin is not configured as a bit i/o port, the bit in this register has no effect. initial value: 0x0 read value: previous value written write effect: modify value sck description: serial clock. when this bit is set to one and the corresponding pin is configured as a bit i/o port in the siofunc register, the pin is configured as an output. otherwise, if this bit is reset and the corresponding pin is configured as a bit i/o port in the siofunc register, the pin is configured as an input. if the pin is not configured as a bit i/o port, the bit in this register has no effect. initial value: 0x0 read value: previous value written write effect: modify value pci description: pci chip select. when this bit is set to one and the corresponding pin is configured as a bit i/o port in the siofunc register, the pin is configured as an output. otherwise, if this bit is reset and the corresponding pin is configured as a bit i/o port in the siofunc register, the pin is con- figured as an input. if the pin is not configured as a bit i/o port, the bit in this register has no effect. initial value: 0x0 read value: previous value written write effect: modify value sdo description: serial data output. reading this bit returns the state of the sdo pin. writing a value to this bit causes the sdo pin to take on the corresponding value if it is configured to be a bit i/o output port in the siofunc and siocfg registers. initial value: sdo pin value siod 0 31 0 28 sdo 1 sdi 1 sck 1 pci 1
idt serial peripheral interface master programming example 79rc32438 user reference manual 16 - 10 november 4, 2002 notes master programming example spi initialization 1. if the pci interface is configured to operate in pci satellite mode with suspended cpu execution, wait until pci serial eeprom done (eed ) bit is set in the pcis register. 2. based on operating ipbus clock frequency and desired spi clock frequency, write spcp register (i.e., 0x0c for 100 mhz ipbus clock, 2 mhz spi clock and spr = 0 in spc). 3. write spic register with 0x0000_00d0. spie = 1 - interrupt enable, spe = 1 - enable interface, mstr = 1 - master mode, spol = 0 - idle clock pol arity low, cpha = 0 - data clocked on first edge, spr = 0 - clock divisor is 2. 4. write imask6 register to disable gpio interrupt, gpiox = 0, where "x" is used gpio pin for spi chip select. if you have more than one device, di sable all interrupts for used gpio pins. 5. write gpiofunc register to set gpiox = 0 ? not alternate function. 6. write gpiocfg register to set gpiox = 1 ? output. 7. write gpiod register to de-assert chip select(s) gpiox = 1. 8. read sps and then spd to clear spif bit. 9. write imask5 register spi = 0 ? enable spi interrupts. read value: previous value written write effect: modify value sdi description: serial data input. reading this bit returns the state of the sdi pin. writing a value to this bit causes the sdi pin to take on the corresponding value if it is configured to be a bit i/o output port in the siofunc and siocfg registers. initial value: sdi pin value read value: previous value written write effect: modify value sck description: serial clock. reading this bit returns the state of the sck pin. writing a value to this bit causes the sck pin to take on the corresponding value if it is configured to be a bit i/o output port in the siofunc and siocfg registers. initial value: sck pin value read value: previous value written write effect: modify value pci description: pci chip select. reading this bit returns the state of the pcigntn[1] pin. writing a value to this bit causes the pcigntn[1] pin to take on the corresponding value if it is configured to be a bit i/o output port in the siofunc and siocfg registers and the pci interface is operating in pci satellite mode. initial value: pcigntn[1] pin value read value: previous value written write effect: modify value
idt serial peripheral interface master programming example 79rc32438 user reference manual 16 - 11 november 4, 2002 notes 10. write gpiod register to assert chip se lect gpiox = 0 for the device to be accessed. 11. write spid register with data to transmit over spi interface to start the transmission process. 12. wait until the spi interrupt occurs. the interrupt routine will perform the following steps: ? read sps register and check for errors. ? mandatory read spd register, to get i nput data and clear spif bit in sps register. ? if finished with (multi-)byte command s equence (i.e., a read sequence: command; address byte 1; address byte 2; 4 data bytes) de-assert chip select writing gpiod register with gpiox = 1. 13. repeat steps 10 - 12 as needed.
idt serial peripheral interface master programming example 79rc32438 user reference manual 16 - 12 november 4, 2002 notes
notes 79rc32438 user reference manual 17 - 1 november 4, 2002 chapter 17 on-chip memory introduction this chapter describes the on-chip memory features and functions of the rc32438. theory of operation on-chip memory supports byte, halfword, triple-b yte, and word memory read and write operations. all ipbus transfer types are supported by on-chip memo ry (e.g., cpu, pci, and dma transfers). the rc32438 device includes 4kb of high speed sram organi zed as 1k x 32 bits of on-chip memory. there is nothing to prohibit the cp u core from accessing on-chip memory. however, access to on-chip memory by user processes/tasks may be prohibit ed by using the cpu?s mmu. pci bus masters may access on-chip memory if the rc32438?s local address range of on-chip memory is contained in a region mapped by one of the four pci base address (pbax) regi sters to the pci bus. some or all of the on-chip memory may be used by the ipbus monitor. for additi onal information on the ipbus monitor, see chapter 18, debugging and performance monitoring. cpu-initiated and ipbus monitor accesses to on-chip memory are conflict-free: cpu accesses to on- chip memory are delayed by, at most, one ipbus clock cycle when both the cpu and ipbus monitor access the same half of on-chip memory, and neither is del ayed when cpu accesses are restricted to the bottom half of memory and the ipbus monitor is c onfigured to use the top half of memory. the contents of on-chip memory is preserved across warm and cold resets. address decoding for on-chip memory is controlled by the on-chip memory base (ocmbase) and on- chip memory mask (ocmmask) registers. the mask r egister is used to select which bits are used for address decoding. when a bit in this register is a one, the correspondi ng address bit is active in address comparisons. if a bit in this register is a zero, t he corresponding address bit does not participate in address comparisons. all of the active address bits not masked by the mask register are compared to the value in the base register. if they all match, then on-chip memory is selected. on-chip memory base register figure 17.1 on-chip memo ry base register (ocmbase) baseaddr description: base address. this field specifies the upper 16-bits of the on-chip memory base address. initial value: 0x0 read value: previous value written write effect: modify value ocmbase 0 31 16 16 baseaddr 0
idt on-chip memory theory of operation 79rc32438 user reference manual 17 - 2 november 4, 2002 notes on-chip memory mask register figure 17.2 on-chip memory mask register (ocmmask) mask description: address mask. this field determines which bits of the upper 16-bits of the address participate in address comparisons. when a bit is set to one in this field, then the corresponding address bit participates in address comparisons. when a bit is set to zero in this field, then the correspond- ing address bit is masked and does not participate in address comparisons. when the mask field is zero, the on-chip memory does not appear in the memory map. initial value: 0x0 read value: previous value written write effect: modify value ocmmask 0 31 16 mask 16 0
notes 79rc32438 user reference manual 18 - 1 november 4, 2002 chapter 18 debugging and performance monitoring introduction this chapter discusses the three different debugging features available on the rc32438: ipbus monitor, event monitor, and debug pins. these feat ures can be used together or independently to aid in system optimization or system debugging. features ? ipbus monitor provides an on-chip ?logi c analyzer? for hardware and software debugging ? eight 24-bit statistics counters ? external debug support pins provide external visibilit y to internal operation debug and performance register description register offset register name register function size 0x09_000 ipbmtcfg ipbus monitor trigger configuration 32-bit 0x09_004 ipbmts ipbus monitor trigger select 32-bit 0x09_008 ipbmmt ipbus monitor manual trigger 32-bit 0x09_00c ipbmtc0 ipbus monitor trigger condition 0 32-bit 0x09_010 ipbmtc1 ipbus monitor trigger condition 1 32-bit 0x09_014 ipbmtc2 ipbus monitor trigger condition 2 32-bit 0x09_018 ipbmtc3 ipbus monitor trigger condition 3 32-bit 0x09_01c ipbmfs ipbus monitor filter select 32-bit 0x09_020 ipbmfc0 ipbus monitor filter control 0 32-bit 0x09_024 ipbmfc1 ipbus monitor filter control 1 32-bit 0x09_028 ipbmfc2 ipbus monitor filter control 2 32-bit 0x09_02c ipbmrc ipbus monitor record control 32-bit 0x09_030 ipbmtt ipbus monitor trigger time 32-bit 0x09_034 ipbmtp ipbus monitor trigger position 32-bit 0x09_038 emc event monitor control 32-bit 0x09_03c em0compare event monitor 0 compare 32-bit 0x09_040 em0count event monitor 0 count 32-bit 0x09_044 em1count event monitor 1 count 32-bit 0x09_048 em2count event monitor 2 count 32-bit 0x09_04c em3count event monitor 3 count 32-bit 0x09_050 em4count event monitor 4 count 32-bit 0x09_054 em5count event monitor 5 count 32-bit table 18.1 debug and performance register map (part 1 of 2)
idt debugging and performance monitoring ipbus monitor 79rc32438 user reference manual 18 - 2 november 4, 2002 notes ipbus monitor the ipbus monitor provides on-chip ?logic anal yzer? functionality for debugging hardware and software. it provides sophisticated support fo r debugging transactions on the internal ipbus that would otherwise not be available to the user. unlike most other blocks in the rc32438, the ipbus monitor is not reset during a warm reset. this allows the ipbus monitor to be used to debug across a warm reset. the ipbus monitor allows ipbus transaction informati on to be recorded in on-chip memory for later anal- ysis (for additional information, refer to chapter 17, on-chip memory). the on-chip memory region used by the ipbus monitor is determined by the ipbmbase field of the ipbmrc register. as shown in figure 18.1, the ipbus monitor uses memory starting at ipbmbase to the end of on-chip memory to record transac- tions. memory below ipbmbase is available for other uses. figure 18.1 ipbus monitor on-chip memory usage transaction information is stored using two types of double word (i.e., 64-bit) records. a clock cycle record is stored in on-chip memory during each cloc k cycle of a transaction. a transaction summary record is stored in on-chip memory at the end of each transacti on (refer to the ipbus monitor trigger time section later in this chapter). records are stored in on-chip memory in a circular fashion. when the end of on-chip memory is reached, recording continues starting at ipbmbase. when the ipbus monitor is enabled (i.e., the en bit is se t in the ipbmtcfg register), it begins recording each ipbus transaction in on-chip memory. recording st ops shortly after a final trigger event occurs. once a final trigger event occurs the ipbus monitor cont inues storing transactions records in on-chip memory until the space allocated by the final trigger reco rd length (ftrl) field in the ipbmrc register is exhausted. the ftrl field provides control over how many transacti ons are recorded before and after a final trigger event. when a final trigger event occurs the ft bit is se t in the ipbmtcfg register. this bit is presented to the interrupt controller as an interrupt source. when the ejtag debug interrupt enable (die) bit is set in the ipbmtcfg register, an ejtag debug interrupt request is generated to the cpu core whenever the ft bit is set in the ipbmtcfg register. this allows synchronization between the ipbus monitor and an external ejtag ice. when the ipbus monitor completes storing transaction records in on-chip memory (i.e., the space allocated by the ftrl field is exhausted) the recording completed (rc) bit is set in the ipbmtcfg register. this bit is presented to the interrupt controller as an interrupt source. 0x09_058 em6count event monitor 6 count 32-bit 0x09_05c em7count event monitor 7 count 32-bit 0x09_0060 through 0x09_7fff reserved register offset register name register function size table 18.1 debug and performance register map (part 2 of 2) 0x0000 0x0fff ipbus monitor space ipbmbase
idt debugging and performance monitoring ipbus monitor registers 79rc32438 user reference manual 18 - 3 november 4, 2002 notes the trigger condition (tc) bit in t he ipbmtcfg allows the and or or of trigger conditions selected in the ipbmts register to result in a trigger event. tri gger conditions are defined by system events, such as a warm reset, or by conditions s pecified in the ipbus monitor tr igger condition [0..3] registers (ipbmtc[0..3]). each time a trigger event occurs, the value in the tcount fiel d of ipbmtcfg is decre- mented. when tcount reaches zero , a final trigger event occurs. the ipbus monitor uses two external pins. one of these is an alternate function input of gpio[29] (ipbmtriginp) whose level can be se lected as a trigger condition. the other is an output pin (ipbmtri- goutp) that is toggled or pulsed when a trigger ev ent occurs. the tip and tom fields of ipbmtcfg control the behavior of these signals. there is a delay of 4 iclk cycles between a transition on the ipbmtrigoutp signal and a final trigger event. there is a delay of 5 iclk cycles between assertion of the ipbmtriginp input (a gpio alternate function) and detection of this event by the ipbus monitor. the ipbus monitor allows transacti ons to be filtered ?in? or ?out? depending on conditions specified in the ipbus monitor filter control [0..2] (ipbmfc[0..2]) r egisters. if a transaction has been filtered ?out,? then none of the clock cycle records or the transaction summ ary record for that transaction are recorded in on- chip memory. if a transaction is filtered ?in,? then a ll clock cycle and transaction summary records for that transaction are recorded in on-chip memory. when the en bit in ipbus monitor filter select (ipbmfs) register is set, filtering is enabled. the filter condition (fc) field cont rols which transactions are recorded. the remaining bits in this register allow one to select which filter conditions are enabled. the ipbus monitor contains a free running counter t hat is incremented on each rising edge of iclk. the time stamp (ts) field in each trans action summary record contains the value of this counter. if the number of iclk clock cycles between the previous and curr ent transaction summary records is greater than or equal to 2 23 , the overflow (ovr) bit is set in the transacti on summary record and the value of the ts field should be disregarded. the ipbus monitor trigger time (ipbmtt) register contains the value of t he free running counter when a final trigger condition occurs. after a final trigger condition is recorded, the addres s of the first transaction summary record that was recorded in on-chip memory is saved in the addr field of the ipbus monito r trigger position (ipbmtp) register. for example, if the final trigger condition occurs due to a data transfer on the ipbus and a clock cycle record format transaction is recorded in on-chip memory for this data transfer, then ipbmtp points to the transactions summary record for that transaction. ipbmtp may not actually point to the transaction summary record that generated the final trigger conditi on since the clock cycle record and even the transac- tion summary record may have been filtered ?out.? in these cases, ipbmtp points to the first transaction summary record stored in on-chip memo ry after a final trigger condition. the bus master index referred to in this section co rresponds to the ipbus master indices listed in table 5.1 of chapter 5, bus arbitration. note: a warm reset does not modify the state of ip bus monitor registers or on-chip memory. a cold reset does not modify the state of on-chip memory but does modify the state of ipbus monitor registers. ipbus monitor registers ipbus monitor trigger configuration register figure 18.2 ipbus monitor trigger configuration register (ipbmtcfg) ipbmtcfg 0 31 tip 1 tcount 8 tom 2 en 1 tc 1 ft 1 ra 1 rc 1 rtcount 8 0 7 die 1
idt debugging and performance monitoring ipbus monitor registers 79rc32438 user reference manual 18 - 4 november 4, 2002 notes en description: enable. when this bit is set to one, the ipbus monitor is armed. each time the trigger condition specified by the tc field and the ipbus monitor trigger select (ipbmts) register are satisfied the trigger count (tcount) field is decremented. when the tcount field reaches zero, the enable bit is set to zero (cleared) and a final trigger event occurs. note : when this bit is set, the ipbus records transactions until a final trigger event occurs or until this bit is cleared by software. initial value: 0x0 read value: previous value written write effect: modify value rc description: recording completed. when the ipbus monitor completes storing transaction records in on- chip memory (i.e., the space allocated by the ftrl field is exhausted) this bit is set. initial value: 0x0 read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) ra description: rearm. when this bit is set to one, the ipbus moni tor is automatically rearmed (i.e., the enable bit is set) after a final trigger event occurs. when the ipbus monitor is rearmed, the value in the rtcount field is loaded into the tcount field. initial value: 0x0 read value: previous value written write effect: modify value ft description: final trigger. this bit is set to one when a final trigger event occurs. initial value: 0x0 read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) tc description: trigger condition. when this bit is set to one, the ipbus monitor triggers when all of the selected trigger conditions selected in the ipbmts register are satisfied (i.e., and of all enabled trigger conditions). when this bit is cleared, the ipbus monitor triggers when any of the selected trigger conditions are satisfied (i.e., or of all enabled trigger conditions). initial value: 0x0 read value: previous value written write effect: modify value
idt debugging and performance monitoring ipbus monitor registers 79rc32438 user reference manual 18 - 5 november 4, 2002 notes tip description: ipbus monitor trigger input polarity. this bit selects the active polarity of the ipbus monitor trigger input (ipbmtriginp). ipbmtriginp is a gpio alternate function and is sampled by extclk. 0 - ipbmtriginp is active low (trigger when signal transitions from 1 to 0) 1 - ipbmtriginp is active high (trigger when signal transitions from 0 to 1) initial value: 0x0 read value: previous value written write effect: modify value tom description: ipbus monitor trigger output mode. this bit selects the operating mode of the ipbus monitor trigger output (ipbmtrigout). 0 - ipbmtrigout is driven low for one extclk clock cycle when final trigger occurs 1 - ipbmtrigout is driven high for one extclk clock cycle when final trigger occurs 2 - ipbmtrigout is inverted (i.e., to ggled) when final trigger event occurs 3 - reserved initial value: 0x0 read value: previous value written write effect: modify value tcount description: trigger count. this field contains a trigger count which is decremented each time a trigger event occurs. initial value: 0x0 read value: previous value written write effect: modify value rtcount description: rearm trigger count. this field contains the rearm trigger count value which is loaded into the tcount field whenever the ipbus monitor is automatically rearmed (i.e., when the ra bit is set and the final trigger event occurs). initial value: 0x0 read value: previous value written write effect: modify value die description: debug interrupt enable. when this bit is set in the ipbmtcfg register, an ejtag debug inter- rupt request is generated to the cpu core whenever the ft bit is set. this allows synchroniza- tion between the ipbus monitor and an external ejtag ice. initial value: 0x0 read value: previous value written write effect: modify value
idt debugging and performance monitoring ipbus monitor registers 79rc32438 user reference manual 18 - 6 november 4, 2002 notes ipbus monitor trigger select register figure 18.3 ipbus monitor tri gger select register (ipbmts) a description: address. this bit selects the address trigger condition in the ipbmtc0 register. a trigger condi- tion occurs when a transaction address matches the address bits in the address (a) field of the ipbmtc0 register which are not masked by the address mask (am) field in the ipbmtc1 regis- ter. initial value: 0x0 read value: previous value written write effect: modify value op description: operation. this bit selects the read or write operation select trigger (rw) condition in the ipbmtc3 register. initial value: 0x0 read value: previous value written write effect: modify value d description: data. this bit selects the data trigger condition in the ipbmtc2 register. initial value: 0x0 read value: previous value written write effect: modify value mg description: ipbus master grant. this bit selects the ipbus master grant trigger condition in the ipbmtc3 register. initial value: 0x0 read value: previous value written write effect: modify value mr description: ipbus master bus requests. this bit selects the ipbus master bus requests trigger condition in the ipbmtc3 register. the trigger condition is determined by the masters selected in the mr field and the state of the mrm field. initial value: 0x0 ipbmts 0 31 op 1 a 1 d 1 mg 1 mr 1 ir 1 wto 1 wr 1 et 1 bto 1 trw 1 uae 1 em0 1 0 17 mt 1 sae 1
idt debugging and performance monitoring ipbus monitor registers 79rc32438 user reference manual 18 - 7 november 4, 2002 notes read value: previous value written write effect: modify value ir description: interrupt request. this bit selects the interrupt request trigger condition in the ipbmtc3 regis- ter. initial value: 0x0 read value: previous value written write effect: modify value wto description: watchdog timer time-out. this bit selects the watchdog timer time-out trigger condition (see the functional overview section in chapter 4, system integrity functions). initial value: 0x0 read value: previous value written write effect: modify value uae description: undecoded address error. this bit selects the undecoded address error trigger condition which is reported by the address space monitor (see the functional overview section in chapter 4, system integrity functions). initial value: 0x0 read value: previous value written write effect: modify value sae description: ipbus slave acknowledge error. this bit selects the ipbus slave acknowledge error trigger condition (see the functional overview section in chapter 4, system integrity functions). initial value: 0x0 read value: previous value written write effect: modify value bto description: bus transaction timer time-out. this bit selects the transaction timer time-out trigger condi- tion which is reported by the memory and peripheral bus transaction timer (see the theory of operation section in chapter 6, device controller). initial value: 0x0 read value: previous value written write effect: modify value wr description: warm reset. this bit selects the warm reset trigger condition. initial value: 0x0
idt debugging and performance monitoring ipbus monitor registers 79rc32438 user reference manual 18 - 8 november 4, 2002 notes ipbus monitor manual trigger register figure 18.4 ipbus monitor ma nual trigger register (ipbmmt) read value: previous value written write effect: modify value et description: external trigger. this bit selects the ipbmtriginp input trigger condition. a trigger event occurs when the state of the ipbmtriginp input is asserted (as specified by the tip field in ipb- mtcfg). the ipbmtriginp input is a gpio alternate function. initial value: 0x0 read value: previous value written write effect: modify value trw description: trigger register write. this bit selects writes to the ipbus monitor manual trigger register as a trigger condition. initial value: 0x0 read value: previous value written write effect: modify value em0 description: event monitor 0 trigger event. this bit selects an event monitor 0 trigger condition (i.e, when t bit is set in the em0compare register). initial value: 0x0 read value: previous value written write effect: modify value mt description: merged transaction trigger event. this bit selects ipbus merged transactions as a trigger condition. this event occurs with the dma controller merges two transactions on the ipbus. merged transactions eliminate the bus overhead associated with consecutive ipbus transactions to the same peripheral. initial value: 0x0 read value: previous value written write effect: modify value ipbmmt 0 31 trig 32
idt debugging and performance monitoring ipbus monitor registers 79rc32438 user reference manual 18 - 9 november 4, 2002 notes ipbus monitor trigger condition 0 register figure 18.5 ipbus monitor trigger condition 0 register (ipbmtc0) ipbus monitor trigger condition 1 register figure 18.6 ipbus monitor trigger condition 1 register (ipbmtc1) trig description: trigger. a write to this field results in a ?trigger register write? event which may be selected as an ipbus monitor trigger condition by the trw bit in the ipbmts register. initial value: 0x0 read value: 0x0 write effect: cause a trigger register write event a description: address. this field contains the trigger address. initial value: 0x0 read value: previous value written write effect: modify value am description: address mask. each bit in this field corresponds to an address bit in the address (a) field of the ipbmtc0 register. when a bit in this field is set, the state of the corresponding address bit in the a field is ignored (i.e., masked) in making trigger decisions. initial value: 0x0 read value: previous value written write effect: modify value ipbmtc0 0 31 a 32 ipbmtc1 0 31 am 32
idt debugging and performance monitoring ipbus monitor registers 79rc32438 user reference manual 18 - 10 november 4, 2002 notes ipbus monitor trigger condition 2 register figure 18.7 ipbus monitor trigger condition 2 register (ipbmtc2) ipbus monitor trigger condition 3 register figure 18.8 ipbus monitor trigger condition 3 register (ipbmtc3) d description: d. this field contains the 32-bit trigger data value. during each data transfer on the ipbus only the data value(s) of active byte lanes are compared to the corresponding byte value(s) in this field. for example, if only byte zero is active in an ipbus data transfer, then only the least signifi- cant byte of this register would be compared. initial value: 0x0 read value: previous value written write effect: modify value mg description: ipbus master grant. this field contains the ipbus master trigger index (i.e., the index of the bus master granted the bus). initial value: 0x0 read value: previous value written write effect: modify value mr description: ipbus master requests . each bit in this field corresponds to an ipbus master index. a trigger condition occurs when the mrm bit is set and all of the masters whose corresponding bit is set in this field are requesting service or when the mrm bit is cleared and any of the masters whose corresponding bit is set in this field are requesting service. initial value: 0x0 read value: previous value written write effect: modify value ipbmtc2 0 31 d 32 ipbmtc3 0 31 mg 5 mr 17 ir 5 0 3 mrm 1 rw 1
idt debugging and performance monitoring ipbus monitor registers 79rc32438 user reference manual 18 - 11 november 4, 2002 notes ipbus monitor filter select register figure 18.9 ipbus monitor filter select register (ipbmfs) mrm description: ipbus master request mode . this field controls the interpretation of the ipbus master request (mr) field in generating a trigger condition. 0 - trigger when all of the masters selected in the mr field are requesting service (i.e. and) 1 - trigger when any of the masters selected in the mr field are requesting service (i.e., or) initial value: 0x0 read value: previous value written write effect: modify value ir description: interrupt request . this field encodes the index of ipend interrupt request presented to the cpu (bit 0 corresponds to ipend2, bit one to ipend3, and so on). a trigger condition occurs when an interrupt request is presented to the cpu and the corresponding bit in the ir field is set. initial value: 0x0 read value: previous value written write effect: modify value rw description: read or write operation select . this field specifies the trigger transaction operation. 0 - read transaction 1 - write transaction initial value: 0x0 read value: previous value written write effect: modify value en description: enable. when this bit is set to one, filtering is enabled. when filtering is disabled, all data is recorded. initial value: 0x0 read value: previous value written write effect: modify value ipbmfs 0 31 fc 2 en 1 a 1 bms 1 op 1 0 26
idt debugging and performance monitoring ipbus monitor registers 79rc32438 user reference manual 18 - 12 november 4, 2002 notes ipbus monitor filter control 0 register figure 18.10 ipbus monitor filter control 0 register (ipbmfc0) fc description: filter condition. this field controls which transactions are recorded using filtering. 0 - record transactions that match all of the conditions selected in the ipbmfs register (i.e filter in and of conditions) 1 - record transactions that match any of the conditions selected in the ipbmfs register (i.e., fil- ter in or of conditions) 2 - record transactions that do not match all of the conditions selected in the ipbmfs register (i.e., filter out and of conditions) 3 - record transactions that do not match any of the conditions selected in the ipbmfs register (i.e., filter out or of conditions) initial value: 0x0 read value: previous value written write effect: modify value a description: address. this bit selects the address filter condition in the ipbmfc0 register. initial value: 0x0 read value: previous value written write effect: modify value bms description: bus master select. this bit selects the bus master select filter condition in the ipbmfc2 regis- ter. initial value: 0x0 read value: previous value written write effect: modify value op description: operation. when this bit is set to one, transactions of the type selected by the rw field in the ipbmfc2 register are selected as a filter condition. initial value: 0x0 read value: previous value written write effect: modify value ipbmfc0 0 31 a 32
idt debugging and performance monitoring ipbus monitor registers 79rc32438 user reference manual 18 - 13 november 4, 2002 notes ipbus monitor filter control 1 register figure 18.11 ipbus monitor filter control 1 register (ipbmfc1 ipbus monitor filter control 2 register r figure 18.12 ipbus monitor filter control 2 register (ipbmfc2) a description: address. this field contains the filter address. a transaction is considered to match the filter condition if its starting address matches unmasked bits (i.e., bits not masked by the am field in the ipbmfc1 register) in this field. initial value: 0x0 read value: previous value written write effect: modify value am description: address mask. each bit in this field corresponds to an address bit in the address (a) field of the ipbmfc0 register. when a bit in this field is set to one, the state of the corresponding address bit in the a field is ignored in making filtering decisions. initial value: 0x0 read value: previous value written write effect: modify value bms description: bus master select. each bit in this field corresponds to a bus master index. when a transaction is generated (i.e., the bus has been granted) from a bus master whose corresponding bit is set in this field, then the transaction is considered to match the filter. initial value: 0x0 ipbmfc1 0 31 am 32 ipbmfc2 0 31 bms 17 0 14 rw 1
idt debugging and performance monitoring ipbus monitor registers 79rc32438 user reference manual 18 - 14 november 4, 2002 notes ipbus monitor record control figure 18.13 ipbus monitor record control register (ipbmrc) read value: previous value written write effect: modify value rw description: read or write operation select. this field selects the type of transactions that are recorded. 0 - write transactions 1 - read transactions initial value: 0x0 read value: previous value written write effect: modify value ipbmbase description: ipbus monitor base recording address. this field contains the on-chip memory double word (i.e., 64-bit) base address used to record transactions. this address corresponds to an offset into on-chip memory and is not a complete local address space address. unused address bits are stored in this field but are ignored by hardware. initial value: 0x0 read value: previous value written write effect: modify value ftrl description: final trigger record limit. this field contains the number of double words written to on-chip memory after a final trigger event. unused address bits are stored in this field but are ignored by hardware. initial value: 0x0 read value: previous value written write effect: modify value dw description: discard wait records. do not write clock cycle records into memory that have the wait (w) bit set. initial value: 0x0 read value: previous value written write effect: modify value ipbmrc 0 31 ipbmbase 11 ftrl 11 0 9 dw 1
idt debugging and performance monitoring ipbus monitor registers 79rc32438 user reference manual 18 - 15 november 4, 2002 notes ipbus monitor trigger position figure 18.14 ipbus monitor tri gger position register (ipbmtp) ipbus monitor trigger time figure 18.15 ipbus monitor trigger time register (ipbmtt) addr description: trigger address. this field contains the on-chip memory double word address of the first ipbus monitor transaction summary record stored in on-chip memory after a final trigger. unused address bits are stored in this field but are ignored by hardware. initial value: 0x0 read value: previous value written write effect: modify value tae description: trigger address error. this bit is set if the addr field is invalid following a final trigger. this occurs when the ipbus monitor is unable to write a transaction summary record following a final trigger due to miscommunication of the frtl field in the ipbmrc register.. initial value: 0x0 read value: previous value written write effect: modify value ts description: time stamp. this field contains the value of the free running counter that is incremented at the iclk clock frequency when the final trigger event occurred. initial value: 0x0 read value: previous value written write effect: modify value ipbmtp 0 31 addr 11 0 20 tae 1 ipbmtt 0 31 ts 23 0 9
idt debugging and performance monitoring ipbus monitor registers 79rc32438 user reference manual 18 - 16 november 4, 2002 notes ipbus monitor record formats the ipbus monitor stores data in the on-chip ram us ing two record formats. both formats consist of double words (i.e., 64-bits or two 32-bit words). figure 18.16 ipbus monitor transaction summary record format rf record format. this bit indicates the format of the record. if this bit is set, then the record has a transaction summary format. if the bit is cleare d, then the record has a clock cycle format. ffiltered. this bit is set if any transactions were filtered between the previously recorded transac- tion and this one. sbe starting byte enables. this field represents the state of the byte enables in the first data transfer of the transaction. bit 0 corresponds to data bits 0 through 7, bit 1 corresponds to data bits 8 through 15, and so on. a bit is set if the byte lane is enabled. ebe ending byte enables. this field represents the state of the byte enables during last first data transfer of the transaction. bit 0 corresponds to data bits 0 through 7, bit 1 corresponds to data bits 8 through 15, and so on. a bit is set if the byte lane is enabled. mg ipbus master grant. this field contains the ipbus master index corresponding to the bus master that generated the transaction. mr ipbus master bus requests. each bit in this field corresponds to an ipbus master index. a bit is set if the corresponding bus master requested ownership of the ipbus at any point after the previ- ously recorded ipbus transaction and this one. in general, the bus master that has been granted the bus for the current transaction will not have its mr bit set (because in order to have been granted the bus, the current master has to have pre- viously requested the bus). however, there are two exceptions to this condition. first, if the bus master generates a request after it has already been granted the bus for the current transaction (this action is called a pre-request) and the current transaction is not yet completed, its mr bit will be set. second, if the bus master requested and performed a transaction that was filtered out after the previously recorded transaction, its mr bit will be set. ipend[2..6] interrupt requests. each bit in this field corresponds to an interrupt request to the cpu. if an interrupt request was generated at any time during the current transaction or since the last trans- action, then the corresponding bit in this field is set. r read. this bit is set if the transaction was an ipbus read transaction (i.e., either an ipbus master read or an ipbus fly-by read). this bit is cleared if the transaction was an ipbus write transaction. ba byte address. this two bit field contains the bottom two bits of the ipbus transaction starting address. the complete address of each transfer in a transaction may be determined by concate- nating this field with the addr field in the ipbus monitor clock cycle record (i.e., 32-bit address equals ((addr << 2) | ba)). ovr overflow. this bit is set if the number of clock cycles between the previously recorded ipbus monitor transaction summary record and this one is greater than or equal to 2 23 . ts time stamp. this field contains the value of the free running counter incremented at the iclk clock frequency when the transaction summary record was recorded. this value is equivalent to that of the last clock cycle in the transaction (i.e., the last clock cycle of the transaction before the ipbus goes idle or starts a new transaction). 0 31 rf 1 f 1 sbe 4 ebe 4 mg 5 mr 17 ipend[2..6] 5 ts 23 0 31 addr + 4 addr r 1 ba 2 ovr 1
idt debugging and performance monitoring event monitor 79rc32438 user reference manual 18 - 17 november 4, 2002 notes figure 18.17 ipbus monitor clock cycle record format event monitor the event monitor provides a means of gathering perfo rmance statistics. unlike most other blocks in the rc32438, the event monitor is not reset during a warm reset. the statisti cs monitor consists of eight 24-bit counters. the count value for each counter may be read or written at any time. a counter?s count value is incremented each time a selected event occurs if t he freeze (frz) bit is not set in the event monitor control (emc) register. setting the frz bit freezes the value of all event monitor counters. the count field may be read or written but is never incremented when the frz bit is cleared. writing a one to the clr bit in the emc register clea rs the value of all event monitor counters to zero. this occurs regardless of the state of the frz bit. each event monitor c ounter contains a 6-bit select (sel) field that maps one of 64 events to the event counter. rf record format. this bit indicates the format of the record. if this bit is set to 1, then the record has a transaction summary format. if the bit is cleared, then the record has a clock cycle format. wwait. this bit is set if a wait state was generated in the clock cycle represented by the current data transfer record or a data transfer occurred in which all the byte lanes were disabled. addr address. this field contains the value of the upper 30 bits of the ipbus address in the clock cycle represented by the current data transfer record. data data. this field contains the 32-bit ipbus data value in the clock cycle represented by the current data transfer record. when the wait (w) bit is set, this field may be used to distinguish between a true wait state and a data transfer in which all byte lanes were disabled. 0x0000_0000 - wait state 0x1111_1111 - data transfer with all byte lanes disabled 0x2222_2222 - null data associated with transactions that generate an undecoded address error. event index event description 0 cpu instruction executed 1 cpu instruction cache miss 2 cpu data cache hit 3 cpu data cache miss 4 cpu joint tlb miss 5 cpu instruction tlb miss 6 cpu data tlb miss 7 maximum number of wait states in a single ipbus transaction 1 8 rising edge of ipbus clock (iclk) table 18.2 event monitor sources (part 1 of 3) 0 31 rf 1 w 1 addr 30 data 32 0 31 addr + 4 addr
idt debugging and performance monitoring event monitor 79rc32438 user reference manual 18 - 18 november 4, 2002 notes 9 event monitor trigger event (i.e., t bit in em0compare register tran- sition from 0 to 1) 10 ipbus monitor final trigger event 11 pmbus transaction 12 pmbus cpu transaction 13 pmbus ipbus transaction 14 pmbus sneak transaction 15 pmbus delay (each iclk cycle in which an ipbus transaction is delayed due to a sneak transaction) 16 ddr read transaction 17 ddr write transaction 18 ipbus arbiter grants bus to a bus master with a cmtc equal to zero (uses round robin arbitration) 19 number of double words written to on-chip memory by ipbus monitor 20 ipbus transaction (an event is generated for each transaction even if the transaction is merged with another transaction) 21 ipbus idle cycle 22 ipbus master index 0 bytes transferred 23 ipbus master index 1 bytes transferred 24 ipbus master index 2 bytes transferred 25 ipbus master index 3 bytes transferred 26 ipbus master index 4 bytes transferred 27 ipbus master index 5 bytes transferred 28 ipbus master index 6 bytes transferred 29 ipbus master index 7 bytes transferred 30 ipbus master index 8 bytes transferred 31 ipbus master index 9 bytes transferred 32 ipbus master index 10 bytes transferred 33 ipbus master index 11 bytes transferred 34 ipbus master index 12 bytes transferred 35 ipbus master index 14 bytes transferred 36 ipbus master index 15 bytes transferred 37 ipbus master index 16 bytes transferred 38 maximum number of idle cycles between ipbus transactions 1 39 ipbus read transaction 40 ipbus write transaction 41 ipbus transaction that transferred between 1 and 16 bytes 42 ipbus transaction that transferred between 17 and 32 bytes event index event description table 18.2 event monitor sources (part 2 of 3)
idt debugging and performance monitoring event monitor 79rc32438 user reference manual 18 - 19 november 4, 2002 notes the event monitor 0 count register has a corre sponding compare register. when the value of the count field in em0count equals or is greater than the value in t he compare field of em0compare, then the triggered (t) bit in the em0compare register is set. the t bit in the em0compare register is presented to the interrupt controller as an interrupt source. when the ejtag debug interrupt enable (die) bit is set in the em0compare register, an ejtag debug interrupt request is generated to the cpu core whenever the t bit is set in the em0compare register. this allows synchr onization between the event monito r and an external ejtag ice. note: the state of event monitor registers is not modified due to a warm reset (i.e., they are not reset). note: when an event that occurs at the pclk cl ock frequency is selected as an event monitor event source (e.g., cpu instruction executed), t he event counter value may be overstated by up to 12 cycles due to synchronization delays (the counter is updated every 12 cpu cycles). 43 ipbus transaction that transferred between 33 and 48 bytes 44 ipbus transaction that transferred between 49 and 64 bytes 45 ipbus unaligned transfer transaction (i.e., a transaction starting on a non-word boundary) 46 number of ipbus transaction merges (each merge is countered within a transaction) 47 ipbus master index 0 transaction 48 ipbus master index 1 transaction 49 ipbus master index 2 transaction 50 ipbus master index 3 transaction 51 ipbus master index 4 transaction 52 ipbus master index 5 transaction 53 ipbus master index 6 transaction 54 ipbus master index 7 transaction 55 ipbus master index 8 transaction 56 ipbus master index 9 transaction 57 ipbus master index 10 transaction 58 ipbus master index 11 transaction 59 ipbus master index 12 transaction 60 external memory and peripheral bus master granted bus 61 ipbus master index 14 transaction 62 ipbus master index 15 transaction 63 ipbus master index 16 transaction 1. this field records a maximum count. a shadow counter is maintained that records the actual count, and this counter is incremented only when a shadow count exceeds the value in an actual counter that selects this event. event index event description table 18.2 event monitor sources (part 3 of 3)
idt debugging and performance monitoring event monitor 79rc32438 user reference manual 18 - 20 november 4, 2002 notes event monitor control register figure 18.18 event monito r control register (emc) event monitor [0..7] count register figure 18.19 event monitor [0..7] count register (em[0..7]count) frz description: freeze. when this bit is set to zero (cleared), event monitor count registers are incremented when the selected event occurs. when this bit is set to one, events are ignored and the event monitor count registers remain ?frozen.? initial value: 0x1 read value: previous value written write effect: modify value clr description: clear counters. writing a one to this bit causes the count field in all event monitor [0..7] count (em[0..7]count) registers to be set to zero (cleared). initial value: 0x0 read value: 0x0 write effect: writing a one clears all event monitor counters, writing a zero has no effect zor description: zero on read. when this bit is set to one, reading an event monitor count (emxcount) regis- ter causes it to be automatically cleared as a side effect of the read. initial value: 0x0 read value: previous value written write effect: modify value count description: count. this field contains the current event monitor count. emc 0 31 0 29 frz 1 clr 1 zor 1 em[0..7]count 0 31 6 sel 24 count 1 0 1 ovr
idt debugging and performance monitoring event monitor 79rc32438 user reference manual 18 - 21 november 4, 2002 notes event monitor 0 compare register figure 18.20 event monitor 0 compare register (em0compare) initial value: 0x0 read value: current event count write effect: modify value ovr description: overflow. this bit is set when the event monitor co unt register overflows (i.e., when count rolls over from 0xffffff to 0x000000). initial value: 0x0 read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) sel description: event select. this field selects the event monitor counter event source. initial value: 0x0 read value: previous value written write effect: modify value compare description: event compare. when the count field in the event monitor 0 count (em0count) register is equal to or greater than the value in this field, an event monitor 0 trigger event occurs and the t bit in this register is set. initial value: 0xff_ffff read value: current event count write effect: modify value die description: debug interrupt enable. when this bit is set to 1, an ejtag debug interrupt request is gener- ated to the cpu core whenever the t bit is set. this allows synchronization between the event monitor and an external ejtag ice. initial value: 0x0 read value: previous value written write effect: modify value em0compare 0 31 24 compare 6 0 t 1 die 1
idt debugging and performance monitoring debug pins 79rc32438 user reference manual 18 - 22 november 4, 2002 notes debug pins the rc32438 provides external debug pins to aid in system debugging. the cpu pin is asserted during all ddr and memory and peripheral bus transactions caused by the cp u. during cpu transactions, the inst pin is asserted if the transaction is due to an in struction fetch. the inst and cpu pins are valid when- ever a memory and peripheral bus chip select is asse rted or when a ddr chip select is asserted during a read or write transaction. table 18.3 describes the operation of these pins. t description: triggered. this bit is set when the count value in the em0count register equals or is greater than the compare value in this register. a subsequent trigger can occur only when the count value becomes less than the compare value (i.e., the counter rolls over or software resets the counter). note : the t bit is not set under the following conditions: (a) when any of the following event indices are selected by event monitor zero: 20 ipbus trans- action, 40 ipbus write transaction, 45 ipbus unaligned transfer transaction, or 46 ipbus merged transaction and (b) an ipbus master accesses the on-chip memory when the count value in the em0count register is equal to or greater than the compare value in that same register. initial value: 0x0 read value: status write effect: sticky bit (a sticky bit is set by the hardware and can only be cleared by the cpu) csnx ddr- csnx cpu inst description 01 1 1. don?t care. 0 x dma read or write from memory and peripheral bus. 0110cpu data r ead or write from memory and peripheral bus. 0111cpu instruction fetch from memory and peripheral bus. 1 0 0 x dma read or write from ddr. 1010cpu data r ead or write from ddr. 1011cpu instruction fetch from ddr. 0 0 x 0 cpu data read or write from ddr with an external dma operation to the memory and peripheral bus. 0 0 x 1 cpu instruction fetch from ddr with an external dma operation to the memory and peripheral bus. table 18.3 debug pin operation
notes 79rc32438 user reference manual 19 - 1 november 4, 2002 chapter 19 jtag boundary scan introduction the rc32438 is a general-purpose in tegrated processor that incorporates a high performance cpu core and a number of on-chip peripherals. there ar e 2 tap controllers on the rc32438, one for the cpu core (referred to as the mips32 cpu core tap cont roller), described in the next chapter (chapter 20), and one for system logic controller, described in this chapter. the system logic tap controller is used to provide conventional standard jtag boundary scan access to the rc32438 pin interface. the mips32 cpu co re tap controller is used to provide access to the ejtag interface on the cpu core. the two tap controllers are connected in parallel as shown in figure 19.1 and share the jtag control pins, except for separate jtag_tms and ejtag_tms pi ns. thus at least one of the two tap controllers must be in test-logic-reset at any given time, so t hat the jtag_tdo pin is onl y actively being driven from no more than one of the tap controllers. for example, if neither tap controller is in use, they both can be reset by asserting jtag_trst_n, or by asserti ng both jtag_tms and ejtag_tms high for 5 consecutive jtag_tcks clocks. if the mips32 cpu core tap controlle r is to be used, then the system controller tap controller must be reset by asserting jtag_tms high for 5 consecutive jtag_tck clocks. if the system controller tap controller is to be used, then the mips32 cpu core tap controller must be reset by asserting ejtag_tms high for 5 consecutive jtag_tck clocks. the mips32 cpu core tap controller is used primarily for ejtag support, since many ejtag func- tions are accessed via the mips32 cpu core tap controller jtag port. note that the boundary scan register for the internal cpu core is not us ed, as it would access internally connected cpu core ports/pins. instead the system controller tap controller boundary scan register is provided for rc32438 conventional jtag pin access, control, and boundary scan. figure 19.1 dual tap controller block diagram boundary scan cells system controller tap cpu core tap ejtag jtag_tck, jtag_tdi, jtag_tms ejtag_tms jtag_tdo boundary scan cells boundary scan cells boundary scan cells jtag_trst_n
idt jtag boundary scan system logic tap controller overview 79rc32438 user reference manual 19 - 2 november 4, 2002 notes system logic tap controller overview the system logic utilizes a 16-state, six-bit tap cont roller, a four-bit instruction register, and five dedi- cated pins to perform a variety of functions. the primary use of the jtag tap controller state machine is to allow the five external jtag control pins to cont rol and access the rc32438's m any external signal pins. the jtag tap controller can also be used for identif ying the device part number. the jtag logic of the rc32438 is depicted in figure 19.2. figure 19.2 diagram of the jtag logic signal definitions jtag operations such as reset, state-transiti on control and clock sampling are handled through the signals listed in table 19.1. a functional overview on the tap controller and boundary scan registers is provided in the sections following the table. the system logic tap controller transitions from st ate to state, according to the value present on jtag_tms, as sampled on the rising edge of jtag_t ck. the test-logic reset state can be reached either by asserting jtag_trst_n or by applying a 1 to jtag_tms for five consecutive cycles of pin name type description jtag_trst_n input jtag reset asynchronous reset for jtag tap controller (internal pull-up) jtag_tck input jtag clock test logic clock. jtag_tms and jtag_tdi are sampled on the rising edge. jtag_tdo is output on the falling edge. jtag_tms input jtag mode select requires an external pull-up. controls the state transitions for the tap controller state machine (internal pull-up) jtag_tdi input jtag input serial data input for bsc chain, instructio n register, idcode register, and bypass register (internal pull-up) jtag_tdo output jtag output serial data out. tri-stated except when shifting while in shift-dr and shift-ir tap con- troller states. table 19.1 jtag pin descriptions bypass register instruction register decoder 4-bit instruction register tap controller m u x m u x device id register boundary scan register jtag_tdi jtag_tms jtag_tck jtag_trst_n jtag_tdo
idt jtag boundary scan test data register (dr) 79rc32438 user reference manual 19 - 3 november 4, 2002 notes jtag_tck. a state diagram for the tap controller appears in figure 19.3. the value next to state repre- sent the value that must be applied to jtag_tms on the next rising edge of jtag_tck, to transition in the direction of the associated arrow. figure 19.3 state diagram of rc32438?s tap controller test data register (dr) the test data register contains the following: ? the bypass register ? the boundary scan registers ? the device id register these registers are connected in parallel betw een a common serial input and a common serial data output, and are described in the following sections. for more detailed descriptions, refer to ieee standard test access port (ieee std. 1149.1-1990). boundary scan registers the rc32438 scan chain is 489 bits long and compri ses 259 logical elements ? where each logical element represents a signal pin. the five jtag pi ns do not have scan elements associated with them, nor does the ejtag ejtag_tms pin. in addition, ddrv ref and plltest do not have scan elements asso- ciated with them. of the 259 logical elements, 141 are tw o-bit bidirectional cells, 89 are two-bit tri-statable outputs, and 29 are one-bit dedicated inputs. this boundary scan chain is connected between jtag_tdi and jtag_tdo when the extest or sample/preload instructions are selected. once extest is selected and the tap controller passes through the update-ir state, whatever value is currently held in the boundary scan register?s output latches is immediately transferred to the corresponding outputs or output enables. test- logic reset run-test/ idle select- dr-scan capture-dr shift-dr exit1 -dr pause-dr exit2-dr select- ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-dr update-ir 11 0 0 0 1 1 0 0 1 1 0 1 0 1 0 0 1 1 1 0 0 11 0 1 0 1 1 0 00 0
idt jtag boundary scan test data register (dr) 79rc32438 user reference manual 19 - 4 november 4, 2002 notes therefore, the sample/preload instruction must first be used to load suitable values into the boundary scan cells, so that inappropriate values ar e not driven out onto the system pins. all of the boundary scan cells feature a negative edge latch, which guarantees that clock skew cannot cause incor- rect data to be latched into a cell. the input cells ar e sample-only cells. the simp lified logic configuration is shown in figure 19.4. figure 19.4 diagram of observe-only input cell the simplified logic configuration of t he output cells is shown in figure 19.5. figure 19.5 diagram of output cell the output enable cells are also bas ically output cells. the simp lified logic appears in figure 19.6. input pin shift_dr from previous cell clock_dr dq to next cell to core logic mux data from core data from previous cell shift_dr to next cell to output pad clock_dr update_dr mux d q dq extest mux
idt jtag boundary scan instruction register (ir) 79rc32438 user reference manual 19 - 5 november 4, 2002 notes figure 19.6 diagram of output enable cell the bidirectional cells are composed of only two boundary scan cells. they contain one output enable cell and one capture cell, which contains only one register. the input to this single register is selected via a mux that is driven selected by the output enable cell when extest is disabled. when the output enable cell is driving a high out to the pad (which enables the pad for output) and extest is disabled, the single capture register will be configured to capture from the output signal from the core to the pad. however, in the case where the output enable is low (signifying a tri-stat e condition at the pad) or extest is enabled, then the capture regi ster will capture from the input from the pad. the configuration is shown graphically in figure 19.7. figure 19.7 diagram of bidirectional cell instruction register (ir) the instruction register allows an instruction to be sh ifted serially into the processor at the rising edge of jtag_tck. the instruction is then used to select t he test to be performed or the test register to be accessed, or both. the instruction shifted into the register is latched at the completion of the shifting process, when the tap controller is at the update-ir state. dq d q from core data from previous cell extest to output enable clock_dr shift_dr update_dr output enable to next cell mux mux from previous cell output enable cell output enable from core extest output from core input to core capture cell to next cell i/o pin mux
idt jtag boundary scan instruction register (ir) 79rc32438 user reference manual 19 - 6 november 4, 2002 notes the instruction register contains six shift-register-based cells that can hold instruction data. these mandatory cells are located near the serial outputs and ar e the least significant bits . the values of the bits are 0 and 1 (1 is the least significant bit). this register is decoded to perform the following functions: ? to select test data registers that may operate wh ile the instruction is current. the other test data registers should not interfere with ch ip operation and selected data registers. ? to define the serial test data register path used to shift data between jtag_tdi and jtag_tdo during data register scanning. the instruction register is comprised of 6 bits to decode instructions as follows in table 19.2. extest the external test (extest) instruction is used to control the boundary scan register, once it has been initialized using the sample/preload instruction. using extest, the user can then sample inputs from or load values onto the external pins of the rc32438. on ce this instruction is selected, the user then uses the shift-dr tap controller state to shift values into the boundary scan chain. when the tap controller passes through the update-dr state, these values w ill be latched onto the output pins or into the output enables. instruction definition opcode extest mandatory instruction allowing the testing of board level interconnections. data is typ- ically loaded onto the latched parallel outputs of the boundary scan shift register using the sample/preload instruction prior to use of the extest instruction. extest will then hold these values on the outputs while being executed. also see the clamp instruction for similar capability. 000000 sample/ preload mandatory instruction that allows data values to be loaded onto the latched parallel output of the boundary-scan shift register prior to selection of the other boundary- scan test instruction. the sample instruction allows a snapshot of data flowing from the system pins to the on-chip logic or vice versa. 000001 device_id provided to select device identification to read out manufacturers identity, part, and version number. 000010 highz tri-states all output and bidirectional boundary scan cells. 000011 reserved behaviorally equivalent to the bypass instruction as per the ieee std. 1149.1 speci- fication. however, the us er is advised to use th e explicit bypass instruction. 000100 ? 100011 unused the unused instru ctions are behaviora lly equivalent to the bypass instruction as per the ieee std. 1149.1 specification. however, the user is advised to use the explicit bypass instruction, as the inte rnal usage of these curr ently unused instructions could possibly vary in future implementations of the device. 100100 ? 101100 validate automatically loaded into the instruction register whenever the tap controller passes through the capture-ir state. the lower two bits ?01? are mandated by the ieee std. 1149.1 specification. 101101 unused same as other unused instructions above. 101110 ? 111100 reserved behaviorally equivalent to the bypass instruction as per the ieee std. 1149.1 speci- fication. however, the us er is advised to use th e explicit bypass instruction. 111101 clamp provides jtag user the option to bypass the part?s jtag controller while keeping the part outputs controlled similar to extest. 111110 bypass the bypass instruction is us ed to truncate the boundary scan register as a single bit in length. 111111 table 19.2 instructions supported by rc32438?s jtag boundary scan
idt jtag boundary scan instruction register (ir) 79rc32438 user reference manual 19 - 7 november 4, 2002 notes sample/preload the sample/preload instruction has a dual use. the prim ary use of this instruction is for preloading the boundary scan register prior to enabl ing the extest instruction. failure to preload will result in unknown random data being driven onto the output pins when extest is selected. the secondary function of sample/preload is for sampling the system state at a particular moment. using the sample function, the user can halt the device at a certain state and shift out the status of all of the pins and output enables at that time. bypass the bypass instruction is used to truncate the boundary scan register to a single bit in length. during system level use of the jtag, the boundary scan chains of all the devices on the board are connected in series. in order to facilitate rapid testing of a gi ven device, all other devices are put into bypass mode. therefore, instead of having to shift 499 times to get a value through the rc32438, the user only needs to shift one time to get the value from jtag_tdi to jtag_tdo. when the tap controller passes through the capture-dr state, the value in the bypass register is updated to be 0. if the device being used does not have a device_id r egister, then the bypass instruction will automat- ically be selected into the instruction register whenever the tap controller is reset. therefore, the first value that will be shifted out of a device without a device_i d register is always 0. devices such as the rc32438 that include a device_id register will automatic ally load the device_id instruction when the tap controller is reset, and they will shift out an initial val ue of 1. this is done to allow the user to easily distin- guish between devices having device _id registers and those that do not. clamp this instruction, listed as optional in the ieee 1149.1 jtag specifications, allows the boundary scan chain outputs to be clamped to fixed values. when t he clamp instruction is issued, the scan chain will bypass the rc32438 and pass through to devic es further down the scan chain. deviceid the deviceid instruction is automatically loaded when the tap controller state machine is reset either by the use of the jtag_trst_n signal or by the applic ation of a ?1? on jtag_tms for five or more cycles of jtag_tck as per the ieee std 1149.1 specification. the least significant bit of this value must always be 1. therefore, if a device has a device_id register, it will shift out a 1 on the first shift if it is brought directly to the shift-dr tap controller state after t he tap controller is reset. the board- level tester can then examine this bit and determine if t he device contains a device_id register (the first bit is a 1), or if the device only contains a bypass r egister (the first bit is 0). however, even if the device contains a device_id r egister, it must also contain a bypass register. the only difference is that the bypass register will not be the default register selected during the tap controller reset. when the device_id instruction is active and the t ap controller is in the shift-dr state, the thirty- two bit value that will be shifted out of the device-id register is 0x00022067 . bit(s) mnemonic description r/w reset 0 reserved reserved 0x1 r 1 11:1 manuf_id manufacturer identity (11 bits) idt 0x33 r0x33 27:12 part_number part number (16 bits) this field identifies the part number of the processor derivative. for the rc32438 this value is: 0x0022 rimpl. dep. 31:28 version version (4 bits) this field identifies the version number of the processor derivative. for the rc32438, this value is 0x0 rimpl. dep. table 19.3 system controller device identification register
idt jtag boundary scan usage considerations 79rc32438 user reference manual 19 - 8 november 4, 2002 notes validate the validate instruction is automatically loaded into the instruction register whenever the tap controller passes through the capture-ir state. the lower two bits ?01? are mandated by the ieee std. 1149.1 specification. reserved reserved instructions implement various test modes used in the device manufacturing process. the user should not enable these instructions. unused 1 the unused instructions are behaviorally equivalent to the bypass instruction as per the ieee std. 1149.1 specification. however, the user is advised to use the explicit bypass instruction as the internal usage of these currently unused instructions could possi bly vary in future implementations of the device. usage considerations as previously stated, there are internal pul l-ups on jtag_trst_n, jtag_tms, and jtag_tdi. however, jtag_tck also needs to be driven to a know n value. however, it is best to drive a zero on the jtag_tck pin when it is not in use or use an exter nal pull-down resistor. in order to guarantee that the jtag does not interfere with normal system operation, the tap controller should be forced into the test- logic-reset controller state by continuously hol ding jtag_trst_n low and/or jtag_tmsnovember 4, 2002 high when the chip is in normal operation. if jtag will not be used, externa lly pull-down jtag_trstn low to disable it. version part number vendor id lsb 0000 0000|0000|0010|0010 0000|0110|011 1 figure 19.8 system controller device id instruction format 1. any unused instruction is defaul ted to the bypass instruction
notes 79rc32438 user reference manual 20 - 1 november 4, 2002 chapter 20 ejtag system introduction this chapter describes the behavior and organizati on of on-chip ejtag hardware resources on the rc32438 device. ejtag is a hardware/software sub system that provides comprehensive debugging and performance tuning capabilities to system-on-a-chip components that include a mips cpu core. it exploits the infrastructure provided by the ieee 1149.1 jt ag test access port (tap) standard to provide an external interface, and it extends the mips instruction set and privileged resource architectures to provide a standard software architecture for integrated system debugging. functional description ejtag provides a standard debug i/o interface, e nabling the use of traditional mips debug facilities on system-on-a-chip components. in addition, ejtag prov ides the following new c apabilities for software and system debug: ? off-board ejtag memory ejtag allows a mips processor in debug mode to refe rence instructions or data that are not resi- dent on the system under test. this ejtag memory is mapped to the processor as if it were physi- cal memory, and references to it are converted into transactions on the tap interface. both instructions and data can be accessed in ejta g memory, which allows debugging of systems with- out requiring the presence of a rom monitor or debugger scratchpad ram. it also provides a com- munications channel between debug software ex ecuting on the processor and an external debugging agent. ? hardware breakpoints ejtag introduces two types of hardware breakpoi nts, which can be configured to cause a debug exception on: ? an instruction fetch from a specific virtual address ? a memory reference from a specific virtual addr ess, which additionally can be qualified by a data value. these breakpoints can be used to implement wa tchpoints and breakpoints in programs executing out of rom or ram. ? single-step execution ejtag provides support for si ngle-step execution of program s and operating systems, without requiring that the code reside in ram. ? system access via the ejtag tap ejtag allows an external debugging agent connected to the ejtag tap to obtain information about the configuration and state of the processo r under test and to force processor entry into debug mode. debug software can then provide fu rther system access via ejtag memory. ? debug breakpoint instruction ejtag introduces a new breakpoint instruction, sdbbp, which differs from the mips32 and mips64 break instruction in that the resulting exception, like the single-step and hardware break- point debug exceptions described above, places th e processor in debug mode and can fetch its associated handler code from ejtag memory. ejtag components ejtag hardware support consists of several distinct components: extensions to the mips processor core, the ejtag test access port, the debug control register, and the hardware breakpoint unit. figure 20.1 shows the relationship between these components on the rc32438 device.
idt ejtag system functional description 79rc32438 user reference manual 20 - 2 november 4, 2002 notes figure 20.1 simplified ejtag block diagram debug control register the debug control register (dcr) is a memory-m apped register that is implemented as part of the processor core and indicates the availability and status of ejta g features. the memory-mapped region containing the dcr is availabl e to software only in debug mode. hardware breakpoint unit the hardware breakpoint unit implements memory -mapped registers that control the instruction and data hardware breakpoints. the memory-mapped region containing the hardware breakpoint registers is accessible to software only in debug mode. ejtag hardware breakpoint support is impl emented with the following functionality: ? supports 4 instructions ? supports 2 data hardware breakpoints ? breakpoint address comparisons for instruction and data hardware breakpoints optionally qualified with a comparison of the mmu asid ? data hardware breakpoints optionally qualified with a data value comparison the presence or absence of hardwar e breakpoint capability is indicated to debug software in the dcr. the number of breakpoints and the availability of optional qualifiers is indicated to debug software in the instruction and data breakpoint status registers. register and memory map overview this section summarizes the regi sters and special memory that are used for the ejtag debug solution. more detailed information regarding mandatory and opti onal registers and memory locations is available in the relevant chapters. processor coprocessor 0 mmu (tlb) cache controller bus interface unit (biu) memory system interface and hardware breakpoint unit pc addr asid type bytelane data debug control register (dcr) debug exception interrupt and nmi control, etc. drseg access bus ejtag tap debug exception control, debug interrupt request, etc. dmseg access bus tap dint debug interrupt request ejtag features non-ejtag features
idt ejtag system functional description 79rc32438 user reference manual 20 - 3 november 4, 2002 notes coprocessor 0 register table table 20.1 summarizes the coprocessor 0 (cp0) registers. these register s are accessible by the debug software executed on the processor; they pr ovide debug control and status information. general information about the debug cp0 registers is found in section ?ejtag coprocessor 0 registers? on page 20-24. memory mapped ejtag register the memory-mapped ejtag registers are located in the debug register segment (drseg), which is a subsegment of the debug segment (dseg). they are a ccessible by the debug software when the processor is executing in debug mode. thes e registers provide both miscell aneous debug control and control of hard- ware breakpoints. general information about the de bug segment and registers is found in section ?debug mode address space? on page 20-7. debug control register table 20.2 summarizes the debug control register (dcr) which provides miscellaneous debug control. instruction hardware breakpoint register table 20.3 summarizes the instruction hardware break point registers, which are controlled through a number of memory-mapped registers. certain registers are provided fo r each implemented instruction hard- ware breakpoint, as indicated with an ?n?. general information about the instruction hardware breakpoint registers is found in section ?instruc tion breakpoint registers? on page 20-43. register name register mnemonic functional description reference debug debug debug indications and controls for the processor, including information about recent debug exception. refer to section ?debug register (cp0 register 23, select 0)? on page 20-25. debug exception program counter depc program counter at last debug excep- tion or exception in debug mode. refer to section ?debug exception program counter register (cp0 register 24, select 0)? on page 20-29. debug excep- tion save desave scratchpad register available for the debug handler. refer to section ?debug exception save register (cp0 register 31, select 0)? on page 20-30. table 20.1 overview of coprocessor 0 registers for ejtag register name register mnemonic functional description reference debug control register dcr indicates available ejtag memory, and controls enable of interrupts and nmi in non-debug mode. refer to section ?debug control register? on page 20-30. table 20.2 overview of debug control regi ster as memory-mapped register for ejtag
idt ejtag system functional description 79rc32438 user reference manual 20 - 4 november 4, 2002 notes data hardware breakpoint register table 20.4 summarizes the data hardware breakpoi nts, which are controlled through a number of memory-mapped registers. certain registers are pr ovided for each implemented data hardware breakpoint, as indicated with an ?n?. general information about the data hardware breakpoint registers is found in section ?data breakpoint registers? on page 20-47. register name register mnemonic functional description reference instruction breakpoint status ibs indicates number of instruction hard- ware breakpoints and status on a previ- ous match. see section ?instruction breakpoint status (ibs) register? on page 20-43. instruction breakpoint address n iban address to compare for breakpoint n. see section ?instruction breakpoint address n (iban) register? on page 20-44. instruction breakpoint address mask n ibmn mask for address comparison for breakpoint n. see section ?instruction breakpoint address mask n (ibmn) register? on page 20-45. instruction breakpoint asid n ibasidn asid value to compare for breakpoint n. see section ?instruction breakpoint asid n (ibasidn) register? on page 20-45. instruction breakpoint con- trol n ibcn control of breakpoint n comparison of asid and generated event on match. see section ?instruction breakpoint control n (ibcn) register? on page 20-46. table 20.3 overview of instruct ion hardware bre akpoint registers register name register mnemonic functional description reference data breakpoint status dbs indicates number of data hardware breakpoints and status on a previous match. see section ?data break- point status (dbs) register? on page 20-47. data breakpoint address n dban address to compare for breakpoint n. see section ?data break- point address n (dban) register? on page 20-48. data breakpoint address mask n dbmn mask for address comparison for breakpoint n. see section ?data break- point address mask n (dbmn) register? on page 20-49. table 20.4 overview of data hardware breakpoint registers (part 1 of 2)
idt ejtag system functional description 79rc32438 user reference manual 20 - 5 november 4, 2002 notes memory-mapped ejtag memory the memory-mapped ejtag memory is located in the debug memory segment (dmseg), which is a subsegment of the debug segment (dseg). it is acce ssible by the debug software when the processor is executing in debug mode. the ejtag probe handles all accesses to this segment through the test access port (tap), whereby the processor has access to dedicated debug memory even if no debug memory was originally located in the system. general info rmation about the debug segment and memory is found in section ?debug mode address space? on page 20-7. ejtag test access port registers the probe accesses ejtag test access port (tap) r egisters (shown in table 20.5) through the tap, so the processor can not access these r egisters. these registers allow specif ic control of the target processor through the tap. general information about the tap regi sters is found in section ?tap data registers? on page 20-59. data breakpoint asid n dbasidn asid value to co mpare for breakpoint n. see section ?data break- point asid n (dbasidn) register? on page 20-49. data breakpoint control n dbcn control of breakpoint n match on load/ store, data bytes, access to data bytes, comparison of asid, and generated event on match. see section ?data break- point control n (dbcn) reg- ister? on page 20-49. data breakpoint value n dbvn data value to match for breakpoint n. see section ?data break- point value n (dbvn) regis- ter? on page 20-51. register name register mnemonic functional description reference device id none identifies device and accessed processor in the device. see section ?device identifi- cation (id) register (tap instruction idcode)? on page 20-61. implementation none identifies main debug features implemented and accessible through the tap. see section ?implementa- tion register (tap instruc- tion impcode)? on page 20-62. data none data register for processor accesses used to support the ejtag memory. see section ?data register (tap instruction data, all, or fastdata)? on page 20-63. table 20.5 overview of test acce ss port registers (part 1 of 2) register name register mnemonic functional description reference table 20.4 overview of data hardware breakpoint registers (part 2 of 2)
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 6 november 4, 2002 notes ejtag processor core extensions overview the extensions for ejtag provi de the following major features: ? debug mode, associated exceptions and dedicated debug vector ? instruction set extensions: sdbbp (softw are debug breakpoint) and deret (debug exception return) ? cp0 registers: debug, depc and desave ? memory-mapped debug segment (dseg) ? interrupt and nmi control ? single step ? debug interrupt request signal debug mode execution debug mode is entered only through a debug exception. it is exited as a result of either execution of a deret instruction or application of a reset or soft reset. when the processor is operating in debug mode it has access to the same resources, instructions, and cp0 registers as in kernel mode. restrictions on kernel mode access (non-zero coprocessor references, access to extended addressing controlled by ux, sx, kx, etc.) apply equally to debug mode, but debug mode provides some additional capabilit ies as described in this chapter. other processor modes (kernel mode, supervisor m ode, user mode) are collectively considered as non-debug mode. debug software c an determine if the processor is in non-debug mode or debug mode through the dm bit in the debug register. debug mode instruction set the full native isa of the processor is accessible in debug mode. coprocessor loads and stores to the dseg segment are not supported. the operation of the processor is undefined if a coprocessor load or store to dseg is executed in debug mode. refer to section ?debug mode address space? on page 20-7 for more information on the dseg address space. address none address register for processor access used to support the ejtag memory. see section ?address regis- ter (tap instruction address or all)? on page 20-64. ejtag control ecr control register for most ejtag features used through the tap. see section ?ejtag control register (ecr) (tap instruction control or all)? on page 20-65. bypass none provides a one-bit shift path through the tap. see section ?bypass regis- ter (tap instruction bypass, (ejtag/nor- mal) boot, or unused)? on page 20-70. register name register mnemonic functional description reference table 20.5 overview of test acce ss port registers (part 2 of 2)
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 7 november 4, 2002 notes debug mode address space debug mode access to unmapped address space is identic al to that of kernel mode. mapped areas are accessible as in kernel mode, but only if a vali d translation is possible i mmediately by the mmu. the reason is that a memory accesses that would cause an tlb-type exception if tried from kernel mode will cause re-entry into debug mode (see section ?d ebug mode exceptions? on page 20-19) through an excep- tion if the memory access is tried while in debug m ode. memory accesses usually causing tlb-type excep- tion are therefore not handled by the usual memory management routines if these memory accesses are made while in debug mode. updating and handling of cac hed areas is the same as that in kernel mode. in addition, an uncached and unmapped debug segment dseg (ejtag area) appears in the address range 0xff20 0000 to 0xff3f ffff. the dseg thereby appears in the ks eg part of the compatibility segment, and access to kseg is possible with dseg pr ovided as described in se ction ?debug mode address space? on page 20-7. coprocessor loads and stores to dseg are not allowed. the dseg area is implemented only if the debug cont rol register (dcr) is included in the implementa- tion. refer to ?debug control register? on page 20-30 for additional information on the dcr. the imple- mentation-dependent value of the nodcr bit in the debug register (see section ?debug register (cp0 register 23, select 0)? on page 20-25) indicates the pr esence of the dseg segment as shown in table 20.6. if dseg is not present, then all transactions from the processor in debug mode go to the kernel mode address space. debug software must check the d ebugnodcr bit before trying to access the dseg segment. conditions for access to dseg ar e described in section ?access to dmseg (ejtag memory) address range? on page 20-9 and section ?access to drseg (ejtag registers) address range? on page 20-10. figure 2-1 shows the layout of the virtual address space. nodcr bit in debug register dseg presence 0 dseg present 1 no dseg table 20.6 overview of t est access port registers
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 8 november 4, 2002 notes figure 20.2 virtual address spaces with debug mode segments the dseg segment is subdivided into dmseg (ejtag memory) segment and t he drseg (ejtag regis- ters) segment. the dmseg segment is used when t he probe services the memory segment. the drseg segment is used when the memory-mapped debug register s are accessed. table 20.7 shows the subdivi- sion and attributes for the segments. 0x4000 0000 0x8000 0000 virtual memory address space 32-bit compatibility address space 0xffff ffff 0xe000 0000 0xc000 0000 0xa000 0000 0x8000 0000 0x7fff ffff 0x0000 00000 0xc000 0000 xkseg xkphys xsseg xuseg useg kseg0 kseg1 sseg kseg3 kernel unmapped kernel mapped supervisor mapped kernel unmapped uncached user mapped kernel mapped supervisor mapped kernel unmapped user mapped 2 31 -byte compatibility segment 2 31 -byte compatibility segment user mapped debug unmapped uncached 0xff3f ffff dseg 0xff20 0000 debug mode segment the dseg appears at an address range also used for access to kseg. however, kseg is still available when in debug mode.
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 9 november 4, 2002 notes the sync instruction, followed by appropriate spac ing (as described in section ?sync instruction behavior? on page 20-11 and section ?cp0 and dseg ha zards? on page 20-12) must be executed to ensure that an access to dseg is committe d (for example, after writing to dseg and before leaving debug mode). this procedure ensures that locations in dseg ar e fully updated for non-debug mode, otherwise behavior of the processor is undefined. access to dmseg (ejtag memory) address range table 20.8 shows the behavior of processor access es in debug mode to the dmseg address range from 0xff20 0000 to 0xff2f ffff. note: when proben equals 0 for dmseg accesses, debug software accessed dmseg when the proben bit was 0, indicating that there is no probe available to service the request. debug software must read the state of the proben bit in the dcr register before attempting to reference dmseg. however, accessing dmseg while proben is 0 can occur because there is an inherent race between the debug software sampling the proben bit as 1 and the probe clearing it to 0. the probe can therefore not assume that a reference to dmseg never occurs if the proben bit is dynamically cleared to 0. if debug software referenc es dmseg when proben is 0, the reference hangs until it is satisfied by the probe. segment name subseg- ment name virtual address reference address cache attribute dseg dmsg 0xff20 0000 to 0xff2f ffff because the dseg address range is serviced exclusively by the ejtag features, there are no physical address per se. instead the lower 21 bits of the virtual address select the appropriate reference in either ejtag mem- ory or registers. references are not mapped through the tlb, nor do the accesses appear on the external system memory interface. uncached dreg 0xff30 0000 to 0xff3f ffff table 20.7 physical address and cache attribute for dseg?s dmsg and drseg nodcr bit in debug register trans- action proben bit in dcr register lsnm bit in debug register access 1x 1 1. x = don?t care (not present) 0 (read only) kernel mode address space 0 fetch 1 x dmseg 0 x see note below table on proben behavior load/store 1 0 dmseg 1 kernel mode address space 0 1 kernel mode address space 0 see note below table on proben behavior table 20.8 access to dmseg address range
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 10 november 4, 2002 notes there are no timing requirements with respect to transactions to dmseg, which the probe services. therefore, a system watchdog must be disabled during dseg transactions, so accesses can take any amount of time without being terminated. the protocol for accesses to dmseg does not allow a transaction to be aborted once started, except by a reset or soft re set. transactions of all sizes are allowed to dmseg. merging is allowed for accesses to dmseg, wher eby for example two byte accesses can be merged to one halfword access, and debug software is thus required to allow merging. however, merging must only occur for accesses which can be combined into legal processors accesses, since processor access can only indicate accesses which can occur due to a singl e load/store, thus not for example accesses to only first and last bytes of a word. the sync instruction, followed by appropriate spacing, can be executed to ensure that earlier accesses to dmseg are committed thus will not be merged with later accesses. the processor can do speculative fetching from dmseg whereby it can fetch doublewords even if an instruction that is not required in the execution flow is thereby fetched. for example, if the deret instruc- tion is fetched as the first word of a doubleword, the instruction in the second word is not executed. for details, refer to architecture description coveri ng speculative fetching from uncached area in general. if the tap is not present in the implementation, t he operation of the processor is undefined if the dmseg is accessed. access to drseg (ejtag registers) address range note: instruction fetches from drseg are not al lowed. the operation of the processor is undefined if the processor tries to fetch from drseg. when the nodcr bit is 0 in the debug register, it indi cates that the processor is allowed to access the entire drseg segment and can therefore respond to all transactions to drseg. the dcr register, at offset 0x0000 in drseg, is always available if dseg is present. debug software is expected to read the dcr register to determine what other memory-mapped register s exist in drseg. the value returned in response to a read of any un- implemented memory-mapped r egister is unpredict- able, and writes are ignored to any un-implemented regi ster in drseg. the allowed transaction size is limited for drseg. only word size transactions are allowed for 32- bit processors, and only doubleword size transactions are allowed for 64-bit pr ocessors. operation of the processo r is undefined fo r other transac- tion sizes. debug mode handling of processor resources unless otherwise specified, the processor resource s in debug mode are handled identically to those in kernel mode. some identical cases are described in the following sect ions for emphasis. in addition, see the following related sections for more information: ?debug mode exceptions? on page 20-19 cove ring exception handling in debug mode. ?interrupts and nmis? on page 20-21 for handling in both debug and non-debug modes. ?reset and soft reset of processor? on page 20-22 for handling in both debug and non-debug modes. nodcr bit in debug register trans- action lsnm bit in debug register access 1x 1 1. x = don?t care 0 (read only) kernel mode address space fetch x operation of the processor is unde- fined at fetch. load/store 0 drseg 1 kernel mode address space table 20.9 access to drseg address range
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 11 november 4, 2002 notes coprocessors a debug mode coprocessor unusable exception is raised under the sa me conditions as for a copro- cessor unusable exception in kernel mode (see se ction ?exceptions taken in debug mode? on page 20- 19). therefore, debug mode software cannot reference c oprocessors 1 through 2 without first setting the respective enable in the status register. random register the random register (cp0 register 1, select 0) can be frozen in debug mode, whereby execution with and without debug exceptions are identic al with respect to tlb exception handling. if the values that the random register provides cannot be identical in behavior to the case where debug exceptions do not occur, then freezing the random register has no effect, because execution wi th and without debug exceptions will not be identical. stalls when entering debug mode (for example, due to pending scheduled loads resolved at context save in the debug handler) can make it impos sible in some implementations to ensure that the random register will provide the same set of values when running with and without debug exceptions. there is no bit to indicate or control if the random register is frozen in debug mode, so the user must consult system documentation. counter register the count register (cp0 register 9) operation in debug mode depends on the state of the countdm bit in the debug register (see section ?debug register (cp0 register 23, select 0)? on page 20-25). the count register has three possible configur ations, depending on the implementation: ? count register runs in debug mode the same as in non-debug mode ? count register is stopped in debug mode but is running in non-debug mode ? the countdm bit controls the count register behavior in debug mode whereby it can be either running or stopped. stopping of the count register in debug mode is allow ed in order to prevent generation of an interrupt at every return to non-debug mode, if the debug handler takes so long to execute that the count/compare registers request an interrupt. in this case, system timing behavior might not be the same as if no debug exception occurred. watchlo/watchhi registers the watchlo/watchhi registers (cp0 registers 18 and 19) are inhibit ed from matching any instruction executed in debug mode. load linked (ll/lld) and store co nditional (sc/scd) instruction pair a deret instruction does not clear the llbit (see section ?deret instruction? on page 20-24), neither does the occurrence of a debug exception. loads and st ores to uncacheable locations that do not match the physical address of the previous ll instruction do not af fect the result of sc instruction. the value of the llbit is not directly visible by software. sync instruction behavior the sync instruction is used to request the hardwar e to commit certain oper ations before proceeding. for example, a sync is required to remove memory haz ards on reference to dseg. also, the sync instruc- tion ensures that status bits in the debug register and the hardware breakpoint registers are fully updated before the debug handler accesses them and before debug mode is exited. similarly, a sync combined with appropriate spacing is used to remove coproces sor 0 (cp0) hazards (see the next section, cp0 and dseg hazards). the sync instruction must provi de specific behavior as described in table 20.10.
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 12 november 4, 2002 notes the sync instruction must be exec uted before leaving debug mode in order to commit all accesses to dseg, such as accesses to set up hardware breakpoints. it may be necessary to remove hazards in relation to the sync instruction. other requirements of the sync instruction is described in the mips32 and mips64 specifications. cp0 and dseg hazards because resources controlled via coprocessor 0 and ejtag memory and registers in dseg affect the operation of various pipeline stages of the processor, manipulation of these resources may produce results that are not detectable by subsequent instructions for some number of execution cycles. when no hard- ware interlock exists between one instruction that causes an effect that is visible to a second instruction, a cp0 or dseg hazard exists. implementations can place the entire burden on t he debug software to pad the instruction stream in such a way that the second instruction is spaced far en ough from the first that the effects of the first are seen by the second. otherwise, the implementations can add full hardwar e interlocks such that the debug software need not pad. the trade-off is between debug software changes for each new processor vs. more complex hardware interlocks required in the processor. the ejtag architecture does not dictate the solu- tion that is required for a compatible implementation. the choice of implementat ion ranges from full hard- ware interlocks to full dependence on debug software paddi ng, to some combination of the two. for an implementation choice that relies on debug software padding, see table 20.11 which lists the ?typical? spacing required to allow the consumer to eliminate t he hazard. the ?required? val ues shown in this table represent spacing that is required to be used by debug software. an implementation which requires less spacing to clear the hazard (incl uding one which has full hardware inte rlocking) should operate correctly with the debug software that uses this hazard table. an implementation which requires more spacing to clear the hazard incurs the burden of validatin g debug software against the new hazard requirements. behavior references commit accesses to dseg see section ?debug mode address space? on page 20-7. update the ddblimpr and ddbsimpr bits in the debug register see section ?debug data break load/store imprecise exception? on page 20-17 and section ?debug register (cp0 register 23, select 0)? on page 20-25. update the bs bits in the ibs and dbs registers in drseg see section ?debug exception by data breakpoint? on page 20-40. update the ibusep, dbusep, cacheep, and mcheckp bits in the debug register see section ?exceptions on impre- cise errors? on page 20-20 and section ?debug register (cp0 register 23, select 0)? on page 20- 25. table 20.10 sync instruction references
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 13 november 4, 2002 notes dependencies from the sync instruction as producer takes effect since specific updates of dseg memory and resolving of pending imprec ise exception indications are tr iggered by the sync instruction. this is described in the sync instruction behavior section. note that, for superscalar mips implementa- tions, the number of instructions issued per cycle may be greater than one, and thus that the duration of the hazard in instructions may be greater than the duration in cycles. for this reason, the ssnop instruction is defined to convert instruction issues to cycles in a superscalar design. ssnop instruction behavior the ssnop instruction ensures that instructions are executed and not eliminat ed by processors during optimization. the ssnop instruction can be used, fo r example, with execution of the sync and mtc0/ dmtc0 instruction to remove cp0 and dseg hazards. debug exceptions debug exceptions bring the processor from n on-debug mode into debug mode. implementations need only support those debug exceptions that are applicable to that implementation. exceptions can occur in debug mode, and these are denoted as debug mode except ions. these exceptions are handled differently from exceptions that occur in non-debug mode, as described in section ?debug mode exceptions? on page 20-19. debug exception priorities table 20.12 lists the exceptions that can occur in non-debug mode in order of priority, from highest to lowest. the table also categorizes each excepti on with respect to type (debug or non-debug). each debug exception has an associated status bit in the debug r egister (indicated in the table in parentheses). for additional information, refer to section ?debug r egister (cp0 register 23, select 0)? on page 20-25. producer consumer hazard on ?required? spacing (cycles) sync deret dseg memory locations 2 sync load/store bs bits in the ibs and dbs registers in drseg 2 sync mfco debug debug ddbsimpr debug ddblimpr debug ibusep debug dbusep debug cacheep debug mcheckp 2 mtco depc depc 2 mtco debug deret debug 2 mtco debug[lsnm] load/store in dseg debug[lsnm] 3 mtco debug[iexi] instructions that can cause an imprecise exception debug[iexi] 3 table 20.11 ?required? cp0 and dseg hazard spacing
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 14 november 4, 2002 notes the specific implementation determ ines which exceptions can occu r and the priority of asynchronous exceptions, such as interrupts. debug exception vector location the same debug exception vector location is used for all debug exceptions. the probtrap bit in the ejtag control register (ecr) in the optional test access port (tap) determines the vector location. priority exception exception type highest reset non-debug soft reset debug single step debug debug interrupt; by external signal (dint), from ejtagbrk in tap, or through use of ejtag boot. debug data break load/store imprecise (ddblimpr/ddbsimpr). nonmaskable interrupt (nmi) non-debug machine check interrupt deferred watch debug instruction break debug watch on instruction fetch non-debug address error on instruction fetch tlb refill on instruction ifetch tlb invalid on instruction ifetch cache error on instruction ifetch bus error on instruction ifetch debug breakpoint; execution of sdbbp instruc- tion debug other execution-based exceptions non-debug debug data break on load/store address match only or debug data break on store address+data value match debug watch on data access non-debug address error on data access tlb refill on data access tlb invalid on data access tlb modified on data access cache error on data access bus error on data access lowest debug data break on load address+data match debug table 20.12 priority of non-debug and debug exceptions
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 15 november 4, 2002 notes general debug exception processing all debug exceptions have the same basic processing flow: ? the depc register is loaded with the pc at whic h execution can be restarted, and the dbd bit is set to indicate whether the last debug exception occurred in a branch delay slot. the value loaded into the depc register is either t he current pc (if the instruction is not in the delay slot of a branch) or the pc of the branch or jump (if the instruct ion is in the delay slot of a branch or jump). ? the dss, dbp, ddbl, ddbs, dib, dint, ddblimpr , and ddbsimpr bits in the debug register are updated appropriately depending on the debug exception. ? dexccode field in the debug register is undefined. ? halt and doze bits in the debug register are updated appropriately. ? iexi bit is set to inhibit imprecise ex ceptions in the start of the debug handler. ? dm bit in the debug register is set to 1. ? the processor begins fetching instruct ions from the debug exception vector. the value loaded into the depc register represent s the restart address from the debug exception and does not need to be modified by the debug exception handler software. debug software need only look at the dbd bit in the debug register if it wishes to ident ify the address of the instruction that actually caused a precise debug exception. the dss, dbp, ddbl, ddbs, dib, dint, ddblimpr , and ddbsimpr bits in the debug register indicate the occurrence of distinct debug exceptions, exc ept when a debug data break load/store imprecise exception occurs (see section ?debug data break load/store imprecise exception? on page 20-17). note that occurrence of an exception while in debug mode will clear these bits. the handler can thereby deter- mine whether an debug exception or an exception in debug mode occurred. no other cp0 registers or fields are changed due to the debug exception, thus no additional state is saved. the overall exception processing flow is shown below: operation : if (instructioninbranchdelayslot) then depc branchinstructionpc debugdbd 1 else depc pc debugdbd 0 endif debugdss, dbp, ddbl, ddbs, dib, dint, dd blimpr and ddbsimpr debugexceptiontype debugdexccode unpredictable debughalt haltstatusatdebugexception debugdoze dozestatusatdebugexception debugiexi 1 probtrap bit in ecr register debug exception vector address 0 0xbfc0 0480 1 0xff20 0200 in dmseg table 20.13 debug exception vector location
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 16 november 4, 2002 notes debugdm 1 if ecrprobtrap = 1 then pc 0xff20 0200 else pc 0xbfc0 0480 endif debug breakpoint exception a debug breakpoint exception occurs when an sdbbp instruction is executed. the contents of the depc register and the dbd bit in the debug register indicate that the sdbbp instruction caused the debug exception. debug register debug status bit set dbp additional state saved none entry vector used debug exception vector debug instruction break exception a debug instruction break exception occurs w hen an instruction hardwar e breakpoint matches an executed instruction. the depc register and dbd bit in the debug register indicate the instruction that caused the instruction hardware breakpoint match. debug register debug status bit set dib additional state saved none entry vector used debug exception vector debug data break load/store exception a debug data break load/store exception occurs when a data hardware breakpoint matches the load/ store address of an executed load/store instruction. the depc register and dbd bit in the debug register indicate the load/store instruction that caused the data hardware breakpoint to match, as this is a precise debug exception. the load/store instruction that c aused the debug exception has not completed (it has not updated the destination register or memory location) , and the instruction therefore is executed on return from the debug handler. debug register debug status bit set ddbl for a load instruction or ddbs for a store instruction additional state saved none entry vector used debug exception vector
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 17 november 4, 2002 notes debug data break load/store imprecise exception a debug data break load/store imprecise exception occurs when a data hardware breakpoint matches a load/store access of an executed load/store instructio n, if it is not possible to take a precise debug excep- tion on the instruction. this case occurs when a data hardware breakpoint was set up with a value compare, and a load access did not return data until a fter the load instruction had left the pipeline as for non-blocking loads. the depc regist er and the dbd bit in the debug register indicate an instruction later in the execution flow instead of the load/store instruct ion that caused the data hardware breakpoint to match. the ddblimpr/ddbsimpr bits in the debug register indicate that a debug data break load/store impre- cise exception occurred. the instruction that c aused the debug data break load/store imprecise excep- tion will have completed. it updates its destination r egister, and is not executed on return from the debug handler. imprecise debug exceptions from data hardware breakpoints are i ndicated together with another debug exception if the load/store transaction that made the data hardware breakpoint match did not complete until after another debug exception occurred. in this case, the other debug exception was the cause of entering debug mode, so the depc register and the dbd bit in d ebug register point to this instruction. ddblimpr/ ddbsimpr are set concurrently with th e status bit for that debug exception. the sync instruction, followed by appropriate spac ing (as described in section ?sync instruction behavior? on page 20-11 and section ?cp0 and dseg ha zards? on page 20-12), must be executed in debug mode before the ddblimpr and ddbsimpr bits in the debug register and the bs bits for the data hardware breakpoint are read in order to ens ure that all imprecise breaks are resolved and the bits are fully updated. a match of the data hardware break point is indicated in ddblimpr/ddbsimpr so the debug handler can handle this together with the debug exception. this scheme ensures that all breakpoints matchi ng due to code executed before the debug exception are indicated by the ddblimpr, ddbsimpr, and bs bits for the following debug handler. matches are neither queued nor do they cause debug exceptions at a later point. a debug exception occurring later than the debug exception handler is therefor caused by code executed in non-debug mode after the debug exception handler. debug register debug status bit set ddblimpr for a load instruction or ddbsimpr for a store instruction additional state saved none entry vector used debug exception vector debug single step exception when single-step mode is enabled, a debug single step exception occurs each time the processor has taken a single execution step in non-debug mode. an ex ecution step is a single instruction, or an instruc- tion pair consisting of a jump/branch instruction and the instruction in the associated delay slot. the sst bit in the debug register enables debug single step except ions. they are disabled on the first execution step after a deret. the depc register points to the instruction on wh ich the debug single step exception occurred, which is also the next instruction to execute when retu rning from debug mode. the debug software can examine the system state before this instruction is executed. thus the depc will not point to the instruction(s) that have just executed in the execution step, but rather the instruction following the execution step. the debug single step exception never occurs on an instruction in a jump/branch delay slot, because the jump/branch and the instruction in the delay slot are always ex ecuted in one execution step; thus the dbd bit in the debug register is never set fo r a debug single step exception.
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 18 november 4, 2002 notes exceptions occurring on the instruction(s) in the execution step are taken r egardless, so if a non-debug exception occurs (other than reset or soft reset), a debug single step exception is taken on the first instruc- tion in the non-debug exception handler. the non-debug exc eption occurs during the execution step, and the instruction(s) that received a non-debug exception counts as the execution step. debug exceptions are unaffected by single-step mode; returning to an sdbbp instruction with single step enabled causes a debug breakpoint ex ception with the depc register pointing to the sdbbp instruc- tion. also, returning to an instruction (not jump/br anch) just before the sdbbp instruction causes a debug single step exception with the depc regi ster pointing to the sdbbp instruction. to ensure proper functionality of single-step execut ion, the debug single step exception has priority over all exceptions, except resets and soft resets. debug single step exception is only possible when the nosst bit in the debug register is 0 (see section ?debug register (cp0 register 23, select 0)? on page 20-25). debug register debug status bit set dss additional state saved none entry vector used debug exception vector debug interrupt exception the debug interrupt exception is an asynchronous debug exception that is tak en as soon as possible, but with no specific relation to the executed instruct ions. the depc register and the dbd bit in the debug register reference the instruction at which exec ution can be resumed after debug interrupt exception service. debug interrupt requests are ignored when the pr ocessor is in debug mode, and pending requests are cleared when the processor takes any debug except ion, including debug exceptions other than debug interrupt exceptions. a debug interrupt restarts the pipeline if stopped by a wait instruction and the processor clock is restarted if it was stopped due to a low-power mode. debug register debug status bit set dint additional state saved none entry vector used debug exception vector the possible sources for debug interrupts depend on the implementation. the following sources can cause debug interrupt exceptions: ? the dint signal from the probe note: this signal is not connected on the rc32438. ? the ejtagbrk bit in the ejtag control register the ejtagbrk bit in the ejtag control register requests a debug interrupt exception when set (see section ?ejtag control register (ecr) (tap instruction control or all)? on page 20-65). ? a debug boot by ejtagboot the ejtagboot feature allows a debug interrupt to be requested immediately after a reset or soft reset has occurred (see section ?ejtagboot feature? on page 20-22 and section ?ejtagboot and normalboot instructions? on page 20-59).
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 19 november 4, 2002 notes ? an implementation-specific debug in terrupt signal to the processor through the availability of an optional debug inte rrupt request signal to t he processor system, an external device can request a debug interrupt e xception, for example, when a signal goes from deasserted to asserted. debug mode exceptions the handling of exceptions generated in debug mode, other than through resets and soft resets, differs from those exceptions generated in non-debug mode in that only the debug and depc registers are updated. all other cp0 registers are unchanged by an exception taken in debug mode. the exception vector is equal to the debug exception vector (see section ?debug exception vector location? on page 20- 14), and the processor stays in debug mode. reset and soft reset are handled as when occurring in non-debug mode (see section ?reset and soft reset of processor? on page 20-22). exceptions taken in debug mode only some non-debug mode exception events caus e exceptions while in debug mode. remaining events are blocked. exceptions occurring in debug m ode have the same relative priorities as the non- debug mode exceptions for the same exception event. these except ions are called debug mode . for example, a debug m ode breakpoint exception is caused by execution of a break instruction in debug mode, and a debug mode address error exc eption is caused by an address error due to an instruction executed in debug mode. table 20.14 lists all the debug mode exceptions with their corresponding non-debug exception event names, priorities, and handling. priority event in debug mode debug mode handling highest reset reset and soft reset handled as for non-debug mode, see sec- tion ?reset and soft reset of processor? on page 20-22. soft reset debug single step blocked debug interrupt debug data break load/store imprecise nmi machine check re-enter debug mode interrupt blocked deferred watch debug instruction break, dib watch on instruction fetch address error on instruction ifetch re-enter debug mode tlb refill on instruction ifetch tlb invalid on instruction ifetch cache error on instruction ifetch bus error on in struction ifetch table 20.14 priority of non-debug and debug exceptions (part 1 of 2)
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 20 november 4, 2002 notes the specific implementation determi nes which exceptions can occur. exceptions that are blocked in debug mode are simply ignored, no t causing updates in any state. handling of the exceptions causing debug mode re-enter are described below. exceptions on imprecise errors exceptions on imprecise errors are possible in d ebug mode due to a bus error on an instruction fetch or data access, cache error, or machine check. the iexi bit in the debug register blocks imprecise error exceptions on entry or re-entry into debug mode. they can be re-enabled by the debug exception handler once suff icient context has been saved to allow a safe re-entry into debug mode and the debug handler. pending exceptions due to instruction fetch bus er rors, data access bus errors, cache errors, and machine checks are indicated and controlled by the ibusep, dbusep, cacheep and mcheckp bit in the debug register. the sync instruction, followed by appropriate sp acing, must be executed in debug mode before the ibusep, dbusep, cacheep, and mcheckp bits are r ead in order to ensure that all pending causes for imprecise errors are resolv ed and all bits are fully updated. those bits required to handle the pos sible imprecise errors in an impl ementation are implemented as r/ w, otherwise they are read only. debug mode excep tion processing all exceptions that are allowed in debug mode (e xcept for reset and soft reset) have the same basic processing flow: ? the depc register is loaded with the pc at whic h execution will be restarted and the dbd bit is set appropriately in the debug register. the value loaded into the depc register is either the current pc (if the instruction is not in the delay slot of a branch or jump) or the pc of the branch or jump if the instruction is in the delay slot of a branch or jump). ? the dss, dbp, ddbl, ddbs, dib, dint, ddblimpr , and ddbsimpr bits in the debug register are all cleared to differentiate from debug excepti ons where at least one of the bits are set. ? the dexccode field in the debug register is updated to indicate the type of exception that occurred. debug breakpoint; execution of sdbbp instruc- tion re-enter debug mode as for execution of the break instruc- tion other execution-based exceptions re-enter debug mode debug data break load/store address match only or debug data break store address+data value match blocked watch on data access address error on data access re-enter debug mode tlb refill on data access tlb invalid on data access tlb modified on data access cache error on data access bus error on data access lowest debug data break on load address+data match blocked priority event in debug mode debug mode handling table 20.14 priority of non-debug and debug exceptions (part 2 of 2)
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 21 november 4, 2002 notes ? the halt and doze bits in the debug register are unpredictable. ? the iexi bit is set to inhibit imprecise exceptions at the start of the debug handler. ? the dm bit in the debug register is unc hanged, leaving the processor in debug mode. ? the processor is started at the debug exception ve ctor, specified in section ?debug exception vec- tor location? on page 20-14. the value loaded into the depc regi ster represents the restart addre ss for the exception. typically, debug software does not need to modify this value at the location of the debug exception. debug software need not look at the dbd bit in the debug register unless it wishes to identify the address of the instruction that actually caused the exception in debug mode. it is the responsibility of the debug handler to sa ve the contents of the debug, depc, and desave registers before nested entries into the handler at the debug exception vector can occur. the handler returns to the debug exception handler by a jump instruction, not a deret, in order to kept the processor in debug mode. the cause of the exception in debug mode is indicated through the dexccode field in the debug register, and the same codes are used for the except ions as those for the exccode field in the cause register when the exceptions with the same names occur in non-debug mode, with addition of the code 30 (decimal) with the mnemonic cacheerr for cache errors. no other cp0 registers or fields are changed due to the exception in debug mode. the overall processing flow for exceptions in debug mode is shown below: operation: if (instructioninbranchdelayslot) then depc branchinstructionpc debugdbd 1 else depc pc debugdbd 0 endif debugdss, dbp, ddbl, ddbs, dib, dint, ddblimpr and ddbsimpr 0 debugdexccode debugexceptiontype debughalt unpredictable debugdoze unpredictable debugiexi 1 if ecrprobtrap = 1 then pc 0xff20 0200 else pc 0xbfc0 0480 endif interrupts and nmis interrupts interrupts are requested through either asserted exter nal hardware signals or in ternal software-control- lable bits. interrupt excepti ons are disabled when any of t he following conditions are true: ? the processor is operating in debug mode ? the interrupt enable (inte) bit in the debug cont rol register (dcr) is cleared (see section ?debug
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 22 november 4, 2002 notes control register? on page 20-30) ? a non-ejtag related mechanism disables the interrupt exception. a pending interrupt is indicated through the cause regi ster, even if interrupt exceptions are disabled. nmis an nmi is requested on the asserting edge of the nmi signal to the processor, and an internal indicator holds the nmi request until the nmi exception is actually taken. nmi exceptions are disabled when either of the following is true: ? the processor is operating in debug mode ? the nmi enable (nmie) bit in the debug contro l register (dcr) is cleared (see section ?debug control register? on page 20-30). if an asserting edge on the nmi signal to the processor is detected while nmi exception is disabled, then the nmi request is held pending and is deferred until nm i exceptions are no longer disabled. a pending nmi is indicated in the nmipend bit in the dcr even if nmi exceptions are disabled. reset and soft reset of processor for ejtag features, there are no differences between a reset and a soft reset occurring to the cpu core; they behave identically in both debug mode and non- debug mode. in this section, references to reset include both reset (hard reset) and soft reset, ejtagboot feature the ejtagboot feature allows a debug interrupt to be requested as a result of a reset, whereby a debug interrupt exception is taken right after reset, and before any of the instructions from the reset exception handler are executed. the debug exception handler is, in this case, provided by the probe through dmseg, even if no instructions can be fetched from the reset exception handler. control and details of ejtagboot are described in section ?ejtag boot and normalboot instructions? on page 20-59. reset from probe while asserted, the rstn signal from the probe is required to generate a reset or soft reset to the system. the srste bit in the debug control register does not mask this source. for more information, see section ?system reset signal? on page 20-77. processor reset by probe through test access port the prrst bit in the ejtag control register c an optionally cause a reset depending on the implementa- tion. if a reset occurs, then all par ts of the system are reset, becaus e partial resets are not allowed. reset occurred indication through test access port the rocc bit in the ejtag control register is set at both reset and soft reset in order to indicate the event to the probe. refer to section ?ejtag control register (ecr) (tap instruction control or all)? on page 20-65 for more information on the ejtag control register. soft reset enable the optional soft reset enable (srste) bit in the d ebug control register (dcr) can mask the soft reset signal outside the processor. because srste masks the so ft reset signal before it arrives at the processor, there is no masking of soft reset within the processor itself. reset of other debug features the operation of processor resets and soft rese ts also apply to resets of the following: ? debug control register (dcr) ? hardware breakpoint ? test access port (tap) ejtag control register , (see ?ejtag test access port? on page 20-54.)
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 23 november 4, 2002 notes ejtag instructions the sdbbp and deret instructions are added to the cpu core?s instruction set as part of the required ejtag features. sdbbp instruction format: sdbbp code mips16 / mips32 / mips64 purpose: to cause a debug breakpoint exception description: if the processor is operating in non-debug mode, then a debug breakpoint exception occurs, immedi- ately and unconditionally transferring control to the debug exception handler. if the processor is operating in debug mode, then a debug mode exception occurs, re sulting in an immediate and unconditional re-entry into the debug exception handler with the debugdexccode field indicating bp. the code field is available as a software parameter. the debug exception handler re trieves it only by loading the contents of the memory containing the instruction. restrictions: none. operation: if (debugdm = 0) then initiatedebugbreakpointexception() else initiatedebugmodebreakpointexception() endif exceptions: debug breakpoint exception debug mode breakpoint exception software debug breakpoint sdbbp 31 0 6 20 spec2 26 25 sdbbp 6 65 mips32? mips64? 15 0 5 rr 11 10 sdbbp 5 54 mips16? 6 code 0 1 1 1 0 0 1 1 1 1 1 1 code 0 0 0 0 1 1 1 1 0 1
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 24 november 4, 2002 notes deret instruction format: deret mips32 / mips64 purpose: return from debug exception description: the deret instruction returns from debug mode and resumes non-debug execution at the instruction pointed to by the depc register. deret does not execute the next instruction (it has no delay slot). restrictions: this instruction is legal only if the processor is executing in debug mode, and the deret instruction is not placed in a delay slot of a branch or a jump inst ruction. if the deret instruction is executed in user mode when the statuscu0 bit is cl eared, then a coprocessor unusable exception occurs. if the deret instruction is executed in other circumstances including if placed in the delay slot of a branch or a jump instruction when the processor is executing in d ebug mode, then operation of the processor is unde- fined. if the depc register with the return address for deret was modified by an mtc0/dmtc0 instruction, then it must be followed by an appropriate spaci ng (refer to section ?cp0 and dseg hazards? on page 20- 12) before a deret instruction in order to remove cp0 hazards. deret implements a software barrier for all changes in the cp0 state that could affect the fetch and decode of the instruction at the pc to which the deret returns, such as changes to the effective asid, user-mode state, and addressing mode. operation: if (debugdm = 1) then debugdm 0 debugiexi 0 pc depc elseif (in user mode) and (srcu0 = 0) then initiatecoprocessorunusableexception(0) else undefined endif exceptions: coprocessor unusable exception. ejtag coprocessor 0 registers the coprocessor 0 registers for ej tag are shown in table 20.15. each register is described in more detail in the following subsections. debug exception return deret 31 0 6 1 19 cop0 co 24 26 25 deret 0 6 6 5 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 25 november 4, 2002 notes the cp0 instructions mtc0, mfc0, dmtc0, and dm fc0 work with the three ejtag cp0 registers. operation of the processor is undefined if the d ebug, depc, or desave registers are written from non- debug mode. the value of the debug, depc, or d esave registers is unpr edictable when read from non-debug mode, unless otherwise explic itly stated in the individual regist er description. however, for test purposes, the implementations can allow writes to and reads from t he registers from non-debug mode. to avoid pipeline hazards, there must be an appr opriate spacing (refer to section ?cp0 and dseg hazards? on page 20-12) between the update of the debug and depc registers by mtc0/dmtc0 and use of the new value. this applies for example to modification of the lsnm bit of the debug register and a load/ store affected by that bit. debug register (cp0 register 23, select 0) compliance level : required for ejtag debug support. the debug register contains the cause of the most recent debug exception and exception in debug mode. it also controls single stepping. this regist er indicates low-power and clock states on debug excep- tions, debug resources, and other internal states. only the dm bit and the ejtagv er field are valid when read from the debug register in non-debug mode; the value of all other bits and fields is unpredict- able. the following bits and fields are only updat ed on debug exceptions and/or exceptions in debug mode: ? dss, dbp, ddbl, ddbs, dib, dint, ddblimpr, and ddbsimpr are updated on both debug exceptions and on exceptions in debug modes ? dexccode is updated on exceptions in debug mode, and is undefined after a debug exception ? halt and doze are updated on a debug exception, and are undefined after an exception in debug mode ? dbd is updated on both debug and on exceptions in debug modes the sync instruction, followed by appropriate spac ing, (as described in section ?sync instruction behavior? on page 20-11 and section ?cp0 and dseg ha zards? on page 20-12) must be executed to ensure that the ddblimpr, ddbsimpr, ibusep, dbusep, cacheep, and mcheckp bits are fully updated. this register number sel register name function reference 23 0 debug debug indications and controls for the processor. see section ?debug register (cp0 register 23, select 0)? on page 20-25. 24 0 depc program counter at last debug exception or exception in debug mode. see section ?debug excep- tion program counter regis- ter (cp0 register 24, select 0)? on page 20-29. 31 0 desave debug exception save register. see section ?debug excep- tion save regis- ter (cp0 register 31, select 0)? on page 20-30. table 20.15 coprocessor 0 registers for ejtag
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 26 november 4, 2002 notes instruction sequence must be used both in the begi nning of the debug handler before pending imprecise errors are detected from non-debug mode, and at the end of the debug handler before pending imprecise errors are detected from debug mode. the iexi bit c ontrols enable/disable of im precise error exceptions. figure 20.3 shows the format of the debug register and table 20.16 describes the debug register fields. figure 20.3 debug register format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dbd dm no dcr lsnm doze halt count dm ibus ep m check p cache ep dbus ep iexi ddbs impr ddbl impr ejtagver [2:1] 1514 109876543210 ejtag ver [0] dexccode nosst sst 0 dint dib ddbs ddbl dbp dss fields name bits description read/ write reset state dbd 31 indicates whether the last debug exception or exception in debug mode occurred in a branch or jump delay slot: 0: not in delay slot 1: in delay slot r undefined dm 30 indicates that the processor is operating in debug mode: 0: processor is operating in non-debug mode 1: processor is operating in debug mode r0 nodcr 29 indicates whether the dseg memory segment is present: 0: dseg is present 1: no dseg present rpreset lsnm 28 controls access of loads/stores between dseg and remaining memory when dseg is present: 0: loads/stores in dseg address range go to dseg 1: loads/stores in dseg address range go to system memory see section debug mode address space. this bit is read-only (r) and reads as zero if not implemented. r/w 0 doze 27 indicates that the processor was in a low-power mode when a debug exception occurred: 0: processor not in low-power mode when debug exception occurred 1: processor in low-power mode when debug exception occurred the doze bit indicates reduced power (rp) and wait, and other implementation-dependent low-power modes. r undefined halt 26 indicates that the internal processor system bus clock was stopped when the debug exception occurred: 0: internal system bus clock running 1: internal system bus clock stopped halt indicates wait, and other implementation-dependent events that stop the system bus clock. r undefined table 20.16 debug register fiel d descriptions (part 1 of 4)
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 27 november 4, 2002 notes countdm 25 controls or indicates the count register behavior in debug mode. implementations can have fixed behavior, in which case this bit is read-only (r), or the implementation can allow this bit to control the behavior, in which case this bit is read/write (r/ w). the reset value of this bit indicates the behavior after reset, and depends on the implementation. r1 note: this value is always 1. ibusep 24 indicates if a bus error exception is pending from an instruction fetch. set when an instruction fetch bus error event occurs or a 1 is written to the bit by software. cleared when a bus error exception on an instruction fetch is taken by the processor. if ibusep is set when iexi is cleared, a bus error exception on an instruction fetch is taken by the processor, and ibusep is cleared. in debug mode, a bus error exception applies to a debug mode bus error exception. r/w1 0 mcheckp 23 indicates if a machine check exception is pending. set when a machine check event occurs or a 1 is written to the bit by soft- ware. cleared when a machine check exception is taken by the processor. if mcheckp is set when iexi is cleared, a machine check exception is taken by the processor, and mcheckp is cleared. in debug mode, a machine check exception applies to a debug mode machine check exception. r/w 0 note: this value is always 0. cacheep 22 indicates if a cache error is pending. set when a cache error event occurs or a 1 is written to the bit by software. cleared when a cache error exception is taken by the processor. if cacheep is set when iexi is cleared, a cache error exception is taken by the processor, and cacheep is cleared. in debug mode, a cache error exception applies to a debug mode cache error exception. r/w1 0 note: this value is always 0. dbusep 21 indicates if a data access bus error exception is pending. set when a data access bus error event occurs or a 1 is written to the bit by software. cleared when a bus error exception on data access is taken by the processor. if dbusep is set when iexi is cleared, a bus error exception on data access is taken by the processor, and dbusep is cleared. in debug mode, a bus error exception applies to a debug mode bus error exception. r/w1 0 iexi 20 an imprecise error exception inhibit (iexi) controls exceptions taken due to imprecise error indications. set when the proces- sor takes a debug exception or an exception in debug mode occurs. cleared by execution of the deret instruction. other- wise modifiable by debug mode software. when iexi is set, then the imprecise error exceptions from bus errors on instruction fetches or data accesses, cache errors, or machine checks are inhibited and deferred until the bit is cleared. r/w 0 fields name bits description read/ write reset state table 20.16 debug register fiel d descriptions (part 2 of 4)
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 28 november 4, 2002 notes ddbsimpr 19 indicates that a debug data break store imprecise exception due to a store was the cause of the debug exception, or that an imprecise data hardware break due to a store was indicated after another debug exception occurred. cleared on exception in debug mode. 0: no match of an imprecise data hardware breakpoint on store 1: match of imprecise data hardware breakpoint on store r0 note: this value is always 0. ddblimpr 18 indicates that a debug data break load imprecise exception due to a load was the cause of the debug exception, or that an imprecise data hardware break due to a load was indicated after another debug exception occurred. cleared on exception in debug mode. 0: no match of an imprecise data hardware breakpoint on load 1: match of imprecise data hardware breakpoint on load r0 note: this value is always 0. ejtagver 17:15 provides the ejtag version. 0: version 1 and 2.0 1: version 2.5 2-7: reserved r1 note: this value is always 1. dexccode 14:10 indicates the cause of the latest exception in debug mode. the field is encoded as the exccode field in the cause register for those exceptions that can occur in debug mode (the encod- ing is shown in mips32 and mips64 specifications), with addi- tion of code 30 with the mnemonic cacheerr for cache errors. r undefined nosst 9 indicates whether the single-step feature controllable by the sst bit is available in this implementation: 0: single-step feature available 1: no single-step feature available a minimum number of hardware instruction breakpoints must be available if no single-step feature is implemented in hard- ware. refer to section ?number of instruction breakpoints without single stepping? on page 20-52 for more information. r0 note: this value is always 0. sst 8 controls whether single-step feature is enabled: 0: no enable of single-step feature 1: single-step feature enabled r/w 0 0 7:6 must be written as zeros; return zeros on reads. 0 0 dint 5 indicates that a debug interrupt exception occurred. cleared on exception in debug mode. 0: no debug interrupt exception 1: debug interrupt exception r undefined dib 4 indicates that a debug instruction break exception occurred. cleared on exception in debug mode. 0: no debug instruction break exception 1: debug instruction break exception r undefined fields name bits description read/ write reset state table 20.16 debug register fiel d descriptions (part 3 of 4)
idt ejtag system ejtag processor core extensions 79rc32438 user reference manual 20 - 29 november 4, 2002 notes debug exception program counter regi ster (cp0 register 24, select 0) the debug exception program counter (depc) register is a read/wri te register that contains the address at which processing resumes after the exception has been serviced. the size of this register is 32 bits for 32-bit processors and 64 bi ts for 64-bit processors, even wi th only 32-bit virtual addressing enabled. all bits of the depc register are significant and writable. a dmfc0 from the depc register returns the full 64-bit depc on 64-bit processors. hardware updates this register on debug exceptions and exceptions in debug mode. for precise debug exceptions and pr ecise exceptions in debug mode, the depc register contains either: ? the virtual address of the instruction that was the direct cause of the exception, or ? the virtual address of the immedi ately preceding branch or jump in struction, when the exception- causing instruction is in a branch delay slo t, and the debug branch delay (bdb) bit in the debug register is set. for imprecise debug exceptions and imprecise exceptions in debug m ode, the depc register contains the address at which execution is resumed when returning to non-debug mode. figure 20.4 shows the format of the depc register and table 20.17 describes the depc register field. figure 20.4 depc register forma ddbs 3 indicates that a debug data break store exception occurred on a store due to a precise data hardware break. cleared on exception in debug mode. 0: no debug data break store exception 1: debug data break store exception r undefined ddbl 2 indicates that a debug data break load exception occurred on a load due to a precise data hardware break. cleared on exception in debug mode. 0: no debug data break store exception 1: debug data break store exception r undefined dbp 1 indicates that a debug breakpoint exception occurred. cleared on exception in debug mode. 0: no debug breakpoint exception 1: debug breakpoint exception r undefined dss 0 indicates that a debug single step exception occurred. cleared on exception in debug mode. 0: no debug single-step exception 1: debug single-step exception r undefined 31 0 depc fields name bits description read/ write reset state table 20.16 debug register fiel d descriptions (part 4 of 4)
idt ejtag system debug control register 79rc32438 user reference manual 20 - 30 november 4, 2002 notes table 20.17 depc register field description debug exception save register (cp0 register 31, select 0) the debug exception save (desave) register is a read/write register that functions as a simple scratchpad register. the size of this register is 32 bi ts for 32-bit processors and 64 bits for 64-bit processor. the debug exception handler uses this to save one of the gprs, which is then used to save the rest of the context to a pre-determined memory area, for exam ple, in the dmseg. this register allows the safe debugging of exception handlers and other types of code w here the existence of a valid stack for context saving cannot be assumed. figure 2-4 shows the format of the desave regist er; table 2-13 describes the desave register field. figure 20.5 desave register format debug control register the debug control register (dcr) controls and pr ovides information about debug issues. the width of the register is 32 bits for 32-bit processors, and 64 bi ts for 64-bit processors. t he dcr is located in the drseg at offset 0x0000. the debug control register (dcr) provides the fo llowing key features: ? interrupt and nmi control when in non-debug mode ? nmi pending indication ? availability indicator of instru ction and data hardware breakpoints. for ejtag features, there are no difference between a reset and a soft reset occurring to the processor; they behave identically in both d ebug mode and non-debug mode. references to reset in the following therefore refers to both reset (hard reset) and soft rese t. the databrk and instbrk bits within the dcr indi- cate the types of hardware breakpoints implemented . debug software is expected to read hardware break- point registers for additional information on the num ber of implemented breakpoints. refer to section ?hardware breakpoints? on page 20-32 for a descr iption of the hardware breakpoint registers. hardware and software interrupts can be disabled in non-debug mode using the dcr?s inte bit. this bit is a global interrupt enable used along with several ot her interrupt enables that enable specific mecha- nisms. the nmi interrupt can be disabled in non- debug mode using the dcr?s nmie bit; a pending nmi is indicated through the nmipend bit. pending interrupts are indicated in the cause register, and pending fields description read/ write reset state compli- ance name bits depc msb:0 debug exception program counter r/w undefined required 31 0 desave fields description read/ write reset state compli- ance name bits desave msb:0 debug exception save contents r/w undefined required table 20.18 desave register field description
idt ejtag system debug control register 79rc32438 user reference manual 20 - 31 november 4, 2002 notes nmis are indicated in the dcr regi ster nmipend bit, even when disabled. hardware and software interrupts and nmis are always disabled in debug mode (refer to section ?int errupts and nmis? on page 20-21 for more information). the optional srste bit allows masking of soft rese ts. a soft reset can be applied to the system based on different events, referred to as sources. it is implementation dependent which soft reset sources in a system can be masked by the srste bit. soft reset masking can be applied to a soft reset source only if that source can be efficiently masked in the system. the result is no reset at all for any part of the system, if masked. if only a partial soft reset is possible, then that soft re set source is not to be masked, because a ?half? soft reset might cause the system to fail or hang without warning. there is no automatic indication of whether the srste bit is effective, so the us er must consult system documentation. the proben bit reflects the state of the proben bit from the ejtag control register (ecr). through this bit, the probe can indicate to the debug software runni ng on the cpu if it expects to service dmseg accesses. for more information, see section ?ejtag control register (ecr) (tap instruction control or all)? on page 20-65. figure 20.6 shows the format of the dcr register; table 20.19 describes the dc r register fields. the reset values in table 20.19 take effect on both hard resets and soft resets. figure 20.6 dcr register format 31302928 18171615 543210 0en m 0dat a brk inst brk 0intenmi e nmi pen d srst e prob en fields name bits description read/ write reset state compli ance enm 29 endianess in which the processor is running in kernel and debug mode: 0: little endian 1: big endian r preset required databrk 17 indicates if data hardware breakpoint is implemented: 0: no data hardware breakpoint implemented 1: data hardware breakpoint implemented r preset required instbrk 16 indicates if instruction hardware breakpoint is imple- mented: 0: no instruction hardware breakpoint implemented 1: instruction hardware breakpoint implemented r preset required inte 4 hardware and software interrupt enable for non- debug mode, in conjunction with other disable mecha- nisms: 0: interrupt disabled 1: interrupt enabled depending on other enabling mechanisms r/w 1 required nmie 3 non-maskable interrupt (nmi) enable for non-debug mode: 0: nmi disabled 1: nmi enabled r/w 1 required nmipend 2 indication for pending nmi: 0: no nmi pending 1: nmi pending r0required table 20.19 dcr register fiel d descriptions (part 1 of 2)
idt ejtag system hardware breakpoints 79rc32438 user reference manual 20 - 32 november 4, 2002 notes hardware breakpoints hardware breakpoints compare addresses and data of executed instructions, including data load/store accesses. instruction breakpoints can be set even on addresses in rom areas, and data breakpoints can cause debug exceptions on specific data accesses. in struction and data hardware breakpoints are alike in many aspects, and are described in parallel in the foll owing sections. when the te rm ?breakpoint? is used in this chapter, then the reference is to a ?hardw are breakpoint?, unless otherwise explicitly noted. the breakpoints provide the following key features: ? from zero to 15 instruction breakpoints c an be implemented to cause debug exceptions on exe- cuted instructions, both in rom and ram. bit ma sking is provided for virtual address compares, and masking of compares with asid (optional) is also provided. ? from zero to 15 data breakpoints can be im plemented to cause debug exceptions on data accesses. bit masking is provided for virtual addr ess compares, masking of compares with asid (optional) is provided, optional dat a value compares allows masking at byte level, and qualification on byte access and access type is possible. ? registers for setup and control are memory m apped in drseg, accessib le in debug mode only. ? breakpoints have several implementation options to ease integration with various microarchitec- tures. hardware breakpoints require the implementation of the debug control register (dcr). several addi- tional options are possible for breakpoints, as descri bed in the following subsections. for ejtag features, there are no difference between a reset and a soft reset occurring to the processor; they behave identically in both debug mode and non-debug mode. references to reset in the following therefore refers to both reset (hard reset) and soft reset. instruction breakpoint features figure 20.7 shows an overview of the instruction br eakpoint feature. the feature compares the virtual address (pc) and the asid of the executed instructio ns with each instruction breakpoint, applying masking on address and asid. when an enabled instruction br eakpoint matches the pc and asid, a debug excep- tion and/or a trigger is generated, and an internal bit in an instruction break point register is set to indicate that a match occurred. srste 1 controls soft reset enable: 0: soft reset masked for soft reset sources depen- dent on implementation 1: soft reset is fully enabled r/w 1 optional proben 0 indicates value of the proben value in the ecr regis- ter: 0: no access should occur to dmseg 1: probe services accesses to dmseg r same value as proben in ecr required of ejtag tap is present, otherwise not imple- mented 0 msb:30, 28:18, 15:5 must be written as zeros; return zeros on reads. 0 0 reserved fields name bits description read/ write reset state compli ance table 20.19 dcr register fiel d descriptions (part 2 of 2)
idt ejtag system hardware breakpoints 79rc32438 user reference manual 20 - 33 november 4, 2002 notes figure 20.7 instruction breakpoint overview data breakpoint features figure 20.8 shows an overview of the data breakpoint feature. the feature co mpares the load or store access type (type), the virtual address of the acce ss (addr), the asid, the accessed bytes (byte- lane), and data value (data) with each data break point, applying masks and/or qualifications on the access properties. figure 20.8 data breakpoint overview when an enabled data breakpoint matches, a debug ex ception and/or a trigger is generated, and an internal bit in a data breakpoint register is set to i ndicate that a match occurred. the match is either precise (the debug exception or trigger occurs on the instruction that caused the breakpoint to match) or imprecise (the debug exception or trigger occu rs later in the program flow). overview of instruction and data breakpoint registers from zero to 15 instruction and data breakpoint s can be implemented independently. implementation of any breakpoint implies that the debug control regist er (dcr) is implemented. the instbrk and databrk bits in the dcr register indicate w hether there are zero or 1 to 15 im plementations of a breakpoint type. if no breakpoints of a specific type are implemented, t hen none of the registers associated with this break- point type are implemented. if any (1 to 15) breakpoints of a specific type are implemented, then the break- point status register associated with that breakpoi nt type is implemented. the instruction and data break status registers indicate the num ber of breakpoints for each corres ponding type. the number of additional registers depends on the number of im plemented breakpoints for the respec tive breakpoint type. registers for asid compares are only implem ented if indicated in the corres ponding breakpoint status register. the next two sections, overview of instruction br eakpoint registers and over view of data breakpoint registers, provide ov erviews of the instruction and data breakpoint registers, respective ly. all registers are memory mapped in the drseg segment. all regi sters are 32 bits wide for 32-bit processors. overview of instructio n breakpoint registers table 20.20 lists the instruction breakpoint registers. the instruction breakpoint status register provides implementation indication and status for instruction breakpoints in general. the 1 to 15 implemented break- points are numbered 0 to 14, respectively, for regist ers and breakpoints. the spec ific breakpoint number is indicated by ?n?. instruction hardware breakpoint debug exception trigger indication asid pc data hardware breakpoint type asid debug exception trigger indication addr data bytelane
idt ejtag system hardware breakpoints 79rc32438 user reference manual 20 - 34 november 4, 2002 notes register addresses are shown in section ?i nstruction breakpoint registers? on page 20-43. overview of data breakpoint registers table 4-2 lists the data breakpoint registers. the da ta breakpoint status register provides implementa- tion indication and status for data breakpoints in general. the 1 to 15 implemented breakpoints are numbered 0 to 14, respectively, for registers and break points. the specific break point number is indicated by ?n?. the registers for data value compares are only implemented if the value compares for the data breakpoints are implemented, which occurs when either the nolvmatch bit or the nosvmatch bit in the dbs is 0. register mnemonic register name and description reference compliance level ibs instruction breakpoint status see section ?instruction breakpoint status (ibs) register? on page 20-43. required if any instruc- tion breakpoints are implemented, optional otherwise. iban instruction breakpoint address n see section ?instruction breakpoint address n (iban) register? on page 20-44. required with instruc- tion breakpoint n, optional otherwise. ibmn instruction breakpoint address mask n see section ?instruction breakpoint address mask n (ibmn) register? on page 20-45. ibasidn instruction breakpoint asid n see section ?instruction breakpoint asid n (ibasidn) register? on page 20-45. required with instruc- tion breakpoint n, optional otherwise. not implemented if asidsup bit in ibs is 0 (zero). ibcn instruction breakpoint control n see section ?instruction breakpoint control n (ibcn) register? on page 20-46. required with instruc- tion breakpoint n, optional otherwise. table 20.20 instruction breakpoint register summary register mnemonic register name and description reference compliance dbs data breakpoint status see section ?data break- point status (dbs) regis- ter? on page 20-47. required if any data breakpoints are implemented, optional other- wise. dban data breakpoint address n see section ?data break- point address n (dban) register? on page 20-48. required with data breakpoint n, optional other- wise. table 20.21 data breakpoint register description (part 1 of 2)
idt ejtag system hardware breakpoints 79rc32438 user reference manual 20 - 35 november 4, 2002 notes conditions for matching breakpoints a number of conditions must be fulfilled in order fo r a breakpoint to match on an executed instruction or a data access. these conditions are described in the following subsecti ons. a breakpoint only matches for instructions executed in non-debug mode, nev er due to instructions executed in debug mode. the match of an enabled breakpoint generates a debug exception as described in section ?debug exceptions from breakpoints? on page 20-40 and/or a tr igger indication as descr ibed in section ?break- points used as triggerpoints? on page 20-42. the be and/or te bits in t he ibcn or dbcn registers enable the breakpoints for breaks and triggers, respectively. it is implementation dependent whether or not a breakpoint stalls the processor in order to evaluate the match expression; for example, if required for timing reasons or in order to wait on a scheduled load to return for evaluation of a data breakpoint with a data va lue compare. in some cases, stalling is avoided with imprecise data breakpoints, as des cribed in section ?debug excepti on by data breakpoint? on page 20-40. conditions for matching instruction breakpoints when an instruction breakpoint is enabled, that br eakpoint is evaluated in non-debug mode with the instruction boundary address (the lowest address of a byte in the instruction) of every executed instruction. the instruction breakpoint is also evaluated on addre sses usually causing an address error exception, a tlb exception, or other exceptions . it is thereby possible to cause a debug instruction break exception on the destination address of a jump, even if a jump to that address would cause an address error exception. the breakpoint is not evaluated on instructi ons from speculative fetches or execution. a match of an instruction breakpoint depends on a num ber of parameters, shown in table 20.22. the fields in the instruction breakpoint registers are in the form reg field . dbmn data breakpoint address mask n see section ?data break- point address mask n (dbmn) register? on page 20-49. dbasidn data breakpoint asid n see section ?data break- point asid n (dbasidn) register? on page 20-49. required with data breakpoint n, optional other- wise. not imple- mented if asidsup bit in dbs is 0 (zero). dbcn data breakpoint control n see section ?data break- point control n (dbcn) register? on page 20-49. required with data breakpoint n, optional other- wise. dbvn data breakpoint value n see section ?data break- point value n (dbvn) reg- ister? on page 20-51. required with data breakpoint n, optional other- wise. only imple- mented with value compares, shown in dbs. register mnemonic register name and description reference compliance table 20.21 data breakpoint register description (part 2 of 2)
idt ejtag system hardware breakpoints 79rc32438 user reference manual 20 - 36 november 4, 2002 notes the pc, ibaniba, and ibmnibm fields are 32 bits wi de for 32-bit processors and 64 bits wide for 64-bit processors. the equation that determines the match is shown be low with ?c?-like operators. in the equation, 0 means all bits are 0?s, and ~0 means all bits are 1?s. the widths are similar to the widths of the parameters. the match equation is ib_match, and is dependent on whether mips16 is supported or not. if there is no support for mips16 then the ib_match equation is: ib_match = ( ! ibcn asiduse || ( asid = = ibasidn asid ) ) && ( ( ibmn ibm | ~ ( pc ^ iban iba ) ) = = ~0 ) if mips16 is supported then the ib_match equation is shown below, in which case the isamode bit is compared with bit 0 of iban iba instead of compare with bit 0 in pc: ib_match = ( ! ibcn asiduse || ( asid = = ibasidn asid ) ) && ( ( ibmn ibm | ~ ( ( ( pc[msb:1] << 1 ) + isamode ) ^ iban iba ) ) = = ~0 ) the ib_match equation also applies to 64-bit proce ssors running in 32-bit addressing mode, in which case all 64 bits are compared between the pc and the iban iba register. the match indication for instruction breakpoints is always precise; that is , it is indicated on the instruction causing the ib_match to be true. it is implementation dependent for an instruction breakpoint to match when the memory system does not ever respond to the fetch or generates a bus error from a system watchdog. if no match occurs, then the processor hangs without the instruction breakpoint generating either a debug ex ception or a trigger. parameter description width asid asid field in entryhi cp0 register. 8 bits ibcn asiduse use asid value in compare for instruction breakpoint n: 0: do not use asid value in compare 1: use asid value in compare 1 bit ibasidn asid conditional instruction breakpoint n asid value for comparing. 8 bits pc virtual address of instruction boundary or target for jump/branch. 32 / 64 bits isamode used only when mips16 isa support is imple- mented. it indicates the isa mode for the executed instruction or the mode at the target of a jump/ branch: 0: 32-bit mips instruction 1: mips16 instruction 1 bit iban iba instruction breakpoint n address for compare with conditions. 32 / 64 bits ibmn ibm instruction breakpoint n address mask condition: 0: corresponding address bit compared 1: corresponding address bit masked 32 / 64 bits table 20.22 instruction br eakpoint condition parameters
idt ejtag system hardware breakpoints 79rc32438 user reference manual 20 - 37 november 4, 2002 notes conditions for matching data breakpoints when a data breakpoint is enabled, that breakpoint is evaluated in non-debug mode with both the access address of every data access due to load/store in structions (including loads/stores of coprocessor registers) and the address causing address errors upon data access. data breakpoints are not evaluated with addresses from pref (prefetch) or cache instructions. the concept ?data bus? is used in the following to denote the bytes accessed and the data value trans- ferred in a load/store operation. in this notation data bus referees to the naturally-aligned memory word (for 32-bit processors) or doubleword (f or 64-bit processors) containing the accessed address referred to as addr. this notation is independent of the actual width of the processor bus, e.g., the ?data bus? width of a 64-bit processor is 64, even if that processor has a 32-bit processor bus. a match of the data breakpoint depends on a number of parameters, shown in table 20.23. the fields in the data breakpoint registers are in the form reg field . reference description width type data access type is either load or store. no width dbcn nosb controls whether condition for data breakpoint is ful- filled on a store access: 0: condition can be fulfilled on store access 1: condition is never fulfilled on store access 1 bit dbcn nolb controls whether condition for data breakpoint is ful- filled on a load access: 0: condition can be fulfilled on load access 1: condition is never fulfilled on load access 1 bit asid asid field in entryhi cp0 register. 8 bits dbcn asiduse asid value used in compare for data breakpoint n: 0: do not use asid value in compare 1: use asid value in compare 1 bit dbasidn asid conditional data breakpoint n asid value for com- parison. 8 bits addr virtual address of data access, effective address. 32 / 64 bits dban dba data breakpoint n address for compare with condi- tions. 32 / 64 bits dbmn dbm conditional data breakpoint n address mask: 0: corresponding address bit compared 1: corresponding address bit masked 32 / 64 bits bytelane byte lane access indica tion, where bytelane[0] is 1 only if the byte at bits [7:0] of the data bus is accessed, bytelane[1] is 1 only if the byte at bits [15:8] of the data bus is accessed, etc. 4 / 8 bits dbcn bai determines whether access is ignored to specific bytes. bai[0] controls ignore of access to the byte at bits [7:0] of the data bus, bai[1] ignores access to byte at bits [15:8] of the data bus, etc.: 0: condition depends on access to corresponding byte 1: access for corresponding byte is ignored 4 / 8 bits table 20.23 data breakpoint condi tion parameters (part 1 of 2)
idt ejtag system hardware breakpoints 79rc32438 user reference manual 20 - 38 november 4, 2002 notes the addr, dbandba, dbmndbm, data, and dbvndbv fields are 32 bits wi de for 32-bit processors and 64 bits wide for 64-bit processo rs. the bytelane, dbcnblm, and dbcn bai fields are four bits wide for 32-bit processors and eight bits wide for 64-bit processors. the width is indicated as ?n? in the equations below. the match equations are shown below with ?c?-like operators. in the equation, 0 means all bits are 0?s, and ~0 means all bits are 1?s. the bit widths are similar to the wi dths of the parameters. db_match is the overall match equation (the db_addr_match, db_no_value_compare, and db_value_match equations in the db_match equation are defined below): db_match = ( ( ( type = = load ) && ! dbcn nolb ) || ( ( type = = store ) && ! dbcn nosb ) ) && db_addr_match && ( db_no_value_c ompare || db_value_match ) db_addr_match is defined as: db_addr_match = ( ! dbcn asiduse || ( asid = = dbasidn asid ) ) && ( ( dbmn dbm | ~ ( addr ^ dban dba ) ) = = ~0 ) && ( ( ~ dbcn bai & bytelane ) != 0 ) the db_addr_match equation also applies to 64-bit pr ocessors running in 32-bit addressing mode, in which case all 64 bits are compared between the addr and the dban dba field. db_no_value_compare is defined as: db_no_value_compare = ( ( dbcn blm | dbcn bai | ~ bytelane ) = = ~0 ) if a data value compare is indicated on a breakpoin t, then db_no_value_compare is false, and if there is no data value compare then db_no_value_compare is true. note that a data value compare is a run-time property of the breakpoint if (dbcn blm | dbcn bai ) is not ~0, because db_no_value_compare then depends on bytelane provided by the load/store instructions. if a data value compare is required, then the data value from the data bus is compared and masked with the registers for the data breakpoint, as shown in the db_value_match equation: db_value_match = ( ( data[7:0] = = dbvn dbv[7:0] ) || ! bytelane[0] || dbcn blm[0] || dbcn bai[0] ) && ( ( data[15:8] = = dbvn dbv[15:8] ) || ! bytelane[1] || dbcn blm[1] || dbcn bai[1] ) && ...... ( ( data[8*n-1:8*n-8] = = dbvn dbv[8*n-1:8*n-8] ) || ! bytelane[n-1] || dbcn blm[n-1] || dbcn bai[n-1] ) data data value from the data bus. 32 / 64 bits dbvn dbv conditional data breakpoint n data value for com- pare. 32 / 64 bits dbcn blm conditional byte lane mask for value compare on data breakpoint. blm[0] masks byte at bits [7:0] of the data bus, blm[1] masks byte at bits [15:8], etc.: 0: compare corresponding byte lane 1: mask corresponding byte lane 4 / 8 bits reference description width table 20.23 data breakpoint condi tion parameters (part 2 of 2)
idt ejtag system hardware breakpoints 79rc32438 user reference manual 20 - 39 november 4, 2002 notes data breakpoints depend on endianess, because values on the byte lanes are used in the equations. thus it is required that the debug software programs the breakpoints acco rdingly to endianess. it is imple- mentation dependent for a data breakpoint to match when the memory system does not ever respond to the data access or generates a bus error from a syst em watchdog. if no match occurs, then the processor hangs without the data breakpoint gener ating a debug exception or trigger. data breakpoints in case of unaligned address unaligned addresses can result from explicit halfwor d, word, and doubleword accesses (for example, if an effective address of 0x01 is used as source of a load halfword (lh) instruction). the addr used in the comparison is the effective address. the bytelane val ue is defined according to table 20.24 for a 32-bit processor. with the above well-defined values of bytelane, the behavior is well-defined for data breakpoints without value compares on operations with unaligned addresses. the blm field in the dbcn register can be used to avoid value compares if all blm bits are set to 1. if the data breakpoint depends on a value compare, then loads will cause an address error ex ception, and for stores the data value (data) is unpredictable. this unpredictable data can caus e match of a data breakpoint on a store, but an implementation can choose never to indicate a match on data breakpoints depending on value compare if having unaligned address. if a debug exception is taken on the store then the de bug handler can investigate the processor state and thereby determine if the addr ess was unaligned and unpredictable store data for the memory access thereby caused the debug exception. if a debug exception is not taken for the store, then an address error exception is taken. so, in both cases it is possible for debug software to detect the bug. the blm field in the dbcn register can be used to avoid compare on unpredictable data, in case all of the blm bits are set to 1. if the data breakpoint is used as a triggerpoint, a bs bit might be set after a compare with unpredict- able data; however, an address error exception occurs in this case thereby making it possible to detect the bug. match for data breakpoint with valu e compare on bus or cache error if a data value compare is required to evaluat e a data breakpoint, the db_no_value_compare equation is false (see section ?conditions for matching data br eakpoints? on page 20-37). however, if a bus or cache error occurs on the load, then there is no valid data to use in the compare. this case has two possibilities: ? the match will fail. ? the match will compare on invalid data, and then i ndicate a pending bus or cache error through the dbusep or cacheep bits in the debug register, if a debug exception is taken. this occurrence might cause a trigger indication to be set on the compare with invalid data. a bus or cache error on a store does not affect the data breakpoint compare. refer to section ?data breakpoint compare on invalid data? on page 20-52for recommendations on implementing data breakpoint compares on invalid data. size addr bytelane[3:0] [2] [1] [0] little endian big endian halfword x 1 1. x = don?t care 0 x 0011 2 1100v x1x 1100 2 0011 2 word xxx 1111 2 table 20.24 bytelane at unali gned address for 32-bit processors
idt ejtag system hardware breakpoints 79rc32438 user reference manual 20 - 40 november 4, 2002 notes precise match for data breakpoints a precise match for a data breakpoint occurs when the match equation can be fully evaluated at the time the load/store instruction is executed. a true db_match can thereby be indicated on the very same instruc- tion causing the db_match equation to be true. matc hes on data breakpoints without data value compares are always precise. accesses using data value compar es are either imprecis e or precise depending on the implementation and specific access. imprecise match for data breakpoints an imprecise match for a data breakpoint occurs when the match equation cannot be fully evaluated at the time the load/store instruction is executed. this case occurs when the processor is not stalled on a scheduled load and a data breakpoint must compare on t he data value returned by the load. if the break- point matches, then the db_match equation is true later in the execution flow rather than at the same time as load/store instruction that caused the load/store access to match. only data breakpoints with value compares can be imprecise, in which case the break points can be imprecise for all or some of those accesses depending on the implementation. debug exceptions from breakpoints this section describes how to set up instruct ion and data breakpoints to generate debug exceptions when the match conditions are true. debug exception caused by instruction breakpoint the be bit in the ibcn register must be set for an instruction breakpoint to be enabled. a debug instruc- tion break exception occurs when the ib_match equation is true (see section?conditions for matching instruction breakpoints? on page 20-35). the corresponding bs bit in the ibs register is set when the breakpoint generates the debug exception. the debug instruction break exception is precise, so the depc register and dbd bit in the debug register point to the instruction that caused the ib_match equation to be true. the instruction receiving the debug exception only updates the debug related registers. that instruc- tion will not cause any loads/stores to occur. thus a debug exception from a data breakpoint cannot occur at the same time an instruction receives a debug instruction break exception. the debug handler usually returns to the instructi on causing the debug instruction break exception, whereby the instruction is executed. debug software must disable the breakpoint when returning to the instruction, otherwise the debug instruction break e xception will reoccur. an alternative is for debug soft- ware to emulate the instruction(s) in software and change the depc accordingly. debug exception by data breakpoint the be bit in the dbcn register must be set fo r a data breakpoint to be enabled. a debug exception occurs when the db_match condition is true. a matc hing data breakpoint generates either a precise or an imprecise debug exception (see section ?precise / imprecise debug exceptions on data breakpoints with data value compares? on page 20-52). debug data break load/store exception as a precise debug exception a debug data break load/store exception occurs when a data breakpoint indicates a precise match. in this case, the depc register and dbd bit in the d ebug register point to the load/store instruction that caused the db_match equation to be true, and the corr esponding bs bit in the dbs register is set. details about behavior of the instruction causing the debug exception is shown in table 20.25.
idt ejtag system hardware breakpoints 79rc32438 user reference manual 20 - 41 november 4, 2002 notes thus, in the case a data breakpoint with data val ue compare is set up on a load instruction, the load does occur from the external memory, since the data value is required to eval uate the match condition, but the destination register is not updated, so the loaded va lue is simply discarded. the rules shown in table 20.26 describe update of the bs bits when several data breakpoints match the same access and generate a debug exception any bs bit set prior to the match and debug excepti on is kept set, since only debug software can clear the bs bits. the debug handler usually returns to the instruct ion that caused the debug data break load/store exception, whereby the instruction is re-executed. this re-execution results in a repeated load from system memory after a data breakpoint with a data value co mpare on a load, because the load occurred previously in order to allow evaluation of the breakpoint as described above. memory-mapped devices with side instruction and data breakpoint load/store instruction execution destination register external memory system access store with/without value match not completed not updated 1 1. this applies to the store conditiona l word/doubleword (sc/scd instructions. store to memory is not committed load without value match not updated 2 2. this includes side effects like load linked word/doubleword (ll/lld) instructions. load from memory does not occur loan with value match load from memory does occur table 20.25 behavior on precise exceptions from data breakpoints instruction breakpoints that match update of bs bits matching data breakpoints without value compare with value compare without value compare with value compare load / store one or more none bs bits set for all no matching break- points load one or more one or more bs bits set for all unchanged bs bits since load of data value does not occur, so match of the breakpoint cant be determined load none one or more no matching break- points bs bits set for all store one or more one or more bs bits set for all optional to either set bs bits for all, or change none of the bs bits store none one or more no matching break- points bs bits set for all table 20.26 behavior on precise exceptions from data breakpoints
idt ejtag system hardware breakpoints 79rc32438 user reference manual 20 - 42 november 4, 2002 notes effects on loads must allow such reloads, or debug so ftware should alternativel y avoid setting data break- points with data value compares on the address of such devices. debug software must disable breakpoints when returning to the instruction, otherwise the d ebug data break load/store exception will reoccur. an alternative is for debug software to emulate the inst ruction in software and change the depc accordingly. debug data break load/store excepti on as an imprecise debug exception a debug data break load/store imprecise except ion occurs when a data breakpoint indicates an imprecise match. in this case, the depc register and db d bit in the debug register point to an instruction later in the execution flow rather than at the load/st ore instruction that caused the db_match equation to be true. the load/store instruction causing the debug data break load/store imprecise exception always updates the destination regi ster and completes the access to the external memory system. therefore this load/store instruction is not re-executed on return from the debug handler, because the depc register and dbd bit do not point to that instruction. several imprecise data breakpoints can be pending at a given time, if the bus system supports multiple outstanding data accesses. the br eakpoints are evaluated as the a ccesses finalize, and a debug data break load/store imprecise exception is generated onl y for the first one matching. both the first and succeeding matches cause corresponding bs bits and ddblimpr/ddbsimpr to be set, but no debug exception is generated for succeeding matches because t he processor is already in debug mode. similarly, if a debug exception had already occurred at the time of the first match (for example, due to a precise debug exception), then all matches cause the corr esponding bs bits and ddblimpr/ddbsimpr to be set, but no debug exception is generated because t he processor is already in debug mode. the sync instruction, followed by appropriate s pacing must be executed before the bs bits and ddblimpr/ddbsimpr bits are accessed for read or writ e. this delay ensures that these bits are fully updated. any bs bit set prior to the match and debug exception are kept set, because only debug software can clear the bs bits. breakpoints used as triggerpoints software can set up both instruction and data break points such that a matching breakpoint does not generate a debug exception, but sends an indication th rough the bs bit only. the te bit in the ibcn or dbcn register controls whether an instruction or data breakpoint, respec tively, is used as a triggerpoint. triggerpoints are evaluated for matches under the same cr iteria as breakpoints. the bs bit in the ibs or dbs register is set for a triggerpoint when the res pective ib_match condition (see section ?conditions for matching instruction breakpoints? on page 20-35) or db_match condition (see section ?conditions for matching data breakpoints? on page 20-37) is true. for t he bs bit to be set for an instruction triggerpoint, either the instruction must be fully executed or an exception must occur on the instruction. the bs bit for a data triggerpoint can only be set if no exception with higher priority than the debug data break load/store exception with address match only oc curred on the load/store instruction. for exceptions with equal or lower priority than the debug data break load/store exception with address match only, the bs bits are still set for a matching triggerpoint. for ex ample, the bs bit is set even if a tlb or bus error exception occurred on the load/store instruction. data triggerpoints with value compares require the data value to be valid for the bs bit to be set, which is not the case if, for example, a tlb or bus error exception occurs on a load instruction. however, for stores , the trigger may compare on unpredictable data as described in section ?data breakpoints in case of unaligned address? on page 20-39. the rules for update of the bs bits are shown in table 20.27.
idt ejtag system hardware breakpoints 79rc32438 user reference manual 20 - 43 november 4, 2002 notes data breakpoints with imprecise matches generate imprecise triggers when enabled by the te bit. note that trigger indications by bs may be set based on compare with unpredictable data. a triggerpoint match can be indicated on an optional internal signal or chip pin. instruction breakpoint registers this section describes the instruction breakpoi nt registers for mips32 and mips64 processors, and other r4k privileged environment implem entations of 32-bit and 64-bit proc essors. these registers provide status and control for the instruction breakpoints. all registers are in drseg. t he 1 to 15 implemented break- points are numbered 0 to 14, respectively, for regist ers and breakpoints. the spec ific breakpoint number is indicated by ?n?. the registers and their respec tive addresses offsets are shown in table 20.28. instruction breakpoint status (ibs) register compliance level : required if any instruction breakpoint s are implemented, optional otherwise. the instruction breakpoint status (ibs) register holds implementation and status information about the instruction breakpoints. it is located at drseg offset 0x1000. the asidsup bit applies to all instruction break- points. figure 20.9 shows the format of the ibs regist er and table 20.29 describes the ibs register fields. instruction with/without value compare bs bits update for triggerpoint load / store without value compare bs bit set if no exception with higher priority than the debug data break load/store exception, with address match only, occurred on the instruction. load with value compare bs bit set if no exception with higher priority than the debug data break load exception, with address and data value match, occurred on the instruction. store with value compare bs bit is set if no exception occurred on the instruc- tion, and is optional to be if an exception with equal or lower priority than the debug data break store exception, with address match only, occurred on the instruction, with the requirement that either all the relevant bs bits are set, or none are changed. table 20.27 rules for update of bs bits on data triggerpoints offset in drseg register mnemonic register name and description 0x1000 ibs instruction breakpoint status 0x1100 + 0x100*n iban instruction breakpoint address n 0x1108 + 0x100*n ibmn instruction breakpoint address mask n 0x1110 + 0x100*n ibasi dn instruction breakpoint asid n 0x1118 + 0x100*n ibcn instruction breakpoint control n table 20.28 instruction breakpoint register mapping
idt ejtag system hardware breakpoints 79rc32438 user reference manual 20 - 44 november 4, 2002 notes figure 20.9 ibs register format instruction breakpoint ad dress n (iban) register compliance level: required with in struction breakpoint n, optional otherwise. the instruction break- point address n (iban) register has the address used in the condition for instruction breakpoint n. it is located at drseg offset 0x1100 + 0x100 * n. figure 20. 10 shows the format of the iban register and table 20.30 describes the iban register field. figure 20.10 iban register format 31 30 29 28 27 24 23 15 14 0 0 asi ds up 0 bcn 0 bs[14:0] fields description read/ write reset state compli- ance name bit asidsup 30 indicates if asid compare is supported in instruction breakpoints: 0: no asid compare 1: asid compare (ibasidn register implemented) asid support indication does not guaran- tee a tlb-type mmu, because the same breakpoint implementation can be used with processors having all different types of mmus. r preset required bcn 27:24 number of instruction breakpoints imple- mented: 0: reserved 1-15: number of instructions breakpoints r preset required bs[14:0] 14:0 break status (bs) bit for breakpoint n is at bs[n], where n is 0 to 14. a bit is set to 1 when the condition for its corresponding breakpoint has matched. the number of bs bits implemented corre- sponds to the number of breakpoints indi- cated by the bcn field. debug software is expected to clear the bits before use, because reset does not clear these bits. bits not implemented are read-only (r) and read as zeros. r/w0 undefined required for bits at imple- mented breakpoints, other bits not implemented 0 msb:31, 29:28, 23:15 must be written as zeros on read. 0 0 reserved table 20.29 ibs register field description 31 0 iban
idt ejtag system hardware breakpoints 79rc32438 user reference manual 20 - 45 november 4, 2002 notes instruction breakpoint addr ess mask n (ibmn) register compliance level : required with instruction br eakpoint n, optional otherwise. the instruction breakpoint address mask n (ibmn) register has the address compare mask used in the condition for instruction breakpoint n. the address that is masked is in the iban register. the ibmn register is located at drseg offset 0x1108 + 0x100 * n. figure 20. 11 shows the format of the ibmn register and table 20.31 describes the ibmn register field. figure 20.11 ibmn register format instruction breakpoint asid n (ibasidn) register compliance level : required with instruction breakpoint n if the asidsup bit in the ibs register is 1, optional otherwise. the instruction breakpoint asid n (ibasidn) regist er has the asid value used in the compare for instruction breakpoint n. it is located at drseg offs et 0x1110 + 0x100 * n. figure 20.12 shows the format of the ibasidn register and table 20.32 describes the ibasi dn register fields. the wi dth of the asid field for the compare is 8 bits. it is identical to the width of the asid field in the entryhi register used with the tlb- type mmu. figure 20.12 ibasidn register format fields description read/ write reset state compli- ance name bit iba msb:0 instruction breakpoint address for condi- tion. r/w undefined required table 20.30 iban register field description 31 0 ibmn fields description read/ write reset state compli- ance name bit ibm msb:0 instruction breakpoint address mask for condition: 0: corresponding address bit compared 1: corresponding address bit masked. r/w undefined required table 20.31 ibmn register field description 31 8 7 0 0 asid
idt ejtag system hardware breakpoints 79rc32438 user reference manual 20 - 46 november 4, 2002 notes instruction breakpoint co ntrol n (ibcn) register compliance level : required with instruction br eakpoint n, optional otherwise. the instruction breakpoint control n (ibcn) register determines what constitutes instruction breakpoint n: triggerpoint, breakpoint, asid value inclusion. this register is located at dr seg offset 0x1118 + 0x100 * n. figure 20.13 shows the format of the ibcn register and table 20.33 describes t he ibcn register fields. figure 20.13 ibcn register format fields description read/ write reset state compli- ance name bit asid 7:0 instruction breakpoint asid value for com- pare. r/w undefined required 0 msb:8 must be written as zeros; return zeros on read. 00reserved table 20.32 ibasidn register field description 31 242322 3210 0 asid use 0te0be fields description read/ write reset state compli- ance name bit asiduse 23 use asid value in compare for instruction breakpoint n: 0: do not use asid value in compare 1: use asid value in compare debug software should only set the asi- duse if a tlb in the implementation is used by the application software. this bit is read-only and reads as zero, if not implemented. r/w undefined required if asidsup in ibs register is 1, otherwise not imple- mented te 2 use instruction breakpoint n as trigger- point: 0: do not use it as triggerpoint 1: use it as triggerpoint r/w 0 required be 0 use instruction breakpoint n as breakpoint: 0: do not use it as breakpoint 1: use it as breakpoint r/w 0 required 0 msb:24, 22:3, 1 must be written as zeros; return zeros on read 00required table 20.33 ibcn register field description
idt ejtag system hardware breakpoints 79rc32438 user reference manual 20 - 47 november 4, 2002 notes data breakpoint registers this section describes the data breakpoint registers for mips32 and mips64 processors, and other r4k privileged environment implementations of 32-bit and 64- bit processors. these regi sters provide status and control for the data breakpoints. all registers are in drseg. the 1 to 15 implemented breakpoints are numbered 0 to 14, respectively, for registers and break points. the specific break point number is indicated by ?n?. the registers and their respective addresses offsets are shown in table 20.34. data breakpoint status (dbs) register compliance level : required if any data breakpoints ar e implemented, optional otherwise. the data breakpoint status (dbs) register holds implem entation and status information about the data breakpoints. it is located at drseg offset 0x2000. the asidsup, nosvmatch, and nolvmatch fields apply to all data breakpoints. figure 20.14 shows the format of the dbs register and tabl e 20.35 describes the dbs register fields figure 20.14 dbs register format offset in drseg register mnemonic register name and description 0x2000 dbs data breakpoint status 0x2100 + 0x100*n dban data breakpoint address n 0x2108 + 0x100*n dbmn data breakpoint address mask n 0x2110 + 0x100*n dbasidn data breakpoint asid n 0x2118 + 0x100*n dbcn data breakpoint control n 0x2120 + 0x100*n dbvn data breakpoint value n table 20.34 data breakpoint register mapping 31 30 29 28 27 24 23 15 14 0 0asid sup nosv match nolv- match bcn 0 bs[14:0] fields description read/ write reset state compli- ance name bit asidsup 30 indicates if asid compare is supported in data breakpoints: 0: no asid compare 1: asid compare (dbasidn register implemented) asid support indication does not guaran- tee a tlb-type mmu, because the same breakpoint implementation can be used with processors having all different types of mmus. r preset required table 20.35 dbs register field description (part 1 of 2)
idt ejtag system hardware breakpoints 79rc32438 user reference manual 20 - 48 november 4, 2002 notes data breakpoint address n (dban) register compliance level : required with data breakpoi nt n, optional otherwise. the data breakpoint address n (dban) register has the address used in the condition for data break- point n. this register is located at drseg offset 0x2100 + 0x100 * n. figure 20.15 shows the format of the dban register and table 20.36 descr ibes the dban register field. figure 20.15 dban register format nosv- match 29 indicates if a value compare on a store is supported in data breakpoints: 0: data value and address in condition on store 1: address compare only in condition on store r preset required nolvmatch 28 indicates if a value compare on a load is supported in data breakpoints: 0: data value and address in condition on load 1: address compare only in condition on load r preset required bcn 27:24 number of data breakpoints implemented: 0: reserved 1-15:number of data breakpoints r preset required bs[14:0] 14:0 break status (bs) bit for breakpoint n is at bs[n], where n is 0 to 14. the bit is set to 1 when the condition for its corresponding breakpoint has matched. the number of bs bits implemented corre- sponds to the number of breakpoints indi- cated by the bcn bit. debug software is expected to clear the bits before use, since these are not cleared by reset. bits not implemented are read-only (r) and read as zeros. r/w0 undefined required for bits at imple- mented breakpoints, other bits not implemented 0 msb:31, 23:15 must be written as zeros; return zeros on read. 00reserved 31 0 dban fields description read/ write reset state compli- ance name bit dba msb:0 data breakpoint address for condition. r/w undefined required table 20.36 dban register field description fields description read/ write reset state compli- ance name bit table 20.35 dbs register field description (part 2 of 2)
idt ejtag system hardware breakpoints 79rc32438 user reference manual 20 - 49 november 4, 2002 notes data breakpoint address mask n (dbmn) register compliance level : required with data breakpoi nt n, optional otherwise. the data breakpoint address mask n (ibmn) register has the address compare mask used in the condi- tion for data breakpoint n. the address t hat is masked is in the dban regist er. the dbmn register is located at drseg offset 0x2108 + 0x100 * n. figure 20.16 shows the format of the dbmn register and table 20.37 describes the dbmn register field. figure 20.16 dbmn register format data breakpoint asid n (dbasidn) register compliance level : required with data breakpoint n if the asid sup bit in the dbs register is 1, optional otherwise. the data breakpoint asid n (dbasidn ) register has the asid value used in the compare for data breakpoint n. it is located at drseg offset 0x2110 + 0x100 * n. figure 20.17 shows the format of the dbasidn register and table 20.38 descr ibes the dbasidn register fields . the width of the asid field for the compare is 8 bits. it is identical to the width of the asid field in the entryhi register used with the tlb- type mmu. figure 20.17 dbasidn register format data breakpoint contro l n (dbcn) register compliance level : required with data breakpoi nt n, optional otherwise. 31 0 dbmn fields description read/ write reset state compli- ance name bit dbmn msb:0 data breakpoint address mask for condi- tion: 0: corresponding address bit compared 1: corresponding address bit masked r/w undefined required table 20.37 dbmn register field description 31 8 7 0 0 asid fields description read/ write reset state compli- ance name bit asid 7:0 data breakpoint asid value for compare. r/w undefined required 0 msb:0 must be written as zeros; return zeros on read. 00reserved table 20.38 dbasidn register field description
idt ejtag system hardware breakpoints 79rc32438 user reference manual 20 - 50 november 4, 2002 notes the data breakpoint control n (dbcn) register what constitutes data breakpoint n: triggerpoint, break- point, asid value inclusion, load/stor e access fulfillment, ignore byte ac cess, byte lane mask. this register is located at drseg offset 0x2118 + 0x100 * n. t he ?data bus? is described in section ?conditions for matching data breakpoints? on page 20- 37. figure 20.18 shows the format of the dbcn register and table 20.39 describes the dbcn register fields. figure 20.18 dbcn register format 31 242322 1817 14131211 87 43210 0 asid use 0 bai[7:0] no sb no lb 0blm[7:0]0te0be fields description read/ write reset state compli- ance name bit asiduse 23 use asid value in compare for data break- point n: 0: do not use asid value in compare 1: use asid value in compare debug software should only set the asi- duse if a tlb in the implementation is used by the application software. this bit is read-only and reads as zero, if not implemented. r/w undefined required if asidsup in dbs reg. is 1, otherwise not implemented bai[7:0] 21:14 byte access ignore. controls ignore of access to specific bytes. bai[0] ignores access to byte at bits [7:0] of the data bus, bai[1] ignores access to byte at bits [15:8], etc.: 0: condition depends on access to cor- responding byte 1: access for corresponding byte is ignored. debug software must adjust for endianess when programming this field. bai[7:4] are read-only (r) and read as zeros for 32-bit processors. r/w undefined required for byte lanes in implementa- tion, other- wise not implemented. nosb 13 controls whether condition for data break- point is ever fulfilled on a store access: 0: condition can be fulfilled on store access 1: condition is never fulfilled on store access r/w undefined required nolb 12 controls whether condition for data break- point is ever fulfilled on a load access: 0: condition can be fulfilled on load access 1: condition is never fulfilled on load access r/w undefined required table 20.39 dbcn register field description (part 1 of 2)
idt ejtag system hardware breakpoints 79rc32438 user reference manual 20 - 51 november 4, 2002 notes data breakpoint value n (dbvn) register compliance level : required with data breakpoint n if data value compare is supported (indicated by either nosvmatch or nolvmatch bits in dbs being 0), optional otherwise. the data breakpoint value n (dbvn) register has t he value used in the condition for data breakpoint n. it is located at drseg offset 0x2120 + 0x100 * n. fi gure 20.19 shows the format of the dbvn register and table 20.40 describes the dbvn register field. figure 20.19 dbvn register format recommendations for implementing hardware breakpoints this section provides useful information fo r implementing instruction and data breakpoints. blm[7:0] 11:4 byte lane mask for value compare on data breakpoint. blm[0] masks byte at bits [7:0] of the data bus, blm[1] masks byte at bits [15:8], etc.: 0: compare corresponding byte lane 1: mask corresponding byte lane debug software must adjust for endianess when programming this field. blm[7:4] are un-implemented for 32-bit processors. blm[7:0] are un-implemented if value compare is not implemented, which is the case when nosvmatch and nolv- match bits in dbs are both 1. bits are read-only (r) and read as zeros if not implemented. r/w undefined required for byte lanes in implementa- tion and if value com- pare, other- wise not implemented te 2 use data breakpoint n as triggerpoint: 0: do not use it as triggerpoint 1: use it as triggerpoint r/w 0 required be 0 use data breakpoint n as breakpoint: 0: do not use it as breakpoint 1: use it as breakpoint r/w 0 required 0 msb:24, 22, 3, 1 must be written as zeros; return zeros on read. 00reserved 31 0 dbvn fields description read/ write reset state compli- ance name bit dbv msb:0 data breakpoint data value for condition. debug software must adjust for endianess when programming this field. r/w undefined required table 20.40 dbvn register field description fields description read/ write reset state compli- ance name bit table 20.39 dbcn register field description (part 2 of 2)
idt ejtag system hardware breakpoints 79rc32438 user reference manual 20 - 52 november 4, 2002 notes number of instruction breakpoi nts without single stepping if hardware single stepping is not implemented, then at least two instruction breakpoints are required. four instruction hardwar e breakpoints are recommended. data breakpoints with data value compares data breakpoints should be implemented with data va lue compares. also, data value compares should be implemented even if it is not possible to break on loads with precise data value compares. for more information on precise exceptions, refer to section ?precise / imprecise debug exceptions on data break- points with data value compares? on page 20-52. data breakpoint compare on invalid data data breakpoints should only compare on valid data, meaning they only generate debug exceptions based on valid data in the compare. this does also apply to compare on store data for a store to an unaligned address. for example, no debug exception should be generated for a bus error on a load that has a pending data breakpoint to compare on the data retu rned by the load. however, in some cases, the indication of invalid data is late relative to the data, for example, for a cache error as a result of a complex error detection. in this case, data breakpoints can indicate a debug exception because the data was believed to be valid at the time of the compare, and the pending error is then indicated to the debug handler through the dbusep or cacheep bit in the debug r egister, because the error occurred after the debug exception. note that for bus errors due to external ev ents, the bus error indication usually is available when the compare in the data breakpoint would take place. thus, it is possible to avoid a debug exception. precise / imprecise debug exceptions on data breakpoints with data value compares data breakpoints are recommended to generate precise debug exceptions, if possible in the implemen- tation. thus the depc register and dbd bit in the d ebug register point to the load/store that caused the debug exception to occur. this instruction can then be re-executed when execution resumes after the debug handler. however, data breakpoints are allow ed to cause imprecise debug exceptions when the breakpoint is set up with data value compares; for ex ample, if data breakpoints with compares on loaded data values cannot be made precise due to a non-blocki ng load. in this case, the depc register and dbd bit in the debug register point to an instruction in th e execution flow after the load/store that caused the imprecise debug exception. the bs bit can be u pdated when the match is detected, even though a debug exception is not taken until later due to internal stalls (f or example, a nulled instruction in the pipeline at the time the match is detected). it is implementation spec ific as to which cases a data breakpoint can cause an imprecise debug exception. it is recommended that t he data breakpoints cause imprecise matches in as few cases as possible. implementations can require imprecise debug except ions from data breakpoints on loads with value compares in a specific address range, if re-execution of a load in this range is not acceptable. this case is possible if the load has side effects such as re moving an entry on a queue. imprecise debug exceptions for value compares ensure that the destination register is properly updated with the loaded value, whereby re- execution of the load is avoided. breakpoint examples instruction breakpoint examples this section provides examples that illustrate using an instruction break. instruction break in small rang e of instructions with asid this example shows how to set up an instruction break point to break on the fetch of any one of the four instructions in the virt ual address range shown below: 0x0000 0010 j l1 // asid = 0x5 0x0000 0014 nop 0x0000 0018 j l2 0x0000 001c nop
idt ejtag system hardware breakpoints 79rc32438 user reference manual 20 - 53 november 4, 2002 notes the break registers must be set up as follows: ? iba0 = 0x0000 0010 ? ibm0 = 0x0000 000c ? ibc0: be=1, asiduse=1, asid = 0x5, other bits zero. note that iba0 has the starting address, and ibm0 has the address mask. instruction break on 32-bit mips16? instruction in this example, instruction breakpoint 0 needs to be set up to break on the range 0x0000 0030 to 0x0000 0036, which starts with the second part of an extended mips16 instruction: 0x0000 002e ext // (1st part of mips16 inst.) 0x0000 0030 add // (2nd part) 0x0000 0032 sub 0x0000 0034 sub 0x0000 0036 sub the break registers must be set up as follows: ? iba0 = 0x0000 0031 ? ibm0 = 0x0000 0006 ? ibc0: be = 1, asiduse = 0, other bits zero the cpu does not take a debug exception when fetching the second part of the add instruction, because it does not constitute a whole instruction. the first break is on the sub instruction at 0x0000 0032. data breakpoint this section provides three examples of data breakpoints. data break on load access with asid this example shows how to per form a break on data breakpoint 0 when the cpu loads data 0xaaaa 0000 from memory location 0x0000 0100 in asid=0x7: lw $2, 0x100($0) // asid = 0x7 the break registers must be set up as follows: ? dba0 = 0x0000 0100 ? dbm0 = 0x0 ? dbv0 = 0xaaaa 0000 ? dbc0: be = 1, nolb = 0, nosb = 1, blm = 0, bai = 0, asiduse = 1, asid = 0x7, other bits zero in this example, dba0 contains the breakpoint address; dbm0 has the addr ess mask; dbv0 has the data value; and dbc0 indicates a breakpoint condition might be fulfilled on a load but not on a store, there is a value compare for a corresponding byte, and an asid is used. data break on store(s) to halfword in memory this example shows a break on dat a breakpoint 0 when the cpu stores data in a specific halfword in memory. stores to the other halfword at the same address can be ignored. the data word is illustrated in figure 20.20; the halfword for bits 31:16 is shaded. the store instructions shown in figure 20.20 alter the shaded halfword and cause a break if the breakpo int registers are set up as shown below.
idt ejtag system ejtag test access port 79rc32438 user reference manual 20 - 54 november 4, 2002 notes figure 20.20 data break on store with value compare in this example, the data breakpoint registers are set up as follows: ? dba0 = 0x0000 0200 ?dbm0 = 0 ? dbc0: be = 1, nolb = 1, nosb = 0, blm = 11112, bai = 00112, asiduse = 0, other bits zero data break on store(s) to halfword ra nge in memory with certain value in this example, the most significant halfword in a given memory range is altered, and the most signifi- cant part of the halfword is written a certain value. the data word is illustrated below; the halfword for bits 31:16 is shaded. the store instructions shown in figure 20.21 alter the shaded halfword and cause a break if the breakpoint registers are set up as shown below. figure 20.21 data break on store with value compare in this example, the data breakpoint registers are set up as follows: ? dba0 = 0x0000 0200 ? dbm0 = 0x0000 00fc ? dbv0 = 0xaa00 0000 dbc0: be = 1, nolb = 1, nosb = 0, blm = 01112, bai = 00112, asiduse = 0, other bits zero ejtag test access port the overall features of the ejtag test access port (tap) are: ? identification of device and ejtag debu g features accessed through the tap ? dmseg memory "emulation" (mapping dmseg pr ocessor accesses into probe transactions). ? reset handling allows debug exception immediately after reset ? debug interrupt request from probe ? low-power mode indications ? implementation-dependent processor and peripheral reset. 3 2 break on memory address 0x0000 0200 bit 31:16, little endian 31 0 sw $2, 0x0000 0200 bytes_valid = 1111 2 sh $2, 0x0000 0202 bytes_valid = 1100 2 sb $2, 0x0000 0202 bytes_valid = 0100 2 sb $2, 0x0000 0203 bytes_valid = 1000 2 break on memory address range 0x0000 0200 - 0x0000 02fc write to bits 31:16, bits 31:2 4 with value 0xaa, little endian sw $2, 0x0000 0220 $2=0xaaxx xxxx bytes_valid = 1111 2 sh $2, 0x0000 0242 $2=0xxxxx aaxx bytes_valid = 1100 2 sb $2, 0x0000 0282 $2=0xxxxx xxxx bytes_valid = 0100 2 sb $2, 0x0000 02f3 $2=0xxxxx xxaa bytes_valid = 1000 2 ?x? denotes undefined value. 3 2 31 0
idt ejtag system ejtag test access port 79rc32438 user reference manual 20 - 55 november 4, 2002 notes if the tap is not implemented then other features depen ding on register values and indications from the tap should behave as if these register values and i ndications have the power-up and reset value. figure figure 20.22 shows an overview of the elements in the tap. figure 20.22 test access port (tap) overview the tap consists of the following signals: test clock (jtag_tck), test mode (jtag_tms), test data in (jtag_tdi), test data out (jtag_tdo), and the optional test reset (jtag_trst_n). jtag_tck and ejtag_tms control the state of the tap controller, wh ich controls access to the instruction or selected data register(s). the instruction r egister controls selection of data r egisters. access to the instruction and data register(s) occurs serially through jtag_t di and jtag_tdo. the optional jtag_trst_n is an asynchronous reset signal to the tap. access through the tap does not interfere with the operation of the processor, unless features specif ically described to do so are used. the description of the ejtag tap in this chapter is intended only to cover ejtag issues related to use of a tap. consult the ?ieee std 1149.1-1990, ieee standard test access port and boundary-scan archi- tecture? for detailed information about use of a tap fo r other purposes, for exampl e, integration with jtag boundary scan. for ejtag features, there is no differ ence between a reset and a soft reset occurring to the processor; they behave identically in both debug mode and non-debug mode. references to reset in the following sections refer to both reset (hard reset) and soft reset. tap signals the signals jtag_tck, jtag_tms, jtag_tdi, jtag_tdo, and the optional jtag_trst_n make up the interface for the ejtag tap. these signals are described in detail below. figure 20.37 shows the connection of the signals to chip pins. test clock input (jtag_tck) jtag_tck is the clock that controls the updating of the tap controller and the shifting of data through the instruction or selected data register(s). jtag_tck is independent of the processor clock, with respect to both frequency and phase. test mode select input (jtag_tms) jtag_tms is the control signal for the ejtag tap controller. this signal is sampled on the rising edge of jtag_tck. test data input (jtag_tdi) jtag_tdi is the test data input to the instruction or selected data register(s). this signal is sampled on the rising edge of jtag_tck for some ejtag tap controller states. instruction register selected data register(s) jtag_tdi jtag_tdo ejtag tap interface jtag_tck ejtag_tms jtag_trst_n (optional) tap controller
idt ejtag system ejtag test access port 79rc32438 user reference manual 20 - 56 november 4, 2002 notes test data output (jtag_tdo) jtag_tdo is the test data output from the instruct ion or data register(s). this signal changes on the falling edge of jtag_tck, or becomes tri-stated a synchronously when jtag_trst_n is driven low. the off-chip jtag_tdo is only driven w hen data is shifted out, otherwise the off-chip jtag_tdo is tri-stated. the tri-state notation indicates that t he jtag_tdo off-chip signal is undriven. test reset input (jtag_trst_n) jtag_trst_n is the optional test reset input that asynchronously resets the ejtag tap, with the following immediate effects: ? the tap controller is put into the test-logic-reset state ? the instruction register is loaded with the idcode instruction ? any ejtagboot indication is cleared ? the jtag_tdo output is tri-stated. jtag_trst_n does not reset another other part of t he ejtag tap or processor. thus this type of reset does not affect the processor, and the processor reset is not allowed to have any effect on the above parts of the ejtag tap. even though jtag_trst_ n is an optional signal, the jtag_trst_n signal is referred to in the following discussions. if jtag_trs t_n is not implemented, then a power-up reset of the tap must provide the reset functionality simila r to a low value on jtag_trst_n during power-up. tap controller the tap controller is a state machine whose active state controls tap reset and access to instruction and data registers. the state transitions in the ej tag tap controller occur on the rising edge of jtag_tck or when jtag_trst_n goes low. the jtag_tms signal determines the transition at the rising edge of jtag_tck. figure 20.23 shows the state diagram for the tap controller. figure 20.23 ejtag tap controller state diagram the behavior of the functional states shown in t he figure is described below . the non-functional states are intermediate states in which no registers in t he tap change, and are not described here. events in the following subsections are described with relation to the rising and falling edge of jtag_tck. the described events take place when the tap controller is in the corresponding state when the clock changes. the ejtag tap controller is forced into the test-logic- reset state at power-up either by a low value on jtag_trst_n or by a power-up reset circuit. test-logic-reset jtag_tms=1 run-test / idle 0 select-dr-scan 1 0 capture-dr 0 0 shift-dr 1 exit1-dr 0 pause-dr 1 exit2-dr 1 update-dr 0 0 0 1 1 0 1 select-ir-scan capture-ir 0 0 shift-ir 1 exit1-ir 0 pause-ir 1 exit2-ir 1 update-ir 0 0 0 1 1 0 1 1 1
idt ejtag system ejtag test access port 79rc32438 user reference manual 20 - 57 november 4, 2002 notes test-logic-reset state when the test-logic-reset state is entered, the instru ction register is loaded with the idcode instruc- tion, and any ejtagboot indication is cleared. this stat e ensures that the tap does not interfere with the normal operation of the cpu core. the tap controller always reaches this state after five rising edges on jtag_tck when jtag_tms is set to 1. a low va lue on jtag_trst_n imm ediately places the tap controller in this state asynchronous to jtag_tck. capture-ir state in the capture-ir state, the two lsbs of the inst ruction register are loaded with the value 012, and the upper msbs are loaded with implementation-dependent values. both values are loaded on the rising edge of jtag_tck. shift-ir state in the shift-ir state, the lsb of the instructi on register is output on jtag_tdo on the falling edge of jtag_tck. the instruction regist er is shifted one position from msb to lsb on the rising edge of jtag_tck, with the msb shifted in from jtag_tdi. the value in the instruction register does not take effect until the update-ir state. figure 20.24 shows the shifting direction for the instruction register. figure 20.24 jtag_tdi to jtag_tdo path in shift mode state the length of the instruction register is specified in section ?instruction register and special instruc- tions? on page 20-58. the value loaded in the capture-ir st ate is used as the initial value for the instruction register when shifting starts. thus, it is not possible to read out the previ ous value of the instruction register. update-ir state in the update-ir state, the value in the instructi on register takes effect on the rising or falling edge of jtag_tck. capture-dr state in the capture-dr state, the value of the sele cted data register(s) is captured on the rising edge of jtag_tck for shifting out in the shift-dr state. t he capture-dr state reads the data, in order to output this read value in the shift-dr state. the instruction register controls the selection of the following data register(s): bypass, device id, implementation, ejtag control, address, and data register(s). shift-dr state in the shift-dr state, the lsb of the selected dat a register(s) is output on jtag_tdo on the falling edge of jtag_tck. the selected data regi ster(s) is shifted one position fr om msb to lsb on the rising edge of jtag_tck, with jtag_tdi shifted in at the msb. t he value(s) shifted into t he register(s) does not take effect until the update-dr state. figure 20.25 shows the shifting direction for the selected data register. figure 20.25 jtag_tdi to jtag_tdo path for selected data register(s) in shift-dr state the length of the shift path depends on the selected data register(s). update-dr state in the update-dr state, the update of the selected data register(s) with the value from the shift-dr state occurs on the falling or rising edge of jtag_tck . this update writes the selected register(s). jtag_tdi instruction register msb 0 / lsb jtag_td o msb 0 / lsb jtag_tdi jtag_td o selected data register(s)
idt ejtag system ejtag test access port 79rc32438 user reference manual 20 - 58 november 4, 2002 notes instruction register and special instructions the instruction register controls selection of accessed data register(s), and controls the setting and clearing of the ejtagboot indication. the instruction register is five or mo re bits wide when used with ejtag. table 20.41 shows the allocation of the tap instruction. the instructions idcode, impc ode, address, data, control, and bypass select a single data register, as indicated in the tabl e. the unused instructions reserved for ejtag select the bypass register. the all, ejtagboot, normalboot, and fastdata instructions are described in the following subsections. the instructions that are related to tr ace registers in the trac e control block (tcb) are described in the trace control block specificatio n document. any ejtagboot indication is cleared at power-up either by a low value on the jtag_trst_n or by a power-up reset circuit, and the instruction register is loaded with the idcode instruction. all instruction the address, data, and ejtag control data registers are selected at once with the all instruction, as shown in figure 20.26. code instruction function all 0?s (free for other use) free for other use, such as jtag boundary scan 0x01 idcode selects device identification (id) register 0x02 (free for other use) free for other use, such as jtag boundary scan 0x03 impcode selects implementation register 0x04 ? 0x07 (free for other use) free for other use, such as jtag boundary scan 0x08 address selects address register 0x09 data selects data register 0x0a control selects ejtag control register 0x0b all selects the address, data and ejtag control registers 0x0c ejtagboot makes the processor take a debug exception after reset 0x0d normalboot makes the processor execute the reset handler after reset 0x0e fastdata selects the data and fastdata registers 0x0f (ejtag reserved) reserved for future ejtag use 0x010 tcbcontrola selects the control register tcbtracecontrol in the trace control block 0x011 tcbcontrolb selects another trace control block register 0x012 tcbaddress selects the address register used in the trace control block 0x013 ? 0x1b (ejtag reserved) reserved for future ejtag use 0x01c ? all 1?s (free for other use) free for other use, such as jtag boundary scan all 1?s bypass select bypass register table 20.41 ejtag tap instruction overview
idt ejtag system ejtag test access port 79rc32438 user reference manual 20 - 59 november 4, 2002 notes figure 20.26 jtag_tdi to jtag_tdo path in shft-dr state and all instruction is selected ejtagboot and normal boot instructions the ejtagboot and normalboot in structions control whether a debug interrupt is requested as a result of a reset. if ejtagboot is indicated t hen a debug interrupt is requested at reset, and a debug interrupt exception is taken right after the reset exception. the debug exception handler is in this case fetched from the probe through dmseg. it is possibl e to take the debug exception and execute the debug handler from the probe even if no instructions can be fetched from the reset handler. this condition guaran- tees that the system will not hang at reset when t he ejtagboot feature is used, not even if the normal memory system does not work properly. an internal ejtagboot indication holds information on the action to take at a processor reset, and this is set when the ejtagboot instruction takes effect in the update-ir state. t he indication is cleared when the normalboot instruction takes effect in the u pdate-ir state, or when the test-logic-reset state is entered, for example, when jtag_trst_n is assert ed low. the requirement of clearing the internal ejtagboot indication when the test-logic-reset stat e is entered, and not on a jtag_tck clock when in the state, ensures that the indication can be clear ed with five clocks on jtag_tck when jtag_tms is high. the internal ejtagboot indication is cleared at power-up either by a low value on the jtag_trst_n or by a power-up reset circuit. thus, the processor executes the reset handler after power-up unless the ejtagboot instruction is given through the ejtag tap. the bypass register is selected when the ejtagboot or normalboot instru ction is given. the ejtagbrk, proben, and probtrap bits in the ejtag control register follow the internal ejtagboot in dication. they are all set at processor reset if a debug interrupt exception is to be generated, wi th execution of the debug handler from the probe. fastdata instruction this selects the data and the fastdata registers at once, as shown in figure 20.27. figure 20.27 jtag_tdi to jtag_tdo path in shift-dr state and fastdata instruction is selected tap data registers table 20.42 summarizes the data regi sters in the ejtag tap. complete descriptions of these registers are given in the following sections. instruction used to access register register name function reference compli- ance idcode device id identifies device and accessed processor in the device. ?device identification (id) register (tap instruction idcode)? on page 20- 61 required table 20.42 ejtag tap data registers (part 1 of 2) jtag_tdi address register ejtag control register data register jtag_tdo msb 0 / lsb msb 0 / lsb msb 0 / lsb jtag_tdi fastdata register data register jtag_tdo msb 0 / lsb 0
idt ejtag system ejtag test access port 79rc32438 user reference manual 20 - 60 november 4, 2002 notes a read of a data register corresponds only to the capt ure-dr state of the tap controller, and a write of the data register corresponds to the u pdate-dr state only. the initial states of these registers are specified with either a reset state or a power-up state. if a reset state is specified, then the indicated value is applied impcode implementation identifies main debug features implemented and accessible through the tap. ?implementation register (tap instruction impcode)? on page 20- 62 required data, all, or fastdata data data register for processor access. ?data register (tap instruction data, all, or fastdata)? on page 20-63. required address or all address addres s register for processor access. ?address register (tap instruction address or all)? on page 20-64 required control or all ejtag control control register for most ejtag features used through the tap. ?ejtag control regis- ter (ecr) (tap instruc- tion control or all)? on page 20-65 required bypass, ejtag- boot, normal- boot, or unused ejtag instructions bypass provides a one bit shift path through the tap. ?bypass register (tap instruction bypass, (ejtag/normal) boot, or unused)? on page 20-70 required fastdata fastdata provides a one bit register whose value is tagged to the front of the data register to capture the value of the processor access pending (pracc) bit in the ejtag control register. ?fastdata instruction? on page 20-59 required with ejtag ver- sion 02.60 and higher. tcbcontrola tcbcontrola implemented and used in the trace control block (tcb). used by external probe (debugger) soft- ware to control tracing output from the core. see tcb documentation required with ejtag ver- sion 02.60 and higher if trace logic is implemented. tcbcontrolb tcbcontrolb implemented and used in the trace control block (tcb). con- trols tracing configuration options see tcb documentation required with ejtag ver- sion 02.60 and higher if trace logic is implemented. tcbaddress tcbaddress implemented and used in the tcb. used to address the on-chip trace memory, if present. see tcb documentation required with ejtag ver- sion 02.60 and higher if trace logic is implemented. instruction used to access register register name function reference compli- ance table 20.42 ejtag tap data registers (part 2 of 2)
idt ejtag system ejtag test access port 79rc32438 user reference manual 20 - 61 november 4, 2002 notes to the register when a processor reset is applied. if a power-up state is specified, then the indicated value is applied at power-up reset. jtag_tck does not have to be running in order for a processor reset to reset the registers. device identification (id) regist er (tap instruction idcode) compliance level : required with ejtag tap feature. the device id register is a 32-bi t read-only register that identifie s the specific device implementing ejtag. this register is also defined in ieee 1149. 1. the device id register holds a unique number among different devices with ejtag compliant processors implemented. it is recommended that the register is also unique amongst different ejtag compliant proces sors in the same device. figure 20.28 shows the format of the device id register and table 20.43 describes the device id register fields 31 28 27 12 11 1 0 version partnumber manufid 1 0000 0022 033 figure 20.28 device id register format fields description read/ write power-up state compli- ance name bits version 31_28 identifies the version of a specific device. the value in this field must be unique for particular values of manufacturer id and part number values. the value identifies a specific revision of the design (such as a sequence of bug fixes within the same major design). the value is assigned by the design house. r preset required part number 27:12 identifies the part number of a specific device. the value in this field must be unique for a particular manufacturer id value. design houses which wish to use the mips technologies, inc. manufacturer id may request assignment of a group of part numbers which are then managed by that design house. assignment of part num- bers within another manufacturer id value is done by the owner of that manufacturer id. r preset required table 20.43 device id register field description (part 1 of 2)
idt ejtag system ejtag test access port 79rc32438 user reference manual 20 - 62 november 4, 2002 notes implementation register (tap instruction impcode) compliance level : required with ejtag tap feature. the implementation register is a 32- bit read-only register t hat identifies features implemented in this ejtag compliant processor, mainly those accessible from the tap. figure 20.29 shows the format of the implementati on register and table 20.44 describes the implemen- tation register fields. manufid 11:1 identifies the manufacturer identity code of a specific device, which identifies the design house implementing the processor. according to ieee 1149.1-1990 section 11.2, the manufacturer identity code is a compressed form of a jedec standard manufacturer?s identification code in the jedec publications 106, which can be found at: http://www.jedec.org/ manufid[6:0] are derived from the last byte of the jedec code with the parity bit dis- carded. manufid[10:7] provide a binary count of the number of bytes in the jedec code that contain the continuation charac- ter (0x7f). when the number of continua- tions characters exceeds 15, these four bits contain the modulo-16 count of the number of continuation characters. if the design house does not have a jedec standard manufacturer's identifi- cation code, which is encoded for use in this field, the design house can request use of the mips technologies, inc. assigned number, or use the number assigned to the core provider. use of the mips technologies, inc. number requires prior approval of the director, mips archi- tecture. the mips technologies, inc. standard manufacturer's identification code is 0x127. r preset required 1 0 ignored on write; returns one on read. r preset required 31 29 28 27 25 24 23 22 21 20 17 16 15 14 13 1 0 ejtagver r4k/ r3k 0di nt sup 0 1 1. select either 000 or 010. asid size 0mi ps 16 0no dm a 0mips 32 010 0000 figure 20.29 implementation register format fields description read/ write power-up state compli- ance name bits table 20.43 device id register field description (part 2 of 2)
idt ejtag system ejtag test access port 79rc32438 user reference manual 20 - 63 november 4, 2002 notes data register (tap instruction data, all, or fastdata) compliance level : required with ejtag tap feature. the read/write data register is used for opcode and data transfers during processor accesses. the width of the data register is 32 bi ts for 32-bit processors and 64 bits fo r 64-bit processor. the value read in the data register is valid only if a processor access for a write is pending, in which case the data register holds the store value. the value written to the data register is only used if a processor access for a pending read is finished afterwards, in which case the data va lue written is the value for the fetch or load. this behavior implies that the data register is not a me mory location where a previously written value can be read afterwards. figure 20.30 shows the format of t he data register and table 20.45 describes the data register field. fields description read/ write power-up state compli- ance name bits ejtagver 31:29 version 2.6 r preset required r4k/rk3 28 indicated rk4 or rk3 privileged environ- ment: 0: r4k privileged environment r preset required dintsup 24 indicates support for dint signal from probe: 0: dint signal from the probe is not sup- ported by this processor 1: probe can use dint signal to make debug interrupt on this processor r preset required asidsize 22:21 indicates size of the asid field: 0: no asid in implementation r preset required mips16 16 indicates mips16? ase support in the processor: 0: no mips16 support r preset required nodma 14 indicates no ejtag dma support: 1: no ejtag dma support r preset required mips32/64 0 indicates 32-bit or 64-bit processor: 0: 32-bit processor see the r4k/r3k bit for indication of privi- leged environment. r preset required 0 27:25, 23, 20:17, 15, 13:1 ignored on writes; return zeros on reads. r preset required table 20.44 implementation register field description 31 0 data figure 20.30 data register format
idt ejtag system ejtag test access port 79rc32438 user reference manual 20 - 64 november 4, 2002 notes the contents of the data register are not aligned but hold data as it is seen on a data bus for an external memory system. thus the bytes are positioned in t he data register based on access size, address, and endianess. the bytes not accessed for a processor a ccess write are undefined, and the bytes not accessed for a processor access read can be written with any value by the probe shifting the value into the data register. table 20.46 shows the byte positioning for a 32-bit pr ocessor (mips32/64 = 0), in which case the two lsbs of the address register are used. byte 0 refers to bits 7:0, byte 1 refers to bits 15:8, byte 2 refers to bits 23:16, and byte 3 refers to bits 31:24, independent of endianess. address register (tap in struction address or all) compliance level : required with ejtag tap feature. the read-only address register prov ides the address for a processor access. the width of the register corresponds to the size of the physical address in t he processor implementation (from 32 to 64 bits). the specific length is determined by shifting through the address register, because the length is not indicated elsewhere. the value read in the r egister is valid if a processor access is pending, otherwise the value is undefined. the two or three lsbs of the register are used with the psz field from the ejtag control register to indicate the size and data position of t he pending processor access tr ansfer. these bits are not taken directly from the addre ss referenced by the load/store. figure 20.31 shows the format of the address regi ster and table 20.47 describes the address register field. fields description read/ write reset state compli- ance name bit data msb:0 data used by processor access. r/w undefined required table 20.45 data register field description psz from ecr size address[1: 0] little endian big endian 32103210 0byte 00 2 01 2 10 2 11 2 1 halfword 00 2 10 2 2word 00 2 3triple 00 2 01 2 reserved n.a. n.a. table 20.46 data register contents for 32-bit processors
idt ejtag system ejtag test access port 79rc32438 user reference manual 20 - 65 november 4, 2002 notes ejtag control register (ecr) (tap instruction control or all) compliance level : required with ejtag tap feature. the 32-bit ejtag control regist er (ecr) handles processor rese t and soft reset indication, debug mode indication, access start, finish, and size and read/write indication. the ecr also: ? controls debug vector location and indica tion of serviced processor accesses, ? allows a debug interrupt request, ? indicates processor low-power mode, and ? allows implementation-dependent processor and peripheral resets. the ejtag control register is not updated/written in the update-dr state unless the reset occurred; that is rocc (bit 31) is either already 0 or is wr itten to 0 at the same time. this condition ensures proper handling of processor accesses after a reset. reset of the processor can be indicated through the rocc bit in the jtag_tck domain a number of jtag_tck cycles after it is removed in the processor clock domain in order to allow for proper synchronization between the two clock domains. bits that are r/w in the register return their written value on a subsequent read, unless other behavior is defined. internal synchronization ensures that a written value is updated for reading i mmediately afterwards, even when the tap controller takes the shortest path from the update-dr to capt ure-dr state. figure 20.32 shows the format of the ejtag control register and table 20.48 descri bes the ejtag control register fields. msb 0 address figure 20.31 address register format fields description read/ write reset state compli- ance name bit address msb:0 address used by processor access. r undefined required table 20.47 address register field description 31302928 2322 212019 1817161514131211 4320 rocc psz 0 doze halt per rst prn w pr acc 0pr rst prob en prob trap 0ejta g brk 0dm0 figure 20.32 ejtag control register format
idt ejtag system ejtag test access port 79rc32438 user reference manual 20 - 66 november 4, 2002 notes fields description read/ write reset state compli- ance name bit rocc 31 indicates if a processor reset or soft reset has occurred since the bit was cleared: 0: no reset occurred 1: reset occurred the rocc bit stays set as long as reset is applied. this bit must be cleared to acknowledge that the reset was detected. the ejtag control register is not updated in the update-dr state unless rocc is 0 or writ- ten to 0 at the same time. this is in order to ensure correct handling of the processor access after reset. r/w0 1 required psz 30:29 indicates the size of a pending processor access, in combination with the address register: 32-bit processor mips32=0 mips32=1 0: byte byte 1: halfword halfword 2: word word, 5-7 bytes 3: triple triple, doubleword a full description is located in section ?data register (tap instruction data, all, or fastdata)? on page 20-63, including reserved combinations with address regis- ter bits. this field is valid only when a pro- cessor access is pending, otherwise the read value is undefined. r undefined required doze 22 indicates if the processor is in low-power mode: 0: processor is not in low-power mode 1: processor is in low-power mode doze indicates reduced power (rp) and wait, and other implementation-depen- dent low-power modes. if the implementation does not support low- power modes, then this bit always reads as 0. r0required halt 21 indicates if the internal system bus clock is running: 0: internal system bus clock is running 1: internal system bus clock is stopped halt indicates wait, and other implemen- tation-dependent events that stop the sys- tem bus clock. if the implementation does not support a halt state, then the bit always reads as 0. r0required table 20.48 ejtag control register field description (part 1 of 4)
idt ejtag system ejtag test access port 79rc32438 user reference manual 20 - 67 november 4, 2002 notes perrst 20 controls the peripheral reset with imple- mentation-dependent behavior: 0: no peripheral reset applied 1: peripheral reset applied this bit perrst might not have any effect. there is no inherent indication of whether the perrst is effective, so the user must consult system documentation. when this bit is changed, then it is only guaranteed that the new value has taken effect when it can be read back here. this handshake mechanism ensures that the setting from the jtag_tck clock domain takes effect in the processor clock domain and in peripherals. this bit is read-only (r) and reads as zero if not implemented. r/w 0 optional prnw 19 indicates read or write of a pending pro- cessor access: 0: read processor access, for a fetch/ load access 1: write processor access, for a store access this value is defined only when a proces- sor access is pending. r undefined required pracc 18 indicates a pending processor access and controls finishing of a pending processor access. when read: 0: no pending processor access 1: pending processor access a write of 0 finishes a processor access if pending; otherwise operation of the pro- cessor is undefined if the bit is written to 0 when no processor access is pending. a write of 1 is ignored. the fastdata access can clear this bit. r/w0 0 required fields description read/ write reset state compli- ance name bit table 20.48 ejtag control register field description (part 2 of 4)
idt ejtag system ejtag test access port 79rc32438 user reference manual 20 - 68 november 4, 2002 notes prrst 16 controls the processor reset with imple- mentation-dependent behavior: 0: no processor reset applied 1: processor reset applied the prrst bit might not have any effect. there is no inherent indication of an effec- tive prrst, so the user must consult system documentation. if a reset occurs on prrst, then all parts of the system are reset. it is not allowed for only some device to be reset. when this bit is changed then it is guaran- teed that the new value has taken effect when it can be read back here. this hand- shake mechanism ensures that the setting from the jtag_tck clock domain takes effect in the processor clock domain and in peripherals. however, because a processor reset clears this bit, then the effect of setting it can be that the bit is cleared when the reset takes effect. in this case, the rocc bit should be observed to detect that the reset took effect. this bit is read-only (r) and reads as zero if not implemented. r/w 0 optional proben 15 controls whether the probe handles accesses to dmseg through servicing of processors accesses: 0: probe does not service processors accesses 1: probe will service processor accesses the proben bit is reflected as a read-only bit in the debug control register (dcr) bit 0. when this bit is changed, then it is guaran- teed that the new value has taken effect in the dcr when it can be read back here. this handshake mechanism ensures that the setting from the jtag_tck clock domain takes effect in the processor clock domain. however, a change of the proben prior to setting the ejtagbrk bit will be effective for the debug handler. not all combinations of proben and prob- trap are allowed, see section ?combina- tions of probtrap and proben? on page 20- 70. r/w see section ?ejtag- boot indica- tion determines reset value of ejtagbrk, probtrap and proben? on page 20-70 required fields description read/ write reset state compli- ance name bit table 20.48 ejtag control register field description (part 3 of 4)
idt ejtag system ejtag test access port 79rc32438 user reference manual 20 - 69 november 4, 2002 notes probtrap 14 controls location of the debug exception vector: 0: normal memory 0xbfc0 0480 1: in dmseg at 0xff20 0200 when this bit is changed, then it is guaran- teed that the new value is indicated to the processor when it can be read back here. this handshake mechanism ensures that the setting from the jtag_tck clock domain takes effect in the processor clock domain. however, a change of the probtrap prior to setting the ejtagbrk bit will be effective at the debug exception. not all combinations of proben and prob- trap are allowed, see section?combina- tions of probtrap and proben? on page 20- 70. r/w see section ?ejtag- boot indica- tion determines reset value of ejtagbrk, probtrap and proben? on page 20-70 required ejtagbrk 12 requests a debug interrupt exception to the processor when this bit is written as 1. the debug exception request is ignored if the processor is already in debug at the time of the request. a write of 0 is ignored. the debug request restarts the processor clock if the processor was in a low-power mode. the read value indicates a pending debug interrupt exception requested through this bit: 0: no pending debug interrupt exception requested through this bit 1: pending debug interrupt exception the read value can, but is not required to, indicate other pending dint debug requests (for example, through the dint signal). this bit is cleared by hardware when the processor enters debug mode. r/w1 see section ?ejtag- boot indica- tion determines reset value of ejtagbrk, probtrap and proben? on page 20-70 required dm 3 indicates if the processor is in debug mode: 0: processor is in non-debug mode 1: processor is in debug mode r0required 0 28:23, 17, 13, 11:4, 2:0 must be written as zeros; return zeros on reads. 00required fields description read/ write reset state compli- ance name bit table 20.48 ejtag control register field description (part 4 of 4)
idt ejtag system ejtag test access port 79rc32438 user reference manual 20 - 70 november 4, 2002 notes ejtagboot indication determ ines reset value of ejtagbrk, probtrap and proben the reset value of the ejtagbrk, probtrap, and probe n bits follows the setting of the internal ejtag- boot indication. if the ejtagboot instruction has been given, and the internal ejtagboot indication is active, then the reset value of the three bits is set (1), otherwise the reset value is clear (0). the results of setting these bits are: ? a debug interrupt exception is requested ri ght after reset because ejtagbrk is set ? the debug handler is executed from the ejtag me mory because probtrap is set to indicate debug vector in ejtag memory at 0xff20 0200 ? service of the processor access is indicated because proben is set. thus, it is possible to execute the debug handler right after reset, without executing any instructions from the normal reset handler. combinations of probtrap and proben use of probtrap and proben allows independent specif ication of the debug exception vector location and availability of ejtag memory. behavior for the di fferent combinations is shown in table 20.49. note that not all combinations are allowed. bypass register (tap instruction bypa ss, (ejtag/normal) boot, or unused) compliance level : required with ejtag tap. the bypass register is a one-bit read-only register, which provides a minimum shift path through the tap. this register is also defined in ieee 1149.1. figure 20.33 shows the format of the bypass register and table 20.50 describes the bypass register field. examples of use an example of the tap operation is shown in figure 20.34. jtag_trst_n is assumed deasserted high. probtrap proben debug exception vector processor accesses 0 0 normal memory at 0xbfc0 0480 not serviced by probe 0 1 not serviced by probe 1 0 if these two bits are changed to this state, the operation of the processor is undefined, indicating that the debug exception vector is in ejtag memory, but the probe will not service processor accesses. 1 1 ejtag memory at 0xff20 0200 serviced by probe table 20.49 combinations of probtrap and proben 0 32-bit processor 0 figure 20.33 bypass register format fields description read/ write reset state compli- ance name bit 0 0 ignored on writes; returns zero on reads. r 0 required table 20.50 bypass register field description
idt ejtag system ejtag test access port 79rc32438 user reference manual 20 - 71 november 4, 2002 notes figure 20.34 tap operation example the five-bit instruction register is initially loaded wi th 000012. the first bit shifted out of the instruction register is a 1 followed by four 0?s. ir0 to ir4 indicate the new value fo r the instruction register. ir0, the new lsb, is shifted in first, because it will be at t he lsb position once all five bits are shifted in. this example is similar for the selected data register. manufid value table 20.51shows the values of the manufid field in the device id register as defined by the manufac- turer. the device id register is described in section ?device identification (i d) register (tap instruction idcode)? on page 20-61. rocc bit usage the r/w0 rocc bit in the ejtag control register acknowledges that the pr obe has seen a processor reset, and further accesses take this reset into account. th is bit is set at reset. the probe must clear it as an acknowledge of the reset. all other writes to the ejta g control register, except for the reset acknowledge, should write 1 to this bit in order to not acknowledge any resets occu rring between reads and writes of the ejtag control register. correct use of the rocc bit ens ures safe handling of processor access even across reset. an example is the following scenario: 1. a processor access is pending and the pracc is read with value 1 (rocc has been cleared previ- ously). 2. the address and data registers are acce ssed and set up to handle the processor access. 3. the ejtag control register is accessed to finish the processor access. the register is read in the capture-dr state. shifting in of the value to write begins. company jdec code continuations last byte without carry manufid value idt 0xb3 0 0x33 0x33 table 20.51 manufid field value example run-test/idle jtag_tck select-dr-scan capture-ir shift-ir exit1-ir update-ir select-dr-scan capture-dr shift-dr select-ir-scan jtag_tms jtag_tdi jtag_tdo tap controller ir0 ir1 ir2 ir3 ir4 dr0 dr1 dr2
idt ejtag system ejtag test access port 79rc32438 user reference manual 20 - 72 november 4, 2002 notes 4. a reset of the processor occurs, the rocc bit is set, and the pracc bit is cleared. 5. a new processor access occurs, because ejtagboot was indicated. 6. a write of the ejtag control register is a ttempted with pracc equal to 0 and rocc equal to 1, but the write does not occur because the rocc bit is set. the new processor access that was not seen is not finished. 7. polling of the ejtag control register conti nues. the probe detects that the rocc bit is set. 8. the probe writes the ejtag control register wi th rocc equal to 0 to acknowledge that the probe has seen the reset. 9. the new processor access is serviced as usual. inhibiting writes to the ejtag control register bec ause of the rocc bit ensures that the new processor access is not finished by mistak e due to detection of a pending processor access before the reset occurred. ejtag memory access through processor access the processor access feature makes it possible fo r the probe to handle accesses from the processor to the specific ejtag memory area (dmseg). the pr ocessor can execute a debug handler from ejtag memory, whereby applications that are not prepared wi th ejtag code in the system memory can still be debugged. the probe can get information about the ac cess through the tap, as shown in table 20.52. the servicing of processor accesses works with a polling scheme, where the pracc bit is polled until a pending processor access is indicated by pracc equal to 1. then the address register is read to get the address of the transaction, and the data register is accessed to get the write data or provide the read data. finally the pracc bit is cleared, in order to finish the access from the processor. in addition, the probtrap and proben bits control the debug exception vector location and the indication to the processor that the probe will service acce sses to the ejtag memory through processor accesses. handling of processor access in relation to reset re quires specific handling. a pending processor access is cleared at reset. at the same time, the rocc bit is set, thereby inhibiting any processor accesses to be finished until rocc is cleared. thus, the probe will have to acknowledge that a reset occurred, preventing it from accidentally finishing a processor access that occurred before the reset. a pending processor access can only finish if the probe clears pr acc or a processor reset occurs. the width of the address register is 32 to 64 bits. the specific lengt h is determined by shifting a known bit pattern through the register. the following sections show examples of servic ing read and write processor accesses. write processor access figure 20.35 shows a possible flow for servicing a write processor access. the example implements a 32-bit processor with 32-bit address register, running in little-endian mode. a halfword store is performed to address 0xff20 1232 of value 0x5678. information field and register pending processor access pracc field in the ejtag control register read or write access prnw field in the ejtag control register size and data location psz field in ejtag control register, and two or three lsbs in the address register address address register data data register table 20.52 information provided to probe at processor access
idt ejtag system ejtag test access port 79rc32438 user reference manual 20 - 73 november 4, 2002 notes figure 20.35 write processor access example the different probe actions shown on the figure are described below: 1. the ejtag control register is polled to get the indication for a pending pracc bit. the pracc bit is written to 1 when polling, in order to prevent a processor access from finishing before being serviced. the values of prnw and psz are sa ved when pracc indicates a pending processor access. 2. the address register is read. it contains the address of the store resulting in the write processor access. 3. the data register is read, which contains the data from the store resulting in the write processor access. 4. the pracc bit is written to 0, in order to finish the processor access. the probe must update the appropriate bytes in its inte rnal memory used for ejtag memory with the value of the write. note that the two lower bytes of the data register are undefined, and that the two lower bytes of the saved register are shifted up on the two hi gh bytes in the data register as on a data bus for an external memory system. the address register in this case contains the address from the store; however, for some accesses, this is not the case because t he two lsbs (32-bit processor) are modified for some accesses depending on size and address. read processor access figure 20.36 shows a possible flow for servicing a read processor access. the example implements a 64-bit processor with 36-bit address register. a doubleword load/fetch from address 0xff20 3450 is shown in the figure. pracc probe action prnw psz address data 1 1 data = = 0x5678 xxxx address = = 0xff20 1232 size = 1 2 3 4 1 1
idt ejtag system on-chip interfaces 79rc32438 user reference manual 20 - 74 november 4, 2002 notes figure 20.36 read processor access example the different probe actions shown in the above figure are described below: 1. the ejtag control register is polled to get the indication for a pending pracc bit. the pracc bit is written to 1 when polling, in order to prevent a processor access from finishing before being serviced. the values of prnw and psz are sa ved when pracc indicates a pending processor access. 2. the address register is read. it contains the address of the load/fetc h resulting in the write processor access, with the three lsbs (64-bi t processor) modified to allow si ze indication together with the psz. 3. the data register is written with the data to retu rn for the load/fetch, resulting in the read processor access. 4. the pracc bit is cleared in order to finish the processor access. the probe must provide data for the read processor ac cess from the internal ejtag memory. note that the address register does not contai n the direct address from the acce ss, because the three lsbs (64-bit processor) are modified to indicate t he size in conjunction with psz. also notice that in this case, there is no shifting of the data returned for the processor access by writing to the data register, because a doubleword is provided. for other accesses, the data register must be written with a shifted value depending on the specific access. on-chip interfaces optional jtag_trst_n pin the jtag_trst_n signal to the tap is optional, and need not be provided as a pin on the chip for a processor implementing the ejtag tap. if a jtag_trst_ n chip pin is not provided, then a tap reset like the one provided when jtag_trst_n is asserted (low ) must be applied to the tap at power-up, for example, through a power-up reset circuit on the chip. this power-up tap reset must be finished after the time t viorise (see figure 20.41). if a jtag_trst_n chip pin is provided, then the power-up tap reset is applied by a pull-down resistor, because the pr obe will not drive jtag_trst_n at power-up. input buffers with pull-up/down and output drivers for chip pins if an input buffer with an integrated pull-up resistor is used for the jtag_trst_n chip pin, then its resistor value must be sufficiently large that it is ov erruled by the external pull- down resistor on the pcb, so a well-defined logical level is present on the jtag_trs t_n pin (refer to section ?electrical connection? on page 20-81). observe the additional rules described in the ieee std. 1149.1 specification, if the same tap pracc probe action prnw psz address data 1 1 data = address = = 0xf ff20 3457 size = 3 2 3 4 1 1 0x0..0 0..0 0..0 beef
idt ejtag system off-chip and probe interfaces 79rc32438 user reference manual 20 - 75 november 4, 2002 notes is used for jtag boundary scan also. the output driver for the jtag_tdo chip pin must be capable of supplying the iol and ioh current required for the pr obe (see ?dc electrical characteristics? on page 20- 79). connecting multi-core test access port (tap) controllers this section is concerned with building a multi-co re system where each core has its own tap controller, but share one set of external ejtag tap controller pins . note that this section does not attempt to address the full issue of multi-core debug, which involv es resolving debugger issues and other hardware issues such as debug signalling among multiple cores, and handling breakpoints across multiple cores, etc. figure 20.37 shows the recommended daisy-chain connection fo r a multi-core configuration, where the jtag_tck, jtag_tms and optional jtag_trst_n si gnals of all the tap controllers are connected together. the jtag_tdi and jtag_tdo signals are daisy chained together so that the information flow between the selected register of all the tap controllers is a continuous sequence. figure 20.37 daisy chaining of multi-core ejtag tap controllers the simplest usage model for this multi-core c onnection, under most circumstance, only uses one ?active? device. this is accomplished by including bypass tap instruction for ?non-active? devices in every tap command chain sent by the debugger. ?non-active? devices only get attention when made ?active?. note that it is not necessary that only one device be ?active? at a time, it depends entirely on how the debugger and the end-user want to control the multiple on-chip tap controllers. it is recommended that the ejtag taps are connecte d in a single daisy-chain without any non-ejtag taps in that chain, since this provide the fastest access to the ejtag taps and it allows the most debug software packages to operate the ejtag taps. special care must be taken by the system designer if both ejtag taps and non-ejtag taps are connected in the same chain. in this case the system designer must ensure that both the ejtag debug hardware and software, and the external device using the non- ejtag taps can apply the bypass tap instruction when the taps unrelated to the current operation are to be made ?non-active?. off-chip and probe interfaces the off-chip interface forms the connection from t he chip over the target system pcb and to the probe connector, thereby allowing the probe to connect to t he target processor. the probe connection is optional in the target system. the probe si gnals are described with respect to logical functionality, timing behavior, electrical characteristics, and connector and pcb design. comments ar e also added with respect to probe functionality. the descriptions in this chapter only co ver issues related to ejtag use of the test access port (tap). issues related to reuse of the same tap on a chip, for example, for jtag boundary scan, are not covered. probe jtag_tck jtag_tms jtag_tdo jtag_tdi jtag_trst_n connector jtag_tck jtag_tms jtag_tdo jtag_tdi jtag_trst_n ejtag tap 1 (jtag_trst_n is optional) jtag_tck jtag_tms jtag_tdo jtag_tdi jtag_trst_n ejtag tap n (jtag_trst_n is optional) several ejtag taps possible
idt ejtag system off-chip and probe interfaces 79rc32438 user reference manual 20 - 76 november 4, 2002 notes logical signals this section describes the ejtag signal s categorized according to functionality: ? test access port: jtag_tck, jtag_tms, jt ag_tdi, jtag_tdo, and jtag_trst_n (optional) ? system reset (reset or soft reset): rstn ? voltage sense for i/o: vcc i/o. figure 20.38 shows the signal flow between the chip, target system pcb, and probe. figure 20.38 signal flow between chip, target system pcb, and probe test access port signals the jtag_tck, ejtag_tms, jtag_tdi, jtag_t do, and jtag_trst_n signals make up the test access port (tap). for more details about the logical functionality of these signals, refer to section ?ejtag test access port? on page 20-54. these five signals are described in table 20.53 below. signal description direction compliance jtag_tck test clock input is the clock that controls the updates of the tap controller and the shifts through the instruction or selected data register(s). both the rising and the falling edges of jtag_tck are used. input required with probe connection ejtag_tms test mode select input is the control signal for the tap controller. this signal is sampled at the rising edge of jtag_tck. input jtag_tdi test data input has the data shifted into the instruction or data register. this signal is sampled on the rising edge of jtag_tck input jtag_tdo test data output has the data shifted out from the instruc- tion or data register. this signal is changed on the falling edge of jtag_tck. output jtag_trst_n test reset input is used for the tap reset of the tap con- troller, instruction register, and ejtagboot indication. tap reset is applied asynchronously when low. input optional with probe connection table 20.53 tap signals overview target system probe tck tms tdo tdi trst* rstn vcc i/o connector jtag_tck ejtag_tms jtag_tdo jtag_tdi jtag_trst_n chip with ejtag reset other reset sources (jtag_trst_n is optional, see description) chip i/o voltage reset circuit target system dint no connect
idt ejtag system off-chip and probe interfaces 79rc32438 user reference manual 20 - 77 november 4, 2002 notes the jtag_trst_n chip pin is optional. if jtag_trs t_n is not provided, then the tap controller must be reset by a power-up reset circuit on-chip. refer to section ?voltage sense for i/o (vcc i/o) timing? on page 20-79 for duration of this power-up reset. system reset signal the system reset (rstn) signal from the probe is required to generate a reset of the target board. it is recommended that assertion of rstn results in a (hard) reset of the processor, but it is allowed to generate a soft reset. table 20.54 briefly describes the rstn signal. the probe controls the rstn via an open-collector (oc) output. thus, rstn is actively driven low when asserted (low) but is tri-stated when deasserted (high). voltage sense for i/o signal the voltage sense for i/o (vcc i/o) indicates target power is applied and voltage levels are present at the probe i/o connections. table 20.55 br iefly describes the vcc i/o signal. with vcc i/o, the probe can auto adjust the voltage level for the signals, and detect if power is lost at the target system. ac timing characteristics the timing relations and ac requirements for the signal s are described in this section. the timing is measured at the probe connector for the target system, and must be valid in the full operating range of the target board. all setup and hold times are meas ured with respect to the 50% value between v il / v ih for inputs, and v ol / v oh for outputs. all rise and fall times are measured at 20% and 80% of the values of v il / v ih for inputs and v ol / v oh for outputs. the capacitance of c target and c probe is assumed to be as seen from the probe connector for the inputs and outputs. test access port timing figure 20.39 shows the timing relationships of the five tap signals, jtag_tck, ejtag_tms, jtag_tdi, jtag_tdo, and jtag_trst_n. table 20.56 s hows the absolute times for the symbols in the figure. signal description direction compliance rstn rstn is the system reset of the target board. when the probe asserts rstn low, the re sult is either a reset (rec- ommended) or soft reset of the processor. no reset is applied when the rstn is undriven (tri-stated from the probe). input required with probe connection table 20.54 tap signals overview signal description direction compliance vcc i/o voltage sense for i/o indicates if target power is applied, and indicates the voltage level for the probe signals. output required with probe connection table 20.55 tap signals overview
idt ejtag system off-chip and probe interfaces 79rc32438 user reference manual 20 - 78 november 4, 2002 notes figure 20.39 tap signals timing jtag_trst_n is independent of the jtag_tck signal , because jtag_trst_n is a truly asynchro- nous signal. note the ieee 1149.1 recommendation in 3. 6.1 (d): ?to ensure deterministic operation of the test logic, ejtag_tms should be held at 1 while the signal applied at jtag_trst_n changes from 0 to 1.? a race might otherwise occur if jtag_trst_n is deasserted (going from low to high) on a rising edge of jtag_tck when ejtag_tms is low, because the tap controller might go either to run-test/idle state or stay in the test-logic-reset state. system reset timing figure 20.40 shows the timing for the rstn signal from the probe. table 20.57 shows the absolute times for the symbols in the figure. the target s ystem is responsible for extending the rstn pulse if required. symbol description min. max. unit t tckcyc jtag_tck cycle time 25 ns t tckhigh jtag_tck high time 10 ns t tcklow jtag_tck low time 10 ns t tsetup tap signals setup time before rising jtag_tck 5 ns t thold tap signals hold time after rising jtag_tck 3 ns t tdoout tdo output delay time from falling jtag_tck 5 ns t tdozstate tdo tri-state delay time from falling jtag_tck 5 ns t trst*low jtag_trst_n low time 25 ns t rf tap signals rise / fall time, all input and output 3 ns table 20.56 tap signals timing values jtag_tck t tckcyc t tckhigh t tcklow jtag_trst_n t trst*low ejtag_tms jtag_tdi t tdoout t thold t tdozstate jtag_tdo t tsetup undefined defined t rf t rf t rf t rf t rf
idt ejtag system off-chip and probe interfaces 79rc32438 user reference manual 20 - 79 november 4, 2002 notes figure 20.40 system reset signal timing voltage sense for i/o (vcc i/o) timing figure 20.41 shows the timing for the vcc i/o signal. table 20.58 shows the absolute time for the symbol in the figure. vcc i/o must rise to the stable level within a specific time t viorise after the probe detects vccio to be above a certain limit t vioactive . figure 20.41 voltage sense for i/o signal timing the target system must ensure that t viorise is obeyed after the t vioactive value is reached, so the probe can use this value to determine when the target has powered-up. the probe is allowed to measure the t viorise time from a higher value than t vioactive (but lower than vcc i/o mini mum) because the stable indi- cation in this case comes later than the time when target power is guaranteed to be stable. if jtag_trst_n is asserted by a pulse at power-up, ei ther on-chip or on pcb, then this reset must be completed after t viorise . if jtag_trst_n is asserted by a pull-dow n resistor, then the probe will control jtag_trst_n. at power-down, no power is indi cated to the probe when vcc i/o drops under the t vioactive value, which the probe uses to stop driv ing the input signals, except for rstn. dc electrical characteristics table 20.59 describes the dc electrical characte ristics for voltage and current measured at the probe connector. current measures positive in direction fr om the probe to the target system, and negative in the other direction. the characteristics apply to the full operating range of the target system. symbol description min. max. unit t rstnlow rstn low time. 1 ms table 20.57 system reset signal timing value symbol description min. max. unit t viorise vcc i/o rise time from t vioactive to stable vcc i/o value. 2 sec table 20.58 voltage sense for i/o signal timing value rstn t rstnlow driven low undriven tri-stated vcc i/o t viorise t vioactive
idt ejtag system off-chip and probe interfaces 79rc32438 user reference manual 20 - 80 november 4, 2002 notes the i zstate specifies the current that a tri-stated (undriv en) output driver and pull- up/down can provide. it sets a limit for the drivers in the probe for jt ag_tck, ejtag_tms, jtag_tdi, jtag_trst_n, and rstn, and it sets a limit for the output driver on-chip for jtag_tdo. this limit allows design of pull-up/ down resistors that can keep a logical leve l when no driver is controlling the signal. c target and c probe are the capacitances in the target syst em for inputs and the capacitances for the probe for outputs. additional capacitance in the target system must be added to c probe when designing the output driver, and additional capacitanc e for the probe driver is added to c tar get . mechanical connector figure 20.42 shows the recommended ejtag connecto r on a target system. the connector is a common pin strip with dimensions 0.100? x 0.100?, for example, samtec part number tsw-107-23-l-d or compatible. the socket on the probe side must allow for an angled connector on the target system. symbol description condition min. type max. unit vcc i/o vcc i/o voltage when stable 1.5 5.0 v t vioactive t vio active indication 0.5 v i vio i vio output current 20 ma v il low-level input voltage 2.8v < t vio -0.3 0.8 v t vio < 2.8v -0.3 0.3*t vio v v ih high-level input voltage 2.8v < t vio 2.0 t vio +0.3 v t vio < 2.8v 0.7*t vio t vio +0.3 v v ol low-level output voltage 2.8v < t vio -0.3 .04 v t vio < 2.8v -0.3 0.15*t vio v v oh high-level output voltage 2.8v < t vio 2.4 t vio +0.3 v t vio < 2.8v 0.85*t vio t vio +0.3 v i il low-level input current, except rstn -8.0 ma i rst rstn low-level input current -10 ma i ih high level input current 8.0 ma i ol low level output current 8.0 ma i oh high level output current -8.0 ma i zstate tri-state input or output current 0 < v sig < t vio -50 50 a c target capacitance for target system 25 pf c probe capacitance for probe 25 pf table 20.59 dc electrical characteristics
idt ejtag system off-chip and probe interfaces 79rc32438 user reference manual 20 - 81 november 4, 2002 notes figure 20.42 ejtag connector mechanical dimensions note: the connector in figure 20.42 does not provi de pc trace signals. an additional connector, probably with 0.05? x 0.05? spacing, will be def ined later when the pc trace feature is redefined. table 20.60 shows the pin assignments for the connector. note: pin 12 on the target system connector should be removed to provide keying, thus ensuring the probe is correctly connected to the target system. target system pcb design this section provides guidelines for usi ng the ejtag connector on a target system. electrical connection figure 20.43 shows the electrical connection of t he target system connector. this subsection only covers the case where the probe connects directly to a chip with an ejtag compliant processor. pin signal direction pin signal direction 1 jtag_trst_n test reset input input 2 ground gnd 3 jtag_tdi test data input input 4 ground gnd 5 jtag_tdo test data output output 6 ground gnd 7ejtag_tms test mode select input input 8 ground gnd 9 jtag_tck test clock input input 10 ground gnd 11 rstn system reset input 12 key - pin removed on connector na 13 dint (no connect) debug interrupt input 14 vcc i/o voltage sense for i/o output table 20.60 ejtag connector pinout 2.54 mm top view on pcb 2.54 mm 12 13 14 pin 12 removed to allow for key 0.64 mm 5.84 mm side view on pcb gnd signal positions 1 gnd gnd gnd gnd key vccio jtag_trstn jtag_tdi jtag_tdo ejtag_tms jtag_tck rstn (no connect) dint
idt ejtag system off-chip and probe interfaces 79rc32438 user reference manual 20 - 82 november 4, 2002 notes figure 20.43 target system electrical ejtag connection in figure 20.43, the pull-up resistors for jtag_t ck, ejtag_tms, jtag_tdi, and rstn, the pull-down resistor for jtag_trst_n, and the series resistor fo r jtag_tdo must be adjusted to the specific design. however, the recommended pull-up/down resistor is 1.0 k ? , because a low value reduces crosstalk on the cable to the connector, allowing higher jtag_tck frequenc ies. a typical value for the series resistor is 33 ? . recommended resistor values have 5% tolerance. the ieee 1149.1 specification requires that the ejta g tap controller is reset at power-up, which can occur through a pull-down resistor on jtag_trst_n if the probe is not connected. however, on-chip pull- up resistors are implemented on the rc32438 due to an ieee 1149.1 requirement. having on-chip pull-up and external pull-down resistors for the jtag_trst_n signal requires special care in the design to ensure that a valid logical level is provided to jtag_trs t_n, for example, using a small external pull-down resistor to ensure this level overrides the on-chip pull -up. an alternative is to use an active power-up reset circuit for jtag_trst_n, which drives jt ag_trst_n low only at power-up and then holds jtag_trst_n high afterwards with a pull-up resistor. the pull-up resistor on jtag_tdo must ensure that the jtag_tdo level is high when no probe is connected and the jtag_tdo output is tri-stated. this requirement allows reli able connection of the probe if it is hooked-up when the power is already on ( hot plug). the pull-up resistor value of around 47 k ? should be sufficient. optional diodes to protect against overshoot and undershoot voltage can be provided on the signals to the chip with ejtag. the rst* signal must have a pull-up resistor because it is controlled by an open-collector (oc) driver in the probe, and thus is actively pull ed low only. the pull-up re sistor is responsible for the high value when not driven by the probe. the input on the target system reset circuit must be able to accept the rise time when the pull-up resistor charges the c target and c probe capacitance to a high logical level. vcc i/o must connect to a voltage refer ence that drops rapidly to below t vioactive when the target system loses power, even with the capacitive load of c probe . the probe can thus detect the lost power condition. layout considerations layout around the pin connector on the target system mu st provide for sufficient clearance for the probe to connect. figure 20.44 shows the recommended clearanc e. place the connector at the edge of the pcb. avoid tall components around the connector to allow for easy access. gnd 1 gnd gnd gnd gnd trst* tdi tdo tms tck rst* dint jtag_trst_n jtag_tdi jtag_tdo ejtag_tms jtag_tck gnd vdd gnd vccio voltage reference pull-up pull-down series-res. reset (soft/hard) target system reset circuit pull-up other reset sources vccio rc32438 no connect
idt ejtag system off-chip and probe interfaces 79rc32438 user reference manual 20 - 83 november 4, 2002 notes figure 20.44 target system layout for ejtag connection probe requirements and recommendations a probe connected to the target system at power-up is not allowed to drive the inputs before vio indi- cates a stable voltage. jtag_trst_n (if present) is t hen asserted by the target system pull-down resistor at power-up, whereby a tap reset is app lied through jtag_trst_n for taps, depending on jtag_trst_n. this step implies that inputs are not driven until the target system is powered up; otherwise the communication on the tap might be undefined or damage could occur. at power-down the probe is not allowed to drive the inputs after vio has dropped under a ce rtain level (refer to section ?voltage sense for i/ o (vcc i/o) timing? on page 20-79). the rstn signal is an exception to the above description because it can be driven low by the probe during power-up. hot plug in of probe the probe must not drive any inputs to the target syst em if it is connected while the system is running (hot plug). detection of a stable vcc i/o from the tar get system is required before any input is allowed. to avoid spikes or changes in the input voltage to the ta rget system when the probe is connected, the level of the signal on the probe must be adjusted to the same leve l as the signals on the target system. this adjust- ment can be done with large pull-up/dow n resistors (in the range of 150 k ? ) on the probe signals, so the level of these signals matches the level on the target system shown in figure 20.44. the specific implemen- tation of this feature is dependent on the probe, the driver type, etc. used in the probe. jtag_tdo level when tri-stated the probe must apply a pull-up resistor on jtag_tdo to have a well-defined logical level when jtag_tdo on the tap is tri-stated. the pull-up on the target system ensures the level at hot plug. the size of the pull-up on the probe is expected to be 1.0 k ? or more. the resistor value must be chosen so i zstate is observed. rstn drive by open collector drive the rstn signal with an open-collector (oc) out put driver to allow for easy connection of the rstn signal in the target system. target system pcb 4.0 mm 4.0 mm 3.0 mm 3.0 mm no components taller than the base of the pin header should be placed in the marked area 1
idt ejtag system off-chip and probe interfaces 79rc32438 user reference manual 20 - 84 november 4, 2002 notes changing jtag_tms and jtag_tdi it is recommended that the ejtag_tms and jtag_tdi signals driven by the probe change in relation to the falling edge generated on the jtag_tck, since th is ensures a high setup and hold time for the ejtag_tms and jtag_tdi in relation to the ri sing edge of jtag_tck, on which these signals are sampled by the target processor. if the jtag_tck clock speed can be adjusted by extending the high and low period time of the jtag_tck clock, then the behavior described above will also make the probe work even with a target processor not respecting set up and hold time, simply by lowering the jtag_tck frequency. mechanical connector the female connector from the probe must allow for an angled board connector. block hole 12 on the probe connector in order to provide keying and ensure correct connection of the probe to the target system. connect the signal from the probe at line 12 to gnd on the probe.
notes 79rc32355 user reference manual a - 1 november 4, 2002 appendix a 4kc processor core instructions introduction this appendix contains additional info rmation about the 4kc processor core instruction set. chapter 2 of this manual contains a description of the processor core and its operation. understanding the instruction set figure a.1 shows an example instruction.
idt understanding the instruction set 79rc32355 user reference manual a - 2 november 4, 2002 notes figure a.1 example of instruction description instruction fields fields encoding the instruction word are shown in regi ster form at the top of the instruction description. the following rules are followed: the values of constant fields and the opcode names for opcode fields are listed in uppercase (spe- cial and add in figure a.1). all variable fields are listed with the lowercase nam es used in the instruction description (rs, rt and rd in figure a.1). fields that contain zeros but are not named are unus ed fields that are required to be zero (bits 10:6 instruction mnemonic and descriptive name instruction encoding constant and variable field names and values architecture level at which instruction was defined/ redefined and assembler format(s) for each definition short description symbolic description full description of instruction operation restrictions on instruction and operands high-level language description of instruction operation exceptions that instruction can cause notes for programmers notes for implementors example instruction name example 31 25 26 20 21 15 16 special rs rt 655 rd 0 example 55 6 11 10 6 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 format: example rd, rs,rt mips32 purpose: to execute an exampe op description: rd rs exampleop rt. this section describes the operation of the instruction in text, tables, and illustra- tions. it includes information that would be difficult to encode in the operation section. restrictions: this section lists any restrictions for the instruction. this can include values of the instruction encoding fields such as register specifiers, operand values, oper- and formats, address alignment, instruction scheduling hazards, and type of memory access for addressed locations. operation: /* this section describes the operation of an instruction in a */ /* high-level pseudo-language. it is precise in ways that the */ /* description section is not, but is also missing information */ /* that is hard to express in pseudocode.*/ temp gpr[rs] exampleop gpr[rt] gpr[rd] temp exceptions: a list of exceptions taken by the instruction programming notes: information useful to programmers, but not necessary to describe the operation of the instruction implementation notes: like programming notes , except for processor implementors
idt understanding the instruction set 79rc32355 user reference manual a - 3 november 4, 2002 notes in figure a.1) if such fields are set to non-zero values, the operation of the processor is unpre- dictable. figure a.1 example of instruction fields instruction descriptive name and mnemonic the instruction descriptive nam e and mnemonic are printed as page headings for each instruction, as shown in figure a.2. figure a.2 example of instruction descriptive and mnemonic name format field the assembler formats for the instruction and the architecture level at which the instruction was origi- nally defined are given in the format field. if the in struction definition was later extended, the architecture levels at which it was extended and the assembler formats for the extended definition are shown in their order of extension (for an example, see c.cond.fmt). the mips architec ture levels are inclusive; higher architecture levels include all instructions in previ ous levels. extensions to instructions are backwards compatible. the original assembler formats are valid for the extended architecture. figure a.3 example of instruction format the assembler format is shown with literal parts of the assembler instruction printed in uppercase char- acters. the variable parts, the operands , are shown as the lowercase names of the appropriate fields. the architectural level at which the instruction was first def ined, for example ?mips32? is shown at the right side of the page. purpose field the purpose field gives a short descrip tion of the use of the instruction. figure a.4 example of instruction purpose description field if a one-line symbolic description of the instruction is feasible, it appears immediately to the right of the description heading. the main purpose is to show how fields in the instruction are used in the arithmetic or logical operation. 31 26 25 21 20 16 15 11 10 6 5 0 special 000000 rs rt rd 0 00000 add 100000 6 55556 add word add format: add rd, rs rt mips32 purpose: to add 32-bit integers. if an overflow occurs, then trap.
idt understanding the instruction set 79rc32355 user reference manual a - 4 november 4, 2002 notes figure a.5 example of instruction description the body of the section is a description of the operat ion of the instruction in text, tables, and figures. this description complements the high-leve l language description in the operation section. this section uses acronyms for register descriptions . ?gpr rt? is cpu general- purpose register specified by the instruction field rt. restrictions field the restrictions field documents any possible restrictions that may affe ct the instruction. most restric- tions fall into one of the following six categories: valid values for instruction fields (f or example, see fl oating-point add.fmt) alignment requirements for memory addresses (for example, see lw) valid values of operands (for example, see dadd) valid operand formats (for exampl e, see floating-point add.fmt) order of instructions necessary to guarantee corr ect execution. these or dering constraints avoid pipeline hazards for which some processors do not have hardware interlocks (for example, see mul). valid memory access types (for example, see ll/sc). figure a.6 example of instruction restrictions operation field the operation field descr ibes the operation of the instruct ion as pseudocode in a high-level language notation resembling pascal (see figure a.7). this form al description complements the description section; it is not complete in itself because many of the rest rictions are either difficult to include in the pseudocode or are omitted for legibility. description: rd rs + rt the 32-bit word value in gpr rt is added to the 32- bit value in dpr rs to produce a 32-bit result. if the addition results in 32-bit 2?s complement arit hmetic overflow, the destination register is not modified and an integer over flow exception occurs. if the addition does not overflow, the 32- bit result is placed into gpr rd. restrictions: processor operation is unpredictable if a branch, jump, eret, deret, or wait instruction is placed in the delay slot of a branch or jump.
idt operation section notation and functions 79rc32355 user reference manual a - 5 november 4, 2002 notes figure a.7 sample instruction operation exceptions field the exceptions field lists the exc eptions that can be caused by oper ation of the instruction. it omits exceptions that can be caused by the instruction fetc h, for instance, tlb refill, and also omits exceptions that can be caused by asynchronous external events su ch as an interrupt. although a bus error exception may be caused by the operation of a load or store inst ruction, this section does not list bus error for load and store instructions because the relationship between load and store instructions and external error indi- cations, like bus error, ar e dependent upon the implementation. figure a.8 sample instruction exception an instruction may cause implementation-dependent exc eptions that are not present in the exceptions section. programming notes and implementation notes fields the notes sections contain material that is useful for programmer s and implementors, respectively, but that is not necessary to describe the instruct ion and does not belong in the description sections. figure a.9 sample instruction programming notes operation section nota tion and functions in an instruction description, the operation secti on uses a high-level language notation to describe the operation performed by each instruction. the cont ents of the operation section are described here, including the special symbols and functions that are used. instruction execution ordering each of the high-level language statements in the operations section are executed sequentially (except as constrained by conditi onal and loop constructs). operation: temp (gpr[rs] 31 ||gpr[rs] 31..0 ) + (gpr[rt] 31 ||gpr[rt] 31..0 ) if temp32 temp 31 then signalexception(intergeroverflow) else gpr[rd] temp endif exceptions: integer overflow programming notes: addu performs the same arithmetic operation but does not trap on overflow.
idt operation section notation and functions 79rc32355 user reference manual a - 6 november 4, 2002 notes special symbols in pseudocode notation special symbols used in the pseudocode notation are listed in table a.1. symbol meaning assignment =, tests for equality and inequality || bit string concatenation x y a y -bit string formed by y copies of the single-bit value x b#n a constant value n in base b . for instance 10#100 represents the decimal value 100, 2#100 represents the binary value 100 (decimal 4), and 16#100 represents the hexadecimal value 100 (decimal 256). if the "b#" prefix is omitted, the default base is 10. x y..z selection of bits y through z of bit string x . little-endian bit notation (rightmost bit is 0) is used. if y is less than z , this expression is an empty (zero length) bit string. +, ? 2?s complement or floating-point arithmetic: addition, subtraction ?, 2?s complement or floating point multiplication (both used for either) div 2?s complement integer division mod 2?s complement modulo / floating-point division < 2?s complement less-than comparison > 2?s complement greater-than comparison 2?s complement less-than or equal comparison 2?s complement greater-than or equal comparison nor bitwise logical nor xor bitwise logical xor and bitwise logical and or bitwise logical or gprlen the length in bits (32 or 64) of the cpu general-purpose registers gpr[x] cpu general-purpose register x . the content of gpr[0] is always zero. cpr[z,x,s] coprocessor unit z , general register x, select s ccr[z,x] coprocessor unit z , control register x xlat[x] translation of the mips16 gpr number x into the corresponding 32-bit gpr num- ber bigendianmem endian mode as configured at chip reset (0 little-endian, 1 big-endian). specifies the endianness of the memory interface (see loadmemory and store- memory sections in this chapter), and the endianness of kernel and supervisor mode execution. bigendiancpu the endianness for load and store instructions (0 little-endian, 1 big- endian). in user mode, this endianness may be switched by setting the re bit in the status register. thus, bigendiancpu may be computed as (bigendianmem xor reverseendian). table a.1 symbols used in instruction operation statements (part 1 of 2)
idt operation section notation and functions 79rc32355 user reference manual a - 7 november 4, 2002 notes pseudocode functions there are several functions used in the pseudocode de scriptions. these are used either to make the pseudocode more readable, to abstract implementation-s pecific behavior, or both. these functions include the following: load memory and store memo ry functions, and miscellaneous functions. load memory and store memory functions regardless of byte ordering (big- or little-endian), the address of a halfword, word, or doubleword is the smallest byte address of the bytes that form the obj ect. for big-endian ordering this is the most-significant byte; for a little-endian ordering this is the least-significant byte. in the operation pseudocode for load and store operat ions, the following functions summarize the handling of virtual addresses and the access of physica l memory. the size of the data item to be loaded or stored is passed in the accesslength field. the valid constant names and values are shown in table 11-2. the bytes within the addressed unit of memory (word for 32-bit processors or doubleword for 64-bit proces- sors) that are used can be determined directly from t he accesslength and the two or three low-order bits of the address. reverseendian signal to reverse the endianness of load and store instructions. this feature is avail- able in user mode only, and is implemented by setting the re bit of the status regis- ter. thus, reverseendian may be computed as (sr re and user mode). llbit bit of virtual state used to specify operation for instructions that provide atomic read-modify-write. llbit is set when a linked load occurs; it is tested and cleared by the conditional store. it is cleared, during other cpu operation, when a store to the location would no longer be atomic. in particular, it is cleared by exception return instructions. i:, i+n:, i-n: this occurs as a prefix to operation description lines and functions as a label. it indi- cates the instruction time during which the pseudocode appears to ?execute.? unless otherwise indicated, all effects of the current instruction appear to occur dur- ing the instruction time of the current instruction. no label is equivalent to a time label of i . sometimes effects of an instruction appear to occur either earlier or later ? that is, during the instruction time of another instruction. when this happens, the instruction operation is written in sections labeled with the instruction time, relative to the current instruction i , in which the effect of that pseudocode appears to occur. for example, an instruction may have a result that is not available until after the next instruction. such an instruction has the portion of the instruction operation descrip- tion that writes the result register in a section labeled i + 1 . the effect of pseudocode statements for the current instruction labelled i + 1 appears to occur ?at the same time? as the effect of pseudocode statements labeled i for the following instruction. within one pseudocode sequence, the effects of the state- ments take place in order. however, between sequences of statements for different instructions that occur ?at the same time,? there is no defined order. programs must not depend on a particular order of evaluation between such sections. pc the program counter value. during the instruction time of an instruction, this is the address of the instruction word. the address of the instruction that occurs during the next instruction time is determined by assigning a value to pc during an instruction time. if no value is assigned to pc during an instruction time by any pseudocode statement, it is automatically incremented by either 2 (in the case of a 16-bit mips16 instruction) or 4 before the next instruction time. a taken branch assigns the target address to the pc during the instruction time of the instruction in the branch delay slot. pabits the number of physical add ress bits implemented is represented by the symbol pabits. as such, if 36 physi cal address bits were impl emented, the size of the physical address space would be 2 pabits = 2 36 bytes. symbol meaning table a.1 symbols used in instruction operation statements (part 2 of 2)
idt operation section notation and functions 79rc32355 user reference manual a - 8 november 4, 2002 notes addresstranslation the addresstranslation function translates a virtual address to a physical address and its cache coher- ence algorithm, describing the mechanism used to resolve the memory reference. given the virtual address vaddr, and whether the referenc e is to instructions or data (iord), find the corresponding physical address (paddr) and the cache coherence algorithm (cca) used to resolve the reference. if the virtual address is in one of the unmapped address spaces, the physical address and cca are determined directly by the virt ual address. if the virtual address is in one of the mapped address spaces then the tlb determines the physical address and access ty pe; if the required translation is not present in the tlb or the desired access is not permitted, the function fails and an exception is taken. (paddr, cca) addresstranslation (vaddr, iord, lors) /* paddr: physical address */ /* cca: cache coherence algorithm, t he method used to access caches*/ /* and memory and resolve the reference */ /* vaddr: virtual address */ /* iord: indicates whether access is for instruction or data */ /* lors: indicates whether access is for load or store */ /* see the address translation description for the appropriate mmu */ /* type in volume iii of this book for the exact translation mechanism */ endfunction addresstranslation loadmemory the loadmemory function loads a value from memory. this action uses cache and main memory as spec ified in both the cache coherence algorithm (cca) and the access (iord) to find the contents of acce sslength memory bytes, starting at physical location paddr. the data is returned in a fixed-width natura lly aligned memory element (memelem). the low-order two (or three) bits of the address and the accesslengt h indicate which of the bytes within memelem need to be passed to the processor. if the memory access type of the reference is uncached, only the referenced bytes are read from memory and marked as valid within the memory element. if the access type is cached but the data is not present in cache, an implementation- specific size and alignment block of memory is read and loaded into the cache to satisfy a load referenc e. at a minimum, this block is the entire memory element. memelem loadmemory (cca, accesslength, paddr, vaddr, iord) /* memelem: data is returned in a fixed width with a */ /* natural alignment. the width is the same size */ /* as the cpu general-purpose register, */ /* 32 or 64 bits, aligned on a 32- or 64-bit */ /* boundary, respectively. */ /* cca: cache coherence algorithm, the method used to */ /* access caches and memory and resolve the reference */ /* accesslength: length, in bytes, of access */ /* paddr: physical address */ /* vaddr: virtual address */ /* iord: indicates whether access is for instructions or data */ endfunction loadmemory
idt operation section notation and functions 79rc32355 user reference manual a - 9 november 4, 2002 notes storememory the storememory function st ores a value to memory. the specified data is stored into the physical locati on paddr using the memory hierarchy (data caches and main memory) as specified by the cache coher ence algorithm (cca). the memelem contains the data for an aligned, fixed-width memory element (a word for 32-bit processors, a doubleword for 64-bit processors), though only the bytes that are actually stored to memory need be valid. the low-order two (or three) bits of paddr and the access length field indicate which of the bytes within the memelem data should be stored; only these bytes in memory will actually be changed. storememory (cca, accesslengt h, memelem, paddr, vaddr) /* cca: cache coherence algorithm , the method used to access */ /* caches and memory and resolve the reference. */ /* accesslength: length, in bytes, of access */ /* memelem: data in the width and alignment of a memory element. */ /* the width is the same size as the cpu general */ /* purpose register, either 4 or 8 bytes, aligned on */ /* a 4- or 8-byte boundary. for a partial-memory-element */ /* store, only the bytes that will be*/ /* stored must be valid.*/ /* paddr: physical address */ /* vaddr: virtual address */ prefetch the prefetch function prefetches data from memory. prefetch is an advisory instruction for which an implem entation-specific action is taken. the action taken may increase performance but must not change the meaning of the program or alte r architecturally visible state. prefetch (cca, paddr, vaddr, data, hint) /* cca: cache coherence algorithm , the method used to access */ /* caches and memory and resolve the reference. */ /* paddr: physical address */ /* vaddr: virtual address */ /* data: indicates that access is for data */ /* hint: hint that indicates the possible use of the data */ endfunction prefetch table a.1 lists the data access lengt hs and their labels for loads and stores. miscellaneous functions this section lists miscellaneous functions not covered in previous sections. accesslength name value meaning word 3 4 bytes (32 bits) triplebyte 2 3 bytes (24 bits) halfword 1 2 bytes (16 bits) byte 0 1 byte (8 bits) table a.1 accesslength spec ifications for loads/stores
idt operation section notation and functions 79rc32355 user reference manual a - 10 november 4, 2002 notes syncoperation the syncoperation function orders loads and stores to synchronize shared memory. this action makes the effects of the synchronizabl e loads and stores indicated by type occur in the same order for all processors. syncoperation(stype) /* stype: type of load/store ordering to perform. */ /* perform implementation-dependent operation to complete the */ /* required synchronization operation */ endfunction syncoperation signalexception the signalexception function signals an exception condition. this action results in an exception that aborts the instruction. the instruction operation pseudocode never sees a return from this function call. signalexception(exception, argument) /* exception: the excepti on condition that exists. */ /* argument: an exception-dependent argument, if any */ endfunction signalexception nullifycurrentinstruction the nullifycurrentinstruction functi on nullifies the current instruction. the instruction is aborted. for branch-likely instructi ons, nullification kills the instruction in the delay slot during its execution. nullifycurrentinstruction() endfunction nullifycurrentinstruction coprocessoroperation the coprocessoroperation function perform s the specified coprocessor operation. coprocessoroperation (z, cop_fun) /* z: coprocessor unit number */ /* cop_fun: coprocessor function from function field of instruction */ /* transmit the cop_fun value to coprocessor z */ endfunction coprocessoroperation jumpdelayslot the jumpdelayslot function is used in the pseudocode fo r the four pc-relative instructions. the func- tion returns true if the instruction at vaddr is exec uted in a jump delay slot. a jump delay slot always immediately follows a jr, jal, jalr, or jalx instruction.
idt cpu opcode map 79rc32355 user reference manual a - 11 november 4, 2002 notes jumpdelayslot(vaddr) /* vaddr: virtual address */ endfunction jumpdelayslot op and function subfield notation in some instructions, the instruction subfields op and function can have constant 5- or 6-bit values. when reference is made to these instructions, upper case mnemonics are used. for instance, in the floating-point add instruction, op=co p1 and function=add. in other ca ses, a single field has both fixed and variable subfields, so the name contai ns both uppercase and lowercase characters. cpu opcode map ? capitalized text indicates an opcode mnemonic ? italicized text indicates to look at the spec ified opcode submap for further instruction bit decode ? entries containing the a symbol indicate that a rese rved instruction fault occurs if the core executes this instruction. ? entries containing the b symbol indicate that a c oprocessor unusable exception occurs if the core executes this instruction. opcode bits 28...26 0123 4 567 bits 31...29 000 001 010 011 100 101 110 111 0 000 special regimm j jal beq bne blez bgtz 1 001 addi addiu slti sltiu andi ori xori lui 2010cop0 || beql bnel blezl bgtzl 3011 special2 4 100 lb lh lwl lw lbu lhu lwr 5 101 sb sh swl sw swr cache 6110ll | pref || 7111sc || || table a.2 encoding of the opcode field function bits 2...0 0123 4 567 bits 5...3 000 001 010 011 100 101 110 111 0000sll srl sra sllv srlv srav 1 001 jr jalr movz movn syscall break sync 2 010 mfhi mthi mflo mtlo table a.3 special opcode encodi ng of function field (part 1 of 2)
idt cpu opcode map 79rc32355 user reference manual a - 12 november 4, 2002 notes 3 011 mult multu div divu 4 100 add addu sub subu and or xor nor 5101 slt sltu 6 110 tge tgeu tlt tltu teq tne 7111 function bits 2...0 0123 4 567 bits 5...3 000 001 010 011 100 101 110 111 0 000 madd maddu mul msub msubu 1001 2010 3011 4100clzclo 5101 6110 7111 sdbbp table a.4 special2 opcode encoding of function field rt bits 18...16 0 1 2 34567 bits 20...19 000 001 010 011 100 101 110 111 0 bltz bgez bltzl bgezl 1 tgei tgeiu tlti tltiu teqi tnei 2 bltzal bgezal bltzall bgezall 3 table a.5 regimm encoding of rt field function bits 2...0 0123 4 567 bits 5...3 000 001 010 011 100 101 110 111 table a.3 special opcode encodi ng of function field (part 2 of 2)
idt instruction set 79rc32355 user reference manual a - 13 november 4, 2002 notes instruction set this section describes the core instructions. tabl e a.8 lists the instructions in alphabetical order, followed by a detailed descr iption of each instruction. rs bits 23...21 0123 4 567 bits 25...24 000 001 010 011 100 101 110 111 000mfco mtco 101 210 co 311 table a.6 cop0 encoding of rs field function bits 2...0 0123 4 567 bits 5...3 000 001 010 011 100 101 110 111 0000 tlbr tlbwi tlbwr 1001tlbp 2010 3011eret deret 4100wait 5101 6110 7111 table a.7 cp0 encoding of function field when rs=co instruction description function add integer add rd = rs + rt addi integer add immediate rt = rs + immed addiu unsigned integer add immediate rt = rs +u immed addu unsigned integer add rd = rs +u rt and logical and rd = rs & rt andi logical and immediate rt = rs & (016 || immed) b unconditional branch (assembler idiom for: beq r0, r0, offset) pc += (int)offset table a.8 instruction set (part 1 of 6)
idt instruction set 79rc32355 user reference manual a - 14 november 4, 2002 notes bal branch and link (assembler idiom for: bgezal r0, offset) gpr[31] = pc + 8 pc += (int)offset beq branch on equal if rs == rt pc += (int)offset beql branch on equal likely if rs == rt pc += (int)offset else ignore next instruction bgez branch on greater than or equal to zero if !rs[31] pc += (int)offset bgezal branch on greater than or equal to zero and link gpr[31] = pc + 8 if !rs[31] pc += (int)offset bgezall branch on greater than or equal to zero and link likely gpr[31] = pc + 8 if !rs[31] pc += (int)offset else ignore next instruction bgezl branch on greater than or equal to zero likely if !rs[31] pc += (int)offset else ignore next instruction bgtz branch on greater than zero if !rs[31] && rs != 0 pc += (int)offset bgtzl branch on greater than zero likely if !rs[31] && rs != 0 pc += (int)offset else ignore next instruction blez branch on less than or equal to zero if rs[31] || rs == 0 pc += (int)offset blezl branch on less than or equal to zero likely if rs[31] || rs == 0 pc += (int)offset else ignore next instruction bltz branch on less than zero if rs[31] pc += (int)offset bltzal branch on less than zero and link gpr[31] = pc + 8 if rs[31] pc += (int)offset bltzall branch on less than zero and link likely gpr[31] = pc + 8 if rs[31] pc += (int)offset else ignore next instruction bltzl branch on less than zero likely if rs[31] pc += (int)offset else ignore next instruction instruction description function table a.8 instruction set (part 2 of 6)
idt instruction set 79rc32355 user reference manual a - 15 november 4, 2002 notes bne branch on not equal if rs != rt pc += (int)offset bnel branch on not equal likely if rs != rt pc += (int)offset else ignore next instruction break breakpoint break exception cache cache operation see cache description cop0 coprocessor 0 operation see coprocessor description clo count leading ones rd = numleadingones(rs) clz count leading zeroes rd = numleadingzeroes(rs) deret return from debug exception pc = depc exit debug mode div divide lo = (int)rs / (int)rt hi = (int)rs % (int)rt divu unsigned divide lo = (uns)rs / (uns)rt hi = (uns)rs % (uns)rt eret return from exception if sr[2] pc = errorepc else pc = epc sr[1] = 0 sr[2] = 0 ll = 0 j unconditional jump pc = pc[31:28] || offset<<2 jal jump and link gpr[31] = pc + 8 pc = pc[31:28] || offset<<2 jalr jump and link register rd = pc + 8 pc = rs jr jump register pc = rs lb load byte rt = (byte)mem[rs+offset] lbu unsigned load byte rt = (ubyte))mem[rs+offset] lh load halfword rt = (half)mem[rs+offset] lhu unsigned load halfword rt = (uhalf)mem[rs+offset] ll load linked word rt = mem[rs+offset] ll = 1 lladr = rs + offset lui load upper immediate rt = immediate << 16 lw load word rt = mem[rs+offset] lwl load word left see instruction later in this chapter ?????? lwr load word right see instruction later in this chapter ?????? instruction description function table a.8 instruction set (part 3 of 6)
idt instruction set 79rc32355 user reference manual a - 16 november 4, 2002 notes madd multiply - add hi, lo += (int)rs * (int)rt maddu multiply - add unsigned hi, lo += (uns)rs * (uns)rt mfc0 move from coprocessor 0 rt = cpr[0, n, sel] = rt mfhi move from hi rd = hi mflo move from lo rd = lo movn move conditional on not zero if gpr[rt] ? 0 then gpr[rd] gpr[rs] movz move conditional on zero if gpr[rt] = 0 then gpr[rd] gpr[rs] msub multiply-subtract hi, lo -= (int)rs * (int)rt msubu multiply-subtract unsigned hi, lo -= (uns)rs * (uns)rt mtc0 move to coprocessor 0 cpr[0, n] = rt sel mthi move to hi hi = rs mtlo move to lo lo = rs mul multiply with register write hi | lo =unpredictable rd = lo mult integer multiply hi | lo = (int)rs * (int)rd multu unsigned multiply hi | lo = (uns)rs * (uns)rd nop no operation (assembler idiom for: sll r0, r0, r0) nor logical nor rd = ~(rs | rt) or logical or rd = rs | rt ori logical or immediate rt = rs | immed pref prefetch load specified line into cache sb store byte (byte)mem[rs+offset] = rt sc store conditional word if ll =1 mem[rxoffs] = rt rt = ll sdbbp software debug break point trap to sw debug handler sh store half (half)mem[rs+offset] = rt sll shift left logical rd = rt << sa sllv shift left logical variable rd = rt << rs[4:0] slt set on less than if (int)rs < (int)rt rd = 1 else rd = 0 slti set on less than immediate if (int)rs < (int)immed rt = 1 else rt = 0 instruction description function table a.8 instruction set (part 4 of 6)
idt instruction set 79rc32355 user reference manual a - 17 november 4, 2002 notes sltiu set on less than immediate unsigned if (uns)rs < (uns)immed rt = 1 else rt = 0 sltu set on less than unsigned if (uns)rs < (uns)immed rd = 1 else rd = 0 sra shift right arithmetic rd = (int)rt >> sa srav shift right arithmetic variable rd = (int)rt >> rs[4:0] srl shift right logical rd = (uns)rt >> sa srlv shift right logical variable rd = (uns)rt >> rs[4:0] ssnop superscalar inhibit no operation sub integer subtract rt = (int)rs - (int)rd subu unsigned subtract rt = (uns)rs - (uns)rd sw store word mem[rs+offset] = rt swl store word left see store word left instruc- tion later in this chapter ??? swr store word right seestore word right instruc- tion later in this chapter ??? sync synchronize see sync instruction later in this chapter ????? syscall system call sy stemcallexception teq trap if equal if rs == rt trapexception teqi trap if equal immediate if rs == (int)immed trapexception tge trap if greater than or equal if (int)rs >= (int)rt trapexception tgei trap if greater than or equal immediate if (int)rs >= (int)immed trapexception tgeiu trap if greater than or equal i mmediate unsigned if (uns)rs >= (uns)immed trapexception tgeu trap if greater than or equal unsigned if (uns)rs >= (uns)rt trapexception tlbwi write indexed tlb entry see tlbwi instruction later in this chapter ??? tlbwr write random tlb entry see tlbwr instruction later in this chapter ??? tlbp probe tlb for matching entry see tlbp instruction later in this chapter ??? tlbr read index for tlb entry see tlbr instruction later in this chapter ??? instruction description function table a.8 instruction set (part 5 of 6)
idt instruction set 79rc32355 user reference manual a - 18 november 4, 2002 notes tlt trap if less than if (int)rs < (int)rt trapexception tlti trap if less than immediate if (int)rs < (int)immed trapexception tltiu trap if less than immediate unsigned if (uns)rs < (uns)immed trapexception tltu trap if less than unsigned if (uns)rs < (uns)rt trapexception tne trap if not equal if rs != rt trapexception tnei trap if not equal immediate if rs != (int)immed trapexception wait wait for interrupts stall until interrupt occurs xor exclusive or rd = rs ^ rt xori exclusive or immediate rt = rs ^ (uns)immed instruction description function table a.8 instruction set (part 6 of 6)
idt instruction set 79rc32355 user reference manual a - 19 november 4, 2002 notes add format: add rd, rs, rt mips32 purpose: to add 32-bit integers. if an overflow occurs, then trap. description: rd rs + rt the 32-bit word value in gpr rt is added to the 32-bit value in gpr rs to produce a 32-bit result. ? if the addition results in 32-bit 2?s complement ar ithmetic overflow, the destination register is not modified and an integer ov erflow exception occurs. ? if the addition does not overflow, the 32-bit result is placed into gpr rd . restrictions: none operation: temp (gpr[rs] 31 ||gpr[rs] 31..0 ) + (gpr[rt] 31 ||gpr[rt] 31..0 ) if temp 32 temp 31 then signalexception(integeroverflow) else gpr[rd] temp endif exceptions: integer overflow programming notes: addu performs the same arithmetic operation but does not trap on overflow. 31 26 25 21 20 16 15 11 10 6 5 0 special 000000 rs rt rd 0 00000 add 100000 6 5555 6 add word add
idt instruction set 79rc32355 user reference manual a - 20 november 4, 2002 notes addi format: addi rt, rs, immediate mips32 purpose: to add a constant to a 32-bit integer. if overflow occurs, then trap . description: rt rs + immediate the 16-bit signed immediate is added to the 32-bit value in gpr rs to produce a 32-bit result. ? if the addition results in 32-bit 2?s complement ar ithmetic overflow, the destination register is not modified and an integer ov erflow exception occurs. ? if the addition does not overflow, the 32-bit result is placed into gpr rt . restrictions: none operation: temp (gpr[rs] 31 ||gpr[rs] 31..0 ) + sign_extend(immediate) if temp 32 temp 31 then signalexception(integeroverflow) else gpr[rt] temp endif exceptions: integer overflow programming notes: addiu performs the same arithmetic operation but does not trap on overflow. 31 26 25 21 20 16 15 0 addi 001000 rs rt immediate 655 16 add immediate word addi
idt instruction set 79rc32355 user reference manual a - 21 november 4, 2002 notes addiu format: addiu rt, rs, immediate mips32 purpose: to add a constant to a 32-bit integer description: rt rs + immediate the 16-bit signed immediate is added to the 32-bit value in gpr rs and the 32-bit arithmetic result is placed into gpr rt. no integer overflow exception occurs under any circumstances. restrictions: none operation: temp gpr[rs] + sign_extend(immediate) gpr[rt] temp exceptions: none programming notes: the term ?unsigned? in the instruction name is a misnomer; this operati on is 32-bit modulo arith- metic that does not trap on overflow. this instru ction is appropriate for unsigned arithmetic, such as address arithmetic, or integer arithmetic env ironments that ignore overflow, such as c lan- guage arithmetic. 31 26 25 21 20 16 15 0 addiu 001001 rs rt immediate 655 16 add immediate unsigned word addiu
idt instruction set 79rc32355 user reference manual a - 22 november 4, 2002 notes addu format: addu rd, rs, rt mips32 purpose: to add 32-bit integers description: rd rs + rt the 32-bit word value in gpr rt is added to the 32-bit value in gpr rs and the 32-bit arithmetic result is placed into gpr rd . no integer overflow exception occurs under any circumstances. restrictions: none operation: temp gpr[rs] + gpr[rt] gpr[rd] temp exceptions: none programming notes: the term ?unsigned? in the instruction name is a misnomer; this operati on is 32-bit modulo arith- metic that does not trap on overflow. this instru ction is appropriate for unsigned arithmetic, such as address arithmetic, or integer arithmetic env ironments that ignore overflow, such as c lan- guage arithmetic. 31 26 25 21 20 16 15 11 10 6 5 0 special 000000 rs rt rd 0 00000 addu 100001 6 5555 6 add unsigned word addu
idt instruction set 79rc32355 user reference manual a - 23 november 4, 2002 notes and format: and rd, rs, rt mips32 purpose: to do a bitwise logical and description: rd rs and rt the contents of gpr rs are combined with the contents of gpr rt in a bitwise logical and opera- tion. the result is placed into gpr rd . restrictions: none operation: gpr[rd] gpr[rs] and gpr[rt] exceptions: none 31 26 25 21 20 16 15 11 10 6 5 0 special 000000 rs rt rd 0 00000 and 100100 6 5555 6 and and
idt instruction set 79rc32355 user reference manual a - 24 november 4, 2002 notes andi format: andi rt, rs, immediate mips32 purpose: to do a bitwise logical and with a constant description: rt rs and immediate the 16-bit immediate is zero-extended to the left and combined with the contents of gpr rs in a bitwise logical and operation. t he result is placed into gpr rt . restrictions: none operation: gpr[rt] gpr[rs] and zero_extend(immediate) exceptions: none 31 26 25 21 20 16 15 0 andi 001100 rs rt immediate 655 16 and immediate andi
idt instruction set 79rc32355 user reference manual a - 25 november 4, 2002 notes b format: b offset assembly idiom purpose: to do an unconditional branch description: branch b offset is the assembly idiom used to denote an unconditional branch. the actual instruction is interpreted by the hardware as beq r0, r0, offset. an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself ), in the branch delay slot, to form a pc-rela- tive effective target address. restrictions: processor operation is unpredictable if a branch, jump, eret, deret, or wait instruction is placed in the delay slot of a branch or jump. operation: i: target_offset sign_extend(offset || 0 2 ) i+1: pc pc + target_offset exceptions: none programming notes: with the 18-bit signed instruction offset, the c onditional branch range is 128 kbytes. use jump (j) or jump register (jr) instructions to branch to addresses outside this range. 31 26 25 21 20 16 15 0 beq 000100 0 00000 0 00000 offset 655 16 unconditional branch b
idt instruction set 79rc32355 user reference manual a - 26 november 4, 2002 notes bal format: bal rs, offset assembly idiom purpose: to do an unconditional pc-r elative procedure call description: procedure_call bal offset is the assembly idiom used to denot e an unconditional branch. the actual instruction is interpreted by the hardware as bgezal r0, offset. place the return address link in gpr 31. the return link is the address of the second instruction following the branch, where executi on continues after a procedure call. an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself ), in the branch delay slot, to form a pc-rela- tive effective target address. restrictions: processor operation is unpredictable if a branch, jump, eret, deret, or wait instruction is placed in the delay slot of a branch or jump. gpr 31 must not be used for the source register rs , because such an instruction does not have the same effect when re-executed. the result of executing such an instruction is unpredict- able . this restriction permits an exception handler to resume execution by reexecuting the branch when an exception occurs in the branch delay slot. operation: i: target_offset sign_extend(offset || 0 2 ) gpr[31] pc + 8 i+1: pc pc + target_offset exceptions: none programming notes: with the 18-bit signed instruction offset, the conditional branch range is 128 kbytes. use jump and link (jal) or jump and link register (jalr) instructions for procedure calls to addresses out- side this range. 31 26 25 21 20 16 15 0 regimm 000001 0 00000 bgezal 10001 offset 655 16 branch and link bal
idt instruction set 79rc32355 user reference manual a - 27 november 4, 2002 notes beq format: beq rs, rt, offset mips32 purpose: to compare gprs then do a pc-relative conditional branch description: if rs = rt then branch an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself ), in the branch delay slot, to form a pc-rela- tive effective target address. if the contents of gpr rs and gpr rt are equal, branch to the effect ive target address after the instruction in the delay slot is executed. restrictions: processor operation is unpredictable if a branch, jump, eret, deret, or wait instruction is placed in the delay slot of a branch or jump. operation: i: target_offset sign_extend(offset || 0 2 ) condition (gpr[rs] = gpr[rt]) i+1: if condition then pc pc + target_offset endif exceptions: none programming notes: with the 18-bit signed instruction offset, the c onditional branch range is 128 kbytes. use jump (j) or jump register (jr) instructions to branch to addresses outside this range. beq r0, r0 offset, expressed as b offset, is the assembly idiom used to denote an unconditional branch. 31 26 25 21 20 16 15 0 beq 000100 rs rt offset 655 16 branch on equal beq
idt instruction set 79rc32355 user reference manual a - 28 november 4, 2002 notes beql format: beql rs, rt, offset mips32 purpose: to compare gprs then do a pc-relative conditional branch; execute the delay slot only if the branch is taken. description: if rs = rt then branch_likely an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself ), in the branch delay slot, to form a pc-rela- tive effective target address. if the contents of gpr rs and gpr rt are equal, branch to the target address after the instruction in the delay slot is executed. if the branch is not ta ken, the instruction in the delay slot is not exe- cuted. restrictions: processor operation is unpredictable if a branch, jump, eret, deret, or wait instruction is placed in the delay slot of a branch or jump. operation: i: target_offset sign_extend(offset || 0 2 ) condition (gpr[rs] = gpr[rt]) i+1: if condition then pc pc + target_offset else nullifycurrentinstruction() endif exceptions: none 31 26 25 21 20 16 15 0 beql 010100 rs rt offset 655 16 branch on equal likely beql
idt instruction set 79rc32355 user reference manual a - 29 november 4, 2002 notes programming notes: with the 18-bit signed instruction offset, the conditional branch range is 128 kbytes. use jump (j) or jump register (jr) instructions to branch to addresses outside this range. software is strongly encouraged to avoi d the use of the branch likely instructions, as they will be removed from a future revision of the mips architecture. branch on equal likely (cont.) beql
idt instruction set 79rc32355 user reference manual a - 30 november 4, 2002 notes bgez format: bgez rs, offset mips32 purpose: to test a gpr then do a pc-relative conditional branch description: if rs 0 then branch an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself ), in the branch delay slot, to form a pc-rela- tive effective target address. if the contents of gpr rs are greater than or equal to zero (si gn bit is 0), branch to the effective target address after the instruction in the delay slot is executed. restrictions: processor operation is unpredictable if a branch, jump, eret, deret, or wait instruction is placed in the delay slot of a branch or jump. operation: i: target_offset sign_extend(offset || 0 2 ) condition gpr[rs] 0 gprlen i+1: if condition then pc pc + target_offset endif exceptions: none programming notes: with the 18-bit signed instruction offset, the conditional branch range is 128 kbytes. use jump (j) or jump register (jr) instructions to branch to addresses outside this range. 31 26 25 21 20 16 15 0 regimm 000001 rs bgez 00001 offset 655 16 branch on greater than or equal to zero bgez
idt instruction set 79rc32355 user reference manual a - 31 november 4, 2002 notes bgezal format: bgezal rs, offset mips32 purpose: to test a gpr then do a pc-rel ative conditional procedure call description: if rs 0 then procedure_call place the return address link in gpr 31. the return link is the address of the second instruction following the branch, where executi on continues after a procedure call. an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself ), in the branch delay slot, to form a pc-rela- tive effective target address. if the contents of gpr rs are greater than or equal to zero (si gn bit is 0), branch to the effective target address after the instruction in the delay slot is executed. restrictions: processor operation is unpredictable if a branch, jump, eret, deret, or wait instruction is placed in the delay slot of a branch or jump. gpr 31 must not be used for the source register rs , because such an instruction does not have the same effect when re-executed. the result of executing such an instruction is unpredict- able . this restriction permits an exception handler to resume ex ecution by re-executing the branch when an exception occurs in the branch delay slot. operation: i: target_offset sign_extend(offset || 0 2 ) condition gpr[rs] 0 gprlen gpr[31] pc + 8 i+1: if condition then pc pc + target_offset endif exceptions: none programming notes: with the 18-bit signed instruction offset, the conditional branch range is 128 kbytes. use jump and link (jal) or jump and link register (jalr) instructions for procedure calls to addresses out- side this range. bgezal r0, offset, expressed as bal offset, is the assembly idiom used to denote a pc-relative branch and link. bal is used in a manner similar to jal, but pr ovides pc-relative addressing and a more limited target pc range. 31 26 25 21 20 16 15 0 regimm 000001 rs bgezal 10001 offset 655 16 branch on greater than or equal to zero and link bgezal
idt instruction set 79rc32355 user reference manual a - 32 november 4, 2002 notes bgezall format: bgezall rs, offset mips32 purpose: to test a gpr then do a pc-relative conditional pr ocedure call; execute the delay slot only if the branch is taken. description: if rs 0 then procedure_call_likely place the return address link in gpr 31. the return link is the address of the second instruction following the branch, where executi on continues after a procedure call. an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself ), in the branch delay slot, to form a pc-rela- tive effective target address. if the contents of gpr rs are greater than or equal to zero (si gn bit is 0), branch to the effective target address after the instruction in the delay sl ot is executed. if the branch is not taken, the instruction in the delay slot is not executed. restrictions: gpr 31 must not be used for the source register rs , because such an instruction does not have the same effect when re-executed. the result of executing such an instruction is unpredict- able . this restriction permits an exception handler to resume ex ecution by re-executing the branch when an exception occurs in the branch delay slot. processor operation is unpredictable if a branch, jump, eret, deret, or wait instruction is placed in the delay slot of a branch or jump. operation: i: target_offset sign_extend(offset || 0 2 ) condition gpr[rs] 0 gprlen gpr[31] pc + 8 i+1: if condition then pc pc + target_offset else nullifycurrentinstruction() endif exceptions: none 31 26 25 21 20 16 15 0 regimm 000001 rs bgezall 10011 offset 655 16 branch on greater than or equal to zero and link likely bgezall
idt instruction set 79rc32355 user reference manual a - 33 november 4, 2002 notes programming notes: with the 18-bit signed instruction offset, the conditional branch range is 128 kbytes. use jump and link (jal) or jump and link register (jalr) instructions for procedure calls to addresses out- side this range. software is strongly encouraged to avoi d the use of the branch likely instructions, as they will be removed from a future revision of the mips architecture. branch on greater than or equal to zero and link likely (con?t.) bgezall
idt instruction set 79rc32355 user reference manual a - 34 november 4, 2002 notes bgezl format: bgezl rs, offset mips32 purpose: to test a gpr then do a pc-relative conditional br anch; execute the delay slot only if the branch is taken. description: if rs 0 then branch_likely an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself ), in the branch delay slot, to form a pc-rela- tive effective target address. if the contents of gpr rs are greater than or equal to zero (si gn bit is 0), branch to the effective target address after the instruction in the delay sl ot is executed. if the branch is not taken, the instruction in the delay slot is not executed. restrictions: processor operation is unpredictable if a branch, jump, eret, deret, or wait instruction is placed in the delay slot of a branch or jump. operation: i: target_offset sign_extend(offset || 0 2 ) condition gpr[rs] 0 gprlen i+1: if condition then pc pc + target_offset else nullifycurrentinstruction() endif exceptions: none 31 26 25 21 20 16 15 0 regimm 000001 rs bgezl 00011 offset 655 16 branch on greater than or equal to zero likely bgezl
idt instruction set 79rc32355 user reference manual a - 35 november 4, 2002 notes programming notes: with the 18-bit signed instruction offset, the conditional branch range is 128 kbytes. use jump (j) or jump register (jr) instructions to branch to addresses outside this range. software is strongly encouraged to avoi d the use of the branch likely instructions, as they will be removed from a future revision of the mips architecture. branch on greater than or equal to zero likely (cont.) bgezl
idt instruction set 79rc32355 user reference manual a - 36 november 4, 2002 notes bgtz format: bgtz rs, offset mips32 purpose: to test a gpr then do a pc-relative conditional branch description: if rs > 0 then branch an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself ), in the branch delay slot, to form a pc-rela- tive effective target address. if the contents of gpr rs are greater than zero (sign bit is 0 but value not zero), branch to the effective target address after the instruction in the delay slot is executed. restrictions: processor operation is unpredictable if a branch, jump, eret, deret, or wait instruction is placed in the delay slot of a branch or jump. operation: i: target_offset sign_extend(offset || 0 2 ) condition gpr[rs] > 0 gprlen i+1: if condition then pc pc + target_offset endif exceptions: none programming notes: with the 18-bit signed instruction offset, the conditional branch range is 128 kbytes. use jump (j) or jump register (jr) instructions to branch to addresses outside this range. 31 26 25 21 20 16 15 0 bgtz 000111 rs 0 00000 offset 655 16 branch on greater than zero bgtz
idt instruction set 79rc32355 user reference manual a - 37 november 4, 2002 notes bgtzl format: bgtzl rs, offset mips32 purpose: to test a gpr then do a pc-relative conditional br anch; execute the delay slot only if the branch is taken. description: if rs > 0 then branch_likely an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself ), in the branch delay slot, to form a pc-rela- tive effective target address. if the contents of gpr rs are greater than zero (sign bit is 0 but value not zero), branch to the effective target address after the instruction in the delay slot is executed. if the branch is not taken, the instruction in the delay slot is not executed. restrictions: processor operation is unpredictable if a branch, jump, eret, deret, or wait instruction is placed in the delay slot of a branch or jump. operation: i: target_offset sign_extend(offset || 0 2 ) condition gpr[rs] > 0 gprlen i+1: if condition then pc pc + target_offset else nullifycurrentinstruction() endif exceptions: none 31 26 25 21 20 16 15 0 bgtzl 010111 rs 0 00000 offset 655 16 branch on greater than zero likely bgtzl
idt instruction set 79rc32355 user reference manual a - 38 november 4, 2002 notes programming notes: with the 18-bit signed instruction offset, the conditional branch range is 128 kbytes. use jump (j) or jump register (jr) instructions to branch to addresses outside this range. software is strongly encouraged to avoi d the use of the branch likely instructions, as they will be removed from a future revision of the mips architecture. branch on greater than zero likely (cont.) bgtzl
idt instruction set 79rc32355 user reference manual a - 39 november 4, 2002 notes blez format: blez rs, offset mips32 purpose: to test a gpr then do a pc-relative conditional branch description: if rs 0 then branch an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself ), in the branch delay slot, to form a pc-rela- tive effective target address. if the contents of gpr rs are less than or equal to zero (sign bit is 1 or value is zero), branch to the effective target address after the instruction in the delay slot is executed. restrictions: processor operation is unpredictable if a branch, jump, eret, deret, or wait instruction is placed in the delay slot of a branch or jump. operation: i: target_offset sign_extend(offset || 0 2 ) condition gpr[rs] 0 gprlen i+1: if condition then pc pc + target_offset endif exceptions: none programming notes: with the 18-bit signed instruction offset, the conditional branch range is 128 kbytes. use jump (j) or jump register (jr) instructions to branch to addresses outside this range. 31 26 25 21 20 16 15 0 blez 000110 rs 0 00000 offset 655 16 branch on less than or equal to zero blez
idt instruction set 79rc32355 user reference manual a - 40 november 4, 2002 notes blezl format: blezl rs, offset mips32 purpose: to test a gpr then do a pc-relative conditional br anch; execute the delay slot only if the branch is taken. description: if rs 0 then branch_likely an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself ), in the branch delay slot, to form a pc-rela- tive effective target address. if the contents of gpr rs are less than or equal to zero (sign bit is 1 or value is zero), branch to the effective target address after the instruction in the delay slot is executed. if the branch is not taken, the instruction in the delay slot is not executed. restrictions: processor operation is unpredictable if a branch, jump, eret, deret, or wait instruction is placed in the delay slot of a branch or jump. operation: i: target_offset sign_extend(offset || 0 2 ) condition gpr[rs] 0 gprlen i+1: if condition then pc pc + target_offset else nullifycurrentinstruction() endif exceptions: none 31 26 25 21 20 16 15 0 blezl 010110 rs 0 00000 offset 655 16 branch on less than or equal to zero likely blezl
idt instruction set 79rc32355 user reference manual a - 41 november 4, 2002 notes programming notes: with the 18-bit signed instruction offset, the conditional branch range is 128 kbytes. use jump (j) or jump register (jr) instructions to branch to addresses outside this range. software is strongly encouraged to avoi d the use of the branch likely instructions, as they will be removed from a future revision of the mips architecture. branch on less than or equal to zero likely (cont.) blezl
idt instruction set 79rc32355 user reference manual a - 42 november 4, 2002 notes bltz format: bltz rs, offset mips32 purpose: to test a gpr then do a pc-relative conditional branch description: if rs < 0 then branch an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself ), in the branch delay slot, to form a pc-rela- tive effective target address. if the contents of gpr rs are less than zero (sign bit is 1), branch to the effective target address after the instruction in the delay slot is executed. restrictions: processor operation is unpredictable if a branch, jump, eret, deret, or wait instruction is placed in the delay slot of a branch or jump. operation: i: target_offset sign_extend(offset || 0 2 ) condition gpr[rs] < 0 gprlen i+1: if condition then pc pc + target_offset endif exceptions: none programming notes: with the 18-bit signed instruction offset, the conditional branch range is 128 kbytes. use jump and link (jal) or jump and link register (jalr) instructions for procedure calls to addresses out- side this range. 31 26 25 21 20 16 15 0 regimm 000001 rs bltz 00000 offset 655 16 branch on less than zero bltz
idt instruction set 79rc32355 user reference manual a - 43 november 4, 2002 notes bltzal format: bltzal rs, offset mips32 purpose: to test a gpr then do a pc-rel ative conditional procedure call description: if rs < 0 then procedure_call place the return address link in gpr 31. the return link is the address of the second instruction following the branch, where executi on continues after a procedure call. an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself ), in the branch delay slot, to form a pc-rela- tive effective target address. if the contents of gpr rs are less than zero (sign bit is 1), br anch to the effective target address after the instruction in the delay slot is executed. restrictions: gpr 31 must not be used for the source register rs , because such an instruction does not have the same effect when reexecuted. the result of executing such an instruction is unpredict- able. this restriction permits an exception handl er to resume execution by re-executing the branch when an exception occurs in the branch delay slot. processor operation is unpredictable if a branch, jump, eret, deret, or wait instruction is placed in the delay slot of a branch or jump. operation: i: target_offset sign_extend(offset || 0 2 ) condition gpr[rs] < 0 gprlen gpr[31] pc + 8 i+1: if condition then pc pc + target_offset endif exceptions: none programming notes: with the 18-bit signed instruction offset, the conditional branch range is 128 kbytes. use jump and link (jal) or jump and link register (jalr) instructions for procedure calls to addresses out- side this range. 31 26 25 21 20 16 15 0 regimm 000001 rs bltzal 10000 offset 655 16 branch on less than zero and link bltzal
idt instruction set 79rc32355 user reference manual a - 44 november 4, 2002 notes bltzall format: bltzall rs, offset mips32 purpose: to test a gpr then do a pc-relative conditional pr ocedure call; execute the delay slot only if the branch is taken. description: if rs < 0 then procedure_call_likely place the return address link in gpr 31. the return link is the address of the second instruction following the branch, where executi on continues after a procedure call. an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself ), in the branch delay slot, to form a pc-rela- tive effective target address. if the contents of gpr rs are less than zero (sign bit is 1), branch to the effective target address after the instruction in the delay slot is executed. if the branch is not taken, the instruction in the delay slot is not executed. restrictions: gpr 31 must not be used for the source register rs , because such an instruction does not have the same effect when re-executed. the result of executing such an instruction is unpredict- able. this restriction permits an exception handl er to resume execution by re-executing the branch when an exception occurs in the branch delay slot. processor operation is unpredictable if a branch, jump, eret, deret, or wait instruction is placed in the delay slot of a branch or jump. operation: i: target_offset sign_extend(offset || 0 2 ) condition gpr[rs] < 0 gprlen gpr[31] pc + 8 i+1: if condition then pc pc + target_offset else nullifycurrentinstruction() endif exceptions: none 31 26 25 21 20 16 15 0 regimm 000001 rs bltzall 10010 offset 655 16 branch on less than zero and link likely bltzall
idt instruction set 79rc32355 user reference manual a - 45 november 4, 2002 notes programming notes: with the 18-bit signed instruction offset, the conditional branch range is 128 kbytes. use jump and link (jal) or jump and link register (jalr) instructions for procedure calls to addresses out- side this range. software is strongly encouraged to avoi d the use of the branch likely instructions, as they will be removed from a future revision of the mips architecture. branch on less than zero and link likely (cont.) bltzall
idt instruction set 79rc32355 user reference manual a - 46 november 4, 2002 notes bltzl format: bltzl rs, offset mips32 purpose: to test a gpr then do a pc-relative conditional br anch; execute the delay slot only if the branch is taken. description: if rs < 0 then branch_likely an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself ), in the branch delay slot, to form a pc-rela- tive effective target address. if the contents of gpr rs are less than zero (sign bit is 1), branch to the effective target address after the instruction in the delay slot is executed. if the branch is not taken, the instruction in the delay slot is not executed. restrictions: processor operation is unpredictable if a branch, jump, eret, deret, or wait instruction is placed in the delay slot of a branch or jump. operation: i: target_offset sign_extend(offset || 0 2 ) condition gpr[rs] < 0 gprlen i+1: if condition then pc pc + target_offset else nullifycurrentinstruction() endif exceptions: none 31 26 25 21 20 16 15 0 regimm 000001 rs bltzl 00010 offset 655 16 branch on less than zero likely bltzl
idt instruction set 79rc32355 user reference manual a - 47 november 4, 2002 notes programming notes: with the 18-bit signed instruction offset, the conditional branch range is 128 kbytes. use jump (j) or jump register (jr) instructions to branch to addresses outside this range. software is strongly encouraged to avoi d the use of the branch likely instructions, as they will be removed from a future revision of the mips architecture. branch on less than zero likely (cont.) bltzl
idt instruction set 79rc32355 user reference manual a - 48 november 4, 2002 notes bne format: bne rs, rt, offset mips32 purpose: to compare gprs then do a pc-relative conditional branch description: if rs rt then branch an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself ), in the branch delay slot, to form a pc-rela- tive effective target address. if the contents of gpr rs and gpr rt are not equal, branch to the effective target address after the instruction in the delay slot is executed. restrictions: processor operation is unpredictable if a branch, jump, eret, deret, or wait instruction is placed in the delay slot of a branch or jump. operation: i: target_offset sign_extend(offset || 0 2 ) condition (gpr[rs] ? gpr[rt]) i+1: if condition then pc pc + target_offset endif exceptions: none programming notes: with the 18-bit signed instruction offset, the conditional branch range is 128 kbytes. use jump (j) or jump register (jr) instructions to branch to addresses outside this range. 31 26 25 21 20 16 15 0 bne 000101 rs rt offset 655 16 branch on not equal bne
idt instruction set 79rc32355 user reference manual a - 49 november 4, 2002 notes bnel format: bnel rs, rt, offset mips32 purpose: to compare gprs then do a pc-relative conditional branch; execute the delay slot only if the branch is taken. description: if rs ? rt then branch_likely an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself ), in the branch delay slot, to form a pc-rela- tive effective target address. if the contents of gpr rs and gpr rt are not equal, branch to the effective target address after the instruction in the delay slot is executed. if the branch is not taken, the instruction in the delay slot is not executed. restrictions: processor operation is unpredictable if a branch, jump, eret, deret, or wait instruction is placed in the delay slot of a branch or jump. operation: i: target_offset sign_extend(offset || 0 2 ) condition (gpr[rs] ? gpr[rt]) i+1: if condition then pc pc + target_offset else nullifycurrentinstruction() endif exceptions: none 31 26 25 21 20 16 15 0 bnel 010101 rs rt offset 655 16 branch on not equal likely bnel
idt instruction set 79rc32355 user reference manual a - 50 november 4, 2002 notes programming notes: with the 18-bit signed instruction offset, the conditional branch range is 128 kbytes. use jump (j) or jump register (jr) instructions to branch to addresses outside this range. software is strongly encouraged to avoi d the use of the branch likely instructions, as they will be removed from a future revision of the mips architecture. branch on not equal likely (cont.) bnel
idt instruction set 79rc32355 user reference manual a - 51 november 4, 2002 notes break format: break mips32 purpose: to cause a breakpoint exception description: a breakpoint exception occurs, immediately and un conditionally transferring control to the excep- tion handler. the code field is available for use as softwar e parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction. restrictions: none operation: signalexception(breakpoint) exceptions: breakpoint 31 26 25 6 5 0 special 000000 code break 001101 620 6 breakpoint break
idt instruction set 79rc32355 user reference manual a - 52 november 4, 2002 notes clo format: clo rd, rs mips32 purpose: to count the number of leading ones in a word description: rd count_leading_ones rs bits 31..0 of gpr rs are scanned from most significant to l east significant bit. the number of lead- ing ones is counted and the result is written to gpr rd . if all of bits 31..0 were set in gpr rs , the result written to gpr rd is 32. restrictions: to be compliant with the mips32 and mips64 architecture, software must place the same gpr number in both the rt and rd fields of the instruction. t he operation of the instruction is unpre- dictable if the rt and rd fields of the instruction contain different values. operation: temp 32 for i in 31 .. 0 if gpr[rs] i = 0 then temp 31 - i break endif endfor gpr[rd] temp exceptions: none 31 26 25 21 20 16 15 11 10 6 5 0 special2 011100 rs rt rd 0 00000 clo 100001 6 5555 6 count leading ones in word clo
idt instruction set 79rc32355 user reference manual a - 53 november 4, 2002 notes clz format: clz rd, rs mips32 purpose count the number of leading zeros in a word description: rd count_leading_zeros rs bits 31..0 of gpr rs are scanned from most significant to l east significant bit. the number of lead- ing zeros is counted and the result is written to gpr rd . if no bits were set in gpr rs , the result written to gpr rt is 32. restrictions: to be compliant with the mips32 and mips64 architecture, software must place the same gpr number in both the rt and rd fields of the instruction. the operation of the instruction is unpre- dictable if the rt and rd fields of the instruction contain different values. operation: temp 32 for i in 31 . . 0 if gpr[rs] i = 1 then temp 31 - i break endif endfor gpr[rd] temp exceptions: none 31 26 25 21 20 16 15 11 10 6 5 0 special2 011100 rs rt rd 0 00000 clz 100000 6 5555 6 count leading zeros in word clz
idt instruction set 79rc32355 user reference manual a - 54 november 4, 2002 notes deret format: deret ejtag purpose: to return from a debug exception. description: deret returns from debug mode and resumes non-debug execution at the instruction whose address is contained in the depc register. deret does not execute the next instruction (i.e. it has no delay slot). restrictions: a deret placed between an ll and sc instru ction does not cause the sc to fail. if the depc register with the return address for the deret was modified by an mtc0 or a dmtc0 instruction, a cp0 hazard exists that must be removed via software insertion of the appropriate number of ssnop instructions. the deret instruction implements a software barrier for all changes in the cp0 state that could affect the fetch and decode of the instruction at the pc to which the deret returns, such as changes to the effective asid, user-mode state, and addressing mode. this instruction is legal only if the processor is executing in debug mode.the operation of the pro- cessor is undefined if a deret is executed in the delay slot of a branch or jump instruction. 31 26 25 24 6 5 0 cop0 010000 c o 1 0 000 0000 0000 0000 0000 deret 011111 61 19 6 debug exception return deret
idt instruction set 79rc32355 user reference manual a - 55 november 4, 2002 notes operation: debug dm 0 debug iexi 0 if ismips16implemented() then pc depc 31 ..1 || 0 isamode 0 || depc 0 else pc depc endif exceptions: coprocessor unusable exception reserved instruction exception debug exception return (cont.) deret
idt instruction set 79rc32355 user reference manual a - 56 november 4, 2002 notes div format: div rs, rt mips32 purpose: to divide a 32-bit signed integers description: (lo, hi) rs / rt the 32-bit word value in gpr rs is divided by the 32-bit value in gpr rt, treating both operands as signed values. the 32-bit quotient is placed into special register lo and the 32-bit remainder is placed into special register hi . no arithmetic exception occurs under any circumstances. restrictions: if the divisor in gpr_ rt is zero, the arithmetic result value is unpredictable . operation: q gpr[rs] 31..0 div gpr[rt] 31..0 lo q r gpr[rs] 31..0 mod gpr[rt] 31..0 hi r exceptions: none 31 26 25 21 20 16 15 6 5 0 special 000000 rs rt 0 00 0000 0000 div 011010 655 10 6 divide word div
idt instruction set 79rc32355 user reference manual a - 57 november 4, 2002 notes programming notes: no arithmetic exception occurs under any circumstances. if divide- by-zero or overflow conditions are detected and some action taken, then the divi de instruction is typically followed by additional instructions to check for a zero divisor and/or fo r overflow. if the divide is asynchronous then the zero-divisor check can execute in parallel with th e divide. the action tak en on either divide-by- zero or overflow is either a convention within t he program itself, or more typically within the sys- tem software; one possibility is to take a break exception with a code field value to signal the problem to the system software. as an example, the c pr ogramming language in a unix ? environment expects division by zero to either terminate the program or execute a program-specified signal handler. c does not expect overflow to cause any exceptional condition. if the c compiler uses a divide instruction, it also emits code to test for a zero divisor and execut e a break instruction to inform the operating sys- tem if a zero is detected. where the size of the operands are known, softw are should place the shorter operand in gpr rt . this may reduce the latency of the instructi on on those processors which implement data-depen- dent instruction latencies. divide word (cont.) div
idt instruction set 79rc32355 user reference manual a - 58 november 4, 2002 notes divu format: divu rs, rt mips32 purpose: to divide a 32-bit unsigned integers description: (lo, hi) rs / rt the 32-bit word value in gpr_ rs is divided by the 32-bit value in gpr rt, treating both operands as unsigned values. the 32-bit quotient is placed into special register lo and the 32-bit remain- der is placed into special register hi . no arithmetic exception occurs under any circumstances. restrictions: if the divisor in gpr rt is zero, the arithmetic result value is undefined. operation: q (0 || gpr[rs] 31..0 ) div (0 || gpr[rt] 31..0 ) r (0 || gpr[rs] 31..0 ) mod (0 || gpr[rt] 31..0 ) lo sign_extend(q 31..0 ) hi sign_extend(r 31..0 ) exceptions: none programming notes: see ?programming notes? for the div instruction. 31 26 25 21 20 16 15 6 5 0 special 000000 rs rt 0 00 0000 0000 divu 011011 655 10 6 divide unsigned word divu
idt instruction set 79rc32355 user reference manual a - 59 november 4, 2002 notes eret format: eret mips32 purpose: to return from interrupt, exception, or error trap. description: eret returns to the interrupted instruction at t he completion of interrupt, exception, or error trap processing. eret does not execute the next instruction (i.e., it has no delay slot). restrictions: the operation of the processor is undefined if an eret is executed in the delay slot of a branch or jump instruction. an eret placed between an ll and sc instru ction will always cause the sc to fail. eret implements a software barrier for all changes in the cp0 state that could affect the fetch and decode of the instruction at the pc to which the eret returns, such as changes to the effec- tive asid, user-mode state, and addressing mode. operation: if status erl = 1 then temp errorepc status erl 0 else temp epc status exl 0 endif if ismips16implemented() then pc temp 31 ..1 || 0 isamode temp 0 else pc temp endif llbit 0 exceptions: coprocessor unusable exception 31 26 25 24 6 5 0 cop0 010000 c o 1 0 000 0000 0000 0000 0000 eret 011000 61 19 6 exception return eret
idt instruction set 79rc32355 user reference manual a - 60 november 4, 2002 notes j format: j target mips32 purpose: to branch within the current 256 mb-aligned region description: this is a pc-region branch (not pc -relative); the effective target address is in the ?current? 256 mb-aligned region. the low 28 bits of the target address is the instr_index field shifted left 2 bits. the remaining upper bits are the corresponding bits of the address of the instruction in the delay slot (not the branch itself). jump to the effective target address. execute the instruction that follows the jump, in the branch delay slot, before executing the jump itself. restrictions: processor operation is unpredictable if a branch, jump, eret, deret, or wait instruction is placed in the delay slot of a branch or jump. operation: i: i+1: pc pc gprlen..28 || instr_index || 0 2 exceptions: none programming notes: forming the branch target address by catenati ng pc and index bits rather than adding a signed offset to the pc is an advantage if all program code addresses fit into a 256 mb region aligned on a 256 mb boundary. it allows a branch from anywher e in the region to anywhere in the region, an action not allowed by a signed relative offset. this definition creates the following boundary case: when the jump instruction is in the last word of a 256 mb region, it can branch only to the fo llowing 256 mb region c ontaining the branch delay slot. 31 26 25 0 j 000010 instr_index 626 jump j
idt instruction set 79rc32355 user reference manual a - 61 november 4, 2002 notes jal format: jal target mips32 purpose: to execute a procedure call with in the current 256 mb-aligned region description: place the return address link in gpr 31. the return link is the address of the second instruction following the branch, at which location exec ution continues after a procedure call. this is a pc-region branch (not pc -relative); the effective target address is in the ?current? 256 mb-aligned region. the low 28 bits of the target address is the instr_index field shifted left 2 bits. the remaining upper bits are the corresponding bits of the address of the instruction in the delay slot (not the branch itself). jump to the effective target address. execute the instruction that follows the jump, in the branch delay slot, before executing the jump itself. restrictions: processor operation is unpredictable if a branch, jump, eret, deret, or wait instruction is placed in the delay slot of a branch or jump. operation: i: gpr[31] pc + 8 i+1: pc pc gprlen..28 || instr_index || 0 2 exceptions: none programming notes: forming the branch target address by catenati ng pc and index bits rather than adding a signed offset to the pc is an advantage if all program code addresses fit into a 256 mb region aligned on a 256 mb boundary. it allows a branch from anywher e in the region to anywhere in the region, an action not allowed by a signed relative offset. this definition creates the following boundary case : when the branch instruction is in the last word of a 256 mb region, it can branch only to the following 256 mb r egion containing the branch delay slot. 31 26 25 0 jal 000011 instr_index 626 jump and link jal
idt instruction set 79rc32355 user reference manual a - 62 november 4, 2002 notes jalr format: jalr rs (rd = 31 implied) mips32 jalr rd, rs mips32 purpose: to execute a procedure call to an instruction address in a register description: rd return_addr, pc rs place the return address link in gpr rd . the return link is the address of the second instruction following the branch, where executi on continues after a procedure call. for processors that do not implement the mips16 ase: ? jump to the effective target address in gpr rs . execute the instruction that follows the jump, in the branch delay slot, before executing the jump itself. for processors that do implement the mips16 ase: ? jump to the effective target address in gpr rs . set the isa mode bit to the value in gpr rs bit 0. bit 0 of the target address is always ze ro so that no address exceptions occur when bit 0 of the source register is one at this time the only defined hint field value is 0, which sets default handling of jalr. future ver- sions of the architecture ma y define additional hint values. restrictions: register specifiers rs and rd must not be equal, because such an instruction does not have the same effect when re-executed. the result of executing such an instruction is undefined. this restriction permits an exception handler to resu me execution by re-executing the branch when an exception occurs in the branch delay slot. the effective target address in gpr rs must be naturally-aligned. for processors that do not implement the mips16 ase, if either of the two least-significant bits are not zero, an address error exception occurs when the branch target is subsequently fetched as an instruction. for pro- cessors that do implement the mips16 ase, if bi t 0 is zero and bit 1 is one, an address error exception occurs when the jump target is subsequently fetched as an instruction. processor operation is unpredictable if a branch, jump, eret, deret, or wait instruction is placed in the delay slot of a branch or jump. 31 26 25 21 20 16 15 11 10 6 5 0 special 000000 rs 0 00000 rd hint jalr 001001 6 5555 6 jump and link register jalr
idt instruction set 79rc32355 user reference manual a - 63 november 4, 2002 notes operation: i: temp gpr[rs] gpr[rd] pc + 8 i+1: if config1 ca = 0 then pc temp else pc temp gprlen-1..1 || 0 isamode temp 0 endif exceptions: none programming notes: this is the only branch-and-link instruction that c an select a register for the return link; all other link instructions use gpr 31. the default register for gpr rd , if omitted in the assembly language instruction, is gpr 31. jump and link register, cont. jalr
idt instruction set 79rc32355 user reference manual a - 64 november 4, 2002 notes jr format: jr rs mips32 purpose: to execute a branch to an instruction address in a register description: pc rs jump to the effective target address in gpr rs . execute the instruction following the jump, in the branch delay slot, before jumping. for processors that implement the mips16 ase, set the isa mode bit to the value in gpr rs bit 0. bit 0 of the target address is always zero so that no address exceptions occur when bit 0 of the source register is one restrictions: the effective target address in gpr rs must be naturally-aligned. for processors that do not implement the mips16 ase, if either of the two least-significant bits are not zero, an address error exception occurs when the branch target is subsequently fetched as an instruction. for pro- cessors that do implement the mips16 ase, if bi t 0 is zero and bit 1 is one, an address error exception occurs when the jump target is subsequently fetched as an instruction. at this time the only defined hint field value is 0, which sets default handling of jr. future ver- sions of the architecture ma y define additional hint values. processor operation is unpredictable if a branch, jump, eret, deret, or wait instruction is placed in the delay slot of a branch or jump. operation: i: temp gpr[rs] i+1: if config1 ca = 0 then pc temp else pc temp gprlen-1..1 || 0 isamode temp 0 endif exceptions: none 31 26 25 21 20 11 10 6 5 0 special 000000 rs 0 00 0000 0000 hint jr 001000 65 10 56 jump register jr
idt instruction set 79rc32355 user reference manual a - 65 november 4, 2002 notes programming notes: software should use the value 31 for the rs field of the instruction word on return from a jal, jalr, or bgezal, and should use a value ot her than 31 for remaining uses of jr. jump register, cont. jr
idt instruction set 79rc32355 user reference manual a - 66 november 4, 2002 notes lb format: lb rt, offset(base) mips32 purpose: to load a byte from memory as a signed value description: rt memory[base+offset] the contents of the 8-bit byte at the memory location specified by the effective address are fetched, sign-extended, and placed in gpr rt . the 16-bit signed offset is added to the contents of gpr base to form the effective address. restrictions: none operation: vaddr sign_extend(offset) + gpr[base] (paddr, cca) addresstranslation (vaddr, data, load) paddr paddr psize-1..2 || (paddr 1..0 xor reverseendian 2 ) memword loadmemory (cca, byte, paddr, vaddr, data) byte vaddr 1..0 xor bigendiancpu 2 gpr[rt] sign_extend(memword 7+8*byte..8*byte ) exceptions: tlb refill, tlb invalid, address error 31 26 25 21 20 16 15 0 lb 100000 base rt offset 655 16 load byte lb
idt instruction set 79rc32355 user reference manual a - 67 november 4, 2002 notes lbu format: lbu rt, offset(base) mips32 purpose: to load a byte from memory as an unsigned value description: rt memory[base+offset] the contents of the 8-bit byte at the memory location specified by the effective address are fetched, zero-extended, and placed in gpr rt . the 16-bit signed offset is added to the contents of gpr base to form the effective address. restrictions: none operation: vaddr sign_extend(offset) + gpr[base] (paddr, cca) addresstranslation (vaddr, data, load) paddr paddr psize-1..2 || (paddr 1..0 xor reverseendian 2 ) memword loadmemory (cca, byte, paddr, vaddr, data) byte vaddr 1..0 xor bigendiancpu 2 gpr[rt] zero_extend(memword 7+8*byte..8*byte ) exceptions: tlb refill, tlb invalid, address error 31 26 25 21 20 16 15 0 lbu 100100 base rt offset 655 16 load byte unsigned lbu
idt instruction set 79rc32355 user reference manual a - 68 november 4, 2002 notes lh format: lh rt, offset(base) mips32 purpose: to load a halfword from memory as a signed value description: rt memory[base+offset] the contents of the 16-bit halfword at the memo ry location specified by the aligned effective address are fetched, sign-extended, and placed in gpr rt . the 16-bit signed offset is added to the contents of gpr base to form the effective address. restrictions: the effective address must be naturally-aligned. if the least-significant bi t of the address is non- zero, an address error exception occurs. operation: vaddr sign_extend(offset) + gpr[base] if vaddr 0 0 then signalexception(addresserror) endif (paddr, cca) addresstranslation (vaddr, data, load) paddr paddr psize?1..2 || (paddr 1..0 xor (reverseendian || 0)) memword loadmemory (cca, halfword, paddr, vaddr, data) byte vaddr 1..0 xor (bigendiancpu || 0) gpr[rt] sign_extend(memword 15+8*byte..8*byte ) exceptions: tlb refill, tlb invalid, bus error, address error 31 26 25 21 20 16 15 0 lh 100001 base rt offset 655 16 load halfword lh
idt instruction set 79rc32355 user reference manual a - 69 november 4, 2002 notes lhu format: lhu rt, offset(base) mips32 purpose: to load a halfword from memory as an unsigned value description: rt memory[base+offset] the contents of the 16-bit halfword at the memo ry location specified by the aligned effective address are fetched, zero-extended, and placed in gpr rt . the 16-bit signed offset is added to the contents of gpr base to form the effective address. restrictions: the effective address must be naturally-aligned. if the least-significant bi t of the address is non- zero, an address error exception occurs. operation: vaddr sign_extend(offset) + gpr[base] if vaddr 0 0 then signalexception(addresserror) endif (paddr, cca) addresstranslation (vaddr, data, load) paddr paddr psize?1..2 || (paddr 1..0 xor (reverseendian || 0)) memword loadmemory (cca, halfword, paddr, vaddr, data) byte vaddr 1..0 xor (bigendiancpu || 0) gpr[rt] zero_extend(memword 15+8*byte..8*byte ) exceptions: tlb refill, tlb invalid, address error 31 26 25 21 20 16 15 0 lhu 100101 base rt offset 655 16 load halfword unsigned lhu
idt instruction set 79rc32355 user reference manual a - 70 november 4, 2002 notes ll format: ll rt, offset(base) mips32 purpose: to load a word from memory for an atomic read-modify-write description: rt memory[base+offset] the ll and sc instructions provide the primitives to implement atomic read-modify-write (rmw) operations for cached memory locations. the 16-bit signed offset is added to the contents of gpr base to form an effective address. the contents of the 32-bit word at the memory locati on specified by the aligned effective address are fetched, sign-extended to the gpr register length if necessary, and written into gpr rt . this begins a rmw sequence on the current pr ocessor. there can be only one active rmw sequence per processor. when an ll is executed it starts an active rmw sequence replacing any other sequence that was active. the rmw sequence is completed by a subsequent sc instruction that either completes the rmw sequence atomically and succeeds, or does not and fails. executing ll on one processor does not cause an ac tion that, by itself, causes an sc for the same block to fail on another processor. an execution of ll does not have to be followed by execution of sc; a program is free to aban- don the rmw sequence without attempting a write. restrictions: the addressed location must be cached; if it is not, the result is undefined. the effective address must be naturally-aligned. if eit her of the 2 least-significant bits of the effec- tive address is non-zero, an a ddress error exception occurs. operation: vaddr sign_extend(offset) + gpr[base] if vaddr 1..0 0 2 then signalexception(addresserror) endif (paddr, cca) addresstranslation (vaddr, data, load) memword loadmemory (cca, word, paddr, vaddr, data) gpr[rt] memword llbit 1 31 26 25 21 20 16 15 0 ll 110000 base rt offset 655 16 load linked word ll
idt instruction set 79rc32355 user reference manual a - 71 november 4, 2002 notes exceptions: tlb refill, tlb invalid, address error, reserved instruction programming notes: there is no load linked word unsigned oper ation corresponding to load word unsigned. load linked word (cont.) ll
idt instruction set 79rc32355 user reference manual a - 72 november 4, 2002 notes lui format: lui rt, immediate mips32 purpose: to load a constant into the upper half of a word description: rt immediate || 0 16 the 16-bit immediate is shifted left 16 bits and concatenated with 16 bits of low-order zeros. the 32-bit result is placed into gpr rt . restrictions: none operation: gpr[rt] immediate || 0 16 exceptions: none 31 26 25 21 20 16 15 0 lui 001111 0 00000 rt immediate 655 16 load upper immediate lui
idt instruction set 79rc32355 user reference manual a - 73 november 4, 2002 notes lw format: lw rt, offset(base) mips32 purpose: to load a word from memory as a signed value description: rt memory[base+offset] the contents of the 32-bit word at the memory lo cation specified by the aligned effective address are fetched, sign-extended to the gpr regist er length if necessary, and placed in gpr rt . the 16-bit signed offset is added to the contents of gpr base to form the effective address. restrictions: the effective address must be naturally-aligned. if either of the 2 least-significant bits of the address is non-zero, an address error exception occurs. operation: vaddr sign_extend(offset) + gpr[base] if vaddr 1..0 0 2 then signalexception(addresserror) endif (paddr, cca) addresstranslation (vaddr, data, load) memword loadmemory (cca, word, paddr, vaddr, data) gpr[rt] memword exceptions: tlb refill, tlb invalid, bus error, address error 31 26 25 21 20 16 15 0 lw 100011 base rt offset 655 16 load word lw
idt instruction set 79rc32355 user reference manual a - 74 november 4, 2002 notes lwl format: lwl rt, offset(base) mips32 purpose: to load the most-significant part of a word as a signed value from an unaligned memory address description: rt rt merge memory[base+offset] the 16-bit signed offset is added to the contents of gpr base to form an effective address (effaddr ). effaddr is the address of the most-significant of 4 consecutive bytes forming a word (w ) in memory starting at an arbitrary byte boundary. the most-significant 1 to 4 bytes of w is in the aligned word containing the effaddr . this part of w is loaded into the most-significant (left) part of the word in gpr rt . the remaining least-significant part of the word in gpr rt is unchanged. the figure below illustrates this operation usi ng big-endian byte ordering for 32-bit and 64-bit reg- isters. the 4 consecutive bytes in 2..5 form an unaligned word starting at location 2. a part of w , 2 bytes, is in the aligned word containing the most -significant byte at 2. first, lwl loads these 2 bytes into the left part of the destination register word and leaves the right part of the destination word unchanged. next, the complementary lwr loads the remainder of the unaligned word. figure a.10 unaligned word load using lwl and lwr 31 26 25 21 20 16 15 0 lwl 100010 base rt offset 655 16 load word left lwl word at byte 2 in big-endian memory; each memory byte contains its own address most - significance - least 01 2345 6 7 8 9 memory initial contents e f g h gpr 24 initial contents 23 g h after executing lwl $24,2($0) 23 45 then after lwr $24,5($0)
idt instruction set 79rc32355 user reference manual a - 75 november 4, 2002 notes the bytes loaded from memory to the destinati on register depend on both the offset of the effec- tive address within an aligned word, that is, the low 2 bits of the address (vaddr 1..0 ), and the cur- rent byte-ordering mode of the processor (big- or little-endian). the figure below shows the bytes loaded for every combination of offset and byte ordering. figure a.11 bytes load ed by lwl instruction memory contents and byte offsets initial contents of dest register 0123 big-endian i j k l offset (vaddr 1..0 ) e f g h 3210 little-endian most least most least ? significance ? ? significance ? destination register contents after instruction (shaded is unchanged) big-endian vaddr 1..0 little-endian i jkl0l f g h jkl h1kl g h kl g h2jkl h l f g h3 i jkl load word left (con?t) lwl
idt instruction set 79rc32355 user reference manual a - 76 november 4, 2002 notes restrictions: none operation: vaddr sign_extend(offset) + gpr[base] (paddr, cca) addresstranslation (vaddr, data, load) paddr paddr psize-1..2 || (paddr 1..0 xor reverseendian 2 ) if bigendianmem = 0 then paddr paddr psize-1..2 || 0 2 endif byte vaddr 1..0 xor bigendiancpu 2 memword loadmemory (cca, byte, paddr, vaddr, data) temp memword 7+8*byte..0 || gpr[rt] 23-8*byte..0 gpr[rt] temp exceptions: none tlb refill, tlb invalid, bus error, address error programming notes: the architecture provides no direct support fo r treating unaligned words as unsigned values, that is, zeroing bits 63..32 of the desti nation register when bit 31 is loaded. load word left (con?t) lwl
idt instruction set 79rc32355 user reference manual a - 77 november 4, 2002 notes lwr format: lwr rt, offset(base) mips32 purpose: to load the least-significant part of a word from an unaligned memory address as a signed value description: rt rt merge memory[base+offset] the 16-bit signed offset is added to the contents of gpr base to form an effective address (effaddr ). effaddr is the address of the leas t-significant of 4 consecutive bytes forming a word (w ) in memory starting at an arbitrary byte boundary. a part of w , the least-significant 1 to 4 bytes, is in the aligned word containing effaddr . this part of w is loaded into the least-significant (right) part of the word in gpr rt . the remaining most-sig- nificant part of the word in gpr rt is unchanged. executing both lwr and lwl, in either order, de livers a sign-extended word value in the destina- tion register. the figure below illustrates this operation usi ng big-endian byte ordering for 32-bit and 64-bit reg- isters. the 4 consecutive bytes in 2..5 form an unaligned word starting at location 2. a part of w , 2 bytes, is in the aligned word containing the leas t-significant byte at 5. first, lwr loads these 2 bytes into the right part of the destination re gister. next, the complementary lwl loads the remainder of the unaligned word. 31 26 25 21 20 16 15 0 lwr 100110 base rt offset 655 16 load word right lwr
idt instruction set 79rc32355 user reference manual a - 78 november 4, 2002 notes figure a.12 unaligned word load using lwl and lwr the bytes loaded from memory to the destinati on register depend on both the offset of the effec- tive address within an aligned word, that is, the low 2 bits of the address (vaddr 1..0 ), and the cur- rent byte-ordering mode of the processor (big- or little-endian). the figure below shows the bytes loaded for every combination of offset and byte ordering. load word right (cont.) lwr word at byte 2 in big-endian memory; each memory byte contains its own address most - significance - least 01 2345 6 7 8 9 memory initial contents e f g h gpr 24 initial contents e f 45 after executing lwr $24,5($0) 23 4 5 then after lwl $24,2($0)
idt instruction set 79rc32355 user reference manual a - 79 november 4, 2002 notes figure a.13 bytes loaded by lwl instruction memory contents and byte offsets initial contents of dest register 0123 big-endian i j k l offset (vaddr 1..0 ) e f g h 3210 little-endian most least most least ? significance? ? significance ? destination register contents after instruction (shaded is unchanged) big-endian vadd r 1..0 little-endian little-endian e f gi0ijkl e fij1 eijk eijk2 e fij ijkl3 e f gi load word right (cont.) lwr
idt instruction set 79rc32355 user reference manual a - 80 november 4, 2002 notes restrictions: none operation: vaddr sign_extend(offset) + gpr[base] (paddr, cca) addresstranslation (vaddr, data, load) paddr paddr psize-1..2 || (paddr 1..0 xor reverseendian 2 ) if bigendianmem = 0 then paddr paddr psize-1..2 || 0 2 endif byte vaddr 1..0 xor bigendiancpu 2 memword loadmemory (cca, byte, paddr, vaddr, data) temp memword 31..32-8*byte || gpr[rt] 31?8*byte..0 gpr[rt] temp exceptions: tlb refill, tlb invalid, bus error, address error programming notes: the architecture provides no direct support fo r treating unaligned words as unsigned values, that is, zeroing bits 63..32 of the desti nation register when bit 31 is loaded. load word right (cont.) lwr
idt instruction set 79rc32355 user reference manual a - 81 november 4, 2002 notes madd format: madd rs, rt mips32 purpose: to multiply two words and add the result to hi, lo description: (lo,hi) (rs rt) + (lo,hi) the 32-bit word value in gpr rs is multiplied by the 32-bit word value in gpr rt , treating both operands as signed values, to produce a 64-bit re sult. the product is added to the 64-bit concat- enated values of hi and lo . the most significant 32 bits of the result are written into hi and the least significant 32 bits are written into lo . no arithmetic excepti on occurs under any circum- stances. restrictions: none operation: temp (hi || lo) + (gpr[rs] gpr[rt]) hi temp 63..32 lo temp 31..0 exceptions: none programming notes: where the size of the operands are known, softw are should place the shorter operand in gpr rt . this may reduce the latency of the instructi on on those processors which implement data-depen- dent instruction latencies. 31 26 25 21 20 16 15 11 10 6 5 0 special2 011100 rs rt 0 0000 0 00000 madd 000000 6 5555 6 multiply and add word to hi,lo madd
idt instruction set 79rc32355 user reference manual a - 82 november 4, 2002 notes maddu format: maddu rs, rt mips32 purpose: to multiply two unsigned words and add the result to hi, lo. description: (lo,hi) (rs rt) + (lo,hi) the 32-bit word value in gpr rs is multiplied by the 32-bit word value in gpr rt , treating both operands as unsigned values, to produce a 64-bit result. the product is added to the 64-bit con- catenated values of hi and lo . the most significant 32 bits of the result are written into hi and the least significant 32 bits are written into lo . no arithmetic excepti on occurs under any circum- stances. restrictions: none operation: temp (hi || lo) + (gpr[rs] gpr[rt]) hi temp 63..32 lo temp 31..0 exceptions: none programming notes: where the size of the operands are known, softw are should place the shorter operand in gpr rt . this may reduce the latency of the instructi on on those processors which implement data-depen- dent instruction latencies. 31 26 25 21 20 16 15 11 10 6 5 0 special2 011100 rs rt 0 00000 0 00000 maddu 000001 6 5555 6 multiply and add unsigned word to hi,lo maddu
idt instruction set 79rc32355 user reference manual a - 83 november 4, 2002 notes mfc0 format: mfc0 rt, rd mips32 mfc0 rt, rd, sel mips32 purpose: to move the contents of a coprocesso r 0 register to a general register. description: rt cpr[0,rd,sel] the contents of the coprocessor 0 register spec ified by the combination of rd and sel are loaded into general register rt. note that not all coproc essor 0 registers support the sel field. in those instances, the sel field must be zero. restrictions: the results are undefined if coprocessor 0 does not contai n a register as specified by rd and sel . operation: data cpr[0,rd,sel] gpr[rt] data exceptions: coprocessor unusable reserved instruction 31 26 25 21 20 16 15 11 10 3 2 0 cop0 010000 mf 00000 rt rd 0 00000000 sel 6555 83 move from coprocessor 0 mfc0
idt instruction set 79rc32355 user reference manual a - 84 november 4, 2002 notes mfhi format: mfhi rd mips32 purpose: to copy the special purpose hi register to a gpr description: rd hi the contents of special register hi are loaded into gpr rd . restrictions: none operation: gpr[rd] hi exceptions: none 31 26 25 16 15 11 10 6 5 0 special 000000 0 00 0000 0000 rd 0 00000 mfhi 010000 610556 move from hi register mfhi
idt instruction set 79rc32355 user reference manual a - 85 november 4, 2002 notes mflo format: mflo rd mips32 purpose: to copy the special purpose lo register to a gpr description: rd lo the contents of special register lo are loaded into gpr_ rd . restrictions: none operation: gpr[rd] lo exceptions: none 31 26 25 16 15 11 10 6 5 0 special 000000 0 00 0000 0000 rd 0 00000 mflo 010010 610556 move from lo register mflo
idt instruction set 79rc32355 user reference manual a - 86 november 4, 2002 notes movn format: movn rd, rs, rt mips32 purpose: to conditionally move a gpr after testing a gpr value description: if rt 0 then rd rs if the value in gpr rt is not equal to zero, then the contents of gpr rs are placed into gpr rd . restrictions: none operation: if gpr[rt] 0 then gpr[rd] gpr[rs] endif exceptions: none programming notes: the non-zero value tested here is the condition true result from the slt, slti, sltu, and sltiu comparison instructions. 31 26 25 21 20 16 15 11 10 6 5 0 special 000000 rs rt rd 0 00000 movn 001011 6 5555 6 move conditional on not zero movn
idt instruction set 79rc32355 user reference manual a - 87 november 4, 2002 notes movz format: movz rd, rs, rt mips32 purpose: to conditionally move a gpr after testing a gpr value description: if rt = 0 then rd rs if the value in gpr rt is equal to zero, then the contents of gpr rs are placed into gpr rd . restrictions: none operation: if gpr[rt] = 0 then gpr[rd] gpr[rs] endif exceptions: none programming notes: the zero value tested here is the condition false result from the slt, slti, sltu, and sltiu com- parison instructions. 31 26 25 21 20 16 15 11 10 6 5 0 special 000000 rs rt rd 0 00000 movz 001010 6 5555 6 move conditional on zero movz
idt instruction set 79rc32355 user reference manual a - 88 november 4, 2002 notes msub format: msub rs, rt mips32 purpose: to multiply two words and subtract the result from hi, lo description: (lo,hi) (rs rt) - (lo,hi) the 32-bit word value in gpr rs is multiplied by the 32-bit value in gpr rt , treating both operands as signed values, to produce a 64-bit result. the product is subtracted from the 64-bit concate- nated values of hi and lo . the most significant 32 bits of the result are written into hi and the least significant 32 bits are written into lo . no arithmetic excepti on occurs under any circum- stances. restrictions: none operation: temp (hi || lo) - (gpr[rs] gpr[rt]) hi temp 63..32 lo temp 31..0 exceptions: none programming notes: where the size of the operands are known, softw are should place the shorter operand in gpr rt . this may reduce the latency of the instructi on on those processors which implement data-depen- dent instruction latencies. 31 26 25 21 20 16 15 11 10 6 5 0 special2 011100 rs rt 0 00000 0 00000 msub 000100 6 5555 6 multiply and subtract word to hi,lo msub
idt instruction set 79rc32355 user reference manual a - 89 november 4, 2002 notes msubu format: msubu rs, rt mips32 purpose: to multiply two words and subtract the result from hi, lo description: (lo,hi) (rs rt) - (lo,hi) the 32-bit word value in gpr rs is multiplied by the 32-bit word value in gpr rt , treating both operands as unsigned values, to produce a 64-bit re sult. the product is subtracted from the 64-bit concatenated values of hi and lo . the most significant 32 bits of the result are written into hi and the least significant 32 bits are written into lo . no arithmetic exception occurs under any cir- cumstances. restrictions: none operation: temp (hi || lo) - (gpr[rs] gpr[rt]) hi temp 63..32 lo temp 31..0 exceptions: none programming notes: where the size of the operands are known, softw are should place the shorter operand in gpr rt . this may reduce the latency of the instructi on on those processors which implement data-depen- dent instruction latencies. 31 26 25 21 20 16 15 11 10 6 5 0 special2 011100 rs rt 0 00000 0 00000 msubu 000101 6 5555 6 multiply and subtract word to hi,lo msubu
idt instruction set 79rc32355 user reference manual a - 90 november 4, 2002 notes mtc0 format: mtc0 rt, rd mips32 mtc0 rt, rd, sel mips32 purpose: to move the contents of a general regi ster to a coprocessor 0 register. description: cpr[r0, rd, sel] rt the contents of general register rt are loaded in to the coprocessor 0 register specified by the combination of rd and sel. not all coprocessor 0 r egisters support the sel fiel d. in those instances, the sel field must be set to zero. restrictions: the results are undefined if coprocessor 0 does not contai n a register as specified by rd and sel . operation: cpr[0,rd,sel] data exceptions: coprocessor unusable reserved instruction 31 26 25 21 20 16 15 11 10 3 2 0 cop0 010000 mt 00100 rt rd 0 0000 000 sel 6 555 8 3 move to coprocessor 0 mtc0
idt instruction set 79rc32355 user reference manual a - 91 november 4, 2002 notes mthi format: mthi rs mips32 purpose: to copy a gpr to the special purpose hi register description: hi rs the contents of gpr rs are loaded into special register hi . restrictions: a computed result written to the hi / lo pair by div, divu,mult, or multu must be read by mfhi or mflo before a new result can be written into either hi or lo . operation: hi gpr[rs] exceptions: none 31 26 25 21 20 6 5 0 special 000000 rs 0 000 0000 0000 0000 mthi 010001 65 15 6 move to hi register mthi
idt instruction set 79rc32355 user reference manual a - 92 november 4, 2002 notes mtlo format: mtlo rs mips32 purpose: to copy a gpr to the special purpose lo register description: lo rs the contents of gpr rs are loaded into special register lo. restrictions: a computed result written to the hi / lo pair by div, divu, mult, or multu must be read by mfhi or mflo before a new result can be written into either hi or lo . operation: lo gpr[rs] exceptions: none 31 26 25 21 20 6 5 0 special 000000 rs 0 000 0000 0000 0000 mtlo 010011 65 15 6 move to lo register mtlo
idt instruction set 79rc32355 user reference manual a - 93 november 4, 2002 notes mul format: mul rd, rs, rt mips32 purpose: to multiply two words and write the result to a gpr. description: rd rs rt the 32-bit word value in gpr rs is multiplied by the 32-bit value in gpr rt , treating both operands as signed values, to produce a 64-bit result. the leas t significant 32 bits of the product are written to gpr rd . the contents of hi and lo are unpredictable after the operation. no arithmetic exception occurs under any circumstances. restrictions: note that this instruction does not provide the capabi lity of writing the result to the hi and lo reg- isters. operation: temp gpr[rs] gpr[rt] gpr[rd] gpr 31..0 hi uppredictable lo unpredictable exceptions: none programming notes: programs that require overflow detecti on must check for it explicitly. where the size of the operands are known, softw are should place the shorter operand in gpr rt . this may reduce the latency of the instructi on on those processors which implement data-depen- dent instruction latencies. 31 26 25 21 20 16 15 11 10 6 5 0 special2 011100 rs rt rd 0 00000 mul 000010 6 5555 6 multiply word to gpr mul
idt instruction set 79rc32355 user reference manual a - 94 november 4, 2002 notes mult format: mult rs, rt mips32 purpose: to multiply 32-bit signed integers description: (lo, hi) rs rt the 32-bit word value in gpr rt is multiplied by the 32-bit value in gpr rs , treating both operands as signed values, to produce a 64-bit result. the low- order 32-bit word of the result is placed into special register lo , and the high-order 32-bit word is placed into special register hi . no arithmetic exception occurs under any circumstances. restrictions: none operation: prod gpr[rs] 31..0 gpr[rt] 31..0 lo prod 31..0 hi prod 63..32 exceptions: none programming notes: programs that require overflow detecti on must check for it explicitly. where the size of the operands are known, softw are should place the shorter operand in gpr rt . this may reduce the latency of the instructi on on those processors which implement data-depen- dent instruction latencies. 31 26 25 21 20 16 15 6 5 0 special 000000 rs rt 0 00 0000 0000 mult 011000 655 10 6 multiply word mult
idt instruction set 79rc32355 user reference manual a - 95 november 4, 2002 notes multu format: multu rs, rt mips32 purpose: to multiply 32-bit unsigned integers description: (lo, hi) rs rt the 32-bit word value in gpr rt is multiplied by the 32-bit value in gpr rs , treating both operands as unsigned values, to produce a 64- bit result. the low-order 32-bit word of the result is placed into special register lo , and the high-order 32-bit word is placed into special register hi . no arithmetic exception occurs under any circumstances. restrictions: none operation: prod (0 || gpr[rs] 31..0 ) (0 || gpr[rt] 31..0 ) lo prod 31..0 hi prod 63..32 exceptions: none programming notes: programs that require overflow detecti on must check for it explicitly. where the size of the operands are known, softw are should place the shorter operand in gpr rt . this may reduce the latency of the instructi on on those processors which implement data-depen- dent instruction latencies. 31 26 25 21 20 16 15 6 5 0 special 000000 rs rt 0 00 0000 0000 multu 011001 655 10 6 multiply unsigned word multu
idt instruction set 79rc32355 user reference manual a - 96 november 4, 2002 notes nop format: nop assembly idiom purpose: to perform no operation. description: nop is the assembly idiom used to denote no operati on. the actual instruction is interpreted by the hardware as sll r0, r0, 0. restrictions: none operation: none exceptions: none programming notes: the zero instruction word, which represents sll, r0, r0, 0, is the preferred nop for software to use to fill branch and jump delay slots and to pad out alignment sequences. 31 26 25 21 20 16 15 11 10 6 5 0 special 000000 0 00000 0 00000 0 00000 0 00000 sll 000000 6 5555 6 no operation nop
idt instruction set 79rc32355 user reference manual a - 97 november 4, 2002 notes nor format: nor rd, rs, rt mips32 purpose: to do a bitwise logical not or description: rd rs nor rt the contents of gpr rs are combined with the contents of gpr rt in a bitwise logical nor opera- tion. the result is placed into gpr rd . restrictions: none operation: gpr[rd] gpr[rs] nor gpr[rt] exceptions: none 31 26 25 21 20 16 15 11 10 6 5 0 special 000000 rs rt rd 0 00000 nor 100111 6 5555 6 not or nor
idt instruction set 79rc32355 user reference manual a - 98 november 4, 2002 notes or format: or rd, rs, rt mips32 purpose: to do a bitwise logical or description: rd rs or rt the contents of gpr rs are combined with the contents of gpr rt in a bitwise logical or opera- tion. the result is placed into gpr rd . restrictions: none operation: gpr[rd] gpr[rs] or gpr[rt] exceptions: none 31 26 25 21 20 16 15 11 10 6 5 0 special 000000 rs rt rd 0 00000 or 100101 6 5555 6 or or
idt instruction set 79rc32355 user reference manual a - 99 november 4, 2002 notes ori format: ori rt, rs, immediate mips32 purpose: to do a bitwise logical or with a constant description: rt rs or immediate the 16-bit immediate is zero-extended to the left and combined with the contents of gpr rs in a bitwise logical or operation. the result is placed into gpr rt . restrictions: none operation: gpr[rt] gpr[rs] or zero_extend(immediate) exceptions: none 31 26 25 21 20 16 15 0 ori 001101 rs rt immediate 655 16 or immediate ori
idt instruction set 79rc32355 user reference manual a - 100 november 4, 2002 notes pref format: pref hint,offset(base) mips32 purpose: to move data between memory and cache. description: prefetch_memory(base+offset) pref adds the 16-bit signed offset to the contents of gpr base to form an effective byte address. the hint field supplies information about the way that the data is expected to be used. pref is an advisory instruction that may change the performance of the program. however, for all hint values and all effective addresses, it neither changes the architecturally visible state nor does it alter the meaning of the program. pref does not cause addressing-related except ions. if the address specified would cause an addressing exception, the exception condition is ignored and no data movement occurs. however even if no data is prefetched, some action that is not architecturally visible, such as writeback of a dirty cache line, can take place. pref never generates a memory operation for a location with an uncached memory access type. if pref results in a memory operation, the memo ry access type used for the operation is deter- mined by the memory access type of the effective addr ess, just as it would be if the memory oper- ation had been caused by a load or store to the effective address. the hint field supplies information about the way the data is expected to be used. a hint value cannot cause an action to modify architecturally visible state. 31 26 25 21 20 16 15 0 pref 110011 base hint offset 655 16 prefetch pref
idt instruction set 79rc32355 user reference manual a - 101 november 4, 2002 notes any of the following conditions causes the 4k core to treat a pref instruction as a nop. ? a reserved hint value is used ? writeback-invalidate (25) hint value is used ? the address has a translation error ? the address maps to an uncacheable page ? the data is already in the cache ? there is already another load/prefetch outstanding in all other cases, except when hint equals 25, execution of the pref instruction initiates an external bus read transaction. pref is a non-blocking operation and does not cause the pipeline to stall while waiting for the data to be returned. prefetch (cont.) pref
idt instruction set 79rc32355 user reference manual a - 102 november 4, 2002 notes
79rc32438 user reference manual i - 1 november 4, 2002 a address recognition logic ...............................................................11-7 space monitor ................................................................... 4-4 b bypass instruction ................................................................ 19-8 c clock prescalar.......................................................................11-30 control frames ........................................................................11-19 counter timer compare register........................................................... 14-2 control register.............................................................. 14-1 count register................................................................ 14-2 counter timers, general purpose ............................................. 14-1 d dma controller control register5-10, 5-11, 5-12, 10-4, 10-7, 10-10, 10-22, 10- 23, 10-24, 10-26, 10-27, 10-29, 10-38, 10-41, 10-42, 10-43, 10-44, 10-45, 10-47, 10-49, 10-51, 10-52, 10- 53, 10-54, 10-55, 10-56, 10-57, 10-59, 10-60, 16-4, 16-5, ..................................16-7, 16-8, 16-9, 18-14 dma interface ........................................................................11-12 e ethernet interface ....................................................................11-1 address recognition logic .................................................11-7 clock prescalar...............................................................11-30 dma controller .......................................................11-2?11-7 dma interface ................................................................11-12 input and output fifos ....................................................11-2 input dma operations ....................................................11-12 mac (medium access controller)..............11-2, 11-19, 11-22 management clock.........................................................11-34 mii management interface and registers .......................11-30 pause control frames ...................................................11-19 phy.................................................................11-1, 11-30??? ethernet management clock ..................................................11-34 extclk - external clock..........................................................6-11 g gpio controller ...................................................................... 12-1 gpio pins .............................................................12-1, 13-1?13-2 h halfword .....................................................................................1-ii i i2c bus interface clock prescalar....................................................... 15-1?15-4 clock prescalar (i2ccp) register..................................... 15-4 commands ........................................................... 15-3?15-11 control (i2cc) register..................................................... 15-2 loop-back operations .......................................................15-2 master command (i2cmcmd) register ...........................15-5 master interface...............................................................15-5 master status (i2cms) register .......................................15-5 master status mask (i2cmsm) register................15-5, 15-11 prescalar clock .......................................................15-2, 15-4 sclp and sdap signals .................................................15-6 slave acknowledge (i2csack) register ........................15-18 slave status (i2css) register.........................................15-14 speed of the master.........................................................15-6 ieee 1149.1 (jtag) ................................................................19-2 ieee 802 ..................................... 11-1, 11-14, 11-19, 11-24, 11-28 interrupt controller interrupt sources to the ipend registers....................8-4?8-6 j jtag, instruction register ......................................................19-6 m mac (medium access controller)..................... 11-2, 11-19, 11-22 master clock see clkp. mii management interface and registers............................... 11-30 p pause control frames........................................................... 11-19 phy................................................................................. 11-30??? pin descriptions .........................................................................1-7 prescalar clock ...............................................................15-2, 15-4 pseudocode signalexception.............................................................. a-10 syncoperation................................................................ a-10 r registers boundary-scan register .................................................19-3 bypass register ..............................................................19-3 counter timer compare register ...................................14-2 counter timer control register ......................................14-1 counter timer count register ........................................14-2 device identification register..........................................19-3 dma control register5-10, 5-11 , 5-12, 10-4, 10-7, 10-10, 10- 22, 10-23, 10-24, 10-26, 10-27, 10-29, 10-38, 10-41, 10-42, 10-43, 10-44, 10-45, 10-47, 10-49, 10-51, 10- 52, 10-53, 10-54, 10-55, 10-56, 10-57, 10-59, 10-60, .........................16-4, 16-5, 16-7, 16-8, 16-9, 18-14 instruction register .........................................................19-6 mii management registers............................................. 11-30 test data register...........................................................19-3 uart reset register......................................................13-4 watchdog timer compare register (wtcompare) .......4-5 watchdog timer control register (wtc)..........................4-5 watchdog timer count register (wtcount) .................4-5 reverseendian symbol ............................................................ a-7 index
idt index 79rc32438 user reference manual i - 2 november 4, 2002 riscore 32300 cpu core??? .............................................. 15-13 s signalexception pseudocode .................................................a-10 symbol reverseendian .................................................................a-7 syncoperation pseudocode ...................................................a-10 system clock ...................................................................... 3-6, 3-8 t test ..............................1-1, 2-1, 3-1, 4-1, 5-1, 7-1, 9-1, 12-1, 19-1 triple-byte ...................................................................................1-ii u uart ...................................................................................... 13-1 baud rate generator ............................................... 13-1?13-2 configuring ...................................................................... 13-2 interrupts......................................................................... 13-4 pins ................................................................................. 13-1 registers .......................................................................... 13-2 status .............................................................................. 13-1 switching between 16550 and 16450 modes.................. 13-4 undecoded address error.......................................................... 4-4 w watchdog timer compare register (wtcompare).................................. 4-5 control register (wtc) .................................................... 4-5 count register (wtcount) ............................................ 4-5

▲Up To Search▲

Price & Availability of 79RC32438-233BB

	To Download 79RC32438-233BB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .