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sda 5652-2x vps/pdcpro vps/pdc/osd device for vcrs edition feb. 28, 2001 6251-559-1
vps/pdcpro sda 5652-2x specification version 3.00 1. features general features ? low external component count ? no external crystal required ? technology: cmos ? p-dso-20 -1 package pdc features ? reception of vps data in line 16 of the vertical blanking interval ? complete reception of bdsp packet 8/30/1 and packet 8/30/2 ? reception of the complete teletext header row ? 400khz i2c-bus interface ? integrated osd module osd features ? display structure: 14 rows x 32 characters 12 rows x 30 characters (27 characters in visible frame area) ? 128 rom characters (12 pixel * 18 lines) ? fringing ? display start position programmable in horizontal and vertical direction ? insertion of osds in the cvbs signal (black and white) ? colored full screen osd mode ? integrated sync-separator ? integrated secam switch ? analog cvbs output ? 8 programmable background colors (via look up table) ? programmable flashing frequency (1.5hz, 1 hz or 0.5 hz) ? cursor ? four size settings in vertical and horizontal directions p - dso 20 -1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 vssa vssd fsc/osc_in scl sda osc_out sync2 vssd sync1 davn/ehb vdda vddd cvbs_in cvbs_slicer iref cvbs_out pd2/vco2 secam_by pd1/vco1 ht_blank 2
vps/pdcpro sda 5652-2x specification version 3.00 2. order information 3. general description the pdc/osd sda 5652-2x decoder chip receives all vps and 8/30 format 1 and 2 data together with the teletext header information for easy identification of the broadcaster. in addition to the well known pdc/vps decoder an osd module with an yuv to cvbs encoder is integrated. the osd can be synchronized to an cvbs signal or can generate a complete multistandard (pal/ntsc, 50hz/60hz frame rate) cvbs signal with a full screen colored osd. type package ordering code sda 5652-2x p - dso - 20 - 1 3
vps/pdcpro sda 5652-2x specification version 3.00 4. pin configurations vssa vssd scl sda sync2 pd1/vco1 pd2/vco2 cvbs_ iref cvbs_ slicer vddd vdda vssd osc_out cvbs_in secam_by ht_blank osc_out davn/ehb 20 19 18 17 16 15 14 13 12 11 2 3 5 6 7 8 9 10 1 4 fsc/osc out 4
vps/pdcpro sda 5652-2x specification version 3.00 5. pin definitions and functions pin. no. p-dso-20 symbol function 1 v ssa analog ground (0 v) 2 v ssd digital ground (0 v) 3 fsc/osc_in color carrier clock 4 scl serial clock input of i 2 c-bus. 5 sda serial data input of i 2 c-bus. 6 osc_out optional oscillator for 2fsc 7sync2 vertical sync/vertical composite sync (depending on i2c bus definition it can be switched to either input or output. when it is switched as an input, analog or digital signals can be proc- essed) 8v ssd internal used; should be connected to gnd 9 sync1 vertical/horizontal sync (depending on i2c bus definition it can be switched to either digital input or output) 10 davn/ehb output of the signals davn/ehb coming from the vps/pdc- circuit. 11 halftone_blank output-pin for halftone-blanking. goes to high for halftone- blanked video-areas, low for non-halftoneblanked areas 12 pd1/vco1 connector of the loop filter for the syspll. 13 secam_by input for secam bypass. 14 pd2/vco2 connector of the loop filter for the dapll. 15 cvbs_out composite video signal output from the osd path. 16 i ref reference current input for the on-chip analog circuit. 17 cvbs _slicer composite video signal input for the data slicer. the source of this signal must be the same as the source for signal at pin 18. 18 cvbs_in composite video signal input for the osd path. the source of thsi signal must be the same as the source for signal at pin 17. 19 v ddd positive supply voltage for the digital circuits. (+ 5 v nom.). 20 v dda positive supply voltage for the analog circuits (+ 5 v nom.). iref pd2/vco2 pd1/vco1 cvbs_sli sda scl cvbs_out cvbs_in secam_by fsc sync1 sync2 davn/ehb 5
vps/pdcpro sda 5652-2x specification version 3.00 6.block diagram the processing of the data in the sda 5652-2x works in the following way: data / sync - slicer and acq -pll data - acquisition memory for sliced data and osd information (512 byte) acquisition timing i2c- bus interface cvbs encoder display timing sync /pixelclock generation character generator character rom 6
vps/pdcpro sda 5652-2x specification version 3.00 7. circuit description 7.1 vps/pdc functions referring to the functional block diagram the composite video signal with negative going sync pulses is coupled to the pin cvbs through a capacitor which is used for clamping the bottom of the sync pulses to an internally fixed level. the signal is passed to the slicer, an analogue circuitry separating the sync and the data parts of the cvbs signal, thus yielding the digital composite sync signal vcs and a digital data signal for further processing by comparing those signals to internally generated slicing levels. the output of this sync separator is forwarded to the acquisition clock generator and the acquisition timing block in which teletext / vps related data-valid-windows are generated. the data slicer separates the data signal from the cvbs signal by comparing the video volt- age to an internally generated slicing level which is found by averaging the data signal dur- ing tv line no. 16 in the vps mode or by averaging the data signal during the clock run-in period of the teletext lines during the data entry window (dew) in pdc mode. the acquisition clock generator delivers the system clock needed for the basic timing as well as for the regeneration of the dataclock. it is based on two phase locked loops (plls) all parts of which are integrated on chip with the exception of the loop filter components. each of the plls is composed of a voltage controlled relaxation oscillator (vco), a phase/ frequency detector (pfd), and a charge pump which converts the digital output signals of the pfd to an analogue current. that current is transformed to a control voltage for the vco by the off-chip loop filter. the generated vco frequencies are 10 mhz and 13.875 mhz for vps mode and pdc mode, respectively. all signals necessary for the control of sync and data slicing as well as for the data acquisi- tion are generated by this timing block. the sda 5652-2x can be operated in three different modes: depending on the selected operating mode, either teletext lines carrying 8/30 packages, the dedicated tv line no. 16(vps) or the teletext header bytes are acquired. in pdc mode, only teletext rows 8/30 containing broadcast data service package (bdsp) information are acquired. the relevant bytes of 8/30 format 1 (8/30/1) and 8/30 format 2 (8/ 30/2) are extracted. the 8/30/1-bytes are stored in the acquisition register in a transparent way without any bit manipulation, whereas the hamming coded bytes of packet 8/30/2 are hamming-checked and bytes with one bit error are corrected. in ttx header mode all bytes of the headers are stored. hamming protected bytes are cor- rected and need not to be processed by the external controller. for the order of the stored bytes see i2c bus register description. a micro controller can read the stored bytes via the i2c bus interface at any time. in order to achieve maximum system performance it is recommended to start the sda 5652-2x in vps mode (state after power on) and read the register to check whether line 16 is received. after reception of vps data in line 16 the sda 5652-2x can be switched to 8/30 7
vps/pdcpro sda 5652-2x specification version 3.00 mode and waiting for packet 8/30 data. since vps data in line 16 is transmitted every frame and pdc data in packet 8/30 is transmitted nearly every second the recognition of both vps and 8/30 packets can be done within pdc-system constraints (about 1 sec). to differ between older (sda5649/5650) and future (SDA5652-2X/...) pdc versions a spe- cial method can be used for chip identification: sda5649/5650 pdc-versions are not writeable. first step is, the user chooses a pattern of bytes and writes them to the ram. second step is to read these bytes from the ram. by comparing the written bytes and the read bytes there may be correspondence or not. if theres correspondence the present ic is a new version (SDA5652-2X/...) if theres no corre- spondence its a older version (sda5650/5651). in addition further versions (SDA5652-2X/ ...) could be differed with a special i2c-register. valid-data-recognition: the pdc/vps-registers could be read by the external controller. there is no necessity for the controller reading the pdc/vps-contents if the register-con- tents arent made topical by a new reception. there are three methods to identify if the reg- ister-contents are made topical after a previous reading-operation: 1. data-set-valid-bit after a new reception is fulfilled the data-set-valid-bit is set from low to high. if data-set- valid-bit is high and a i2c-read-operation for a subaddress between 4 and 40 is closed by a stop condition the data-set-valid bit is set from high to low, if during the iic-read-operation no new datas are received. 2. davn-signal on pin10 the signal davn (data valid active low) will be available. the behaviour of this signal is described as follows: a) vps-mode: h/l-transition (set to low): after vps-data has been received. l/h-transition (set to high): at the start of line 16. b) pdc/hta/htb/htc-mode: h/l-transition (set to high): in the line where valid data is carried. l/h-transition (set to low): at the beginning of the next field 3. vps/pdc-register-contents if a stop-condition is send to the i2c-bus-interface after a read-operation has been accessed for the addresses between 4 and 40, all register-contents from 4 to 40 are set to 255 if during the iic-read-operation no new datas are received (falling edge of davn). a new reception of vps/pdc-datas during or after the iic-read-operation, will overwrite these ffh-contents. as a result a new data-reception could be detected by the register-con- tents itself. 8
vps/pdcpro sda 5652-2x specification version 3.00 format of register acq_control (default values in brackets) for1/for2: determines which kind of data is stored in the decoder when pdc mode is active: 0 : bdsp 8/30/2 accessible 1 : bdsp 8/30/1 or header row data accessible (refer to de- scription of bit pdc/vps pdc/vps: 0 : vps mode is active 1 : pdc mode is active att e ntion: p l ea se refe r to erra ta -s hee t ite m - n o. h 5 rela ting to v p s -mo de/by t e 1 3 hdt: determines whether bdsp 8/30/1 data or header row data is stored. 0 : bdsp 8/30/1 accessible 1 : teletext header mode is active. see also bit mab mabc_1...0: 00 : mode a. header bytes are accessed in order 38 - 45, 30 - 37. 01 : mode b. header bytes are accessed in order 22 - 29, 14 - 21. 1x : mode c. header bytes are accessed in linear increasing order 4-45. dsv: data set valid this bit is only read and not writeable. write-operations have got no influence to this bit. declares when pdc/vps-register-contents are renewed af- ter a previous read-operation. it is not allowed to read the content of dsv-bit (subadr. 03h) and vps/pdc-data (sub- adr. 04h - 27h) within one iic-protocol. in this case dsv is not cleared and the data-registers are not set to ffh reli- able. 0: register-contents havent been renewed up to the mo- ment this bit is read. 1: register-contents are renewed. the datas read out by a new iic-read-operation from byte 4-40 are completly valid. bit 7 bit 6 bit 5 b it 4 b it 3 b it 2 b it 1 b it 0 acq_control (0) (0) d sv (0) mabc_1 (0) mabc_0 (0) hdt (0) pdc/ vps (0) for1/ for2 (0) 9
vps/pdcpro sda 5652-2x specification version 3.00 7.1.1 format of stored data bytes bits are stored in the order of their reception, that means the first transmitted bit is stored in bit 7 of the appropriate i2c bus address. in format 2 of packet 8/30 the contents of two trans- mitted bytes is stored in one i2c bus register address. hamming bits are not stored. att e ntion: p l ea se refe r to erra ta -sh e e t item-n o. h5 rela ting to vp s -mode /byt e1 3 (i2 c -subaddress 6) i2c- subaddress456789101112131415 8/30 format 1 15 16 17 18 19 20 21 13 14 22 23 24 8/30 format 2 16,1718,1920,2122,2314,1524,2513,xxxxxx vps 11121314515xxxxxx hta 38 39 40 41 42 43 44 45 30 31 32 33 htb 22 23 24 25 26 27 28 29 14 15 16 17 htc 4,5 6,7 8,9 10,11 12,13 14 15 16 17 18 19 20 i2c- subaddress161718192021222324252627 8/30 format 1 25 26 27 28 29 30 31 32 33 34 35 36 8/30 format 2 x 2627282930313233343536 vps xxxxxxxxxxxx hta 34353637xxxxxxxx htb 18192021xxxxxxxx htc 21 22 23 24 25 26 27 28 29 30 31 32 i2c- subaddress282930313233343536373839 8/30 format 1 37 38 39 40 41 42 43 44 45 x x x 8/30 format 2 37 38 39 40 41 42 43 44 45 x x x vps xxxxxxxxxxxx hta xxxxxxxxxxxx htb xxxxxxxxxxxx htc 33 34 35 36 37 38 39 40 41 42 43 44 i2c- subaddress 40 1 0
vps/pdcpro sda 5652-2x specification version 3.00 8/30 format 1 x 8/30 format 2 x vps x hta x htb x htc 45 1
vps/pdcpro sda 5652-2x specification version 3.00 7.2. osd functions the osd block consists of a character generator unit which reads out character addresses from the internal ram and transforms them by the help of a character rom into pixel infor- mation. the osd memory has a size of 448 bytes. as a result the display is fixed to a for- mat of 14 rows with 32 characters. for a 50hz-system 14 rows are displayed, for a 60hz- system 12 rows. the count of columns can be defined by the user to 30 or 32. for systems using a color-carrier of 4,43mhz 32 characters should be choosen, for systems using a 3,58mhz color-carrier 30 characters should be choosen. so if needed the display-memory- contents from the two columns on the right side or the contents from the two last rows are ignored. bytes are processed in linear binary increasing order. the display memory is accessed via the dataport. starting address is 0 d (see also 7.3.2. dataport access). the character structure is 12 pixels in horizontal direction and 18 lines in vertical direction. with the bits 0 to 6 of the address 128 characters of the character rom can be addressed. the addresses of the characters are orientated on the wellknown ascii-table. horiz ontal _size (2bit) verti- cal _size (2bit) char- attribute_ 2 (2bit) char- attribute_ 1 (2bit) i = 0 ..... i = 31 x x xx xx 0 + i display memory 14 rows with 32 characters x x xx xx 32 + i x x xx xx ... ... ... ... ... ... ... ... ... ... 416 + i 1
vps/pdcpro sda 5652-2x specification version 3.00 bit 7 of the character address is used to switch between two attribute definitions. these two attribute definitions can be chosen for each row individual. for this choice each row has two character-attribute-registers, char_attribute_1 and char_attribute_2 . char-attribute_1 consists of two bit and char-attribute_2 consists of two bits. one out of four character-definitions can be selected by these two bits. these four character-defini- tions are made for char-attribute_1 in the four registers char-definition1_1...1_4 . for char-attribute_2 these four definitions are made in char-definition2_1...2_4 . the format of the char-definition-registers and the char-attribute-registers see below. format of the registers char-definition1_1...1_4 and char-definition2_1...2_4: (default value in brackets): halftone: fullpage-mode or if display is turned off: in fullpage-mode or if display is turned off this bit has got no influence. pin11 is static switched to l-level. mixed-mode: switches between halftone-blanking on and off. characters for which halftone-blanking is turned on, pin11 is switched to h-level during these characters are displayed. other- wise pin11 is switched to l-level. 0: switching halftone-blanking off 1: switching halftone-blanking on hs_1...0 : horizontal size per dot as multiples of the pixel clocks. only used if the row-attribute horizontal_size_select bits are set to 0. 00 : 1 pixel clock per dot. 01 : 2 pixel clocks per dot. 10 : 3 pixel clocks per dot. 11 : 4 pixel clocks per dot. bl_1...0 : defines the blanking mode of the characters in mixed mode. theres a special fringing-mode. fringing means, that the character is surrounded by a border. this border has the size of one pixel: settings for mixed mode: 00 : blanking is switched off. the complete character (bor- der and background) is visible on the screen. 01 : background is blanked, only the foreground information bit 7 bit 6 bit 5 b it 4 b it 3 b it 2 b it 1 b it 0 byte 1 half- tone bl_1 bl_0 hs_1 hs_0 bk_0 bk_1 inv byte 2 fcol_4 fcol_3 fcol_2 fcol_1 fcol_0 bcol_2 bcol_1 bcol_0 1
vps/pdcpro sda 5652-2x specification version 3.00 of the character is visible. 10 : background is blanked, only the foreground information of the character including the border (fringing) is visible. 11 : the complete characters are blanked. (the character is not visible) in full-page-mode no blanking is available. fringing can be switched with bit bl_1. settings for full-page-mode: 0x : fringing is switched off 1x : fringing is switched on bk_1...0 : defines the flashing mode and period for the appropriate row. when flashing is specified for reversed characters, the flashing will be between normal character and reversed dis- play. 00 : flashing is switched off 01 : flashing is switched on. the period is approximately set to 0.5/s 10 : flashing is switched on. the period is approximately set to 1.0/s 11 : flashing is switched on. the period is approximately set to 1.5/s bcol_2...0: in full-page-mode: defines the background color vector. the final color depends on the values of the look up table (see below). in mixed-mode: defines the background grey-value. the final grey-value depends on the luminancevalue described in the look up table (see below). fcol_4...0: defines the foreground grey-value. up to 23 values between 1,4v and 2,9v in steps of about 68mv can be selected in full-page-mode (the values from 0 to 8 are not allowed because there levels are in the sync-area). up to 32 values between 1,4v and 2,9v in steps of about 48 mv can be selected in mixed-mode. inv: 0: inverting is switched off 1: inverting is switched on the characters can be zoomed in horizontal and vertical direction. characters neighboured on the right or below of a zoomed character are overwritten and not shifted. each row has two vertical-size-select bits in which the size of the characters are defined for the whole row. the size can be zoomed in vertical direction up to factor 4. each row has two horizontal-size-select bits in which the size of the characters can 1
vps/pdcpro sda 5652-2x specification version 3.00 be defined for the whole row. the size can be zoomed in horizontal direction up to factor 4. if the horizontal_size_select bits are set to 0 each character can be zoomed indi- vidual by the char_attributes- and char_definition-registers. the horizontal_size_select bits, vertical_size_select bits and the char_attribute_1..2 bits are stored for each row in the register row_attribute: format of the register row_attribute: a t t e ntion: ple a s e re f e r to e rrata-s h e et ite m -no. h1, h4 re lating to ve r t ica l a nd hori- zont al zoom format of the registers vertical_start_position and horizontal_start_position: the position of the display can be adjusted in terms of pixels and lines referring to the hori- zontal and vertical edge of the picture. the position is programmed in the register vertical_start_position and horizontal_start_position. the line-counter for the vertical-start- position is set to 0 during the negative going flank of v-sync. the pixel-counter for the hori- zontal-start-position is set to 0 after the positive going flank of h-sync (negative flank of vcs). att e ntion: ple a s e re fer to e rrata-s h e et ite m -n o. h1, h2 , h3, h4, h 6 re lating to horizontal and vertical st art- posit i on. vsp_6...0: vertical start position of the screen. vsp_6...0 define the shift of the screen in vertical direction as multiples of hori- zontal lines. bit 7 bit 6 bit 5 b it 4 b it 3 b it 2 b it 1 b it 0 row 1 horizo ntal_si ze/bit1 horizo ntal_si ze/bit0 vertic al_size /bit1 vertic al_size /bit0 char_at tribute _2/bit1 char_at tribute _2/bit0 char_at tribute _1/bit1 char_at tribute _1/bit0 row 2 horizo ntal_si ze/bit1 horizo ntal_si ze/bit0 vertic al_size /bit1 vertic al_size /bit0 char_at tribute _2/bit1 char_at tribute _2/bit0 char_at tribute _1/bit1 char_at tribute _1/bit0 .... .... .... .... .... .... .... .... .... row 14 horizo ntal_si ze/bit1 horizo ntal_si ze/bit0 vertic al_size /bit1 vertic al_size /bit0 char_at tribute _2/bit1 char_at tribute _2/bit0 char_at tribute _1/bit1 char_at tribute _1/bit0 bit 7 bit 6 bit 5 b it 4 b it 3 b it 2 b it 1 b it 0 vertical_ start_position (0) vsp_6 vsp_5 vsp_4 vsp_3 vsp_2 vsp_1 vsp_0 horizontal_ start_position (0) hsp_6 hsp_5 hsp_4 hsp_3 hsp_2 hsp_1 hsp_0 1
vps/pdcpro sda 5652-2x specification version 3.00 hsp_6...0: horizontal start position of the screen. hsp_6...0 define the shift of the screen in horizontal direction in pixel clocks. clock-supply the pixel clock (2fsc, fsc, 2fsc/3, fsc/2) is derived from the system-clock (4fsc) depending on the horizontal-zoom-factor. the system-clock(4fsc) is derived from a external frequency. there are two methods to provide these external frequency. one method is to fed in a frequency of 1fsc or 2fsc or 4fsc at pin3. the second method is to plug a 2fsc-crystal-oscillator to pin3 and pin6. which of these methods is used is defined in the register synchronisation. the pixel clock is internally synchronized to the horizontal- sync information by a discrete phase shifter. synchronisation-modes the sync information may be delivered as external v/h impulses, as a composite sync sig- nal or is derived from the analog cvbs-signal. in free run mode the timing block can gener- ate its composite sync signal so a stable display can be produced even if no external sync source is available. there are different synchronisation-modes for mixed-mode-osd. for more information of these modes, see register synchronisation and the figure on page 22. for high-end-sync-performance in mixed-mode a internal hpll can be used for synchroni- sation. the hpll consist of a digital dto, a digital phase-detector and a loop-filter. there are different settings for the loop-filter possible. for high-performance we recom- mend a universal loop-filter-setting. for advanced high-performance there is the possibility to adapt the loop-filter to each customer-specific-vcr in the different replay-modes (fast- forward/fast-backward-mode, long-play/short-play). hpll0: register to justify the integral filter-component 0: 1/128 1: 0 hpll1: register to justify the proportional filter-component 0: 1 1: 4 hpll2..3: register to justify the proportional/integral filter-component 00: 1/32 bit 7 bit 6 bit 5 b it 4 b it 3 b it 2 b it 1 b it 0 hpll (0) (0) (0) (0) hpll_3 hpll_2 hpll_1 hpll_0 1
vps/pdcpro sda 5652-2x specification version 3.00 01: 1/16 10: 1/8 11: 1/4 for universal vcr/tuner-modes we recommend: hpll0: 0 hpll1: 1 hpll2: 1 hpll3: 1 for high-performance noise-surpress we recommend: hpll0: 0 hpll1: 0 hpll2: 0 hpll3: 0 in mixed mode display the signal processing is synchronized to the cvbsin-signal. for this at pin7 and pin9 the h-synchronization and v-synchronization-signals can be fed to the ic. in full-page-mode both pins(pin7 and pin9) are working as a output. in this case they deliver h-sync and v-sync-signals. they also can be switched in a highly impedant state. format of register synchronisation (default values in brackets): dispon: switches the cvbs_in-signal (pin18) to cvbs_out- signal(pin15). this bit has highest priority. switching it to low, the incoming cvbs-signal is fed through the ic to cvbs output. 0: cvbs_in=cvbs_out 1: the two states cvbs_in=cvbs_out and d/a=cvbs_out is controlled by the character- generator iic_switch: after release-bit has been set from 1 to 0, a new iic- bus-protocol should be started to switch iic-switch from 1 to 0. by this, highest noise-surpression of the sda/ scl-signals is guaranteed. (see also ?10.1 after-reset-start-sequence) osc_sys_1...0: defines source for system-clock generation. the frequency of this source is internally multiplied to 4fsc. this frequency is used for color-carrier-generation in full- bit 7 bit 6 bit 5 b it 4 b it 3 b it 2 b it 1 b it 0 synchronisa- tion (0) sync_2 (1) sync_1 (0) sync_0 (0) iic_swi tch(1) dispon (0) osc_sy s_1(0) osc_sy s_0(1) 1
vps/pdcpro sda 5652-2x specification version 3.00 page-mode. 00 : 1 fsc (pin 3) with ext. feedback resistor 01 : 2 fsc (pin 3) with ext. feedback resistor 10 : 4 fsc (pin 3) with ext. feedback resistor 11 : optional, external crystal-oscillator for system-clock- generation(pin3/pin6). this crystal-oscillator must have his resonance-frequency at 2fsc. this mode also can be used as a alternative mode to 01: 2fsc (pin3). in this mode the external feedback resistor is no longer necessary because in this mode a internal resistor is used. the oscillator-mode can be installed by these bits as long as the bit release in the register levels_and_change is set to 1. after setting bit release in register levels_and_change to 0, the oscillator-mode wont change anymore, anyway if the polarity of these bits are changed by the user. next to the oscillator-mode-settings, the bit osc_sys(0) can be used to switch a special vcs-spike-surpress-filter for the slicer on and off. we recommend to keep this filter switched on in all modes. 0: the vcs-spike-filter is switched on. 1: the vcs-spike-filter is switched off. next to the oscillator-mode-settings the bit osc_sys(1) can be used to switch a special algorithm to the slicer. this special algorithm allows high noise-surpress. the algorithm works for signals in which the cri has the same length(8cycles) as it is described inside the etsi-standard for teletext. if a cvbs-signal is processed in which the count of cri-cycles is non-standard the special algorithm should be switched off. we recommend to start the data- slicing by switching the special algorithm on (for standard- signals and high-noise-performance). if this is not success- full we recommend to proceed the data-slicing by switching the special algorithm off. by this, non-standard-signals can be sliced with a little less noise-performance. 0: special algorithm is switched on 1: special algorithm is switched off sync_2...0: three muxes inside the synchronisation-signal-pathes are controlled by these three bits as shown below in the figure. pin9 and pin7 are used as a input/output for external syn 1
vps/pdcpro sda 5652-2x specification version 3.00 chronisation. if bit sync_2 is switched to 0 pin7 is used as output, if sync_0 is switched to 1 pin9 is used as output. next to sync_2...0 the synchronisation-signal-path is con- trolled by the bits sync_himp, hsync_high/ low_detect and vsync_high/low_detect of the register levels_and_change (see also page 26/27). sync_himp is used to switch the outputs in high-imped- ant-state. hsync_high/low_detect and vsync_high/low_detect is used to invert the syn- chronisation-signals for enabling the detection of both edges synchronisation-edges. fig u re : sig nal -pa t hes of the sy nc -s epe ra tio n -c irc u it i/o i/o internal sync- m u x dig. hpll m u x vertical- seperation m u x 0 1 pin17 cvbs_ slicer sync2 pin7 sync1 pin9 sync_2 sync_1 sync_0 sync_himp sync_himp exor vsync_high/ low_detect v h exor hsync_high/ low_detect exor slicer levels_and_change/ display_control/ vcs 0 1 1 0 1
vps/pdcpro sda 5652-2x specification version 3.00 summary of sync-modes (sync2...0) : negative going hsync -pulses are expected by default. using the register levels_and_change this can be switched to positive going syncpulses. with vsync_edge_polarity in the register levels_and_change the user can choose level or edge-sensitive vertical synchronisation. the polarity of the digital output-h-sync-signal are positive going sync-impulses. the color look-up-table the ic is capable to display eight different color values in one picture. these eight values can be defined by the user in the registers color_value : on the assumption, that the color-values are given in voltage values which are related to a cvbs-signal the corresponding register-contents could be derived as follows: given color-value: phase chromaamplitude (peak to peak in mv) luminanceamplitude (in mv above porch-level) corresponding register-contents: luminance-register: integer( 63*(luminanceamplitude+300mv)/1000mv) u-component-register: integer(chromaamplitude*cos(phase)*63/2000mv) v-component-register: -integer(chromaamplitude*sin(phase)*63/2000mv) for example these equations are solved for three color-values: 1. blue phase: -38 chromaphase 162mv chromaamplitude (peak to peak in mv) 200mv luminanceamplitude (above porch-level) luminance-register: 32 u-component-register: +4 sync_ 2 sync_ 1 sync_ 0 h v hpll pin9 pin7 0 0 0 intern extern out of use input output 0 0 1 intern intern out of use output output 0 1 0 intern extern in use input output 0 1 1 intern intern in use output output 1 0 0 extern extern out of use input input 1 0 1 extern intern out of use output input 1 1 0 extern extern in use input input 1 1 1 extern intern in use output input 1
vps/pdcpro sda 5652-2x specification version 3.00 v-component-register: +3 2. blue-green phase: -90 chromaphase 286mv chromaamplitude (peak to peak in mv) 250mv luminanceamplitude (above porch-level) luminance-register: 35 u-component-register: 0 v-component-register: +9 3. grey phase: indifferent chromaphase 0mv chromaamplitude 125mv luminanceamplitude (above porch-level) luminance-register: 27 u-component-register: 0 v-component-register: 0 the u/v-component-registers are programmed in twos-complement. this means: 01111b = +15 01110b = +14 01101b = +13 ..... . .... 00000b = 0 11111b = -1 11110b = -2 11101b = -3 ..... . .... 10001b = -15 the value 10000 b = -16d is not allowed. format of the eight registers color-value1...8: format of border-color-register/fringing-color-register: there is a leftover of active video surrounding the field of characters. the colors of this bor- der can be defined via the look-up-table described above. next to the border-color, the fringing color is defined in this register. bit 7 bit 6 bit 5 b it 4 b it 3 b it 2 b it 1 b it 0 luminance (0) (0) bit5 bit4 bit3 bit2 bit1 bit0 u-componente (0) (0) (0) bit4 bit3 bit2 bit1 bit0 v-componente (0) (0) (0) bit4 bit3 bit2 bit1 bit0 1
vps/pdcpro sda 5652-2x specification version 3.00 border can be switched on and off. border off means for fullpage-mode: the left part of the border in each row is set to the same color as the first character in each row is set. the right part of the border in each row is set to the same color as the last character is set. the upper and lower part of the border is set to the color defined for the border. border on means for fullpage-mode: the whole border has the color which is defined for the border. bo_onoff 0: border on 1: border off border2...0 defines the color of the border via the color-look-up- table (see above). frco_2..0: if fringing is turned on one out of eight fringing grey-values can be selected. the levels for the grey-values in full-page mode are 1.4v and 1.9v in steps of about 67 mv. in mixed mode eight levels between 1.4v and 2.1v in steps of about 93mv can be selected in full-page-mode. format of register display control: switching between full-page-osd and mixed-mode and turning display off, etc. ... is handled with the display-control-register. the ic has a multi standard video output. that means, ntsc/pal-color-systems can be encoded and field-frequencies of 50/60hz can be choosen. in standard-mode the pixel-clock is derived from color-carrier (2fsc). the user is free to choose the color-carrier which is fed in at pin3. for example pal color-carrier is 4.43mhz and ntsc color-carrier is 3.58mhz. the pixel-clock is derived from this color-car- rier. a suitable count of character in horizontal direction can be choosen by the bit norm1. for ntsc and some pal-derivates a frame-rate of 60hz (525 lines) is used. in this case in vertical direction 12 character-rows are produced. in standard-pal a frame-rate of 50hz (625 lines) is used. as a result in vertical direction 14 character-rows are produced. bit 7 bit 6 bit 5 b it 4 b it 3 b it 2 b it 1 b it 0 border_fringin g (0) frco_2 frco_1 frco_0 bo_on off borde r_2 borde r_1 borde r_0 bit 7 bit 6 bit 5 b it 4 b it 3 b it 2 b it 1 b it 0 display con- trol davn/ ehb vcs full- page secam_ switch space norm_2 norm_1 norm_0 1
vps/pdcpro sda 5652-2x specification version 3.00 davn/ehb: the davn and ehb-signals can be made visible on the output-pin10. which of these two signals is shown on the output-pin is defined in the bit davn/ehb. 1: ehb is shown at pin10. 0: davn is shown at pin10. vcs: 0: internal vcs is not inverted (front porch of h is used for synchronisation) . 1: internal vcs is inverted (back porch of h is used for synchronisation). norm0: this bit is only used in full-page-mode. 0: ntsc 1: pal norm1: this bit is used in both modes (full-page and mixed-mode) 0: 30 characters in horizontal direction 1: 32 characters in horizontal direction norm2: this bit is used in both modes (full-page and mixed-mode) 0: 50hz-system 1: 60hz-system following standards can be choosen by norm2 and norm0: space: 0: in this state the character-ram is displayed. 1: in this state the contents of the character-ram are ignored and space-characters are displayed all over the screen. secam_switch: 0: secam-switch off for pal/ntsc 1: secam-switch on for secam-signals. that means the current secam-color-frequency on cvbsin-side is added to the cvbs-out signal in the areas of characters in mixed mode. fullpage: 0: full-page-osd-mode. 1: mixed-mode. norm2 norm0 standard nominal color-car- rier-frequency 00 ntsc(equivalent to mode 10) 3,57954500 mhz 01 pal bg 4,43361875 mhz 10 ntsc(equivalent to mode 00) 3,57954500 mhz 11 pal m 3.57561149 mhz 1
vps/pdcpro sda 5652-2x specification version 3.00 format of register levels_and_change: chng_mixed_full: next to the register-bit fullpage in display_ control-register this bit has to be used for switching between fullpage-mode and mixed-mode. 0: for mixed-mode 1: for fullpage-mode 1. switching from mixed-mode to fullpage-mode: first step: display_control/bit5 set to 0 second step: chng_mixed_full set to 1 2. switching from fullpage-mode to mixed-mode: first step: chng_mixed_full set to 0 second step: display_control/bit5 set to 1 hsync_high/low_detect: defines which polarity of the hsync should be used for osd-synchronization. 0: negative going sync-pulses are expected. 1: positive going sync-pulses are expected. vsync_high/low_detect: defines which edge of the vsync should be used for osd-synchronization. 0: uses the rising edge 1: uses the falling edge sync_himp: 0: the output of the pins 7/9 are not switched to high- impedant-state in all the modes. 1: the output of the pins 7/9 are switched to high- impedant-state in all the modes. release: after power-on-reset the contents of the synchronisation- register may not refer to the frequency which is fed in at pin9/7. after setting the bits osc_sys1..0 in the register synchronisation to the contents which are referring to the input-frequency, the bit release has to be switched from 1 to 0. after switching to 0 the bit release cannot be changed anymore to 1 except by a iic-bus- or power-on- reset. after switching bit release to 0 the bits osc_sys1..0 in register synchronisation cannot be changed anymore without executing a iic- or bit 7 bit 6 bit 5 b it 4 b it 3 b it 2 b it 1 b it 0 levels_and_cha nge (0) (0) vsync_ edge_ polar- ity (1) releas e (1) sync_ himp(1) vsync_ high/ low_ detect (0) hsync_ high/ low_ detect (0) chng_ mixed_ full (1) 1
vps/pdcpro sda 5652-2x specification version 3.00 power-on-reset.. vsync_edge_polarity: this bit is used, to choose the synchronisation-mode in mixed-mode for the vsync. if polarity is choosen the osd is synchronized by the levels of the vsync. in this case the vsync should have a minimum-length of 1line. if edge is choosen the osd is synchronized by the edge of the vsync. in this case there are no special efforts to the vsync-length. in general its recommended to use the edges. 0: osd is synchronized by vsync edges. 1: osd is synchronized by vsync polarity. 1
vps/pdcpro sda 5652-2x specification version 3.00 7.3. i2c-bus information is exchanged between an external controller and the sd 5652-2x on a fast asynchronous bidirectional data bus. the i2c-bus uses two connections, the pins sda (data) and scl (clock), and operates according to the i2c-bus specifications, which limits the maximum transfer rate at 400 kbit/s. the interface operates in the slave mode: either as receiver or transmitter. the chip address is fixed to msb 0010000x lsb . the msb is trans- mitted first. the lsb switches between reading-mode(1) and writing-mode(0). the bus-system isnt blockaded if there is no power-supply switched to the SDA5652-2X 7.3.1 protocols the following protocols are supported (in read mode the subaddress must be defined by a previously access): write followed by a read : please notice: before the stop-condition after the reading-operation, there is no ack_m allowed!!! write followed by a read with stop condition: please notice: before the stop-condition after the reading-operation, there is no ack_m allowed!!! with the following abbreviations: start: start condition (i2c: see technical bus description) stop: stop condition (i2c: see technical bus description) ack_s: acknowledge by slave (i2c: see technical bus description) ack_m: acknowledge by master (i2c: see technical bus description) sl_ad: 7- bit chip select address su_ad: 8- bit subaddress 7.3.2 access modes s t a r t s l _ a d w r i t e a c k _ s s u _ a d a c k _ s d a t a a c k _ s d a t a a c k _ s ... ... ... s t a r t s l _ a d r e a d a c k _ s d a t a a c k _ m d a t a a c k _ m d a t a a c k _ m ... ... ... s t o p s t a r t s l _ a d w r i t e a c k _ s s u _ a d a c k _ s d a t a a c k _ s d a t a a c k _ s ... ... s t o p s t a r t s l _ a d r e a d a c k _ s d a t a a c k _ m d a t a a c k _ m d a t a a c k _ m ... ... ... s t o p 1
vps/pdcpro sda 5652-2x specification version 3.00 there are two possibilities to access sda 5652-2x. one is addressing it direct by use of one of the 256 possible subaddresses of the i2c protocol. the other method is an indirect addressing method. this must be used if a byte from the display ram should be read or written. in that case a dataport must be used for transfer (see below). autoincrement of bus registers after any read or write access to a register the subaddress will be incremented automati- cally. there are only one exceptions: in read and write mode, subaddress ?2 is not incre- mented (see also dataport access). 7.3.3 dataport access the address pointer registers are used to address the internal memory to read or write data via the i2c bus. a dataport (2) is an i2c-bus register which can be read or written by addressing it with its subaddress. independent from the transfer direction (read or write) the memory address is defined by the address pointer registers (0, 1) which must be defined before accessing the dataport. the display-ram is accessed via the dataport. its startad- dress begins at address 0. autoincrement of the dataport the autoincrement for the dataport is always switched on. that means, each time after the dataport address (2) is accessed, the contents of the addresspointer registers is incre- mented. the following protocols are supported: writing the memory including initializing of addressport : writing the memory using an previous defined addressport : reading the memory using an previous defined addressport: please notice: before the stop-condition after the reading-operation, there is no more a s t a r t s l _ a d w r i t e a c k _ s s u _ a 0 a c k _ s a d r _ 0 a c k _ s a d r _ 1 a c k _ s d a t a a c k _ s d a t a a c k _ s d a t a a c k _ s d a t a a c k _ s ... . .. ... ... ... ... ... a c k _ s s t o p s ta r t s l _ a d w r i t e a c k _ s s u _ a 2 a c k _ s d a t a a c k _ s d a t a a c k _ s d a t a a c k _ s d a t a a c k _ s d a t a a c k _ s d a t a a c k _ s d a t a a c k _ s ... ... ... ... ... a c k _ s s t o p s t a r t s l _ a d w r i t e a c k _ s s u _ a 2 a c k _ s s t o p s t a r t s l _ a d r e a d d a t a a c k _ s d a t a a c k _ m d a t a a c k _ m d a t a a c k _ m d a t a a c k _ m ... ... ... ... ... ... s t o p 1
vps/pdcpro sda 5652-2x specification version 3.00 ack_m allowed!!! with the following additional abbreviations: su_a0...2: subaddress adr_1...0: addresspointer start: start condition (i2c: see technical bus description, m3l falling edge of i2cen) stop: stop condition (i2c: see technical bus description, m3l rising edge of i2cen) ack: acknowledge (i2c: see technical bus description) sl_ad: 7-bit chip select address format of the register adr_pointer (default values in brackets): adr_9...0 addressport. defines the internal memory address where data should be written or read from. only address valid ad- dresses defined in the memory map table are allowed. format of register data_port (default values in brackets): dat_7...0 dataport. this register contains the data to be transferred. each time when this register is read or written the contents of the addressport is autoincremented and not the internal subaddress. bit 7 bit 6 bit 5 b it 4 b it 3 b it 2 b it 1 b it 0 adr_pointer_1 (0) (0) (0) (0) (0) (0) adr_9 (0) adr_8 (0) adr_pointer_0 adr_7 (0) adr_6 (0) adr_5 (0) adr_4 (0) adr_3 (0) adr_2 (0) adr_1 (0) adr_0 (0) data_port d at_7 (0) dat_6 (0) dat_5 (0) dat_4 (0) dat_3 (0) dat_2 (0) dat_1 (0) dat_0 (0) bit 7 bit 6 bit 5 b it 4 b it 3 b it 2 b it 1 b it 0 data_port d at_7 (0) dat_6 (0) dat_5 (0) dat_4 (0) dat_3 (0) dat_2 (0) dat_1 (0) dat_0 (0) 1
vps/pdcpro sda 5652-2x specification version 3.00 example for data port access (beginning at address 292d (124h) the following data should be written: 11h, 12h, 13h, 14h 7.3.4 subaddresses and commands of i2c-bus 7.3.4.1 i2c-register-addresses: the above described i2c-registers can be handled with the subaddresses described below. a special function is implemented for the address 255. if this address is submitted to the ic a reset is released. protocol hex values comment chipadress,write 20h sda 5652-2x chipaddress subaddress 00h subaddress is initialized data, ack 24h 24h is transmitted to subaddress ?0 (addresspointer). the internal subaddress is autoincremented. data, ack 01h 01h is transmitted to subaddress ?1 (addresspointer) addresspointer is now set to 124h. data, ack 11h subaddress is now ?2. data is written to the dataport and then internally transferred to ram address 124h. the addresspointer is autoincremented to 125h. the subad- dress is not incremented data, ack 12h data is written to the dataport and then internally trans- ferred to ram address 125h. the addresspointer is autoin- cremented to 126h. data, ack 13h data is written to the dataport and then internally trans- ferred to ram address 126h.the addresspointer is autoin- cremented to 127h. data, ack 14h data is written to the dataport and then internally trans- ferred to ram address 127h. the addresspointer is autoin- cremented to 128h. stop i2c-address register-name read/write 0 adr_pointer_0 write 1 adr_pointer_1 write 2 data-port read/write 3 acq-control read (only bit5) / write(excluding bit5) 4-40 vps/pdc-datas read 41 synchronisation read(only osc_sys1..0)/ write 1
vps/pdcpro sda 5652-2x specification version 3.00 7.3.4.2. i2c-commands reset-command: 255d this command resets the whole ic. the protocol which has to be used is defined as follows: start: start condition (i2c: see technical bus description, m3l falling edge of i2cen) stop: stop condition (i2c: see technical bus description, m3l rising edge of i2cen) ack: acknowledge (i2c: see technical bus description) sl_ad: 7-bit chip select address (write-mode) 255: reset-command data: this data hasnt got any meaning. its only used to keep the restrictions of a protocol. 42 levels_and_change write 254 ic-identification (content:02h) read 255 reset write s t a r t s l _ a d w r i t e a c k 2 5 5 a c k d a t a a c k s t o p 1
vps/pdcpro sda 5652-2x specification version 3.00 7.3.4.3 ram-registers some register-contents are stored in the ram. these register-contents have to be accessed using the data-port of the i2c-bus: from to content 0 447 display-ram 448 484 used ic-internal 485 row_attribute/row1 486 row_attribute/row2 487 row_attribute/row3 488 row_attribute/row4 489 row_attribute/row5 490 row_attribute/row6 491 row_attribute/row7 492 row_attribute/row8 493 row_attribute/row9 494 row_attribute/row10 495 row_attribute/row11 496 row_attribute/row12 497 row_attribute/row13 498 row_attribute/row14 499 char_definition1_1/byte1 500 char_definition1_1/byte2 501 char_definition1_2/byte1 502 char_definition1_2/byte2 503 char_definition1_3/byte1 ............. ............... 507 char_definition2_1/byte1 ............. ............... 514 char_definition2_4/byte2 515 vertical_start_position 516 horizontal_start_position 517 display_control 518 border_color 519 color_value_1/luminance 520 color_value_1/v_componente 1
vps/pdcpro sda 5652-2x specification version 3.00 521 color_value_1/u_componente 522 color_value_2/luminance 523 color_value_2/v_componente 524 ........... ............. 525 color_value_4/luminance ....... color_value_4/v_componente 530 color_value_4/u_componente ............. .............. .............. ............. color_value_8/luminance ........... color_value_8/v_componente 542 color_value_8/u_componente 543 hpll 544 575 out of internal use 576 612 used internal from to content 1
vps/pdcpro sda 5652-2x specification version 3.00 8. electrical characteristics power-on-reset: after power-on a so called power-on-reset is executed. the condition for a power-on-reset is a rising vdda from a voltage value of less than 0,8v to a voltage value of at least 4,5v. absolute maximum ratings t a = 25 c parameter symbol limit values unit test condition min. max. ambient temperature t a 070 c in operation storage temperature t stg C40 125 c by storage total power dissipation p tot tbd mw power dissipation per output p dq 10 mw supply voltage v ddd v dda C0.3 C0.3 6 6 v v thermal resistance r th su 80 k/w operating range supply voltage v ddd v dda 4.5 4.5 5.5 5.5 v v supply current i dd 35 50 ma ambient temperature range t a 070 c characteristics t a = 25 c parameter symbol limit values unit test condition min. max. input signals sda, scl h-input voltage v ih 0.7x v ddd v ddd v l-input voltage v il 00.3x v ddd v input capacitance c i 10 pf input current i im 10 m a input signal tmode h-input voltage v ih 0.9x v ddd v ddd v l-input voltage v il 00.1x v ddd v input capacitance c i 10 pf input current i im 10 m a 1
vps/pdcpro sda 5652-2x specification version 3.00 characteristics (contd) t a = 25 c parameter symbol limit values unit test condition min. max. input signal cvbs/output signal mixed mode: synchron signal amplitude (bottom) v sync 0.7 0.9 v black-porch-level v porch 1.3 1.5 v resistance of the switch between input and output-signal in mixed mode: <50 ohm output signal cvbs in full page mode: supplyvoltage is used as reference for d/a-converter. so the stability of voltage-values for the output signal depend on the supplyvoltage stability. min-values are related to a supplyvoltage of 4,5v and max-values are related to a supplyvoltage of 5,5v. 100% - white level v cvbs 2.6 3.2 v synchron signal amplitude (bottom) v sync 0.7 0.9 v color burst low v burstl 1.0(ntsc) 1.1(pal) 1.2(ntsc) 1.3(pal) v color burst high v bursth 1.6(ntsc) 1.5(pal) 1.9(ntsc) 1.8(pal) v black-porch-level v porch 1.3 1.6 v input signal cvbs_slicer : video input signal level peak to peak v cvbs 0.7 2.0 v synchron signal amplitude peak to peak v sync 0.15 1.0 v vdat=450mv data amplitude peak to peak v dat 0.25 1.0 v vsync=300mv 1
vps/pdcpro sda 5652-2x specification version 3.00 output signals sda (open-drain-stage) l-output voltage v ql 0.4 v i q =3.0ma permissible output voltage 5.5 v open-drain-resistance (sda) r sda 1.7 2.2 k w max. 200pf load capacity open-drain-resistance (scl) r scl 1.7 2.2 k w max. 200pf load capacity pll-loop filter components resistance at pd1/vco1 r 2.2 4.7 k w resistance at pd2/vco2 r 2.2 4.7 k w capacitor at pd1/vco1 c 68 220 nf capacitor at pd2/vco2 c 2,2 100 nf vco C frequence range adjustment resistance at iref (for bias current adjustment) r 4 68+/-5% k w t a = 25 c parameter symbol limit values unit test condition min. max. . . . . . . . . . . . . . . . . . . 1,43 0,8 1,12 1,75 2,9 vsync vburstl vbursth v cvbs vporch 1
vps/pdcpro sda 5652-2x specification version 3.00 i nput signal composite/horizontal/vertical-sync secam-bypass - bandpass filter fscin (1x/2x/4x) clamp components on input cvbs-slicer crystal-oscillator-capacitances : h-input voltage v synch 0.6x v ddd v ddd v l-input voltage v syncl 00.2x v ddd v coil at cvbs_out l 1 10 uh capacitor at secam-bypass c 2 120 pf amplitude of fscin-signal peak to peak a(f sc ) 250 550 mv coupling capacitor c 1 100 nf capacitor c 330 1000 nf resistance r 220 270 kohm capacitor c 27 pf crystal-impedance r 30 ohm 1
vps/pdcpro sda 5652-2x specification version 3.00 environment for a system with 1fsc, 2fsc or 4fsc as external system-clock : environment for a system with a crystal-oscillator as system-clock: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 vssa vssd scl sda vdda vddd cvbs_in cvbs_slicer iref halftone_blank pd2/vco2 cvbs_out pd1/vco1 secam_by 10uh 120pf 100nf 3.3kohm 3.3kohm 68nf 470nf 270kohm 68kohm 100nf(keramik) 100nf(keramik) 1.7kohm 1.7kohm vssd 100nf 1nf - 1uf sync2 sync1 davn/ehb 0nf-10nf 100kohm 0-15pf 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 vssa vssd scl sda vdda vddd cvbs_in cvbs_slicer iref halftone_blank pd2/vco2 cvbs_out pd1/vco1 secam_by 10uh 120pf 100nf 3.3kohm 3.3kohm 68nf 470nf 270kohm 68kohm 100nf(keramik) 100nf(keramik) 1.7kohm1.7kohm vssd 100nf tbd pf tbd pf 2fsc crystal sync2 sync1 davn/ehb 1
vps/pdcpro sda 5652-2x specification version 3.00 environment for a system with 2fsc as external system-clock in oscillator-mode 11: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 vssa vssd scl sda vdda vddd cvbs_in cvbs_slicer iref halftone_blank pd2/vco2 cvbs_out pd1/vco1 secam_by 10uh 120pf 100nf 3.3kohm 3.3kohm 68nf 470nf 270kohm 68kohm 100nf(keramik) 100nf(keramik) 1.7kohm 1.7kohm vssd 100nf 1nf - 1uf sync2 sync1 davn/ehb 0nf-10nf 0-15pf 1
vps/pdcpro sda 5652-2x specification version 3.00 9. character-rom in the character-rom the shape of the characters is defined. 128 characters are stored in the rom. each character has got a structure ot 12columnsx18lines: the pixel-structur of the characters shown in the figure above refer to character-adresses shown in the table below: 79 49 50 51 52 53 54 55 56 57 45 58 47 46 44 39 65 66 67 68 69 70 71 72 73 74 75 76 77 78 80 81 82 83 84 85 86 87 88 89 90 40 41 42 43 48 37 38 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 59 60 61 62 63 64 117 118 119 120 121 122 123 124 125 126 127 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 33 34 35 36 32 1
vps/pdcpro sda 5652-2x specification version 3.00 10. application notes 10.1. after reset starting sequenz after reset a maximum-time of 50us is needed in which the ic initializes itself. after this time, the following registers are set to their default-values: adr_pointer_0, adr_pointer_1, data_port, acq-control synchronisation and levels_and_change. all the other register-values are set to random-values and must be initialized with iic-bus. 1
vps/pdcpro sda 5652-2x specification version 3.00 after the time of 50us, the first iic-access can be executed. within the first iic-bus-accesses the following procedure should be carried out: procedure 1: the register-bits osc_sys0 and osc_sys1 of the register synchronisation have to be set to the values according the used external clock-source (1fsc, 2fsc, 4fsc or crys- tal). procedure 2: the bits osc_sys0 and osc_sys1 are read and compared to the expected values which have been written in procedure 1. by this it is assured, that there has been no transmission- error to the ic. if there has been no transmission error please go on with procedure 3 otherwise please go back to procedure 1. procedure 3: setting bit release of register levels_and_change from high to low. this will initial- ize the internal clock-generation-circuits according to the settings of the bits osc_sys0 and osc_sys1. if once register-bit release ist set to 0 it cannot be set to 1 anymore. setting bit iic_switch of register synchronisation from high to low. this will assure highest iic-bus noise-surpressing. 1
vps/pdcpro sda 5652-2x specification version 3.00 11. errata sheet hardware items item no. bug desig- nation description affected version correction schedule h1 wrong horizon- tal start-posi- tion of character-fields using zoom the position of the characters of a row may be shifted to the left in dependency on: -horizontal zoom-factor of the 1st character in the zoomed row -k = modulo of the start-position of the character- field the dependencies are shown in the following table below (clocks = nr. of clocks by which the charac- ters are moved to the left; pixel = nr. of pixels by which the characters are moved to the left; pixel- frequency is half the clock-frequency): b23 tbd item no. bug desig- nation description affected version correction schedule h2 no display if horizontal start- position>118 if the horizontal start-position of the character-field is larger than 118, the character-field will vanish at all and there is an unexpected line at the beginning of the character-field. uncritical for most applications, because such large horizontal start-positions arent choosen in practise. b23 tbd h3 no display of row 14 at large vertical start- position if the vertical start-position of the character-field is >100, row 14 will vanish. as for those large vertical start-positions row 14 shouldnt be visible on the screen of a normal tv-set at all, this should be uncritical for all applications. b23 tbd zoom k clocks pixel clocks pixel clocks pixel clocks pixel 012 3 0 0 0 0 0 0 0 0 0 2 2 2 0 1 1 1 0 0 4 4 0 0 2 2 0 2 4 6 0 1 2 3 1 2 3 4 1
vps/pdcpro sda 5652-2x specification version 3.00 h4 row 8 at verti- cal zoom-factor 4 if in row 8 zoom-factor 4 is used (and this row is visible on the screen), the next character-row will allready start at row 11 (instead of 12). moreover row 14 will fail at all. b23 tbd h5 pdc-format1 byte 13 byte 13 in pdc-mode format 8-30-1 is falsely par- ity checked (e.g. the msb is set to 1, if byte 13 hasnt odd parity, else 0). b23 tbd h6 forbidden verti- cal and horizon- tal start- positions of the character-field the following vertical and horizontal start-positions are not allowed to use (due to different failures like an offset according to the expected start-position): 1. forbidden positions in fullpage-mode: vpos = 0..16 hpos = 0; hpos != k*4; hpos >=116 2. forbidden positions in mixed-mode: vpos = 0.. 19; vpos >100 hpos = 0; hpos != k*4; >=120 b23 tbd item no. bug desig- nation description affected version correction schedule 1
software/firmware items (optional) item no. bug desig- nation description affected version correc- tion sched- ule 1
software/firmware items (optional) item no. workaround description h5 following algorithm can be used as a workaround for item-no.h5: case msb(byte13) is 1: if byte13 (6:0) = even parity then msb(byte13):=0; else msb(byte13):=1; end if; 0: if byte13 (6:0) = even parity then msb(byte13):=1; else msb(byte13):=0; end if; end case; 4 5
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