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preliminary rev 4.0 k7p801811b 256kx36 & 512kx18 sram k7p803611b aug. 2002 - 1 - document title 256kx36 & 512kx18 synchronous pipelined sram the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions on the parameters of this device. if you have any questions, please contact the samsung branch office near your office, call or cortact headquart ers. revision history rev. no. rev. 0.0 rev. 1.0 rev. 2.0 rev. 3.0 rev. 4.0 remark preliminary final final final final history - initial document. - final specification release - absolute maximum rating vddq changed from 2.825v to 2.4v. - function description modified - add -hc27 part (part number, idd, ac characteristics) draft date feb. 2001 may. 2001 jan. 2002 mar. 2002 aug. 2002
preliminary rev 4.0 k7p801811b 256kx36 & 512kx18 sram k7p803611b aug. 2002 - 2 - pin description pin name pin description pin name pin description k, k differential clocks zz asynchronous power down san synchronous address input zq output driver impedance control dqn bi-directional data bus tck jtag test clock ss synchronous select tms jtag test mode select sw synchronous global write enable tdi jtag test data input sw a synchronous byte a write enable tdo jtag test data output sw b synchronous byte b write enable v ref hstl input reference voltage sw c synchronous byte c write enable v dd power supply sw d synchronous byte d write enable v ddq output power supply m 1 , m 2 read protocol mode pins (m 1 =v ss , m 2 =v ddq ) v ss gnd g asynchronous output enable nc no connection 256kx36 & 512kx18 synchronous pipelined sram features functional block diagram 18 or 19 k, k ss g memory array 256kx36 data out data in s/a array mux0 w/d array 36 or 18 36 or 18 36 or 18 36 or 18 2:1 mux dec. sa[0:17] address register read sw zz internal clock generator write address register data out register clock buffer control register dq 36 or 18 36 or 18 36 or 18 36 or 18 xdin data in register (2 stage) 18 or 19 control logic e way oe 36 or 18 or [0:18] 512kx18 organization part number maximum frequency access time 256kx36 k7p803611b-hc33 333mhz 1.5 k7p803611b-hc30 300mhz 1.6 k7p803611b-hc27 250mhz 1.85 k7p803611b-hc25 250mhz 2.0 512kx18 k7p801811b-hc33 333mhz 1.5 k7p801811b-hc30 300mhz 1.6 K7P801811B-HC27 300mhz 1.85 k7p801811b-hc25 250mhz 2.0 ? 256kx36 or 512kx18 organizations. ? 3.3v v dd /1.5v v ddq (2.0v max v ddq ). ? hstl input and output levels. ? differential, hstl clock inputs k, k . ? synchronous read and write operation ? registered input and registered output ? internal pipeline latches to support late write. ? byte write capability(four byte write selects, one for each 9bits) ? synchronous or asynchronous output e nable. ? power down mode via zz signal. ? programmable impedance output drivers. ? jtag boundary scan (subset of ieee std. 1149.1). ? 119(7x17)pin ball grid array package(14mmx22mm).
preliminary rev 4.0 k7p801811b 256kx36 & 512kx18 sram k7p803611b aug. 2002 - 3 - package pin configurations (top view) k7p803611b(256kx36) 1 2 3 4 5 6 7 a v ddq sa 13 sa 10 nc sa 7 sa 4 v ddq b nc nc sa 9 nc sa 8 sa 17 nc c nc sa 12 sa 11 v dd sa 6 sa 5 nc d dqc 8 dqc 9 v ss zq v ss dqb 9 dqb 8 e dqc 6 dqc 7 v ss ss v ss dqb 7 dqb 6 f v ddq dqc 5 v ss g v ss dqb 5 v ddq g dqc 3 dqc 4 sw c nc sw b dqb 4 dqb 3 h dqc 1 dqc 2 v ss nc v ss dqb 2 dqb 1 j v ddq v dd v ref v dd v ref v dd v ddq k dqd 1 dqd 2 v ss k v ss dqa 2 dqa 1 l dqd 3 dqd 4 sw d k sw a dqa 4 dqa 3 m v ddq dqd 5 v ss sw v ss dqa 5 v ddq n dqd 6 dqd 7 v ss sa 0 v ss dqa 7 dqa 6 p dqd 8 dqd 9 v ss sa 1 v ss dqa 9 dqa 8 r nc sa 15 m 1 v dd m 2 sa 2 nc t nc nc sa 14 sa 16 sa 3 nc zz u v ddq tms tdi tck tdo nc v ddq k7p801811b(512kx18) 1 2 3 4 5 6 7 a v ddq sa 13 sa 10 nc sa 7 sa 4 v ddq b nc nc sa 9 nc sa 8 sa 17 nc c nc sa 12 sa 11 v dd sa 6 sa 5 nc d dqb 1 nc v ss zq v ss dqa 9 nc e nc dqb 2 v ss ss v ss nc dqa 8 f v ddq nc v ss g v ss dqa 7 v ddq g nc dqb 3 sw b nc nc nc dqa 6 h dqb 4 nc v ss nc v ss dqa 5 nc j v ddq v dd v ref v dd v ref v dd v ddq k nc dqb 5 v ss k v ss nc dqa 4 l dqb 6 nc nc k sw a dqa 3 nc m v ddq dqb 7 v ss sw v ss nc v ddq n dqb 8 nc v ss sa 0 v ss dqa 2 nc p nc dqb 9 v ss sa 1 v ss nc dqa 1 r nc sa 15 m 1 v dd m 2 sa 2 nc t nc sa 18 sa 14 nc sa 3 sa 16 zz u v ddq tms tdi tck tdo nc v ddq
preliminary rev 4.0 k7p801811b 256kx36 & 512kx18 sram k7p803611b aug. 2002 - 4 - function description the k7p803611b and k7p801811b are 9,437,184 bit synchronous pipeline burst mode sram devices. they are organized as 262,144 words by 36 bits for k7p803611b and 524,288 words by 18 bits for k7p801811b, fabricated using samsung's advanced cmos technology. single differential hstl level k clocks are used to initiate read/write operation and all internal operations are self-timed. at the rising edge of k clock, addresses, write enables, synchronous select and data ins are registered internally. data outs are updated from output registers at the next rising edge of k clock. an internal write data buffer allows write data to follow one cycle after a ddresses and controls. the package is 119(7x17) ball grid array with balls on a 1.27mm pitch. read operation during read operations, addresses and controls are registered during the first rising edge of k clock and then the internal arra y is read between first and second edges of k clock. data outputs are updated from output registers off the second rising edge of k c lock. during consecutive read operations where the address is the same, the data output must be held constant without any glitches. th is characteristic is because the sram will be read by devices that will operate slower than the sram frequency and will require mul ti- ple sram cycles to perform a single read operation. mode control there are two mode control select pins (m 1 and m 2 ) used to set the proper read protocol. this sram supports single clock pipelined operating mode. for proper specified device operation, m 1 must be connected to v ss and m 2 must be connected to v ddq . these mode pins must be set at power-up and must not change during device operation. power-up/power-down supply voltage sequencing the following power-up supply voltage application is recommended: v ss , v dd , v ddq , v ref , then v in . v dd and v ddq can be applied simultaneously, as long as v ddq does not exceed v dd by more than 0.5v during power-up. the following power-down supply voltage removal sequence is recommended: v in , v ref , v ddq , v dd , v ss . v dd and v ddq can be removed simultaneously, as long as v ddq does not exceed v dd by more than 0.5v during power-down. sleep mode sleep mode is a low power mode initiated by bringing the asynchronous zz pin high. during sleep mode, all other inputs are ignor ed and outputs are brought to a high-impedance state. sleep mode current and output high-z are guaranteed after the specified sleep mode enable time. during sleep mode the memory array data content is preserved. sleep mode must not be initiated until after all pending operations have completed, since any pending operation will not guaranteed once sleep mode is initiated. normal opera- tions can be resumed by bringing the zz pin low, but only after the specified sleep mode recovery time. bypass read operation bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are identical. for this case, data outputs are from the data in registers instead of sram array. bypass read operation occurs on a b yte to byte basis. if only one byte is written during a write operation but a read operation is required on the same address, a partial bypass read operation occurs since the new byte data is from the data in registers while the remaing bytes are from sram arry. write operation(late write) during write operations, addresses and controls are registered at the first rising edge of k clock and data inputs are registere d at the following rising edge of k clock. write addresses and data inputs are stored in the data in registers until the next write opera tion, and only at the next write opeation are data inputs fully written into sram array. byte write operation is supported using sw[ a:d] and the timing of sw[ a:d] is the same as the sw signal. programmable impedance output driver the data output driver impedance is adjusted by an external resistor, rq, connected between zq pin and v ss , and is equal to rq/5. for example, 250 w resistor will give an output impedance of 50 w . output driver impedance tolerance is 15% by test(10% by design) and is periodically readjusted to reflect the changes in supply voltage and temperature. impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles. they may also occur in cycles initiated with g high. in all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the sram. imped- ance updates occur no more often than every 32 clock cycles. clock cycles are counted whether the sram is selected or not and proceed regardless of the type of cycle being executed. therefore, the user can be assured that after 33 continuous read cycles have occurred, an impedance update will occur the next time g are high at a rising edge of the k clock. there are no power up requirements for the sram. however, to guarantee optimum output driver impedance after power up, the sram needs 1024 non- read cycles. the output buffers can also be programmed in a minimum impedance configuration by connecting zq to v ss or v ddq .
preliminary rev 4.0 k7p801811b 256kx36 & 512kx18 sram k7p803611b aug. 2002 - 5 - truth table note : k & k are complementary k zz g ss sw sw a sw b sw c sw d dqa dqb dqc dqd operation x h x x x x x x x hi-z hi-z hi-z hi-z power down mode. no operation x l h x x x x x x hi-z hi-z hi-z hi-z output disabled. - l l h x x x x x hi-z hi-z hi-z hi-z output disabled. no operation - l l l h x x x x d out d out d out d out read cycle - l x l l h h h h hi-z hi-z hi-z hi-z no bytes written - l x l l l h h h d in hi-z hi-z hi-z write first byte - l x l l h l h h hi-z d in hi-z hi-z write second byte - l x l l h h l h hi-z hi-z d in hi-z write third byte - l x l l h h h l hi-z hi-z hi-z d in write fourth byte - l x l l l l l l d in d in d in d in write all bytes recommended dc operating conditions parameter symbol min typ max unit note core power supply voltage v dd 3.15 3.3 3.45 v output power supply voltage v ddq 1.4 1.5 2.0 v input high level v ih v ref +0.1 - v ddq +0.3 v input low level v il -0.3 - v ref -0.1 v input reference voltage v ref 0.68 0.75 1.0 v clock input signal voltage v in -clk -0.3 - v ddq +0.3 v clock input differential voltage v dif -clk 0.1 - v ddq +0.3 v clock input common mode voltage v cm -clk 0.68 0.75 1.0 v absolute maximum ratings note : power dissipation capability will be dependent upon package characteristics and use environment. see enclosed thermal impedan ce data. stresses greater than those listed under " absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol value unit core supply voltage relative to v ss v dd -0.5 to 3.9 v output supply voltage relative to v ss v ddq -0.5 to 2.4 v voltage on any pin relative to v ss v in -0.5 to v ddq +0.5 (2.4v max ) v output short-circuit current(per i/o) i out 25 ma storage temperature t str -55 to 125 c
preliminary rev 4.0 k7p801811b 256kx36 & 512kx18 sram k7p803611b aug. 2002 - 6 - dc characteristics note :1. minimum cycle. i out =0ma. 2. 50% read cycles. 3. |i oh |=(v ddq /2)/(rq/5) 15% @v oh =v ddq /2 for 175 w rq 350 w . 4. |i ol |=(v ddq /2)/(rq/5) 15% @v ol =v ddq /2 for 175 w rq 350 w . 5. programmable impedance output buffer mode. the zq pin is connected to v ss through rq. 6. minimum impedance output buffer mode. the zq pin is connected to v ss or v ddq . parameter symbol min max unit note average power supply operating current-x36 (v in =v ih or v il , zz & ss =v il ) i dd33 i dd30 i dd27 i dd25 - 700 620 580 550 ma 1, 2 average power supply operating current-x18 (v in =v ih or v il , zz & ss =v il ) i dd33 i dd30 i dd27 i dd25 - 650 570 530 500 ma 1, 2 power supply standby current (v in =v ih or v il , zz=v ih ) i sbzz - 70 ma 1 active standby power supply current (v in =v ih or v il , ss =v ih , zz=v il ) i sbss - 200 ma 1 input leakage current (v in =v ss or v ddq ) i li -1 1 m a output leakage current (v out =v ss or v ddq , dq in high-z) i lo -1 1 m a output high voltage(programmable impedance mode) v oh1 v ddq /2 v ddq v 3,5 output low voltage(programmable impedance mode) v ol1 v ss v ddq /2 v 4,5 output high voltage(i oh =-0.1ma) v oh2 v ddq -0.2 v ddq v 6 output low voltage(i ol =0.1ma) v ol2 v ss 0.2 v 6 output high voltage(i oh =-6ma) v oh3 v ddq -0.4 v ddq v 6 output low voltage(i ol =6ma) v ol3 v ss 0.4 v 6 pin capacitance note : periodically sampled and not 100% tested.(t a =25 c , f=1mhz) parameter symbol test condition min max unit input capacitance c in v in =0v - 4 pf data output capacitance c out v out =0v - 5 pf
preliminary rev 4.0 k7p801811b 256kx36 & 512kx18 sram k7p803611b aug. 2002 - 7 - ac test conditions (t a =0 to 70 c , v dd =3.15~3.45v, v ddq =1.5v) note : parameters are tested with rq=250 w and v ddq =1.5v. parameter symbol value unit core power supply voltage v dd 3.15~3.45 v output power supply voltage v ddq 1.5 v input high/low level v ih /v il 1.25/0.25 v input reference level v ref 0.75 v input rise/fall time t r /t f 0.5/0.5 ns input and out timing reference level 0.75 v clock input timing reference level cross point v 50 w 50 w ac test output load 25 w 5 pf dq v ddq /2 5 pf v ddq /2 50 w 50 w vddq/2 ac characteristics parameter symbol -33 -30 -27 -25 unit note min max min max min max min max clock cycle time t khkh 3.0 - 3.3 - 3.65 - 4.0 - ns clock high pulse width t khkl 1.2 - 1.3 - 1.5 - 1.6 - ns clock low pulse width t klkh 1.2 - 1.3 - 1.5 - 1.6 - ns clock high to output valid t khqv - 1.5 - 1.6 - 1.85 - 2.0 ns clock high to output hold t khqx 0.5 - 0.5 - 0.5 - 0.5 - ns address setup time t avkh 0.4 - 0.4 - 0.4 - 0.4 - ns address hold time t khax 0.5 - 0.6 - 0.7 - 0.7 - ns write data setup time t dvkh 0.4 - 0.4 - 0.4 - 0.4 - ns write data hold time t khdx 0.5 - 0.6 - 0.7 - 0.7 - ns sw , sw [a:d] setup time t wvkh 0.4 - 0.4 - 0.4 - 0.4 - ns sw , sw [a:d] hold time t khwx 0.5 - 0.6 - 0.7 - 0.7 - ns ss setup time t svkh 0.4 - 0.4 - 0.4 - 0.4 - ns ss hold time t khsx 0.5 - 0.6 - 0.7 - 0.7 - ns clock high to output hi-z t khqz - 1.5 - 1.6 - 1.85 - 2.0 ns clock high to output low-z t khqx1 0.5 - 0.5 - 0.5 - 0.5 - ns g high to output high-z t ghqz - 1.5 - 1.6 - 1.85 - 2.0 ns g low to output low-z t glqx 0.5 - 0.5 - 0.5 - 0.5 - ns g low to output valid t glqv - 1.5 - 1.6 - 1.85 - 2.0 ns zz high to power down(sleep time) t zze - 15 - 15 - 15 - 15 ns zz low to recovery(wake-up time) t zzr - 20 - 20 - 20 - 20 ns
preliminary rev 4.0 k7p801811b 256kx36 & 512kx18 sram k7p803611b aug. 2002 - 8 - timing waveforms of normal active cycles ( ss controlled, g =low) 1 2 3 4 5 6 7 8 k san ss sw sw x dqn note 1. d 3 is the input data written in memory location a 3 . 2. q 4 is the output data read from the write data buffer(not from the cell array), as a result of address a 4 being a match from the last write cycle address. a 1 a 2 a 3 a 4 a 5 a 4 a 6 a 7 q 1 d 3 d 4 q 5 q 4 timing waveforms of normal active cycles ( g controlled, ss =low) 1 2 3 4 5 6 7 8 k san g sw sw x dqn note 1. d 3 is the input data written in memory location a 3 . 2. q 4 is the output data read from the write data buffer(not from the cell array), as a result of address a4 being a match from the l ast write cycle address. a 1 a 2 a 3 a 4 a 5 a 4 a 6 a 7 q 2 q 1 d 3 d 4 q 5 q 4 q 2 t khkh t khax t avkh t khkl t klkh t khsx t svkh t wvkh t khwx t wvkh t khwx t khqx1 t khqx t wvkh t khwx t khqv t khdx t khqz t dvkh t khdx t khkh t ghqz t glqx t glqv
preliminary rev 4.0 k7p801811b 256kx36 & 512kx18 sram k7p803611b aug. 2002 - 9 - timing waveforms of standby cycles 1 2 3 4 5 6 7 8 k san ss sw sw x dqn zz a 2 a 1 a 2 a 3 q 1 q 2 q 1 a 1 t khkh t zze t zzr t khqv t khqv
preliminary rev 4.0 k7p801811b 256kx36 & 512kx18 sram k7p803611b aug. 2002 - 10 jtag instruction coding note : 1. places dqs in hi-z in order to sample all input data regardless of other sram inputs. 2. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 3. bypass register is initiated to v ss when bypass instruction is invoked. the bypass register also holds serially loaded tdi when exiting the shift dr states. 4. sample instruction does not places dqs in hi-z. ir2 ir1 ir0 instruction tdo output notes 0 0 0 sample-z boundary scan register 1 0 0 1 idcode identification register 2 0 1 0 sample-z boundary scan register 1 0 1 1 bypass bypass register 3 1 0 0 sample boundary scan register 4 1 0 1 bypass bypass register 3 1 1 0 bypass bypass register 3 1 1 1 bypass bypass register 3 ieee 1149.1 test access port and boundary scan-jtag tap controller state diagram jtag block diagram sram core bypass reg. identification reg. instruction reg. control signals tap controller tdo m 2 m 1 tdi tms tck test logic reset run test idle 0 1 1 1 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir 1 1 1 1 1 the sram provides a limited set of ieee standard 1149.1 jtag functions. this is to test the connectivity during manufacturing between sram, printed circuit board and other components. internal data is not driven out of sram under jtag control. in conform - ance with ieee 1149.1, the sram contains a tap controller, instruction register, bypass register and id register. the tap contro l- ler has a standard 16-state machine that resets internally upon power-up, therefore, trst signal is not required. it is possible to use this device without utilizing the tap. to disable the tap controller without interfacing with normal operation of the sram, tck must be tied to v ss to preclude mid level input. tms and tdi are designed so an undriven input will produce a response identical to the application of a logic 1, and therefore can be left unconnected. but they may also be tied to v dd through a resistor. tdo should be left unconnected.
preliminary rev 4.0 k7p801811b 256kx36 & 512kx18 sram k7p803611b aug. 2002 - 11 scan register definition part instruction register bypass register id register boundary scan 256kx36 3 bits 1 bits 32 bits 70 bits 512kx18 3 bits 1 bits 32 bits 51 bits id register definition part revision number (31:28) part configuration (27:18) vendor definition (17:12) samsung jedec code (11: 1) start bit(0) 256kx36 0000 00110 00100 xxxxxx 00001001110 1 512kx18 0000 00111 00011 xxxxxx 00001001110 1 boundary scan exit order(x36) 36 3b sa 9 sa 8 5b 35 37 2b nc sa 17 6b 34 38 3a sa 10 sa 7 5a 33 39 3c sa 11 sa 6 5c 32 40 2c sa 12 sa 5 6c 31 41 2a sa 13 sa 4 6a 30 42 2d dqc 9 dqb 9 6d 29 43 1d dqc 8 dqb 8 7d 28 44 2e dqc 7 dqb 7 6e 27 45 1e dqc 6 dqb 6 7e 26 46 2f dqc 5 dqb 5 6f 25 47 2g dqc 4 dqb 4 6g 24 48 1g dqc 3 dqb 3 7g 23 49 2h dqc 2 dqb 2 6h 22 50 1h dqc 1 dqb 1 7h 21 51 3g sw c sw b 5g 20 52 4d zq g 4f 19 53 4e ss k 4k 18 54 4g nc k 4l 17 55 4h nc sw a 5l 16 56 4m sw dqa 1 7k 15 57 3l sw d dqa 2 6k 14 58 1k dqd 1 dqa 3 7l 13 59 2k dqd 2 dqa 4 6l 12 60 1l dqd 3 dqa 5 6m 11 61 2l dqd 4 dqa 6 7n 10 62 2m dqd 5 dqa 7 6n 9 63 1n dqd 6 dqa 8 7p 8 64 2n dqd 7 dqa 9 6p 7 65 1p dqd 8 zz 7t 6 66 2p dqd 9 sa 3 5t 5 67 3t sa 14 sa 2 6r 4 68 2r sa 15 sa 16 4t 3 69 4n sa 0 sa 1 4p 2 70 3r m 1 m 2 5r 1 boundary scan exit order(x18) 26 3b sa 9 sa 8 5b 25 27 2b nc sa 17 6b 24 28 3a sa 10 sa 7 5a 23 29 3c sa 11 sa 6 5c 22 30 2c sa 12 sa 5 6c 21 31 2a sa 13 sa 4 6a 20 dqa 9 6d 19 32 1d dqb 1 33 2e dqb 2 dqa 8 7e 18 dqa 7 6f 17 34 2g dqb 3 dqa 6 7g 16 dqa 5 6h 15 35 1h dqb 4 36 3g sw b 37 4d zq g 4f 14 38 4e ss k 4k 13 39 4g nc k 4l 12 40 4h nc sw a 5l 11 41 4m sw dqa 4 7k 10 42 2k dqb 5 dqa 3 6l 9 43 1l dqb 6 44 2m dqb 7 dqa 2 6n 8 45 1n dqb 8 dqa 1 7p 7 zz 7t 6 46 2p dqb 9 sa 3 5t 5 47 3t sa 14 sa 2 6r 4 48 2r sa 15 49 4n sa 0 sa 1 4p 3 50 2t sa 18 sa 16 6t 2 51 3r m 1 m 2 5r 1 note : 1. pin 2b is a no connection pin to internal chip. this pin is a place holder for 16m part and the scanned data is fixed to "0" for this 8m part. 2. pins 4g and 4h are no connection pin to internal chip. the scanned data are fixed to "0" and "1" respectively.
preliminary rev 4.0 k7p801811b 256kx36 & 512kx18 sram k7p803611b aug. 2002 - 12 jtag dc operating conditions note : 1. the input level of sram pin is to follow the sram dc specification . parameter symbol min typ max unit note power supply voltage v dd 3.15 3.3 3.45 v input high level v ih 1.7 - v dd +0.3 v input low level v il -0.3 - 0.8 v output high voltage(i oh =-2ma) v oh 2.1 - v dd v output low voltage(i ol =2ma) v ol v ss - 0.2 v jtag timing diagram jtag ac characteristics parameter symbol min max unit note tck cycle time t chch 50 - ns tck high pulse width t chcl 20 - ns tck low pulse width t clch 20 - ns tms input setup time t mvch 5 - ns tms input hold time t chmx 5 - ns tdi input setup time t dvch 5 - ns tdi input hold time t chdx 5 - ns sram input setup time t svch 5 - ns sram input hold time t chsx 5 - ns clock low to output valid t clqv 0 10 ns jtag ac test conditions note : 1. see sram ac test output load on page 7. parameter symbol min unit note input high/low level v ih /v il 2.5/0.0 v input rise/fall time tr/tf 1.0/1.0 ns input and output timing reference level 1.25 v 1 tck tms tdi pi t chch t mvch t chmx t chcl t clch t dvch t chdx t clqv tdo (sram) t svch t chsx
preliminary rev 4.0 k7p801811b 256kx36 & 512kx18 sram k7p803611b aug. 2002 - 13 119 bga package dimensions 0.750 0.15 1.27 1.27 12.50 0.10 0.60 0.10 0.60 0.10 1.50ref c1.00 c0.70 14.00 0.10 22.00 0.10 20.50 0.10 note : 1. all dimensions are in millimeters. 2. solder ball to pcb offset : 0.10 max. 3. pcb to cavity offset : 0.10 max. indicator of ball(1a) location 119 bga package thermal characteristics note : 1. junction temperature can be calculated by : t j = t a + p d x theta_ja. parameter symbol thermal resistance unit note junction to ambient(at still air) theta_ja 30.2 c /w 1w heating junction to case theta_jc 5.9 c /w junction to solder ball theta_jb 4.8 c /w 2w heating

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