imisg501 system clock chip march 1996 reduced emi clock generator international microcircuits, inc. 525 los coches st. milpitas, ca 95035 tel: 408-263-6300 fax 408-263-6571 page 1 of 8 product features t generates cpu clock signals for microprocessor systems t reduces measured emi by 10 db nominal t 4v to 7v operating supply range t supports 80286-, 80386-, 80486-, pentium ? - and 29000-based designs t wide range of selectable output frequencies including 50, 25, 20 and 10 mhz t single, low cost crystal used as reference frequency t glitch-free switching t 50% duty cycle t power down mode for low power consumption t ttl or cmos compatible outputs with 6ma drive capability t low, short- and long-term jitter t 16 pdip and 16 pin soic (300 mil body) package options block diagram spectrum spread clock gen ref /4 or /12 /2 prclk mpclk 44.2 mhz mpsel lf s0 s1 test sson 9 16 8 7 10 5 2 3 14 12 product description the imisg501 is a spectrum spread clock generator specially designed for personal computers, laser printers and other digital systems. imisg501 uses a patent pending concept to generate popular clock frequencies that are intentionally broadbanded to reduce electromagnetic interference. imisg501 attenuates the radiated emission amplitudes from products associated with either the clock harmonics or any signals derived from the clock signals nominally 10 db and could significantly reduce the cost of complying with the regulatory requirements. prclk is the broadbanded output and can be programmed to generate 50, 25, 20 and 10 mhz with s0 and s1 pins. a single, low cost external crystal is required as reference frequency for the synthesizer. output modulation function can be turned off with the sson pin. several power down modes add the flexibility to operate the device in a completely static mode to reduce standby currents and simplify system board tests. pdip/soic connection diagram applications imisg501 eliminates the need for multiple oscillators and generates the cpu clock signals for personal computers, laser printers and other digital systems. supports 8086-, 80286-, 80386-, 80486-, pentium ? - and 29000-based designs. imisg501 can be used with laptop or notebook computers to save power by running the system slower than normal cpu speeds or completely disabling the clocks in standby mode. vdd oscin oscout vss mpsel avdd s0 s1 test vdd mpclk vss prclk avss lf1 sson patent pending 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
imisg501 system clock chip march 1996 reduced emi clock generator international microcircuits, inc. 525 los coches st. milpitas, ca 95035 tel: 408-263-6300 fax 408-263-6571 page 2 of 8 pin description oscin, oscout - these pins form an on-chip reference oscillator when connected to terminals of an external 44.2 mhz third overtone parallel resonant crystal. oscin may also serve as an input for an externally generated cmos level or ac coupled reference signal. s0, and s1 - frequency select inputs. these inputs control the prclk frequency selection. s0-s1 inputs control the cpu clock frequencies. all these inputs have internal pull-downs. table 1 shows the output freuqncy selection conditions. test - controls power down and test mode selection. when high, s0-s1 and mpsel controls the mode selection as shown on table 1 and table 2. when low, device operates in normal mode. this pin has an internal pull-down. mpsel - controls mpclk output frequency selections. table 2 shows the selected frequencies for mpclk. this input has an internal pull-up. sson - this pin controls the sprectrum spread function. when low, prclk is modulated. when high, spreading is turned off. this pin has an internal pull-up. lf1 - this is the control output for the clock generator. it is a single-ended, tri-state output. component connections are shown in figure 1. prclk frequency selection inputs output test s1 s0 prclk 0 0 0 9.96 mhz 0 0 1 19.92 mhz 0 1 0 24.9 mhz 0 1 1 49.80 mhz 1 0 0 0; power down 1 0 1 1; power down 1 1 0 test 1 1 1 hi-z table 1 : when power down address is slected, the vco is turned off and the device goes to standby mode. phase detector is in tri-state mode. mpclk - this is a nonmodulated output. this output can be programmed to be 3.7 mhz or 11.06 mhz. the selection of these frequencies are controlled by the mpsel pin shown in table 1. prclk - output from the spectrum spread clock generator. frequency selection is shown on table 1. when the sson pin is high, outputs are not modulated. when sson is low, sprectrum spread function is enabled. vss - circuit ground vdd - positive power supply avss - analog circuit ground avdd - analog positive power supply figure 1 mpclk frequency selection inputs output test mpsel s1 s0 prclk 0 0 x x 3.7 mhz 0 1 x x 11.06 mhz 1 x 0 0 0; power down 1 x 0 1 1; power down 1 x 1 0 test 1 x 1 1 hi-z table 2 : when power down address is selected, the vco is turned off and the device goes to standby mode. phase detector is in tri-state mode. 2k 2200 pf r2 c2 330 pf c1
imisg501 system clock chip march 1996 reduced emi clock generator international microcircuits, inc. 525 los coches st. milpitas, ca 95035 tel: 408-263-6300 fax 408-263-6571 page 3 of 8 maximum ratings voltage relative to vss: -0.3v to 7v voltage relative to vdd: 0.3v storage temperature: -65 c to 150 c ambient temperature: -0 c to 70 c recommend operating range: 4.5-5.5v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, vin and vout should be constrained to the range: v ss < (vin or vout) < v dd all inputs are tied high or low internally. electrical characteristics characteristic symbol min typ max units input low voltage v il - - 0.8 vdc input high voltage v ih 2.0 - - vdc input low current with pull-up/ pull-down i il /i ih - - 10/100 m a output low voltage iol = 6ma v ol - - 0.4 vdc output high voltage ioh=6ma v oh 2.5 - - vdc tri-state leakage current i oz - - 10 m a static supply current i dd - - 250 m a dynamic supply current i cc - 25 30 ma short circuit current i sc 25 - - ma vdd = 5v + 10%, ta = 0 c to 70 c
imisg501 system clock chip march 1996 reduced emi clock generator international microcircuits, inc. 525 los coches st. milpitas, ca 95035 tel: 408-263-6300 fax 408-263-6571 page 4 of 8 switching characteristics characteristic symbol min typ max units output rise and fall time measured at 10% - 90% of vdd ttlh, tthl - - 5 ns output rise and fall time measured at 0.8v - 2.0v ttlh, tthl - - 3 ns output duty cycles tsymf1 - - 45/55 % jitter one sigma tj1s - - 2 % of fout cycle-to-cycle jitter with normal crystal tjcc - - 50 ps vdd = 5 + 10%, ta = 0 c to 70 c, cl = 15 pf oscillator characteristics characteristic symbol min typ max units conditions transconductance gm 20 80 180 millimho s @ 44.2 mhz output impedance zo - 200 800 ohms @ 44.2 mhz input capacitance ci 8 13 18 pf - output capacitance co 3 6 9 pf - dc bias voltage vb 1.5 vdd/2 3.5 volt - start-up time ts - - 2 ms @ vdd = 4.5v duty cycle tsymf1 - - 45/55 % - input rise time oscin iclkr - - 20 ns - vco characteristics characteristic symbol min typ max units conditions vco gain ko 35 55 65 mhz/volt d f/ d v measured with vco control at 2v - 3v phase detector gain kd 100 145 200 m a/rad
imisg501 system clock chip march 1996 reduced emi clock generator international microcircuits, inc. 525 los coches st. milpitas, ca 95035 tel: 408-263-6300 fax 408-263-6571 page 5 of 8 charts frequency selection s0 s1 scaling factor prclk reference 0 0 .225 0 1 .450 1 0 .562 1 1 1.25 reference range : 35 mhz min to 55 mhz max output range: 8 mhz min to 60 mhz max
imisg501 system clock chip march 1996 reduced emi clock generator international microcircuits, inc. 525 los coches st. milpitas, ca 95035 tel: 408-263-6300 fax 408-263-6571 page 6 of 8 external connections 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 vdd xin xout vss mpsel avdd s0 s1 test vdd mpclk vss prclk avss lf1 sson dvdd avdd dvdd 1 2 dvdd avdd digital power plane analog power plane dvdd test jp4 jp3 jp2 jp1 mpsel s0 s1 c1 330 pf c2 2200pf r2 2k c8 .1uf header jp5 c9 .1uf c7 10 pf .033uf l2 1.2 uh c5 xtal 44.2 mhz c4 10pf c3 10pf r1 10 ohms c10 22uf c11 10uf l1 1.5 uh vcc note1: keep c3, c4, c5, c6 close to their pins (4, 11, 13, 10, 9 respectively). digital gnd plane analog gnd plane sg501
imisg501 system clock chip march 1996 reduced emi clock generator international microcircuits, inc. 525 los coches st. milpitas, ca 95035 tel: 408-263-6300 fax 408-263-6571 page 7 of 8 package drawing and dimensions 16 pin soic outline dimensions inches millimeters symbol min nom max min nom max a 0.097 0.101 0.104 2.46 2.56 2.64 a 1 0.0020 0.009 0.0015 0.060 0.22 0.38 a2 0.090 0.092 0.111 2.29 2.34 2.39 b 0.014 0.016 0.019 0.35 0.41 0.48 c 0.0091 0.010 0.0125 0.23 0.25 0.32 d .399 .407 .412 10.13 10.34 10.46 e 0.285 0.296 0.299 7.24 7.52 7.59 e 0.050 bsc 1.27 bsc h 0.400 0.406 0.410 10.16 10.31 10.41 a 0 5 10 0 5 10 l 0.024 0.032 0.040 0.61 0.81 1.02 16-pin plastic dip dimensions inches millimeters symbol min nom max min nom max a 0.150 0.160 0.170 3.81 4.06 4.318 a 1 0.015 - - 0.381 - - b 0.016 0.018 0.020 0.40 0.45 0.50 b 1 0.056 0.059 0.062 1.47 1.52 1.57 b 2 0.046 0.049 0.052 1.17 1.24 1.32 c 0.008 0.010 0.012 0.20 0.25 0.30 d 0.748 0.750 0.752 19.00 19.05 19.10 e 0.300 0.312 0.325 7.62 7.924 8.255 e 1 0.240 0.252 0.260 6.096 6.49 6.604 e 2 0.335 0.345 0.355 8.51 8.76 9.01 e 1 0.100 bsc 2.54 bsc l 0.25 0.230 0.135 3.175 3.30 3.429 a 0 7 15 0 7 15 q 1 0.059 0.060 0.061 1.50 1.53 1.55 q 2 0.128 0.130 0.132 3.25 3.30 3.35 s 0.073 0.075 0.077 1.85 1.90 1.95 e2 c a e e1 d b e a a 1 a 2 e h a l c d a1 a l b b1 e1 s q q2 b2
imisg501 system clock chip march 1996 reduced emi clock generator international microcircuits, inc. 525 los coches st. milpitas, ca 95035 tel: 408-263-6300 fax 408-263-6571 page 8 of 8 ordering information part number package type production flow imisg501xpb 16 pin plastic dip commercial, 0 c to + 70 c imisg501xxb 16 pin soic commercial, 0 c to + 70c note: the ?x? following the imi device number denotes the device revision. the ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. marking: example: imi sg501xpb date code, lot # imisg501xpb flow b = commercial, 0 c to + 70 c package p = plastic dip x = small outline revision imi device number
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