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xicor, inc. 1999 patents pending 9900-3002.10 2/12/99 t0/c0/d0 1 characteristics subject to change without notice x51638 cpu supervisor with 16kb spi eeprom features extended power-on reset (800ms nominal) selectable watchdog timer low vcc detection and reset assertion five standard reset threshold voltages re-program low vcc reset threshold voltage using special programming sequence reset signal valid to vcc=1v determine watchdog or low voltage reset with a volatile flag bit long battery life with low power consumption <50 m a max standby current, watchdog on ?1 m a max standby current, watchdog off <400 m a max active current during read 16kbits of eeprom built-in inadvertent write protection power-up/power-down protection circuitry protect 0, 1/4, 1/2 or all of eeprom array with block lock tm protection in circuit programmable rom mode 2mhz spi interface modes (0,0 & 1,1) minimize eeprom programming time 32 byte page write mode self-timed write cycle 5ms write cycle time (typical) 1.8v to 3.6v, 2.7v to 5.5v and 4.5v to 5.5v power supply operation available packages 14-lead tssop, 8-lead soic description this device combines four popular functions, power-on reset control, watchdog timer, supply voltage supervi- sion, and block lock protect serial eeprom in one package. this combination lowers system cost, reduces board space requirements, and increases reliability. applying power to the device activates a power on reset circuit which holds reset active for a period of time. this allows the power supply and oscillator to stabilize before the processor can execute code. this device allows 800ms before releasing the controller. the watchdog timer provides an independent protection mechanism for microcontrollers. when the microcontrol- ler fails to restart a timer within a selectable time-out interval, the device activates the reset signal. the user selects the interval from three preset values. once selected, the interval does not change, even after cycling the power. the x51638 low vcc detection circuitry protects the users system from low voltage conditions, resetting the system when vcc falls below the minimum vcc trip point. reset is asserted until vcc returns to proper operating level and stabilizes. five industry standard v trip thresh- olds are available, however, xicors unique circuits allow the thresold to be reprogrammed to meet custom requirements or to ?e-tune the threshold for applications requiring higher precision. block diagram watchdog timer reset data register command decode & control logic si so sck cs /wdi v cc reset & watchdog timebase power on and generation v trip + - reset reset low voltage status register protect logic 4k bits 4k bits 8k bits eeprom array watchdog transition detector wp vcc threshold reset logic
x51638 2 pin description pin configuration pin (soic/pdip) pin tssop name function 11cs /wdi chip select input. cs high, deselects the device and the so output pin is at a high impedance state. unless a nonvolatile write cycle is underway, the device will be in the standby power mode. cs low enables the device, placing it in the active power mode. prior to the start of any operation after power up, a high to low transition on cs is required watchdog input. a high to low transition on the wdi pin restarts the watchdog timer. the absence of a high to low transition within the watchdog time-out period results in reset going active. 22so serial output. so is a push/pull serial data output pin. a read cycle shifts data out on this pin. the falling edge of the serial clock (sck) clocks the data out. 58si serial input. si is a serial data input pin. input all opcodes, byte addresses, and memory data on this pin. the rising edge of the serial clock (sck) latches the input data. send all opcodes (table 1), addresses and data msb ?st. 6 9 sck serial clock. the serial clock controls the serial bus timing for data input and output. the rising edge of sck latches in the opcode, address, or data bits present on the si pin. the falling edge of sck changes the data output on the so pin. 36wp write protect. the wp pin works in conjunction with a nonvolatile wpen bit to ?ock?the setting of the watchdog timer control and the memory write protect bits. 47 v ss ground 814 v cc supply voltage 7 13 reset reset output . reset is an active low open drain output which goes active whenever vcc falls below the minimum vcc sense level. it will remain active until vcc rises above the minimum vcc sense level for 800ms. reset goes active if the watchdog timer is enabled and cs remains either high or low longer than the selectable watchdog time-out period. a falling edge of cs will reset the watchdog timer. reset goes active on power up at 1v and remains active for 800ms after the power supply stabilizes. 3-5,10-12 nc no internal connections 8-lead soic/pdip cs wp so 1 2 3 4 reset 8 7 6 5 v cc 14-lead tssop so wp v ss 1 2 3 4 5 6 7 reset sck si 14 13 12 11 10 9 8 nc v cc nc x51638 v ss sck si cs nc nc nc nc x51638
x51638 3 principles of operation power on reset application of power to the x51638 activates a power on reset circuit. this circuit goes active at v cc sense level (v trip ) and pulls the reset pin low. this signal pre- vents the system microprocessor from starting to operate with insuf?ient voltage or prior to stabilization of the oscil- lator. when vcc exceeds the device v trip value for 800ms (nominal) the circuit releases reset , allowing the processor to begin executing code. low voltage monitoring during operation, the x51638 monitors the v cc level and asserts reset if supply voltage falls below a preset mini- mum v trip . the reset signal prevents the microproces- sor from operating in a power fail or brownout condition. the reset signal remains active until the voltage drops below 1v. it also remains active until vcc returns and exceeds v trip for 800ms. watchdog timer the watchdog timer circuit monitors the microprocessor activity by monitoring the wdi input. the microprocessor must toggle the cs /wdi pin periodically to prevent a reset signal. the cs /wdi pin must be toggled from high to low prior to the expiration of the watchdog time- out period. the state of two nonvolatile control bits in the status register determine the watchdog timer period. the microprocessor can change these watchdog bits, or they may be ?ocked by tying the wp pin low and setting the wpen bit high. vcc threshold reset procedure the x51638 is offered with one of several standard vcc threshold (v trip ) voltages. this value will not change over normal operating and storage conditions. however, in applications where the standard v trip is not exactly right, or for higher precision in the v trip value, the x51638 threshold may be adjusted. setting the v trip voltage this procedure sets the v trip to a higher voltage value. for example, if the current v trip is 4.4v and the new v trip is 4.6v, this procedure directly makes the change. if the new setting is lower than the current setting, then it is necessary to reset the trip point before setting the new value. to set the new v trip voltage, apply the desired v trip threshold to the vcc pin and tie the cs /wdi pin and the wp pin high. reset and so pins are left unconnected. then apply the programming voltage vp to both sck and si and pulse cs /wdi low then high. remove vp and the sequence is complete. figure 1. set v trip voltage resetting the v trip voltage this procedure sets the v trip to a ?ative voltage level. for example, if the current v trip is 4.4v and the v trip is reset, the new v trip is something less than 1.7v. this procedure must be used to set the voltage to a lower value. to reset the v trip voltage, apply a voltage between 2.7 and 5.5v to the vcc pin. tie the cs /wdi pin, the wp pin, and the sck pin high. reset and so pins are left unconnected. then apply the programming voltage vp to the si pin only and pulse cs /wdi low then high. remove vp and the sequence is complete. figure 2. reset v trip voltage sck si vp vp cs sck si vcc vp cs
x51638 4 figure 3. v trip programming sequence flow chart v trip programming apply 5v to vcc decrement vcc reset pin goes active? measured v trip - desired v trip done execute sequence reset v trip set vcc = vcc applied = desired v trip execute sequence set v trip new vcc applied = old vcc applied + error (vcc = vcc - 50mv) execute sequence reset v trip new vcc applied = old vcc applied - error error < 0 error = 0 yes no error > 0 figure 4. sample v trip reset circuit 1 2 3 4 8 7 6 5 x51638 v trip adj. program nc nc v p reset v trip test v trip set v trip nc reset 4.7k 4.7k 10k 10k +
x51638 5 spi serial memory the memory portion of the device is a cmos serial eeprom array with xicors block lock tm protection. the array is internally organized as x 8. the device features a serial peripheral interface (spi) and software protocol allowing operation on a simple four-wire bus. the device utilizes xicors proprietary direct write tm cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. the device is designed to interface directly with the syn- chronous serial peripheral interface (spi) of many popu- lar microcontroller families. it contains an 8-bit instruction register that is accessed via the si input, with data being clocked in on the rising edge of sck. cs must be low during the entire operation. all instructions (table 1), addresses and data are trans- ferred msb ?st. data input on the si line is latched on the ?st rising edge of sck after cs goes low. data is out- put on the so line by the falling edge of sck. sck is static, allowing the user to stop the clock and then start it again to resume operations where left off. write enable latch the device contains a write enable latch. this latch must be set before a write operation is initiated. the wren instruction will set the latch and the wrdi instruc- tion will reset the latch (figure 3). this latch is automati- cally reset upon a power-up condition and after the completion of a valid write cycle. status register the rdsr instruction provides access to the status reg- ister. the status register may be read at any time, even during a write cycle. the status register is formatted as follows: the write-in-progress (wip) bit is a volatile, read only bit and indicates whether the device is busy with an internal nonvolatile write operation. the wip bit is read using the rdsr instruction. when set to a ?? a nonvolatile write operation is in progress. when set to a ?? no write is in progress. 7 6543210 wpen flb wd1 wd0 bl1 bl0 wel wip table 1. instruction set *instructions are shown msb in leftmost position. instructions are transferred msb ?st. table 2. block protect matrix instruction name instruction format* operation wren 0000 0110 set the write enable latch (enable write operations) sflb 0000 0000 set flag bit wrdi/rflb 0000 0100 reset the write enable latch/reset flag bit rsdr 0000 0101 read status register wrsr 0000 0001 write status register(watchdog,blocklock,wpen & flag bits) read 0000 0011 read data from memory array beginning at selected address write 0000 0010 write data to memory array beginning at selected address wren cmd status register device pin block block status register wel wpen wp# protected block unprotected block wpen, bl0, bl1 wd0, wd1 0 x x protected protected protected 1 1 0 protected writable protected 1 0 x protected writable writable 1 x 1 protected writable writable
x51638 6 the write enable latch (wel) bit indicates the status of the write enable latch. when wel=1, the latch is set high and when wel=0 the latch is reset low. the wel bit is a volatile, read only bit. it can be set by the wren instruction and can be reset by the wrds instruction. the block lock bits, bl0 and bl1, set the level of block lock tm protection. these nonvolatile bits are pro- grammed using the wrsr instruction and allow the user to protect one quarter, one half, all or none of the eeprom array. any portion of the array that is block lock protected can be read but not written. it will remain pro- tected until the bl bits are altered to disable block lock protection of that portion of memory. the watchdog timer bits, wd0 and wd1, select the watchdog time-out period. these nonvolatile bits are programmed with the wrsr instruction. the flag bit shows the status of a volatile latch that can be set and reset by the system using the sflb and rflb instructions. the flag bit is automatically reset upon power up. this ?g can be used by the system to deter- mine whether a reset occurs as a result of a watchdog time-out or power failure. the nonvolatile wpen bit is programmed using the wrsr instruction. this bit works in conjunction with the wp pin to provide an in-circuit programmable rom func- tion (table 2). wp is low and wpen bit programmed high disables all status register write operations. in circuit programmable rom mode this mechanism protects the block lock and watchdog bits from inadvertant corruption. in the locked state (programmable rom mode) the wp pin is low and the nonvolatile bit wpen is ?? this mode disables nonvolatile writes to the devices status register. status register bits array addresses protected bl1 bl0 x516x 0 0 none 0 1 $0600?07ff 1 0 $0400?07ff 1 1 $0000?07ff status register bits watchdog time-out (typical) wd1 wd0 0 0 1.4 seconds 0 1 600 milliseconds 1 0 400 milliseconds 1 1 disabled figure 5. read eeprom array sequence 0123 45678910 2021222324252627282930 7 654321 0 data out cs sck si so msb high impedance instruction 16 bit address 151413 3210
x51638 7 setting the wp pin low while wpen is a ? while an internal write cycle to the status register is in progress will not stop this write operation, but the operation dis- ables subsequent write attempts to the status register. when wp is high, all functions, including nonvolatile writes to the status register operate normally. setting the wpen bit in the status register to ? blocks the wp pin function, allowing writes to the status regis- ter when wp is high or low. setting the wpen bit to ? while the wp pin is low activates the programmable rom mode, thus requiring a change in the wp pin prior to subsequent status register changes. this allows manufacturing to install the device in a system with wp pin grounded and still be able to program the status reg- ister. manufacturing can then load con?uration data, manufacturing time and other parameters into the eeprom, then set the portion of memory to be pro- tected by setting the block lock bits, and ?ally set the ?tp mode by setting the wpen bit. data changes now require a hardware change. read sequence when reading from the eeprom memory array, cs is ?st pulled low to select the device. the 8-bit read instruction is transmitted to the device, followed by the 16-bit address. after the read opcode and address are sent, the data stored in the memory at the selected address is shifted out on the so line. the data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. the address is auto- matically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached, the address counter rolls over to address $0000 allowing the read cycle to be continued inde?itely. the read operation is terminated by taking cs high. refer to the read eeprom array sequence (figure 1). to read the status register, the cs line is ?st pulled low to select the device followed by the 8-bit rdsr instruc- tion. after the rdsr opcode is sent, the contents of the status register are shifted out on the so line. refer to the read status register sequence (figure 2). write sequence prior to any attempt to write data into the device, the ?rite enable latch (wel) must ?st be set by issuing the wren instruction (figure 3). cs is ?st taken low, then the wren instruction is clocked into the device. after all eight bits of the instruction are transmitted, cs must then be taken high. if the user continues the write operation without taking cs high after issuing the wren instruction, the write operation will be ignored. to write data to the eeprom memory array, the user then issues the write instruction followed by the 16 bit address and then the data to be written. any unused address bits are speci?d to be ?s? the write opera- tion minimally takes 32 clocks. cs must go low and remain low for the duration of the operation. if the address counter reaches the end of a page and the clock continues, the counter will roll back to the ?st address of the page and overwrite any data that may have been pre- viously written. for the page write operation (byte or page write) to be completed, cs can only be brought high after bit 0 of the last data byte to be written is clocked in. if it is brought high at any other time, the write operation will not be completed (figure 4). to write to the status register, the wrsr instruction is followed by the data to be written (figure 5). data bits 0 and 1 must be ? . while the write is in progress following a status register or eeprom sequence, the status register may be read to check the wip bit. during this time the wip bit will be high. operational notes the device powers-up in the following state: the device is in the low power standby state. a high to low transition on cs is required to enter an active state and receive an instruction. so pin is high impedance. the write enable latch is reset. the flag bit is reset. reset signal is active for t purst . data protection the following circuitry has been included to prevent inad- vertent writes: a wren instruction must be issued to set the write enable latch. ?s must come high at the proper clock count in order to start a nonvolatile write cycle.
x51638 8 figure 6. read status register sequence figure 7. write enable latch sequence 01234567891011121314 76543210 data out cs sck si so msb high impedance instruction 01234567 cs si sck high impedance so
x51638 9 figure 8. write sequence figure 9. status register write sequence 32 33 34 35 36 37 38 39 sck si cs 012345678910 sck si instruction 16 bit address data byte 1 76543210 cs 40 41 42 43 44 45 46 47 data byte 2 76543210 dat a byte 3 76543210 data byte n 15 14 13 3 2 1 0 20 21 22 23 24 25 26 27 28 29 30 31 654 321 0 0123456789 cs sck si so high impedance instruction data byte 765432 10 10 11 12 13 14 15 waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance symbol table
x51638 10 d.c. operating characteristics (over the recommended operating conditions unless otherwise specified.) symbol parameter limits units test conditions min. typ. max. i cc1 v cc write current (active) 5ma sck = v cc x 0.1/v cc x 0.9 @ 2mhz, so = open i cc2 v cc read current (active) 0.4 ma sck = v cc x 0.1/v cc x 0.9 @ 2mhz, so = open i sb1 v cc standby current wdt=off 1a cs = v cc , v in = v ss or v cc , v cc = 5.5v i sb2 v cc standby current wdt=on 50 ? cs = v cc , v in = v ss or v cc , v cc = 5.5v i sb3 v cc standby current wdt=on 20 ? cs = v cc , v in = v ss or v cc , v cc =3.6v i li input leakage current 0.1 10 ? v in = v ss to v cc i lo output leakage current 0.1 10 ? v out = v ss to v cc v il (1) input low voltage ?.5 v cc x0.3 v v ih (1) input high voltage v cc x0.7 v cc +0.5 v v ol1 output low voltage 0.4 v v cc > 3.3v, i ol = 2.1ma v ol2 output low voltage 0.4 v 2v < v cc 3.3v, i ol = 1ma v ol3 output low voltage 0.4 v v cc 2v, i ol = 0.5ma v oh1 output high voltage v cc ?.8 v v cc > 3.3v, i oh = ?.0ma v oh2 output high voltage v cc ?.4 v 2v < v cc 3.3v, i oh = ?.4ma v oh3 output high voltage v cc ?.2 v v cc 2v, i oh = ?.25ma v ols reset output low voltage 0.4 v i ol = 1ma absolute maximum ratings* temperature under bias ........................?5? to +135? storage temperature .............................?5? to +150? voltage on any pin with respect to v ss ....... ?.0v to +7v d.c. output current ....................................................5ma lead temperature (soldering, 10 seconds)............ 300? recommended operating conditions *comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this speci?ation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. temp min. max. commercial 0? 70? industrial ?0? +85? voltage option supply voltage ?.8 1.8v-3.6v ?.7 or -2.7a 2.7v to 5.5v blank or -4.5a 4.5v-5.5v
x51638 11 capacitance t a = +25?, f = 1mhz, v cc = 5v. notes: (1) v il min. and v ih max. are for reference only and are not tested. (2) this parameter is periodically sampled and not 100% tested. symbol test max. units conditions c out (2) output capacitance (so, reset ) 8pfv out = 0v c in (2) input capacitance (sck, si, cs , wp ) 6pfv in = 0v equivalent a.c. load circuit at 5v v cc a.c. test conditions 5v output 100pf 5v 3.3k w reset 30pf 1.64k w 1.64k w so input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5
x51638 12 a.c. characteristics (over recommended operating conditions, unless otherwise specified) serial input timing serial input timing symbol parameter 1.8-3.6v 2.7-5.5v units min. max. min. max. f sck clock frequency 0 1 0 2 mhz t cyc cycle time 1000 500 ns t lead cs lead time 500 250 ns t lag cs lag time 500 250 ns t wh clock high time 400 200 ns t wl clock low time 400 250 ns t su data setup time 50 50 ns t h data hold time 50 50 ns t ri (3) input rise time 100 100 ns t fi (3) input fall time 100 100 ns t cs cs deselect time 500 500 ns t wc (4) write cycle time 10 10 ms sck cs si so msb in t su t ri t lag t lead t h lsb in t cs t fi high impedance
x51638 13 serial output timing notes: (3) this parameter is periodically sampled and not 100% tested. (4) t wc is the time from the rising edge of cs after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. serial output timing symbol parameter 1.8-3.6v 2.7-5.5v units min. max. min. max. f sck clock frequency 0 1 0 2 mhz t dis output disable time 250 250 ns t v output valid from clock low 400 250 ns t ho output hold time 00 ns t ro (3) output rise time 100 100 ns t fo (3) output fall time 100 100 ns sck cs so si msb out msb? out lsb out addr lsb in t cyc t v t ho t wl t wh t dis t lag
x51638 14 power-up and power-down timing reset output timing notes: (5) this parameter is periodically sampled and not 100% tested. symbol parameter min. typ. max. units v trip reset trip point voltage, x51638-4.5a reset trip point voltage, x51638 reset trip point voltage, x51638-2.7a reset trip point voltage, x51638-2.7 reset trip point voltage, x51638-1.8 4.5 4.25 2.85 2.55 1.7 4.62 4.38 2.92 2.62 1.75 4.75 4.5 3.0 2.7 1.8 v v th (5) v trip hysteresis (high to low vs. low to high v trip voltage) 20 mv t purst power-up reset timeout 500 800 1400 ms t rpd (5) v cc detect to reset/output 500 ns t f (5) v cc fall time 100 m s t r (5) v cc rise time 100 m s v rvalid reset valid v cc 1v vcc t purst t purst t r t f t rpd reset 0 volts v trip v trip
x51638 15 cs /wdi vs. reset timing reset output timing (wd1 = 1, wd0 = 0) reset output timing (wd1 = 0, wd0 = 1) reset output timing (wd1 = 0, wd0 = 0) symbol parameter min. typ. max. units t wdo watchdog timeout period 300 400 550 ms t cst cs pulse width to reset the watchdog 400 ns t rst reset timeout 200 400 600 ms symbol parameter min. typ. max. units t wdo watchdog timeout period 450 600 800 ms t cst cs pulse width to reset the watchdog 400 ns t rst reset timeout 100 200 300 ms symbol parameter min. typ. max. units t wdo watchdog timeout period 1 1.4 2 sec t cst cs pulse width to reset the watchdog 400 ns t rst reset timeout 100 200 300 ms cs /wdi t cst reset t wdo t rst t wdo t rst
x51638 16 v trip set conditions v trip reset conditions sck si vp vp cs t vps t vph t p t vps t vph t rp t vpo t vpo t tsu t thd v tr i p vcc sck si vcc vp cs t vps t vph t p t vps t vp1 t rp t vpo t vpo t tsu t thd v tr i p vcc
x51638 17 table 3. v trip programming specifications: vcc=1.7-5.5v; temperature = 0 o c to 70 o c parameter description min max units t vps sck v trip program voltage setup time 1 m s t vph sck v trip program voltage hold time 1 m s t p v trip program pulse width 1 m s t tsu v trip level setup time 10 m s t thd v trip level hold (stable) time 10 ms t wc v trip write cycle time 10 ms t rp v trip program cycle recovery period (between successive programming cycles) 10 ms t vpo sck v trip program voltage off time before next cycle 0ms vp programming voltage 15 18 v v trip v trip programed voltage 1.7 5.0 v vta v trip programed voltage accuracy (vcc applied - v trip ) -0.3 +0.3 v vtr v trip programed voltage repeatability (successive program operations.) -5 +5 mv v trip programming parameters are periodically sampled and are not 100% tested.
x51638 18 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 ?8 x 45 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in p arentheses in millimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint
x51638 19 note: all dimensions in inches (in p arentheses in millimeters) 14-lead plastic, tssop, package type v see detail ? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 ?8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x)
x51638 20 ordering information part mark information vcc range v trip range package operating temperature range part number reset (active low) 4.5-5.5v 4.5-4.75 8 pin pdip 0 o c - 70 o c x51638p-4.5a 8l soic 0 o c - 70 o c x51638s8-4.5a -40 o c - 85 o c x51638s8i-4.5a 4.5-5.5v 4.25-4.5 8 pin pdip 0 o c - 70 o c x51638p 8l soic 0 o c - 70 o c x51638s8 -40 o c - 85 o c x51638s8i 14l tssop 0? - 70? x51638v14 2.7-5.5v 2.85-3.0 8l soic 0 o c - 70 o c x51638s8-2.7a -40 o c - 85 o c x51638s8i-2.7a 14l tssop 0 o c - 70 o c x51638v14-2.7a 2.7-5.5v 2.55-2.7 8l soic 0 o c - 70 o c x51638s8-2.7 14l tssop 0 o c - 70 o c x51638v14-2.7 1.8-3.6v 1.7-1.8v 8l soic 0 o c - 70 o c x51638s8-1.8 14l tssop 0 o c - 70 o c x51638v14-1.8 p = 8-pin dip blank = 8-lead soic v = 14 lead tssop blank = 5v ?0%, 0? to +70?, v trip =4.25-4.5 al=5v?0%, 0? to +70?, v trip = 4.5-4.75 i = 5v ?0%, ?0? to +85?, v trip =4.25-4.5 am = 5v ?0%, ?0? to +85?, v trip =4.5-4.75 f = 2.7v to 5.5v, 0? to +70?, v trip =2.55-2.7 an = 2.7v to 5.5v, 0? to +70?, v trip =2.85-3.0 g = 2.7v to 5.5v, ?0? to +85?, v trip =2.55-2.7 ap = 2.7v to 5.5v, ?0? to +85?, v trip =2.85-3.0 ag = 1.8v to 3.6v, 0? to +70?, v trip =1.7-1.8 ah = 1.8v to 3.6v, ?0? to +85?, v trip =1.7-1.8 w x51638 x
x51638 21 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the f reedom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue production and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874 , 967; 4,883, 976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. xicor's products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) su pport or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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