750ps max. len to output extended 100e v ee range of ?.2v to ?.5v 700ps max. d to output differential outputs asynchronous master reset dual latch-enables fully compatible with industry standard 10kh, 100k ecl levels internal 75k ? input pulldown resistors fully compatible with motorola mc10e/100e154 available in 28-pin plcc package features 5-bit 2:1 mux-latch the sy10/100e154 offer five 2:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ecl systems. the two external latch-enable signals (len 1 , len 2 ) are gated through a logical or operation before use as control for the five latches. when both len 1 and len 2 are at a logic low, the latches are transparent, thus presenting the data from the multiplexers at the output pins. if either len 1 or len 2 (or both) are at a logic high, the outputs are latched. the multiplexer operation is controlled by the sel(select) signal which selects one of the two bits of input data at each mux to be passed through. the mr (master reset) signal operates asynchronously to make all q outputs go to a logic low. description rev.: c amendment: /1 issue date: february, 1998 sy10e154 sy100e154 final block diagram pin function d 0a ? 4a input data a d 0b ? 4b input data b sel data select input len 1 , len 2 latch enables mr master reset q 0 ? 4 true outputs q 0 ? 4 inverted outputs v cco v cc to output pin configuration pin names v ee sel len 1 d 0a mr q 4 26 27 28 1 2 3 4 18 17 16 15 14 13 12 25 24 23 22 21 20 19 567891011 d 0b len 2 q 0 q 0 q 3 v cco plcc top view j28-1 d 4b d 3a d 3b q 3 v cc q 2 q 2 q 1 q 1 v cco d 2b d 2a d 1b d 1a d 4a q 4 mr d r d 0a len 1 len 2 q e n q mux sel sel d 0b d r d 1a q e n q mux d 1b d r d 2a q e n q mux d 2b d r d 3a q e n q mux d 3b d r d 4a q 0 q 0 q 1 q 1 q 2 q 2 q 3 q 3 q 4 q 4 q e n q mux d 4b sel sel sel sel 1
2 sy10e154 sy100e154 micrel v ee = v ee (min.) to v ee (max.); v cc = v cco = gnd t a = 0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition t plh propagation delay to output ps t phl d 325 500 700 325 500 700 325 500 700 sel 475 650 925 475 650 925 475 650 925 len 350 500 750 350 500 750 350 500 750 mr 450 600 800 450 600 800 450 600 800 t s set-up time ps d 300 100 300 100 300 100 sel 500 250 500 250 500 250 t h hold time ps d300 100 300 100 300 100 sel 200 250 200 250 200 250 t rr reset recovery time 800 600 800 600 800 600 ps t pw minimum pulse width, mr 400 400 400 ps t skew within-device skew 50 50 50 ps 1 t r rise/fall time 300 475 800 300 475 800 300 475 800 ps t f 20% to 80% note: 1. within-device skew is defined as identical transitions on similar paths through a device. truth tables sel data ha lb len 1 len 2 latch l l transparent h x latched x h latched dc electrical characteristics v ee = v ee (min.) to v ee (max.); v cc = v cco = gnd t a = 0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition i ih input high current 150 150 150 a i ee power supply current ma 10e 76 91 76 91 76 91 100e 76 91 76 91 87 105 ac electrical characteristics product ordering code ordering package operating code type range sy10e154jc j28-1 commercial sy10e154jctr j28-1 commercial sy100e154jc j28-1 commercial sy100e154jctr j28-1 commercial
3 sy10e154 sy100e154 micrel 28 lead plcc (j28-1) rev. 03
4 sy10e154 sy100e154 micrel micrel-synergy 3250 scott boulevard santa clara ca 95054 usa tel + 1 (408) 980-9191 fax + 1 (408) 914-7878 web http://www.micrel.com this information is believed to be accurate and reliable, however no responsibility is assumed by micrel for its use nor for an y infringement of patents or other rights of third parties resulting from its use. no license is granted by implication or otherwise under any patent or pat ent right of micrel inc. ? 2000 micrel incorporated
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