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fractional-n frequency synthesizer adf4154 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features rf bandwidth 500 mh z to 4 g hz 2.7 v to 3.3 v p o wer supply separate v p all o ws extended t u ning voltage programmable dua l -modul us prescaler 4/5, 8 / 9 programmable charge pump currents 3-wire seri al in terface digital lock det e ct power-down mode pin compatible with the a d f4 110/adf4 111/ adf41 12/adf 4113, adf4 106 and a d f41 53 programmable modulus on fr actional-n synt hesizer trade-off noise vers us spurious performance fast-lock mode with built-in ti mer applic ati o ns catv equipment base stations f o r mobile radi o (gsm, pcs, dcs, cdma, w c dm a) wireless han d s e ts (gsm, p c s, dcs, cdma, w c dma) wireless lans communications test eq uipm ent general description the ad f4154 is a f r ac tio n al-n f r eq uen c y syn t hesizer tha t i m p l em en t s l o cal oscill a t o r s in th e u p co n v e r s i o n a n d d o w n co n v ersio n s e c t io n s o f wir e les s re cei v ers an d tran smi t t e rs. i t c o ns i s t s of a l o w noi s e d i g i t a l ph a s e f r e q u e nc y d e te c t or ( p f d ) , a p r e c isio n cha r ge p u m p , and a p r o g r a mma b l e r e fer e n c e divi de r . ther e is a - b a s e d f r ac t i o n al i n t e r p ol a t o r t o a l lo w p r ogra m- m a bl e f r a c t i on a l - n d i v i s i on . t h e i n t , f r a c , a n d m o d re g i s - t e r s def i ne a n o v erall n divider (n = (int + (fra c/m o d))). i n a d d i t i o n , t h e 4 - bit re f e re nc e c o u n te r ( r c o u n t e r ) a l l o w s s e le c t a b le ref in f r e q uen c ies a t t h e pf d in p u t. a co m p let e p h as e-lo ck e d lo o p (p ll) ca n be im p l em en t e d if th e sy n t h e sizer is us e d w i t h a n ext e r n al lo o p f i l t er a nd a v o l t a g e co n t r o l l e d oscilla t o r ( v co). a k e y f e a t ur e o f th e ad f4154 is th e fas t -lo c k mo de wi t h a b u il t- in t i m e r . th e us er ca n p r og ra m a p r e d et er mi ne d co un t - do w n t i me va l u e s o t h a t t h e pl l wi l l r e ma in in wid e b a ndwid t h m o d e , in s t e a d o f ha ving t o co n t r o l this time ext e r n al l y . c o n t r o l o f al l o n -c hi p r e g i s t ers is v i a a sim p le 3 - wir e in t e r f ace . the de v i ce o p er a t es wi t h a p o w e r s u p p l y ra n g i n g f r o m 2.7 v to 3.3 v , a nd can b e p o w e r e d do w n w h e n n o t i n us e. func tio n a l block di agram lock detect fast-lock switch n counter cp rfcp3 rfcp2 rfcp1 reference data le 24-bit data register clock ref in av dd agnd v dd v dd dgnd r div n div dgnd cpgnd dv dd v p sdv dd r set rf in a rf in b output mux muxout ? + high z phase frequency detector adf4154 third order fractional interpolator modulus reg fraction reg integer reg p = 4/5 or 8/9 b = 9 bits; a = 3 bits current setting 2 doubler 4-bit r counter charge pump 04833-0-001 fi g u r e 1 .
adf4154 rev. 0 | page 2 of 20 table of contents specifications..................................................................................... 3 timing characteristics..................................................................... 4 absolute maximum ratings............................................................ 5 esd caution.................................................................................. 5 pin configuration and pin function descriptions...................... 6 typical performance characteristics ............................................. 7 circuit description........................................................................... 9 reference input section............................................................... 9 rf input stage............................................................................... 9 rf int divider............................................................................. 9 int, frac, mod, and r relationship...................................... 9 rf r counter ................................................................................ 9 phase frequency detector (pfd) and charge pump.............. 9 muxout and lock detect...................................................... 10 input shift registers ................................................................... 10 program modes .......................................................................... 10 registers ........................................................................................... 11 register definition ..................................................................... 15 r-divider register, r1 ............................................................... 15 control register, r2 ................................................................... 15 noise and spur register, r3 ...................................................... 16 reserved bits............................................................................... 16 rf synthesizer: a worked example ........................................ 16 modulus....................................................................................... 17 reference doubler and reference divider ............................. 17 12-bit programmable modulus................................................ 17 spurious optimization and fast-lock...................................... 17 fast-lock timer and register sequences ............................... 17 fast-lock: a worked example ................................................. 18 fast-lock: loop filter topology .............................................. 18 spurious signals.......................................................................... 18 filter designadisimpll....................................................... 18 interfacing ................................................................................... 18 pcb design guidelines for chip scale package .................... 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20
adf4154 rev. 0 | page 3 of 20 specifications table 1. av dd = dv dd = sdv dd = 2.7 v to 3.3 v; v p = av dd to 5.5 v; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted; dbm referred to 50 ?. the operating temperature for the b version is ?40c to +80c. parameter b version unit test conditions/comments rf characteristics (3 v) see figure 18 for input circuit. rf input frequency (rf in ) 1 0.5/4.0 ghz min/max ?8 dbm/0 dbm min/max. for lower frequencies, ensure slew rate > 396 v/s. 1.0/4.0 ghz min/max ?10 dbm/0 dbm min/max. reference characteristics see figure 17 for input circuit. ref in input frequency 1 10/250 mhz min/max for f < 10 mhz, use a dc-coupled, cmos compatible square wave, slew rate > 21 v/s. ref in input sensitivity 0.7/av dd v p-p min/max ac-coupled. 0 to av dd v max cmos compatible. ref in input capacitance 10 pf max ref in input current 100 a max phase detector phase detector frequency 2 32 mhz max charge pump i cp sink/source programmable. see table 5. high value 5 ma typ with r set = 5.1 k?. low value 312.5 a typ absolute accuracy 2.5 % typ with r set = 5.1 k?. r set range 1.5/10 k? min/max i cp three-state leakage current 1 na typ sink and source current. matching 2 % typ 0.5 v < v cp < v p C 0.5. i cp vs. v cp 2 % typ 0.5 v < v cp < v p C 0.5. i cp vs. temperature 2 % typ v cp = v p /2. logic inputs v inh , input high voltage 1.4 v min v inl , input low voltage 0.6 v max i inh /i inl , input current 1 a max c in , input capacitance 10 pf max logic outputs v oh , output high voltage 1.4 v min op en-drain 1 k? pull-up to 1.8 v. v ol , output low voltage 0.4 v max i ol = 500 a. power supplies av dd 2.7/3.3 v min/v max dv dd , sdv dd av dd v p av dd /5.5 v min/v max i dd 3 24 ma max 20 ma typical. low power sleep mode 1 a typ noise characteristics phase noise figure of merit 4 ?213 dbc/hz typ adf4154 phase noise floor 5 ?143 dbc/hz typ @ 10 mhz pfd frequency. ?139 dbc/hz typ @ 26 mhz pfd frequency. phase noise performance 6 @ vco output. 1750 mhz output 7 ?102 dbc/hz typ @ 1 khz offset, 26 mhz pfd frequency. 1 use a square wave for frequencies below f min . 2 guaranteed by design. sample tested to ensure compliance. 3 ac coupling ensures av dd /2 bias. see for typical circuit. figure 17 4 this figure can be used to calculate phase noise for any application. use the formula C213 + 10log(f pfd ) + 20logn to calculate in-band phase noise performance, as seen at the vco output. the value given is the lowest noise mode. 5 the synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the vco and subtracting 2 0logn (where n is the n-divider value). the value given is the lowest noise mode. 6 the phase noise is measured with the EVAL-ADF4154EB1 evaluation board and the hp8562e spectrum analyzer. 7 f refin = 26 mhz; f pfd = 26 mhz; offset frequency = 1 khz; rf out = 1750 mhz; loop b/w = 20 khz; lowest noise mode.
adf4154 rev. 0 | page 4 of 2 0 timing characteristics table 2. av dd = d v dd = s d v dd = 2.7 v to 3. 3 v; v p = a v dd to 5.5 v; agn d = dgn d = 0 v; t a = t min to t max , un less otherwise not e d; db m re f e rred t o 50 ?. parameter 1 limit at t min to t ma x (b version ) unit test condition s /comments t 1 20 ns min le setup time t 2 10 ns min data to clock setup time t 3 10 ns min data to clock hold time t 4 25 ns min clock high duration t 5 25 ns min clock low duration t 6 10 ns min clock to le setup time t 7 20 ns min le pulse width 1 guarante e d by d e sign, but no t pro d uctio n te s t e d . clock data le le db23 (msb) db22 db2 db1 (control bit c2) db0 (lsb) (control bit c1) t 1 t 2 t 3 t 7 t 6 t 4 t 5 04833-0-026 f i g u re 2. ti ming d i ag r a m
adf4154 rev. 0 | page 5 of 2 0 absolute maximum ratings table 3. absol u te maximum ratings. 1, 2, 3 t a = 25c, u n less ot herwi s e not e d. p a r a m e t e r r a t i n g v dd to gnd ?0.3 v to +4 v v dd to v dd ?0.3 v to +0.3 v v p to gnd ?0.3 v to +5.8 v v p to v dd ?0.3 v to +5.8 v digital i/o voltage to gnd ?0.3 v to v dd + 0.3 v analog i/o voltage to gnd ?0.3 v to v dd + 0.3 v ref in , rf in to gn d ?0.3 v to v dd + 0.3 v operating tem p erature range indus t rial (b vers io n) ?40c to +85c storage temperature range ?65c to +150c maximum junction temperature 150c tssop ja ther mal impedance 150.4c/w lfcsp ja ther mal impedance (paddl e sol d ered) 122c/w lfcsp ja ther mal impedance (paddl e not sol d ered) 216c/w lead temperature, soldering vapor phase (60 sec) 215c i n f r a r e d 2 2 0 c s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s r a t i ng o n ly ; f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or a n y o t h e r con d i t io ns a b o v e t h os e list e d i n t h e o p era t io nal s e c t io n s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . 1 this de vice is a high pe rf ormance rf i nte grate d circuit with an e s d rating o f < 2 kv, a n d i t i s e s d sen s i t i v e. pr oper pr eca u t i on s sh ou ld b e t a ken for h a n dli n g a n d a s s e m b ly. 2 gnd = a gnd = d gnd = 0 v. 3 v dd = av dd = dv dd = sd v dd . esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
adf4154 rev. 0 | page 6 of 2 0 pin conf iguration and pi n function descriptions adf4154 top view (not to scale) agnd 4 rf in b 5 rf in a 6 av dd 7 ref in 8 le data clk sdv dd dgnd 13 12 11 10 r set 1 cp 2 cpgnd 3 v p dv dd muxout 16 15 14 9 04833-0-002 f i g u re 3. t s sop p i n conf ig u r at ion 04833-0-003 15 muxout le data clk sdv dd 14 13 12 1 2 3 20 11 6 7 8 9 10 dgnd dgnd re f in av dd av dd 4 5 rf in a rf in b agnd agnd cpgnd 19 18 17 16 adf4154 top view cp r set v p dv d d dv d d pin 1 indicator f i g u re 4. lfcs p pin conf ig ur at i o n ta ble 4. pi n f u nct i on d e s c ri pt i o ns t s s p f c s p m n e m o n i c d e s c r i p t i o n 1 1 9 r set connecting a re sistor betwe e n this pin a n d ground sets the max i mum charge pump output curr ent. the relationship between i cp an d r set is set cp r 5 25 i . max = where r set = 5.1 k? and i cpma x = 5 ma. 2 2 0 c p charge pump output. when en abled, this pr ovi d es i cp to the external l oop fi lter, which in turn drives the external vc o. 3 1 cpgnd charge pump ground. this is th e ground return path for the charge pump. 4 2, 3 agnd analog ground. t h is is the ground return path of the presca ler. 5 4 rf in b complementary input to the rf pres caler . t h is p o int should be d e co upled to the ground plane with a small bypass capacitor, typically 100 pf (see fi gure 18). 6 5 rf in a input to the rf prescaler. th is s m all- signal i n pu t is normal ly ac- c oupled from the vco. 7 6 , 7 av dd positive power s u pply for the rf section. decoupling capacitors to the digital ground plane sh o u ld be placed as c l o s e as po ssible to this pin. av dd has a value of 3 v 10%. av dd must have the same v o ltage as dv dd . 8 8 ref in reference input. this is a cmos in put with a nominal threshold of v dd / 2 and an eq uivalent input resistance of 100 k? (see figure 17). this input c a n be driven from a ttl or c m os crystal osci llat o r, or it can be ac- c oupl ed. 9 9, 10 dgnd digital ground. 1 0 1 1 sdv dd -? power. dec o upling capacit o rs to the digital ground plane s h ould be pla c ed as clo s e as p o s s i ble to this pin. sdv dd has a value of 3 v 10%. sdv dd m u st have the sa me voltage as d v dd . 1 1 1 2 c l k se ria l cl oc k in put. th is s e ria l c l oc k is used to clock in the serial data to the regist ers. the data is latched into the shift register on the clk rising edge . this input is a hig h impedance c m os input. 1 2 1 3 d a t a serial data inpu t. the serial data is loaded msb first with the two lsbs as the cont rol bits. this input is a high impedance cmos input. 1 3 1 4 l e load enable, c m os input. when le is high, the data stored in the shift register s is lo aded into one of the four latches, the latch being selected using the control bits. 1 4 1 5 m u x o u t t h is multiplexer output allows e i ther the rf lock detect, the scaled rf, or the scaled reference freq uency to be accessed ex ternally. 1 5 1 6 , 1 7 dv dd positive power supply for the digital section. de coupling ca paci tors to the digital ground plane should be pla c ed as clo s e as p o ssi ble to this pin. dv dd has a value of 3 v 10%. dv dd must have the sam e voltage as av dd . 1 6 1 8 v p charge pump power supply. this shou ld be greater than or eq u a l to v dd . in systems where v dd is 3 v, it can be set to 5.5 v and used to d r ive a vco with a tuning range of up to 5.5 v.
adf4154 rev. 0 | page 7 of 2 0 typical perf orm ance cha r acte ristics f i gur e 5 t o f i gur e 10, a n d f i gur e 12: rf ou t = 1.722 gh z, p f d f r eq uen c y = 26 mh z, i n t = 66, cha n n e l s p acin g = 200 kh z, m o d u l u s = 130, f r ac tio n = 30/1 30, a n d i cp = 5 m a . lo o p b a nd wid t h = 20 kh z, refer e n c e = 26 mh z, v c o = v a r i -l v c o190-175 0t , e v al u a tion b o a r d = e v al -ad f 4154eb1. m e as ur em en ts w e r e ta k e n on t h e hp8562e s p ec tr um a n al yzer . outp ut p o we r (db) 0 ?3 0 ?5 0 ?8 0 ?9 0 ?100 ?6 0 ?7 0 ?4 0 ?2 0 ?1 0 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 26mhz channel step = 200khz loop bandwidth = 20khz lowest noise mode n = 66 30/130 rbw = 10hz re f e r e nc e l evel = ? 4dbm ?102dbc/hz ? 2khz ?1khz 1khz 2khz 1.722ghz 04833-0-004 f i gure 5. p h ase n o i s e (l o w est n o ise m o de) outp ut p o we r (db) 0 ?30 ?50 ?80 ?9 0 ? 100 ?60 ?70 ?40 ?20 ?10 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 26mhz channel step = 200khz loop bandwidth = 20khz low noise and spur mode n = 66 30/130 rbw = 10hz r e f e re nc e l evel = ? 4.2dbm ? 95dbc/hz ? 2khz ?1khz 1khz 2khz 1.722ghz 04833-0-005 f i g u r e 6 . p h a s e no is e ( l o w no i s e m o de a n d s p u r m o de ) outp ut p o we r (db) 0 ?30 ?50 ?80 ?90 ? 100 ?60 ?70 ?40 ?20 ?10 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 26mhz channel step = 200khz loop bandwidth = 20khz lowest spur mode n = 66 30/130 rbw = 10hz r e f e re nc e l evel = ? 4.2dbm ? 90dbc/hz ? 2khz ?1khz 1khz 2khz 1.722ghz 04833-0-006 f i gure 7. p h ase n o i s e (l o w est spur mo de) outp ut p o we r (db) 0 ?30 ?50 ?80 ?90 ?60 ?70 ?40 ?20 ?10 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 26mhz channel step = 200khz loop bandwidth = 20khz lowest noise mode n = 66 30/130 rbw = 10hz r e f e re nc e l evel = ? 4.2dbm ?71dbc@200khz ?400khz ? 200khz 200khz 400khz 1.722ghz ? 100 04833-0-007 f i gure 8. spu r s (l ow est no ise m o de) outp ut p o we r (db) 0 ?30 ?50 ?80 ?90 ? 100 ?60 ?70 ?40 ?20 ?10 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 26mhz channel step = 200khz loop bandwidth = 20khz low noise and spur mode n = 66 30/130 rbw = 10hz re f e r e nc e l evel = ? 4.2dbm ? 74dbc@200khz ?400khz ? 200khz 200khz 400khz 1.722ghz 04833-0-008 f i g u re 9. spu r s (l ow no is e and sp ur m o de) outp ut p o we r (db) 0 ?30 ?50 ?80 ?90 ? 100 ?60 ?70 ?40 ?20 ?10 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 26mhz channel step = 200khz loop bandwidth = 20khz lowest spur noise n = 66 30/130 rbw = 10hz re f e r e nc e l evel = ? 4.2dbm ?400khz ?200khz 200khz 400khz 1.722ghz 04833-0-009 f i gure 10. spurs (l ow est spur m o de)
adf4154 rev. 0 | page 8 of 2 0 ph a se n o ise ( d b c /h z) phase detector frequency (khz) ?130 ?140 ?150 ?160 ?170 100 1000 10000 100000 04833-0-010 f i gure 11. pfd n o is e f l oo r v s . pfd f r eq uenc y (l o w est n o is e mod e ) frequency (ghz) amp l itude (dbm) 5 0 ?5 ?10 ?20 ?15 ?25 ?30 ?35 0 0.5 1.0 1.5 4.0 3.5 3.0 2.5 2.0 4.5 p = 4/5 p = 8/9 04833-0-011 f i g u re 12. r f input s e ns it iv it y v cp (v) 6 0 ?6 i cp (ma) 4 2 ?2 ?4 ?5 ?3 ?1 1 3 5 012345 04833-0-012 f i gure 1 3 . char ge p u m p o u tput ch a r act e ri sti c s r set value (k ? ) ?8 0 ?8 5 ? 110 03 30 25 20 15 10 5 ph a se n o ise ( d b c /h z) ?9 0 ?9 5 5 ? 105 ? 100 04833-0-013 f i g u re 14. phas e n o is e v s . r set temperature(c) ?9 0 ?9 4 ? 104 ?6 0 1 0 0 ?40 ph a se n o ise ( d b c /h z) ?20 0 2 0 4 0 6 0 ?9 6 ?9 8 ?9 2 ? 102 ? 100 80 04833-0-014 f i g u re 15. phas e n o is e v s . t e mper at ure 04833-0-028 time ( s) 100 0 1 02 03 04 05 0 6 06 57 58 59 5 fre q ue ncy (ghz) 1.700 1.696 1.692 1.688 1.684 1.680 1.676 1.672 1.668 1.664 1.660 1.656 1.652 1.648 1.644 1.640 a b f i g u re 16. a ) l o ck tim e i n f a s t -l ock m o de . f a s t count e r = 15 0, l o w spur mo de : a 1 649 .7 mh z t o 16 86 .8 m h z f r e q ue nc y j u m p . f i na l l o o p ba n d wid t h = 6 0 khz b) l o ck tim e w i th t h e pll in no r m a l mode (n on f a st-lo c k), l o w spu r m o de , a 16 49 .7 m h z to 1 6 8 6 .8 mh z f r eque nc y ju mp . f i nal l o op b a ndw i dth = 60 kh z
adf4154 rev. 0 | page 9 of 2 0 circuit description reference input section the r e fer e n c e i n p u t st a g e is sho w n i n f i gur e 1 7 . sw1 an d s w 2 a r e n o r m al ly clos e d s w i t ch es. sw3 is n o r m al ly o p en. w h e n p o w e r - do wn is i n i t ia t e d , sw3 is clos e d a n d s w 1 a n d sw2 a r e o p ene d . this ensur e s t h a t t h e r e f in p i n is n o t l o aded o n po w e r - d o wn . buffer to r counter ref in 100k ? nc sw2 sw3 no nc sw1 power-down control 04833-0-027 f i gure 17. r e ference input stag e rf input stage t h e rf in p u t st a g e is sh o w n in f i gur e 18. i t is f o l l o w ed b y a 2-st a g e limi t i ng a m plif ier t o g e nera t e t h e c u r r en t m o de log i c (cml) clo c k le v e ls n e e d e d fo r t h e p r es caler . bias generator 1.6v agnd av dd 2k ? 2k ? rf in b rf in a 04833-0-015 f i g u re 18. r f input st ag e rf in t di vi der the rf i n t c m os c o un ter a l lo ws a division r a t i o in t h e pll f eed back co un ter . di visio n ra tios f r o m 31 t o 5 11 a r e al lo w e d . int, frac, mod, a n d r relations h ip the int , fr a c , a n d m o d val u es, in co n j u n c t i o n wi t h t h e r co un t e r , m a k e i t p o s s ib le t o g e n e ra t e o u t p u t f r eq uen c ies tha t a r e sp ace d b y f r ac t i o n s o f t h e phas e f r e q ue n c y dete c t o r (pfd). s e e t h e rf s y n t h e si zer : a w o rk e d e x a m ple s e c t io n fo r m o r e info r m a t io n. the rf v c o f r e q uen c y ( rf ou t ) eq ua tio n is ( ) ( ) + = (1) wher e rf ou t is t h e o u t p u t f r e q uen c y o f t h e ext e r n al v o l t a g e c o n t r o ll ed o s c i lla t o r (v co ). ( ) + = 1 ( 2 ) wher e: ref in i s t h e re f e re nc e i n put f r e q u e nc y . d is t h e ref in do ub ler b i t. r is t h e p r es et di vide ra t i o o f b i na r y 4-b i t p r og ra mma b l e re f e re nc e c o u n t e r ( 1 to 1 5 ) . int is t h e p r es et divide r a tio o f b i na r y 9-b i t co u n t e r (31 t o 511). mod is t h e p r es et m o d u l u s r a t i o o f b i na r y 12-b i t p r og ra m- m a b l e fra c coun t e r (2 t o 4095). fr a c is t h e p r eset f r ac tio n al ra tio o f b i n a r y 12-b i t p r ogra m m a b l e fra c co un t e r ( 0 t o m o d ) . rf r counter the 4- b i t rf r co un t e r al lo ws t h e i n p u t r e fer e nce f r e q uen c y (ref in ) to b e d i vide d down to p r o d uce t h e r e fer e n c e clo c k to th e p f d . divisio n ra tios f r o m 1 t o 15 a r e al lo w e d . third order fractional interpolator frac value mod reg int reg rf n-divider n = int + frac/mod from rf input stage to pfd n counter 04833-0-016 f i gure 19. a and b counters phase frequency detector (pfd) and charge pu mp the p f d t a k e s i n p u ts f r o m t h e r co un t e r and n co un t e r an d pro d u c e s an o u tput prop or t i on a l to t h e ph a s e a n d f r e q u e nc y dif f er en ce b e twe e n t h e m . f i gur e 20 is a sim p lif i e d s c h e ma t i c. the p f d i n cl u d es a f i xe d dela y e l emen t t h a t s e t s t h e wi d t h o f t h e a n t i b a c k l a s h pu l s e, w h i c h i s t y pi c a l l y 3 ns . t h i s pu l s e en sur e s t h a t t h e r e is n o de ad zon e i n t h e p f d t r a n sfer f u n c t i o n an d g i ve s a c o ns i s te n t re f e re nc e spu r l e vel. u3 clr2 q2 d2 u2 down up hi hi cp ?i n + in charge pump delay clr1 q1 d1 u1 04833-0-017 f i gur e 2 0 . p f d simpl i f ie d s c hema ti c
adf4154 rev. 0 | page 10 of 20 muxout and lock detect the output multiplexer on the adf4154 allows the user to access various internal points on the chip. the state of muxout is controlled by m3, m2, and m1 (see table 9). figure 21 shows the muxout section in block diagram form. the n-channel, open-drain, analog lock detect should be operated with an external pull-up resistor of 10 k? nominal. when lock has been detected, the lock detect is high with narrow low-going pulses. r-divider output n-divider output analog lock detect dgnd control mux muxout dv dd logic low fast-lock control three-state output digital lock detect 04833-0-018 logic high figure 21. muxout schematic input shift registers the adf4154 digital section includes a 4-bit rf r counter, a 9-bit rf n counter, a 12-bit frac counter, and a 12-bit modulus counter. data is clocked into the 24-bit shift register on each rising edge of clk. the data is clocked in msb first. data is transferred from the shift register to one of four latches on the rising edge of le. the destination latch is determined by the state of the two control bits (c2 and c1) in the shift register. these are the 2 lsbs, db1, and db0, as shown in figure 2. the truth table for these bits is shown in table 5. table 6 shows a summary of how the latches are programmed. program modes table 5 through table 10 show how to set up the program modes in the adf4154. the adf4154 programmable modulus is double-buffered. this means that two events have to occur before the part uses a new modulus value. first, the new modulus value is latched into the device by writing to the r-divider register. second, a new write must be performed on the n-divider register. therefore, when- ever the modulus value is updated, the n-divider register must then be written to so that the modulus value is loaded correctly. table 5. c2 and c1 truth table control bits c2 c1 data latch 0 0 n-divider register 0 1 r-divider register 1 0 control register 1 1 noise and spur register
adf4154 rev. 0 | page 11 of 20 registers table 6. r e gister summar y noise and spur reg db10 db9 db8 db7 db6 db5 db4 db3 db1 db0 c2 (1) c1 (1) t1 t2 t3 t4 t5 t6 t7 t8 noise and spur mode db2 t9 noi s e and s p u r mo de reserved n-divider reg db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 n1 n3 n4 n5 n6 control bits control bits control bits control bits 12-bit rf fractional value db23 db22 db21 n7 n8 n9 9-bit rf integer value n2 fas t -lock fl1 r-divider reg db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 r1 r3 r4 12-bit modulus 4-bit r counter r2 muxout p2 db20 db19 p1 m1 db23 db22 db21 m2 m3 p3 load control r eser ved r eser ved pr esc a l er control reg re fe re nce double r db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) u1 u2 u3 u4 u5 cp0 cp1 cp2 u6 0 0 0 0 cp current setting pd pol a r i t y reserved ldp power - dow n cp t h r ee- st a t e counte r r eset db15 cp3 cp / 2 04833- 0- 019 table 7. noise and s p ur r e gister db10 db9 db8 db7 db6 db5 db4 db3 db1 db0 c2 (1) c1 (1) t1 t2 t3 t4 t5 t6 t7 t8 control bits noise and spur mode db2 t9 nois e and s p u r mo de reserved r eser ved reserved reserved db10, db5, db4, db3 0 noise and spur setting lowest spur mode low noise and spur mode lowest noise mode db9, db8, db7, db6, db2 00000 11100 11111 these bits must be set to 0 for normal operation. 04833-0-023
adf4154 rev. 0 | page 12 of 20 table 8. n-divider register map f12 0 0 0 0 . . . 1 1 1 1 f11 0 0 0 0 . . . 1 1 1 1 f10 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... f3 0 0 0 0 . . . 1 1 1 1 f2 0 0 1 1 . . . 0 0 1 1 f1 0 1 0 1 . . . 0 1 0 1 fractional value (frac) 0 1 2 3 . . . 4092 4093 4094 4095 n9 0 0 0 0 . . . 1 1 1 n8 0 0 0 0 . . . 1 1 1 n7 0 0 0 0 . . . 1 1 1 n6 0 1 1 1 . . . 1 1 1 n5 1 0 0 0 . . . 1 1 1 n4 1 0 0 0 . . ... 1 1 1 n3 1 0 0 0 . . . 1 1 1 n2 1 0 0 1 . . . 0 1 1 n1 1 0 1 0 . . . 1 0 1 integer value (int) 31 32 33 34 . . . 509 510 511 fl1 0 1 fast-lock normal operation fast-lock enabled db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 n1 n3 n4 n5 n6 control bits 12-bit fractional value (frac) db23 db22 db21 n7 n8 n9 9-bit integer value (int) n2 fast-lock fl1 04833-0-020
adf4154 rev. 0 | page 13 of 20 table 9. r-divider register map m12 0 0 0 . . . 1 1 1 1 interpolator modulus value (mod) 2 3 4 . . . 4092 4093 4094 4095 m11 0 0 0 . . . 1 1 1 1 m10 0 0 0 . . . 1 1 1 1 m3 0 0 1 . . . 1 1 1 1 m2 1 1 0 . . . 0 0 1 1 m1 0 1 0 . . . 0 1 0 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... rf r-counter divide ratio 1 2 3 4 . . . 12 13 14 15 r4 0 0 0 0 . . . 1 1 1 1 r3 0 0 0 1 . . . 1 1 1 1 r2 0 1 1 0 . . . 0 0 1 1 r1 1 0 1 0 . . . 0 1 0 1 p1 0 1 prescaler 4/5 8/9 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 r1 r3 r4 control bits 12-bit interpolator modulus value (mod) 4-bit r counter r2 muxout p2 db20 db19 p1 m1 db23 db22 db21 m2 m3 p3 load control reserved prescaler p3 0 1 load control normal operation load fast-lock timer m3 0 0 0 0 1 1 1 1 m2 0 0 1 1 0 0 1 1 m1 0 1 0 1 0 1 0 1 muxout three-state output digital lock detect analog lock detect n-divider output logic high logic low r-divider output fast-lock switch 04833-0-021
adf4154 rev. 0 | page 14 of 20 table 10. co nt rol register ma p u3 0 1 power-down normal operation power-down u4 0 1 ldp 3 5 i cp (ma) 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 cp0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 cp1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 cp0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2.700k ? 1.090 2.180 3.260 4.350 5.440 6.530 7.620 8.700 0.540 1.100 1.640 2.180 2.730 3.270 3.810 4.350 5.100k ? 0.630 1.250 1.880 2.500 3.130 3.750 4.380 5.000 0.310 0.630 0.940 1.250 1.570 1.880 2.190 2.500 10.00k ? 0.290 0.590 0.880 1.150 1.470 1.760 2.060 2.350 0.150 0.300 0.440 0.588 0.740 0.880 1.030 1.180 u5 0 1 pd polarity negative positive u2 0 1 cp three-state disabled three-state u1 0 1 counter reset disabled enabled reference doubler disabled enabled u6 0 1 re fe re nce double db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) u1 u2 u3 u4 u5 cp0 cp1 cp2 u6 0 0 0 0 control bits cp current setting pd pola r i ty reserved ldp pow e r - down cp th r ee- sta t e counte r r eset db15 cp3 cp /2 04833-0-022
adf4154 rev. 0 | page 15 of 20 register definition n-divider register, r0 the on-chip n-divider register is programmed by setting r0[1, 0] to [0, 0]. table 8 shows the input data format for programming this register. 9-bit int value these nine bits control what is loaded as the int value. this is used to determine the overall feedback division factor (see equation 1). 12-bit frac value these 12 bits control what is loaded as the frac value into the fractional interpolator. this value helps determine the overall feedback division factor (see equation 1). the frac value must be less than the value loaded into the mod register. fast-lock setting the part to logic high enables fast-lock mode. to use fast-lock, the required time value for wide bandwidth mode needs to be loaded into the r-divider register. the charge pump current increases from 16 the minimum current and reverts back to 1 the minimum current once the time value loaded has expired. see the fast-lock timer and register sequences section for more information. r-divider register, r1 the on-chip r-divider register is programmed by setting r1[1, 0] to [0, 1]. table 9 shows the input data format for programming this register. load control when set to logic high, the value being programmed in the modulus is not loaded into the modulus. instead, it sets the fast- lock timer. the value of the fast-lock timer/ f pfd is the amount of time the pll stays in wide bandwidth mode. muxout the on-chip multiplexer is controlled by r1[22...20] on the adf4154. table 9 shows the truth table. digital lock detect the digital lock detect output goes high if there are 40 successive pfd cycles with an input error of less than 15 ns. it stays high until a new channel is programmed or until the error at the pfd input exceeds 30 ns for one or more cycles. if the loop bandwidth is narrow compared to the pfd frequency, the error at the pfd inputs may drop below 15 ns for 40 cycles around a cycle slip. therefore, the digital lock detect may go falsely high for a short period until the error again exceeds 30 ns. in this case, the digital lock detect is reliable only as a loss-of-lock detector. prescaler (p/p + 1) the dual-modulus prescaler (p/p + 1), along with the int, frac, and mod counters, determines the overall division ratio from the rf in to the pfd input. operating at cml levels, it takes the clock from the rf input stage and divides it down for the counters. it is based on a synchronous 4/5 core. when set to 4/5, the maximum rf frequency allowed is 2 ghz. therefore, when operating the adf4154 above 2 ghz, this must be set to 8/9. the prescaler limits the int value. with p = 4/5, n min = 31. with p = 8/9, n min = 91. the prescaler can also influence the phase noise performance. if int < 91, a prescaler of 4/5 should be used. for applications where int > 91, p = 8/9 should be used for optimum noise performance (see table 9). 4-bit rf r counter the 4-bit rf r counter allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the phase frequency detector (pfd). division ratios from 1 to 15 are allowed. 12-bit interpolator modulus/fast-lock timer bits db13Cdb2 have two functions depending on the value of the load control bit: modulus or fast lock timer value. when the load control bit = 0 (db23), the required modulus may be programmed into the r-divider register (db13Cdb2). when the load control bit = 1 (db23), the required fast-lock timer value may be programmed into the r-divider register (db13Cdb2). this programmable register sets the fractional modulus, which is the ratio of the pfd frequency to the channel step resolution on the rf output. refer to the rf synthesizer: a worked example section for more information. the adf4154 programmable modulus is double-buffered. this means that two events must occur before the part uses a new modulus value. first, the new modulus value is latched into the device by writing to the r-divider register. second, a new write must be performed on the n-divider register. therefore, when- ever the modulus value is updated, the n-divider register must be written to so that the modulus value is loaded correctly. control register, r2 the on-chip control register is programmed by setting r2[1, 0] to [0, 1]. table 10 shows the input data format for programming this register. rf counter reset db3 is the rf counter reset bit for the adf4154. when this is 1, the rf synthesizer counters are held in reset. for normal operation, this bit should be 0.
adf4154 rev. 0 | page 16 of 20 rf charge pump three-state this bit puts the charge pump into three-state mode when programmed to 1. it should be set to 0 for normal operation. rf power-down db4 on the adf4154 provides the programmable power-down mode. setting bit db4 to 1 powers down the device. setting bit db4 to 0 returns the synthesizer to normal operation. while in software power-down mode, the part retains all information in its registers. only when supplies are removed are the register contents lost. when a power-down is activated, the following events occur: 1. all active dc current paths are removed. 2. the synthesizer counters are forced to their load state conditions. 3. the charge pump is forced into three-state mode. 4. the digital lock detect circuitry is reset. 5. the rf in input is de-biased. 6. the input register remains active and capable of loading and latching data. lock detect precision (ldp) when the ldp bit is programmed to 0, 24 consecutive reference cycles of 15 ns must occur before the digital lock detect is set. when this bit is programmed to 1, 40 consecutive reference cycles of 15 ns must occur before digital lock detect is set. phase detector polarity db6 in the adf4154 sets the phase detector polarity. when the vco characteristics are positive, this should be set to 1. when they are negative, it should be set to 0. charge pump current setting db7, db8, db9, and db10 set the charge pump current, which should be set according to the loop filter design (see table 10). ref in doubler setting the ref in bit to 0 feeds the ref in signal directly to the 4-bit rf r counter, which disables the doubler. setting the ref in bit to 1 multiplies the ref in frequency by a factor of 2 before feeding into the 4-bit r counter. when the doubler is disabled, the ref in falling edge is the active edge at the pfd input to the fractional synthesizer. when the doubler is enabled, both the rising and falling edges of ref in become active edges at the pfd input. when the doubler is enabled and the lowest spur mode is chosen, the in-band phase noise performance is sensitive to the ref in duty cycle. the phase noise degradation can be as much as 5 db for the ref in duty cycles outside a 45% to 55% range. the phase noise is insensitive to the ref in duty cycle in the lowest noise mode and in the lowest noise and spur mode. the phase noise is insensitive to the ref in duty cycle when the doubler is disabled. noise and spur register, r3 the on-chip noise and spur register is programmed by setting r3[1, 0] to [1, 1]. table 7 shows the input data format for programming this register. noise and spur mode noise and spur mode allows the user to optimize a design either for improved spurious performance or for improved phase noise performance. when the lowest spur setting is chosen, dither is enabled. this randomizes the fractional quantization noise so that it looks more like white noise rather than spurious noise. this means that the part is optimized for improved spurious performance. this operation would normally be used when the pll closed-loop bandwidth is wide for fast-locking applications. a wide-loop bandwidth is seen as a loop bandwidth greater than 1/10 of the rf out channel step resolution (f res ). a wide-loop filter does not attenuate the spurs to a level that a narrow-loop bandwidth would. when the low noise and spur setting is enabled, dither is disabled. this optimizes the synthesizer to operate with improved noise performance. however, the spurious performance is degraded in this mode compared to the lowest spurs setting. to further improve noise performance, the lowest noise setting option can be used, which reduces the phase noise. as well as disabling the dither, it ensures that the charge pump operates in an optimum region for noise performance. this setting is extremely useful where a narrow-loop filter bandwidth is available. the synthesizer ensures extremely low noise and the filter attenuates the spurs. the typical performance characteristics give the user an idea of the trade-off in a typical wcdma setup for the different noise and spur settings. reserved bits these bits should be set to 0 for normal operation. rf synthesizer: a worked example this equation governs how the synthesizer should be programmed. rf out = [ int + ( frac/mod )] [ f pfd ] (3) where: rf out is the rf frequency output. int is the integer division factor. frac is the fractionality. mod is the modulus. f pfd = [ ref in (1 = d)/r ] (4) where: ref in is the reference frequency input. d is the rf ref in doubler bit. r is the rf reference division factor.
adf4154 rev. 0 | page 17 of 20 f o r exa m p l e , in a gs m 1800 syst em , w h er e a 1.8 gh z rf fr e q u e n c y o u t p u t ( r f ou t ) i s re qu i r e d , a 1 3 m h z re f e re n c e fr e q u e n c y i n p u t ( r e f in ) is a v a i l a b l e an d a 200 kh z c h ann e l re s o lut i on ( f res ) is r e q u ir e d o n t h e rf o u t p ut. 65 khz 200 mhz 13 = = = mod f ref mod res in f rom e q u a t i on 4 , f pf d = [13 mh z (1 + 0)/1] = 1 3 mh z (5) ( ) 30 ; 138 65 mhz 13 8 . 1 = = + = frac int frac int g ( 6 ) modulus t h e c h oi c e of m o d u lu s ( m od ) d e p e nd s o n t h e re f e re nc e s i g n a l (ref in ) a v a i l a b l e a nd t h e chan nel r e s o l u t i o n ( f re s ) r e q u ir ed a t th e r f o u t p u t . f o r e x a m p l e , a gs m s y s t em wi th 13 mh z r e f in w o u l d s et t h e mo d u l u s t o 65, r e s u l t in g i n t h e r f o u t p u t r e s o l u - ti o n (f res ) o f 20 0 kh z (13 mh z/65) tha t is n e ces s a r y f o r gs m. reference doubler an d refere nce di vi de r t h e re f e re nc e d o ubl e r on - c h i p a l l o w s t h e i n put re f e re nc e s i g n a l t o b e doub le d . this is us ef u l fo r in cr e a sin g t h e pfd co m p a r is on f r eq ue n c y . m a kin g th e p f d f r eq ue n c y h i g h e r im p r o v e s th e n o is e p e r f o r ma n c e o f t h e sys t e m . d o ub l i n g t h e p f d f r e q uen c y u s u a l l y re su lt s i n an i m prove m e n t i n noi s e p e r f or m a nc e of 3 d b . i t is im p o r t an t to n o t e t h a t t h e p f d ca nn ot b e o p era t e d ab o v e 32 mh z d u e t o a limi t a t i o n i n t h e sp e e d o f t h e - cir c ui t o f t h e n divi der . 12-bit programmable modulus u n li k e m o s t o t h e r f r ac tio n al-n p lls, t h e adf4154 al lo ws th e us er t o p r og ra m t h e m o d u l u s o v er a 12-b i t ra n g e . this m e a n s t h a t t h e us er can s et u p t h e p a r t in man y dif f er en t co nf igura- ti o n s f o r th e a p p l i c a t i o n , w h en co m b in e d w i t h th e r e f e r e n c e do ub ler an d t h e 4-b i t r co u n ter . f o r exa m ple , co n s ider a n a p plic a t io n t h a t r e q u i r es a 1.75 gh z rf a nd a 200 kh z c h ann e l s t ep r e s o l u tio n . th e sys t em has a 1 3 m h z re f e re n c e s i g n a l . on e p o s s i b l e s e t u p is fe e d in g t h e 13 mh z dir e c t ly t o t h e p f d a nd p r o g r a mmi n g t h e mo d u l u s to divide b y 65, w h ich w o u l d r e s u l t in t h e r e q u ir ed 200 kh z res o l u tio n . an o t h e r p o ssib le s e t u p is usin g t h e r e fer e n c e doub ler t o cr e a t e 26 mh z f r o m t h e 13 m h z in p u t sig n al . th e 2 6 mh z sig n al is th en f e d in t o t h e p f d , wh i c h p r ogra m s th e m o d u l u s t o d i v i de b y 130. this s e t u p als o r e s u l t s in 200 kh z r e s o l u tio n and o f f e rs s u p e r i o r phas e n o is e p e r f o r ma n c e o v er t h e p r e v io us s e t u p . t h e p r ogra m m a b le m o d u l u s is also v e r y usef ul f o r m u l t i- s t anda r d a p plic a t io n s . i f a d u a l - m o d e ph on e r e q u ir es p d c and gs m 1800 s t anda r d s, t h e p r og ra mma b l e mo d u l u s is a h u g e b e n e f i t. th e pd c r e q u ir es a 25 kh z cha n ne l s t e p r e s o l u t i o n , wher eas t h e gs m 1800 r e q u ir es a 200 kh z c h anne l s tep re s o lut i on . a 1 3 m h z re f e re n c e s i g n a l c o u l d b e f e d d i re c t ly to th e p f d . the mo d u l u s w o u l d b e p r og ra mm e d to 520 wh en in p d c m o de (13 mh z/520 = 25 kh z). th e m o d u l u s w o u l d be r e p r og ra mm ed t o 65 f o r gs m 1800 o p era t ion (13 mh z/65 = 200 kh z). i t is im p o r t a n t tha t th e p f d f r eq uenc y r e ma in s co n- s t a n t (13 mh z). b y k e ep i n g t h e p f d co n s t a n t , t h e us er can desig n a o n e-lo o p f i l t er tha t c a n b e us ed in bo t h s e t u ps wi t h o u t r u nnin g in t o s t ab i l i t y is s u es. the ra t i o o f t h e rf f r e q uen c y t o th e p f d f r eq ue n c y a f f e ct s th e loo p d e s i gn . k eep i n g th i s r e la ti o n s h i p co n s ta n t i n s t ead o f c h a n gi n g t h e m o d u l u s fa ct o r re su l t s in a st abl e f i l t e r . spurious optim i zation and fast-lock the ad f4154 c a n be o p timize d f o r l o w s p ur io u s sig n als b y usin g t h e n o is e a nd sp ur r e g i ste r . h o w e v e r , in o r der t o achie v e fa s t - l ock tim e , a w i d e r loo p ba n d wi d t h i s n eede d . n o t e th a t a wider lo o p b a nd w i d t h can le ad to n o t a b l e sp ur io us sig n a l s, w h ich ca n n ot b e r e d u ce d sig n if ica n t l y b y t h e lo o p f i l t er . u s in g t h e fas t -l o c k fe a t ur e can achie v e t h e s a me fas t -lo c k t i me as t h e n o i s e and s p ur r e g i s t er , b u t w i t h t h e ad van t a g e o f lo w e r s p ur io us sig n als , sin c e t h e f i nal l o o p ban d wid t h is r e d u ced b y a q u a r ter . fast-lock timer and register sequences i f th e fas t - l ock m o de i s used , a ti m e r v a l u e n e e d s t o be loa d e d in t o t h e p l l t o det e r m i n e t h e t i m e o f t h e wide b a ndwi d t h . w h en t h e lo ad co n t r o l b i t = 1, t h e t i mer val u e i s lo ade d v i a t h e 12-b i t m o d u l u s val u e . t o us e fast-lo c k, t h e p l l m u s t b e wr i t t e n t o in t h e fol l o w in g s e q u e n ce: 1. loa d t h e r- d i v i d e r r e g i s t e r wi t h d b 23 = 1 a n d th e ch os en fa s t - l ock tim e r v a l u e (d b 13C d b 2) i n s t ead o f th e m o d u l u s . n o t e tha t t h e d u ra ti o n o f tim e th e p l l r e m a in s i n w i d e ba n d w id th i s e q ual t o th e fa s t - l oc k tim e r/ f pfd . 2. loa d t h e no i s e an d s p ur re g i st er . 3. loa d t h e co n t r o l r e gi s t e r . 4. loa d r- d i v i d e r r e g i s t e r wi th d b 23 = 0 a nd m u x o ut = 110 (d b22Cd b 20). al l th e o t her n eeded p a ramet e rs, in c l u d in g t h e mo d u l u s, als o n e e d t o b e lo aded . 5. loa d t h e n- div i de r r e g i st e r , in cl ud i n g fas t - l ock = 1 ( d b 2 3 ) , to ac t i v a te f a st - l o c k mo de. on ce t h is p r o c e d ur e is co m p leted , f u t u r e f r eq u e n c y j u m p s d e pl oy i n g f a st - l o c k ne e d to re p e a t on ly ste p 5 .
adf4154 rev. 0 | page 18 of 20 i f fas t -lo c k is n o t us e d , t h en us e t h e fol l o w in g s e q u en c e : 1. loa d t h e no i s e an d s p ur re g i st er . 2. loa d t h e co n t r o l r e gi s t e r . 3. loa d t h e r- d i v i d e r r e g i s t e r wi t h d b 23 = 0 a n d o t h e r ne c e ss ar y p a r a me te r s . 4. loa d t h e n- div i de r r e g i st e r , in cl ud i n g fas t - l ock = 0 (d b23) f o r n o rm al o p era t io n . t o c h a n ge f r eq uen c y , o n l y s t ep 4 n e e d be r e p e a t ed . fast-lock: a worked example c o n s ider a n exam ple i n w h ich p ll has r e fer e nce f r e q uen c ies of 13 mh z and f pf d = 13 mh z a n d a r e q u ir ed lo ck time o f 50 s. ther efo r e , t h e pll is s et t o wide b a ndwi d t h fo r 40 s. i f th e tim e pe riod ch ose n f o r th e w i de ba n d w id th i s 40 s , t h en f a st - l o c k t i me r v a lu e = t i me i n w i d e b a nd w i d t h f pf d f a s t -lo c k t i m e r val u e = 40 s 13 mh z = 520 ther ef o r e , 520 has t o b e lo aded in t o t h e r - di vider r e g i s t er in s t ep 1 o f t h e s e q u en c e des c r i b e d in t h e f a s t - l o c k t i m e r and reg i st er s e q u ences s e c t io n. fast-lo c k: loop f i lter topology t o us e fast-lo c k m o de , a n ext r a co nne c t io n f r om t h e p ll t o t h e lo o p f i l t er is n e e d e d . the mux o ut m u s t r e d u ce t h e da m p in g re s i stor i n t h e l o op f i lte r to ? w h i l e i n w i d e b a n d w i d t h mo d e . this is r e q u ir e d b e c a us e t h e ch arge p u m p c u r r e n t is i n cr e a s e d b y 16 wh ile i n w i de ba n d w i d t h m o de a n d s t a b i l i t y m u s t b e en s u r e d . this can b e don e w i t h t h e fol l o w in g two t o p o log i es: 1. di vi de t h e dam p in g r e sisto r ( r 1) in to tw o va l u es ( r 1 a nd r1a) o f ra tio 1:3 (s ee f i gur e 22). 2. u s e an e x t r a re s i stor ( r 1 a ) a n d c o n n e c t it d i re c t ly f rom t h e m u x o u t , a s s h ow n i n f i g u re 2 2 . t h e e x t r a re s i stor m u st be ch os en s u c h tha t t h e p a ral l e l co m b ina t io n o f a n extra re s i stor an d t h e d a m p i n g re s i sto r ( r 1 ) i s re d u c e d to ? of t h e or i g i n a l v a lu e of r 1 a l one ( s e e f i g u re 2 3 ) . adf4154 cp muxout c1 c2 r2 r1 r1a c3 vco 04833-0-029 f i g u re 22 f a s t -lock l oop f ilt er t o po log y t opo l og y 1 adf4154 cp muxout c1 c2 r2 r1 r1a c3 vco 04833-0-030 f i g u re 23. f a s t -lo c k l oop f ilt er t o po l o g y t opol og y 2 spurious s i gnals predi c ting wh ere th ey ap pe ar a s in in t e g e r - n p lls, s p ur s a p p e a r a t p f d f r eq ue n c y o f fse t s f rom t h e c a r r i e r . i n a f r a c t i on a l - n pl l , spu r s a l s o a p p e ar a t f r eq ue n c i e s eq ual t o th e r f ou t c h a n n e l st ep r e s o l u tio n (f res ). the thir d-o r d er f r ac tio n al in t e r p ola t o r en g i n e o f th e ad f4154 m a y also i n tr o d uce s u b f ra cti o nal s p ur s . i f th e f r a c ti o n al d e n o - m i n a t o r (m o d ) is d i visi b l e b y 2, s p ur s a p p e a r a t ? f res . if t h e f r ac t i o n a l den o mina to r ( m od) is di vis i b l e b y 3, sp urs a p p e a r a t 1/3 f res . h a r m onics o f al l s p urs m e n t ion e d als o a p p e a r . w i t h t h e lo w e st sp ur m o de ena b le d , t h e f r ac t i o n a l a nd sub f r a c t io na l s p urs a r e a t t e n u a t e d dra m a t i c al ly . th e w o rst-c a s e s p urs a p p e a r when t h e f r ac tio n is p r og ra mmed t o 1/m o d . f o r exa m p l e , in a gs m 900 mh z sys t em wi th a 26 mh z p f d f r eq uen c y an d a n rf ou t ch an nel s t e p re s o lut i on ( f res ) o f 200 kh z, th e m o d = 130 . p f d s p urs a p p e a r a t 26 mh z o f fs et a nd f r ac tio n al s p urs a p p e ar a t 200 kh z o f fs et. s i nce t h e m o d is divisib l e b y 2, s u b f rac t io nal s p urs a r e als o p r es en t a t 100 kh z o f fs et. filter designadisimpll a f i l t er desig n and a n al ysis p r og ra m is a v a i lab l e t o he l p t h e us er im ple m e n t t h e p l l desig n . v i si t w w w . a n alog.c o m /pl l fo r a f r e e do wn lo ad o f t h e ad i s impll s o f t wa r e . th e s o f t wa r e desig n s, sim u l a t e s, an d analyzes t h e en t i r e p l l f r e q uen c y a n d t i m e d o m a i n re sp ons e . v a r i ou s p a ss ive an d a c t i ve f i lte r arch ite c tu re s a r e allo w e d . r e v . 2 o f a d i s i m p l l allo w s a n al ysi s o f th e ad f4154. interfacing the ad f4154 has a sim p le , s p i? co m p a t i b le s e r i al in t e r f ace f o r w r i t i n g t o t h e d e v i c e . s c l k , s d a t a , a n d l e c o n t r o l t h e d a t a t r a n sfer . w h en le (la t ch enab le ) is hig h , t h e 22 b i ts t h a t ha v e been c l ock e d i n t o th e in p u t r e gis t e r o n ea ch ri s i n g ed g e o f sclk a r e t r an sfer r e d t o t h e a p pr o p r i a t e la t c h. s e e f i gur e 2 fo r th e tim i n g di a g ra m a n d t a b l e 5 f o r th e la t c h tr u t h ta b l e . the max i m u m a l lo wa ble s e r i a l clo c k r a te is 20 mh z. t h is m e an s t h a t t h e maxim u m u p da t e ra te p o s s ib le fo r t h e de vice is 909 kh z o r o n e u p da te ever y 1.1 s. this is m o r e tha n ade q u a te fo r sys t em s t h a t ha v e typ i cal lo ck t i m e s in t h e h u n d r e ds o f micr o s e c o n ds .
adf4154 rev. 0 | page 19 of 20 aduc812 interface adsp-21xx adf4154 sclock sclk sdata le muxout (lock detect) dt tfs i/o flags 04833-0-025 f i gur e 24 s h o w s th e in t e r f ace betw een t h e ad f 4154 a nd the aduc812 m i croc o n v e r t er?. s i n c e t h e aduc8 12 is bas e d o n an 8051 co r e , this in t e r f ace c a n be us ed wi t h an y 8051-bas e d micr o c o n t r ol ler . the micr oc o n v e r t er is s et u p fo r s p i mas ter m o de wi t h cph a = 0. t o ini t i a t e t h e op era t ion, b r in g t h e i/ o p o r t dr i v ing le lo w . e a c h la t c h o f th e ad f4154 n eeds a 24-b i t w ord , w h i c h i s a c c o m p l i s h e d by w r it i n g t h re e 8 - bi t by t e s f r om t h e mi c r o c on v e r t e r to t h e d e v i c e . a f te r t h e t h i r d b y te i s w r i tte n, th e l e in p u t s h o u ld be b r o u gh t h i gh t o co m p let e th e tra n s f e r . f i gur e 2 5 . adsp -21xx t o adf415 4 int e r f a c e pcb desig n guideline s for chip scale pack age w h en o p era t i n g in t h e m o de des c r i b e d , t h e maxim u m scl o ck ra te of th e adu c 812 is 4 mh z. this m e an s tha t the maxim u m ra te a t w h ich t h e ou t p u t f r e q uen c y c a n b e chan g e d i s 180 kh z. the lan d s on t h e chi p s c ale p a cka g e (c p - 20) a r e r e c t a n gu la r . the p r in te d cir c ui t b o a r d p a d for t h es e sh o u ld b e 0.1 mm lo n g e r th a n th e pa c k a g e la n d len g th a n d 0. 05 m m w i d e r th a n t h e p a cka g e land w i d t h. th e l a nd sh o u ld b e ce n t er e d o n t h e p a d . this ens u r e s t h a t t h e s o lder jo i n t si ze is maxi mize d . aduc812 adf4154 sclock sclk sdata le muxout (lock detect) mosi i/o ports 04833-0-024 the b o t t o m o f t h e chi p s c ale p a cka g e has a ce n t ral t h er mal p a d . the t h er mal p a d o n t h e p r i n t e d cir c ui t b o a r d sh o u ld b e a t le ast as la rg e as t h is e x p o s e d p a d . o n t h e p r in t e d cir c ui t b o a r d , t h er e s h o u ld b e a cle a ra n c e o f a t le as t 0.25 mm b e tw e e n t h e t h er mal p a d an d t h e in ner e d ges o f t h e p a d p a t t er n to a v o i d sh o r t i n g . ther mal v i as ma y b e us e d on t h e p r i n t e d cir c ui t b o a r d t h er mal p a d t o im p r o v e t h er mal p e r f o r ma nce o f t h e p a cka g e . i f vi as a r e used , th ey s h o u ld b e in co r p o r a t ed in t o th e t h e r m a l pa d a t 1.2 mm pi t c h g r id . th e v i a diamet er s h o u ld b e b etw e e n 0.3 mm a nd 0.33 mm, and the via ba r r el s h o u ld be pla t ed wi t h 1 oz. o f co p p er t o pl ug t h e v i a . f i gur e 2 4 . aduc812 to adf415 4 int e r f a c e adsp-2181 interface f i gur e 25 s h o w s th e in t e r f ace betw een t h e ad f 4154 a nd the ads p -21x x dig i t a l sig n a l p r o c ess o r . a s dis c uss e d p r e v io usly , t h e ad f4154 n e e d s a 24-b i t s e r i al w o r d f o r eac h la t c h wr i t e . the ea s i e s t wa y t o acco m p li s h th i s us i n g th e a d s p - 21xx fa m i l y i s t o use th e a u t o b u f f e r ed tra n s m i t m o d e o f o p e r a t i o n wi th al t e rn a t e f r am i n g . t h i s prov i d e s a me ans for t r ans m i t t i n g an e n t i re bl o c k o f s e r i al da ta bef o r e a n in ter r u p t is g e n e r a t e d . s et u p the w o r d len g t h fo r eig h t b i ts an d us e t h re e me m o r y lo ca t i o n s fo r e a ch 2 4 - bit word. t o pro g r a m e a ch 2 4 - b it l a tc h , store e a ch of t h e t h r e e 8-b i t b y t e s , ena b le t h e a u t o b u f f er e d mo de , a nd wr i t e t o t h e tra n s m i t r e gis t er o f th e d s p . t h i s la s t o p e r a t i o n i n i t ia t e s t h e a u t o b u f f er t r a n sfer . the us er s h o u ld co nne c t t h e p r i n t e d cir c ui t b o ar d t h er mal p a d to a g nd .
adf4154 rev. 0 | page 20 of 20 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153ab f i gure 26. 1 6 -l ead thin shr i nk s m a l l o u tline p a ckage [ t ssop ] (ru - 16) di me nsio ns sho w n i n mi ll im e t e r s 1 20 5 6 11 16 15 bottom view 10 2.25 2.10 sq 1.95 0.75 0.55 0.35 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0. 80 m a x 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicator top view 3.75 bs c s q 4.0 bsc sq coplanarity 0.08 0.60 max 0.60 max 0 . 2 5 mi n compliant to jedec standards mo-220-vggd-1 f i gure 27. 2 0 -l ead l e ad f r a m e ch ip s c a l e p a ck ag e [lfcs p ] 4 mm 4 m m b o d y , (cp - 2 0 ) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model description temperature r a nge package option adf4154bru thin shrink small outline package (tssop) ?40c to +85c ru-16 adf4154bru-r eel thin shrink small outline package (tssop) ?40c to +85c ru-16 adf4154bru-r eel7 thin shrink small outlin e package (tssop) ?40c to +85c ru-16 adf4154bcp lead frame chip scale pa ckage (lfcsp) ?40c to +85c cp-20 adf4154bcp-re el lead frame chip scale package (lfcsp) ?40c to +85c cp-20 adf4154bcp-re el7 lead frame chip scale package (lfcsp) ?40c to +85c cp-20 eval-adf4154 e b 1 p u r c hase of lic e nsed i 2 c componen t s of ana l og d e vices, i n c . or one of its subl ic ensed a s s o cia t ed c o mpanie s c o n v ey s a l i c e ns e f o r the p u r c hase r un der t he philips i 2 c p a t e n t r i g h ts t o use these c o mponen ts in an i 2 c sy st em, pr ovided th a t the sy stem c o nf orms to th e i 2 c standar d specifica t ions as defin e d by p h ilips. ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . d04833C0C 4/04(0)

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