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edi2ag27264v 1 megabyte sync/sync burst, small outline dimm 1 edi2ag27264v rev. 0 1/98 eco# the edi2ag27264vxxd1 is a synchronous/synchro- nous burst sram, 72 position so-dimm (144 contacts) module, organized as 2x64kx72. the module contains four(4) synchronous burst ram devices, packaged in the industry standard jedec 14mmx20mm tqfp placed on a multilayer fr4 substrate. the module architecture is defined as a sync/sycn burst, flow-through, with support for linear burst. this module provides high performance, 2- 1-1-1 accesses when used in burst mode, and used as a synchronous only mode, provides a high performance cost advantage over bicmos aysnchronous device architec- tures. synchronous only operations are performed via strap- ping adsc\ low, and adsp\ / adv\ high, which pro- vides for ultra fast accesses in read mode while provid- ing for internally self-timed early writes. synchronous/synchronous burst operations are in rela- tion to an externally supplied clock, registered address, registered global write, registered enables as well as an asynchronous output enable. this module has been defined with full flexibility, which allows individual control of each of the eight bytes, as well as quad words in both read and write operations. ? 2x64kx72 synchronous, synchronous burst ? flow-through architecture ? linear burst mode ? clock controlled registered bank enables (e1\,e2\) ? clock controlled byte write mode enable (bwe\) ? clock controlled byte write enables (bw1\ - bw8\) ? clock controlled registered address ? clock controlled registered global write (gw\) ? aysnchronous output enable (g\) ? internally self-timed write ? gold lead finish ? 3.3v + 10% operation ? access speed(s): tkhqv=8.5, 9, 10, 12ns ? common data i/o ? high capacitance (30pf) drive, at rated access speed ? single total array clock ? multiple vcc and gnd advanced module features dq0-dq63 input/output bus dqp0-dqp7 parity bits a0-a15 address bus e1\, e2\, synchronous bank enables bwe\ byte write mode enable bw1\-bw8\ byte write enables clk array clock gw\ synchronous global write enable g\ asynchronous output enable vcc 3.3v power supply vss gnd pin names electronic designs incorporated ? one research drive ? westborough, ma 01581usa ? 508-366-5151 ? fax 508-836-4850 ? electronic designs europe ltd. ? shelley house, the avenue ? lightwater, surrey gu18 5rf united kingdom ? 01276 472637 ? fax: 01276 473748 http://www.electronic-designs.com advanced 2x64kx72, 3.3v sync/sync burst flow-through
edi2ag27264v 1 megabyte sync/sync burst, small outline dimm 2 edi2ag27264v rev. 0 1/98 eco# pin configuration pin pin pin pin function function function function 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 vss vss a0 rfu rfu a1 a2 a15 a14 a3 a4 a13 a12 a5 a6 a10 a8 vcc g\ gw\ adsp\ e1\ e2\ bw\ vcc dq0 dq1 dq2 dq3 vss bw2\ vcc dq8 dq9 dq10 dq11 vss bw3\ vcc dq16 dq17 dq18 dq19 vss bw4\ vcc dq24 dq25 dq26 dq27 vss bw5\ vcc dq32 dq33 dq34 dq35 vss bw6\ vcc dq40 dq41 dq42 dq43 vss bw7\ vcc dq48 dq49 dq50 dq51 vss bw8\ vcc dq56 dq57 dq58 dq59 vss vss dq60 dq61 dq62 dq63 vcc dqp7 vss dq52 dq53 dq54 dq55 vcc dqp6 vss dq44 dq45 dq46 dq47 vcc dqp5 vss dq36 dq37 dq38 dq39 vcc dqp4 vss dq28 dq29 dq30 dq31 vcc dqp3 vss dq20 dq21 dq22 dq23 vcc dqp2 vss dq12 dq13 dq14 dq15 vcc dqp1 vss dq4 dq5 dq6 dq7 vcc dqp0 bwe\ clk adsc\ adv\ rfu vcc a9 a7 a11 1 2 3 4 5 6 7 8 9
edi2ag27264v 1 megabyte sync/sync burst, small outline dimm 3 edi2ag27264v rev. 0 1/98 eco# functional block diagram adsc\ adsp\ adv\ bwe\ clk g\ gw\ a0-a15 adsc\ adsp\ adv\ bwe\ clk g\ gw\ dq e\ bw\ e1\ bw1\-bw4 adsc\ adsp\ adv\ bwe\ clk g\ gw\ dq e\ bw\ adsc\ adsp\ adv\ bwe\ clk g\ gw\ dq e\ bw\ adsc\ adsp\ adv\ bwe\ clk g\ gw\ dq e\ bw\ u1 u2 u3 u4 e2\ bw5\-bw8 dq0-dq31 dqp0-dqp3 dq32-dq63 dqp4-dqp7 dq32-dq63 dqp4-dqp7 dq0-dq31 dqp0-dqp3
edi2ag27264v 1 megabyte sync/sync burst, small outline dimm 4 edi2ag27264v rev. 0 1/98 eco# pin descriptions dimm pins symbol type description 3, 6, 7, 10, 11 a0-a15 input addresses: these inputs are registered and must meet the setup and hold 14, 15, 18, 19, 20 synchronous times around the rising edge of clk. the burst counter generates internal 17, 16, 13, 12, 9, 8 addresses associated with a0 and a1, during burst and wait cycle. 33, 47, 61 bw1\, bw2\, input byte write: a byte write is low for a write cycle and high for a read 75, 89, 103 bw3\, bw4\, synchronous cycle. bw0/ controls dq0-7 and dqp0, bw1\ controls dq8-15 and dqp1. 117, 131 bw5\, bw6\, bw2\ controls dq16-23 and dqp2. bw3\ controls dq24-31 and dqp3. bw7\, bw8\ bw4\ controls dq32-39 and dqp4. bw5\ controls dq40-47 and dqp5. bw6\ controls dq48-55 and dqp6. bw7\ controls dq56-64 and dqp7. 32 bwe\ input write enable: this active low input gates byte write operations and must synchronous meet the setup and hold times around the rising edge of clk. 25 gw\ input global write: this active low input allows a full 72-bit write to occur synchronous independent of the bwe\ and bwx\ lines and must meet the setup and hold times around the rising edge of clk. 30 clk input clock: this signal registers the addresses, data, chip enables, write control synchronous and burst control inputs on its rising edge. all synchronous inputs must meet setup and hold times around the clocks rising edge. 29, 31 e1\, e2\ input bank enables: these active low inputs are used to enable each individual synchronous bank and to gate adsp\. 23 g\ input output enable: this active low asynchronous input enables the data output drivers. 26 adv\ input address status processor: this active low input is used to control the synchronous internal burst counter. a high on this pin generates wait cycle (no address advance). 27 adsp\ input address status processor: this active low input, along with el\ and eh\ synchronous being low, causes a new external address to be registered and a read cycle is initiated using the new address. 28 adsc\ input address status controller: this active low input causes device to be de- synchronous selected or selected along with new external address to be registered. a read or write cycle is initiated depending upon write control inputs. various dq0-63 input/output data inputs/outputs: first byte is dq0-7, second byte is dq8-15, third byte is dq16-23, fourth byte is dq24-31, fifth byte is dq32-39, sixth byte is dq40-47, seventh byte is dq48-55 and the eight byte is dq56-64. 34, 48, 62 dqp0-7 input/output parity inputs/outputs: dqp0 is parity bit for dq0-7. dqp1 is parity bit for dq8-15 76, 90, 104 dqp2 is parity bit for dq16-23. dqp3 is parity bit for dq24-31. dqp4\ is parity bit 118, 132 for dq32-39. dqp5 is parity bit fordq40-47. dqp6\ is parity bit fordq48-55. dqp7 is parity bit for dq56-64 and dqp7. in order to use the device configured as a 128kx64, the parity bits need to be tied to vss through a 10k ohm resistor. various vcc supply core power supply: +3.3v -5%/+10% various vss ground ground
edi2ag27264v 1 megabyte sync/sync burst, small outline dimm 5 edi2ag27264v rev. 0 1/98 eco# synchronous burst - truth table operation e1\ e2\ adsp\ adsc\ adv\ gw\ g\ clk dq addr. used deselected cycle, power down; bank 1 h x x l x x x l-h high-z none deselected cycle, power down; bank 2 x h x l x x x l-h high-z none read cycle, begin burst; bank 1 l h l x x x l l-h q external read cycle, begin burst; bank 1 l h l x x x h l-h high-z external read cycle, begin burst; bank 2 h l l x x x l l-h q external read cycle, begin burst; bank 2 h l l x x x h l-h high-z external write cycle, begin burst; bank 1 l h h l x l x l-h d external write cycle, begin burst; bank 2 h l h l x l x l-h d external read cycle, begin burst; bank 1 l h h l x h l l-h q external read cycle, begin burst; bank 1 l h h l x h h l-h high-z external read cycle, begin burst; bank 2 h l h l x h l l-h q external read cycle, begin burst; bank 2 h l h l x h h l-h high-z external read cycle, continue burst; bank 1 x h x h l h l l-h q next read cycle, continue burst; bank 1 x h x h l h h l-h high-z next read cycle, continue burst; bank 2 h x x h l h l l-h q next read cycle, continue burst; bank 2 h x x h l h h l-h high-z next read cycle, continue burst; bank 1 h h x h l h l l-h q next read cycle, continue burst; bank 1 h h x h l h h l-h high-z next read cycle, continue burst; bank 2 h h x h l h l l-h q next read cycle, continue burst; bank 2 h h x h l h h l-h high-z next write cycle, continue burst; bank 1 x h h h l l x l-h d next write cycle, continue burst; bank 1 h h x h l l x l-h d next write cycle, continue burst; bank 2 h x h h l l x l-h d next write cycle, continue burst; bank 2 h h x h l l x l-h d next read cycle, suspend burst; bank 1 x h h h h h l l-h q current read cycle, suspend burst; bank 1 x h h h h h h l-h high-z current read cycle, suspend burst; bank 2 h x h h h h l l-h q current read cycle, suspend burst; bank 2 h x h h h h h l-h high-z current read cycle, suspend burst; bank 1 h h x h h h l l-h q current read cycle, suspend burst; bank 1 h h x h h h h l-h high-z current read cycle, suspend burst; bank 2 h h x h h h l l-h q current read cycle, suspend burst; bank 2 h h x h h h h l-h high-z current write cycle, suspend burst; bank 1 x h h h h l x l-h d current write cycle, suspend burst; bank 1 h h x h h l x l-h d current write cycle, suspend burst; bank 2 h x h h h l x l-h d current write cycle, suspend burst; bank 2 h h x h h l x l-h d current *all truth table functions repeat for bank 3 (e3\) and bank 4 (e4\)
edi2ag27264v 1 megabyte sync/sync burst, small outline dimm 6 edi2ag27264v rev. 0 1/98 eco# max description sym typ 8.5 9 10 12 units power supply current icc1 1.55 1.2 1.1 1.1 1.0 a power supply current icc 700 950 800 750 700 a device selected,no operation cmos standby icc3 200 300 300 300 300 ma clock running-deselect icck 500 750 750 750 750 ma dc electrical characteristics - read cycle parameter sym min typ max units supply voltage vcc 3.14 3.3 3.6 v supply voltage vss 0.0 0.0 0.0 v input high vih 1.1 3.0 vcc+0.3 v input low vil -0.3 0.0 0.3 v input leakage ili -2 1 2 m a output leakage ilo -2 1 2 m a recommended dc operating conditions *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. absolute maximum ratings* voltage on vcc relative to vss -0.5v to +4.6v vin -0.5v to vcc +0.5v storage temperature -55c to +125c operating temperature (commercial) 0c to +70c operating temperature (industrial) -40c to +85c short circuit output current 10 ma ac test conditions input pulse levels vss to 3.0v input and output timing ref. 1.25v output test equivalencies ac test load synchronous only - truth table dq z 0 = 50 w fig. 1 output load equivalent vt = 1.25v 50 w operation e1\ e2\ gw\ g\ zz clk dq synchronous write-bank 1 l h l h l high-z synchronous read-bank 1 l h h l l synchronous write-bank 2 h l l h l high-z synchronous read-bank 2 h l h l l
edi2ag27264v 1 megabyte sync/sync burst, small outline dimm 7 edi2ag27264v rev. 0 1/98 eco# first second third fourth address address address address (external) (internal) (internal) (internal) a..a00 a..a01 a..a10 a..a11 a..a01 a..a00 a..a11 a..a10 a..a10 a..a11 a..a00 a..a01 a..a11 a..a10 a..a01 a..a00 8.5ns 9ns 10ns 12ns description sym min max min max min max min max units clock cycle time tkhkh * * 10 12 15 ns clock high time tkhkl * * 4 5 5 ns clock low time tklkh * * 4 5 5 ns clock to output valid tkhqv * * 9 10 12 ns clock to output invalid tkhqx1 * * 3 3 3 ns clock to output low-z tkhqx * * 2 2 2 ns output enable to output valid tglqv * * 4 4 5 ns output enable to output low-z tglqx * * 0 0 0 ns output enable to output high-z tghqz * * 4 4 5 ns address setup tavkh * * 2.5 2.5 2.5 ns bank enable setup tevkh * * 2.5 2.5 2.5 ns address hold tkhax * * 1.0 1.0 1.0 ns bank enable hold tkhex * * 1.0 1.0 1.0 ns read cycle timing parameters burst address table (mode=gnd) burst address table (mode=nc/vcc) first second third fourth address address address address (external) (internal) (internal) (internal) a..a00 a..a01 a..a10 a..a11 a..a01 a..a10 a..a11 a..a00 a..a10 a..a11 a..a00 a..a01 a..a11 a..a00 a..a01 a..a10 *tbd synchronous only read cycle tkhqx dq read cycle q(addr 1) tkhqz gw\ oe\ addr ce\ clk tkhqv addr 1 tkhkh tklkh tkhkl tglqx back to back read q(addr 1) tkhqx1 q(addr 2) tglqv addr 1 tkhax addr 2 tavkh ex\ g\
edi2ag27264v 1 megabyte sync/sync burst, small outline dimm 8 edi2ag27264v rev. 0 1/98 eco# 8.5ns 9ns 10ns 12ns description sym min max min max min max min max units clock cycle time tkhkh 10 12 15 ns clock high time tkhkl 4 5 5 ns clock low time tklkh 4 5 5 ns address setup tavkh 2.5 2.5 2.5 ns address hold tkhax 1.0 1.0 1.0 ns bank enable setup tevkh 2.5 2.5 2.5 ns bank enable hold tkhex 1.0 1.0 1.0 ns global write enable setup twvkh 2.5 2.5 2.5 ns global write enable hold tkhwx 1.0 1.0 1.0 ns data setup tdvkh 2.5 2.5 2.5 ns data hold tkhdx 1.0 1.0 1.0 ns write cycle timing parameters sync-burst read cycle tscvkh tkhscx tghqx burst read cycle tevkh tkhex read cycle tglqv tglqx tkhqx dq oe\ ce\ adv\ bwx\, gw\ tghqz tkhkh tkhkl tspvkh tkhspx tavkh tkhax adsp\ addr adsc\ clk tklkh tkhqv tkhqx tavvkh tkhavx ex\ g\
edi2ag27264v 1 megabyte sync/sync burst, small outline dimm 9 edi2ag27264v rev. 0 1/98 eco# sync (non-burst) write cycle syncburst write cycle tghkh tgwlkh tavkh tdvkh write cycle g\ gw\ addr clk ce\ addr 1 tklkh tkhkh tkhkl back to back writes tkhgh tkhdx tkhgwh addr 1 addr 2 tkhax dq burst - late write- cycle tevkh tkhex early write cycle tdvkh tkhqx dq oe\ ce\ adv\ bwx\, gw\ tkhkh tkhkl tavkh tkhax adsp\ addr adsc\ clk tklkh tkhqx tavvkh tkhavx g\ ex\ ex\
edi2ag27264v 1 megabyte sync/sync burst, small outline dimm 10 edi2ag27264v rev. 0 1/98 eco# sync (non-burst) read/write cycle write cycle tdvkh back to back cycles g\ controlled d (addr 2) gw\ dq q(addr 1) read cycle tkhqx tavkh g\ addr ce\ clk tkhqv addr 1 tkhdx addr 2 tkhkh tklkh tkhkl tkhdx
edi2ag27264v 1 megabyte sync/sync burst, small outline dimm 11 edi2ag27264v rev. 0 1/98 eco# package description ordering information part nu mber organization voltage speed (ns) package edi22ag27264v85d1 2x64kx72 3.3 8.5 144 so-dimm edi22ag27264v9d1 2x64kx72 3.3 9 144 so-dimm edi22ag27264v10d1 2x64kx72 3.3 10 144 so-dimm edi22ag27264v12d1 2x64kx72 3.3 12 144 so-dimm *consult factory for availability electronic designs incorporated ? one research drive ? westborough, ma 01581usa ? 508-366-5151 ? fax 508-836-4850 ? electronic designs europe ltd. ? shelley house, the avenue ? lightwater, surrey gu18 5rf united kingdom ? 01276 472637 ? fax: 01276 473748 http://www.electronic-designs.com package no. 409 144 lead so-dimm 2.667 max. 1.000 max. .788 .157 .181 typ. .913 1.291 1.112 1.490 .175 max. u1 r3 r5 r13 r7 r11 r1 u3 r9 r17 r18 r15 p1

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