8k x 8 static ram f ax id : 1013 cy7c185 cypress semiconductor corporation ? 3901 north first street ? san jose ? ca 95134 ? 408-943-2600 au g ust 12 , 1998 features ? high speed 15 ns ? fast t doe ? low active power 715 mw ? low standby power 220 mw ? cmos for optimum speed/power ? easy memory expansion with ce 1 , ce 2 , and oe features ? ttl-compatible inputs and outputs ? automatic power-down when deselected functional description the cy7c185 is a high-performance cmos static ram orga- nized as 8192 words by 8 bits. easy memory expansion is provided by an active low chip enable (ce 1 ), an active high chip enable (ce 2 ), and active low output enable (oe ) and three-state drivers. this device has an automatic power-down feature (ce 1 or ce 2 ), reducing the power consumption by 70% when deselected. the cy7c185 is in a standard 300-mil-wide dip, soj, or soic package. an active low write enable signal (we ) controls the writ- ing/reading operation of the memory. when ce 1 and we in- puts are both low and ce 2 is high, data on the eight data input/output pins (i/o 0 through i/o 7 ) is written into the memory location addressed by the address present on the address pins (a 0 through a 12 ). reading the device is accomplished by selecting the device and enabling the outputs, ce 1 and oe active low, ce 2 active high, while we remains inactive or high. under these conditions, the contents of the location ad- dressed by the information on address pins are present on the eight data input/output pins. the input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (we ) is high. a die coat is used to insure alpha immunity. logic block diagram pin configurations c185C1 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 0 a 10 a 9 a 11 a 12 i/o 0 c185C2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc we ce 2 a 3 a 2 a 1 oe a 0 ce 1 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 nc a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 i/o 0 i/o 1 i/o 2 gnd 256 x 32 x 8 array input buffer column decoder row decoder sense amps power down i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 ce 1 ce 2 we oe top view dip/soj/soic selection guide [1] 7c185C15 7c185C20 7c185C25 7c185C35 maximum access time (ns) 15 20 25 35 maximum operating current (ma) 130 110 100 100 maximum standby current (ma) 40/15 20/15 20/15 20/15 note: 1. for military specifications, see the cy7c185a datasheet.
cy7c185 2 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. C65 c to +150 c ambient temperature with power applied ............................................. C55 c to +125 c supply voltage to ground potential ............... C0.5v to +7.0v dc voltage applied to outputs in high z state [2] ............................................ C0.5v to +7.0v dc input voltage [2] ......................................... C0.5v to +7.0v output current into outputs (low) ............................. 20 ma static discharge voltage .......................................... >2001v (per mil-std-883, method 3015) latch-up current.................................................... >200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% industrial C40 c to +85 c 5v 10% electrical characteristics over the operating range 7c185C15 7c185C20 parameter description test conditions min. max. min. max. unit v oh output high voltage v cc = min., i oh = C4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3v 2.2 v cc + 0.3v v v il input low voltage [2] C0.5 0.8 C0.5 0.8 v i ix input load current gnd v i v cc C5 +5 C5 +5 m a i oz output leakage current gnd v i v cc , output disabled C5 +5 C5 +5 m a i os output short circuit current [3] v cc = max., v out = gnd C300 C300 ma i cc v cc operating supply current v cc = max., i out = 0 ma 130 110 ma i sb1 automatic power-down current max. v cc , ce 1 3 v ih or ce 2 v il min. duty cycle=100% 40 20 ma i sb2 automatic power-down current max. v cc , ce 1 3 v cc C 0.3v, or ce 2 0.3v v in 3 v cc C 0.3v or v in 0.3v 15 15 ma notes: 2. minimum voltage is equal to C3.0v for pulse durations less than 30 ns. 3. not more than 1 output should be shorted at one time. duration of the short circuit should not exceed 30 seconds.
cy7c185 3 electrical characteristics over the operating range (continued) 7c185C25 7c185-35 parameter description test conditions min. max. min. max. unit v oh output high voltage v cc = min., i oh = C4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3v 2.2 v cc + 0.3v v v il input low voltage [2] C0.5 0.8 C0.5 0.8 v i ix input load current gnd v i v cc C5 +5 C5 +5 m a i oz output leakage current gnd v i v cc , output disabled C5 +5 C5 +5 m a i os output short circuit current [3] v cc = max., v out = gnd C300 C300 ma i cc v cc operating supply current v cc = max., i out = 0 ma 100 100 ma i sb1 automatic power-down current max. v cc , ce 1 3 v ih or ce 2 v il min. duty cycle=100% 20 20 ma i sb2 automatic power-down current max. v cc , ce 1 3 v cc C 0.3v or ce 2 0.3v v in 3 v cc C 0.3v or v in 0.3v 15 15 ma capacitance [4] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 7 pf c out output capacitance 7 pf note: 4. tested initially and after any design or process changes that may affect these parameters. ac test loads and waveforms r1 481 w 3.0v 5v output r1 481 w r2 255 w 30 pf gnd 90% 90% 10% 5ns 5 ns 5v output c185C4 r2 255 w 5 pf c185C5 (a) (b) output 1.73v including jig and scope including jigand scope 10% equivalent to: thvenin equivalent all input pulses 167 w
cy7c185 4 switching characteristics over the operating range [5] 7c185C15 7c185C20 7c185C25 7c185C35 parameter description min. max. min. max. min. max. min. max. unit read cycle t rc read cycle time 15 20 25 35 ns t aa address to data valid 15 20 25 35 ns t oha data hold from address change 3 5 5 5 ns t ace1 ce 1 low to data valid 15 20 25 35 ns t ace2 ce 2 high to data valid 15 20 25 35 ns t doe oe low to data valid 8 9 12 15 ns t lzoe oe low to low z 3 3 3 3 ns t hzoe oe high to high z [6] 7 8 10 10 ns t lzce1 ce 1 low to low z [7] 3 5 5 5 ns t lzce2 ce 2 high to low z 3 3 3 3 ns t hzce ce 1 high to high z [6, 7] ce 2 low to high z 7 8 10 10 ns t pu ce 1 low to power-up ce 2 to high to power-up 0 0 0 0 ns t pd ce 1 high to power-down ce 2 low to power-down 15 20 20 20 ns write cycle [8] t wc write cycle time 15 20 25 35 ns t sce1 ce 1 low to write end 12 15 20 20 ns t sce2 ce 2 high to write end 12 15 20 20 ns t aw address set-up to write end 12 15 20 25 ns t ha address hold from write end 0 0 0 0 ns t sa address set-up to write start 0 0 0 0 ns t pwe we pulse width 12 15 15 20 ns t sd data set-up to write end 8 10 10 12 ns t hd data hold from write end 0 0 0 0 ns t hzwe we low to high z [6] 7 7 7 8 ns t lzwe we high to low z 3 5 5 5 ns notes: 5. test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 6. t hzoe, t hzce , and t hzwe are specified with c l = 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady state voltage. 7. at any given temperature and voltage condition, t hzce is less than t lzce1 and t lzce2 for any given device. 8. the internal write time of the memory is defined by the overlap of ce 1 low, ce 2 high, and we low. all 3 signals must be active to initiate a write and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of th e signal that terminates the write.
cy7c185 5 switching waveforms 9. device is continuously selected. oe , ce 1 = v il . ce 2 = v ih . 10. we is high for read cycle. 11. data i/o is high z if oe = v ih , ce 1 = v ih , we = v il , or ce 2 =v il . 12. the internal write time of the memory is defined by the overlap of ce 1 low, ce 2 high and we low. ce 1 and we must be low and ce 2 must be high to initiate write. a write can be terminated by ce 1 or we going high or ce 2 going low. the data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 13. during this period, the i/os are in the output state and input signals should not be applied. address data out previous data valid data valid t rc t aa t oha c185C6 read cycle no.1 [9,10] 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance impedance icc isb t hzoe t hzce t pd oe high data out v cc supply current ce 1 oe ce 2 c185C7 read cycle no.2 [11,12] c185C8 t hd t sd t pwe t sa t ha t aw t wc t hzoe data in valid ce ce 1 oe we ce 2 data i/o t scei t sce2 address note 13 [10,12] write cycle no. 1 (we controlled)
cy7c185 6 notes: 14. the minimum write cycle time for write cycle #3 (we controlled, oe low) is the sum of t hzwe and t sd . 15. if ce 1 goes high or ce 2 goes low simultaneously with we high, the output remains in a high-impedance state. switching waveforms (continued) t wc t aw t sa t ha t hd t sd t sce1 we data i/o address ce 1 c185C9 data in valid t sce2 ce 2 w rite cycle no. 2 (ce controlled) [12,13,14] t hd t sd t lzwe t sa t ha t aw t wc t hzwe c185C10 data in valid t sce1 t sce2 ce 1 ce 2 address data i/o we write cycle no. 3 (we controlled, oe low) [12,13,14,15] note 13
cy7c185 7 typical dc and ac characteristics C55 25 125 1.2 1.0 0.8 output source current (ma) ambient temperature ( c) 0.6 0.4 0.2 0.0 normalized i , i cc i sb v cc =5.0v v in =5.0v i cc sb 1.2 1.4 1.0 0.6 0.4 0.2 4.0 4.5 5.0 5.5 6.0 1.6 1.4 1.2 1.0 0.8 C55 25 125 normalized t aa 120 100 80 60 40 20 0.0 1.0 2.0 3.0 4.0 supply voltage (v) normalized supply current vs. supply voltage normalized access time vs. ambient temperature ambient temperature ( c) normalized supply current vs. ambient temperature output voltage (v) output source current vs. output voltage 0.0 0.8 1.4 1.3 1.2 1.1 1.0 0.9 4.0 4.5 5.0 5.5 6.0 normalized t aa supply voltage (v) normalized access time vs. supply voltage 120 140 100 60 40 20 0.0 1.0 2.0 3.0 4.0 output sink current (ma) 0 80 output voltage (v) output sink current vs. output voltage normalized i , i cc sb i cc v cc =5.0v v cc =5.0v t a =25 c v cc =5.0v t a =25 c i sb t a =25 c 0.6 0.8 0 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.0 2.0 3.0 4.0 normalized i po supply voltage (v) typical power-on current vs. supply voltage 30.0 25.0 20.0 15.0 10.0 5.0 0 200 400 600 800 delta t (ns) aa capacitance (pf) typical access time change vs. output loading 1.25 1.00 0.75 10 20 30 40 normalized i cc cycle frequency (mhz) normalized i cc vs. cycle time 0.0 5.0 0.0 1000 0.50 v cc =4.5v t a =25 c v cc =5.0v t a =25 c v cc =0.5v
cy7c185 8 document #: 38C00037Ck truth table ce 1 ce 2 we oe input/output mode h x x x high z deselect/power-down x l x x high z deselect/power-down l h h l data out read l h l x data in write l h h h high z deselect address designators address name address function pin number a4 x3 2 a5 x4 3 a6 x5 4 a7 x6 5 a8 x7 6 a9 y1 7 a10 y4 8 a11 y3 9 a12 y0 10 a0 y2 21 a1 x0 23 a2 x1 24 a3 x2 25 ordering information speed (ns) ordering code package name package type operating range 15 cy7c185C15pc p21 28-lead (300-mil) molded dip commercial cy7c185C15sc s21 28-lead molded soic cy7c185C15vc v21 28-lead molded soj cy7c185C15vi v21 28-lead molded soj industrial 20 cy7c185C20pc p21 28-lead (300-mil) molded dip commercial cy7c185C20sc s21 28-lead molded soic cy7c185C20vc v21 28-lead molded soj cy7c185C20vi v21 28-lead molded soj industrial 25 cy7c185C25pc p21 28-lead (300-mil) molded dip commercial cy7c185C25sc s21 28-lead molded soic cy7c185C25vc v21 28-lead molded soj cy7c185C25vi v21 28-lead molded soj industrial 35 cy7c185C35pc p21 28-lead (300-mil) molded dip commercial cy7c185C35sc s21 28-lead molded soic cy7c185C35vc v21 28-lead molded soj cy7c185C35vi v21 28-lead molded soj industrial
cy7c185 9 package diagrams 51-85014-b 28-lead (300-mil) molded dip p21 28-lead (300-mil) molded soic s21 51-85026-a
cy7c185 ? cypress semiconductor corporation, 1998. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams (continued) 28-lead (300-mil) molded soj v21 51-85031-b
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